CN102054865B - MOS (Metal Oxide Semiconductor) transistor used as electrostatic protection structure and manufacturing method thereof - Google Patents
MOS (Metal Oxide Semiconductor) transistor used as electrostatic protection structure and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses an MOS (Metal Oxide Semiconductor) transistor used as an electrostatic protection structure. A field plate is arranged in a position nearest to an isolation structure of a source electrode of the MOS transistor, and the field plate is a layer of polysilicon or metal and is smaller than or equal to the isolation structure in size; the field plate and a grid electrode are connected and are grounded together by being connected with a resistor in series; or the field plate is grounded by being connected with a resistor in series, and the grid electrode is grounded by being connected with the other resistor in series. The invention also discloses a manufacturing method of the MOS transistor, and the field plate and the grid electrode are formed together by etching the same layer of materials. In the invention, the trigger voltage of the MOS transistor used as the electrostatic protection structure can be reduced.
Description
Technical field
The present invention relates to a kind of semiconductor device, particularly relate to a kind of MOS transistor of the electrostatic preventing structure as low pressure or high-tension circuit.
Background technology
Static is masty problem for the injury of electronic product always; In semiconductor integrated circuit, use maximum ESD (Electrical Static Discharge at present; Static discharge) the protection structure is GGMOS (Ground Gate MOSFET, the MOS transistor of grounded-grid).The GGMOS device specifically comprises low pressure MOS (being common MOS transistor), LDMOS (Latetal Diffusion MOSFET, laterally diffused MOS transistor) and DDDMOS (Double Diffusion Drain MOSFET, double-diffused drain electrode MOS transistor) etc.Its mesolow MOS is mainly as the electrostatic preventing structure of low-voltage circuit, and LDMOS and DDDMOS are mainly as the electrostatic preventing structure of high-tension circuit.
What be used as electrostatic preventing structure at present mainly is n type MOS transistor, and the low pressure MOS that relates in the present specification, LDMOS, DDDMOS all describe with the n type.
See also Fig. 1, this is a kind of low pressure MOS of n type, on p type substrate 10, is p trap 12.First isolation structure 131, second isolation structure 132 and the 3rd isolation structure 133 are arranged in the p trap 12.Be grid 14 on the p trap 12, grid 14 both sides are side wall 15.In the p trap 12 and between first isolation structure 131, second isolation structure 132, be p type heavily doped region 161, as the exit of p trap 12.In the p trap 12 and between a side of second isolation structure 132 and side wall 15, be n type heavily doped region 162, as source electrode.In the p trap 12 and between the opposite side of the 3rd isolation structure 133 and side wall 15, be n type heavily doped region 163, as drain electrode.When said low pressure MOS is used as the electrostatic preventing structure of semiconductor integrated circuit, p type heavily doped region 161 and source electrode 162 ground connection, grid 14 is through series connection one grounding through resistance, and drain electrode 163 connects static.
See also Fig. 2 a, this is a kind of n type LDMOS.On p type substrate 10, be n trap 11, p trap 12 is arranged in the n trap 11.First isolation structure 131 is in n trap 11 and/or p trap 12.Second isolation structure 132 is in p trap 12.The 3rd isolation structure 133 and the 4th isolation structure 134 are in n trap 11.Be grid 14 on the n trap 11, a side of grid 14 is on p trap 12, and opposite side is on the 3rd isolation structure 133.Grid 14 both sides are side wall 15.In the p trap 12 and between first isolation structure 131, second isolation structure 132, be p type heavily doped region 161, as the exit of p trap 12.In the p trap 12 and between a side of second isolation structure 132 and side wall 15, be n type heavily doped region 162, as source electrode.In the n trap 11 and between the 3rd isolation structure 133, the 4th isolation structure 134, be n type heavily doped region 163, as drain electrode.When said LDMOS was used as the electrostatic preventing structure of semiconductor integrated circuit, p type heavily doped region 161 and source electrode 162 ground connection, grid 14 were through a grounding through resistance, and drain electrode 163 connects static.
See also Fig. 2 b, this is another kind of n type LDMOS.On p type substrate 10, be p trap 12, n trap 11 is arranged in the p trap 12.First isolation structure 131 and second isolation structure 132 are in p trap 12.The 3rd isolation structure 133 is in n trap 11.The 4th isolation structure 134 is in n trap 11 and/or p trap 12.Be grid 14 on the p trap 12, a side of grid 14 is on p trap 12, and opposite side is on the 3rd isolation structure 133.Grid 14 both sides are side wall 15.In the p trap 12 and between first isolation structure 131, second isolation structure 132, be p type heavily doped region 161, as the exit of p trap 12.In the p trap 12 and between a side of second isolation structure 132 and side wall 15, be n type heavily doped region 162, as source electrode.In the n trap 11 and between the 3rd isolation structure 133, the 4th isolation structure 134, be n type heavily doped region 163, as drain electrode.When said LDMOS was used as the electrostatic preventing structure of semiconductor integrated circuit, p type heavily doped region 161 and source electrode 162 ground connection, grid 14 were through a grounding through resistance, and drain electrode 163 connects static.
See also Fig. 3 a, this is a kind of n type DDDMOS.On p type substrate 10, be n trap 11, p trap 12 is arranged in the n trap 11.First isolation structure 131 is in n trap 11 and/or p trap 12.Second isolation structure 132 is in p trap 12.The 3rd isolation structure 133 is in n trap 11.Be grid 14 on the p trap 11, a side of grid 14 is on p trap 12, and opposite side is on n trap 11.Grid 14 both sides are side wall 15.In the p trap 12 and between first isolation structure 131, second isolation structure 132, be p type heavily doped region 161, as the exit of p trap 12.In the p trap 12 and between a side of second isolation structure 132 and side wall 15, be n type heavily doped region 162, as source electrode.What directly contact (promptly at a distance of certain distance) in the n trap 11 and between the opposite side of the 3rd isolation structure 133 and side wall 15 and not with the opposite side of side wall 15 is n type heavily doped region 163, as drain electrode.When said DDDMOS was used as the electrostatic preventing structure of semiconductor integrated circuit, p type heavily doped region 161 and source electrode 162 ground connection, grid 14 were through a grounding through resistance, and drain electrode 163 connects static.
See also Fig. 3 b, this is another kind of n type DDDMOS.On p type substrate 10, be p trap 12, n trap 11 is arranged in the p trap 12.First isolation structure 131 and second isolation structure 132 are in p trap 12.The 3rd isolation structure 133 is in n trap 11 and/or p trap 12.Be grid 14 on the p trap 11, a side of grid 14 is on p trap 12, and opposite side is on n trap 11.Grid 14 both sides are side wall 15.In the p trap 12 and between first isolation structure 131, second isolation structure 132, be p type heavily doped region 161, as the exit of p trap 12.In the p trap 12 and between a side of second isolation structure 132 and side wall 15, be n type heavily doped region 162, as source electrode.What directly contact (promptly at a distance of certain distance) in the n trap 11 and between the opposite side of the 3rd isolation structure 133 and side wall 15 and not with the opposite side of side wall 15 is n type heavily doped region 163, as drain electrode.When said DDDMOS was used as the electrostatic preventing structure of semiconductor integrated circuit, p type heavily doped region 161 and source electrode 162 ground connection, grid 14 were through a grounding through resistance, and drain electrode 163 connects static.
For for simplicity, the epitaxial loayer that possibly exist on the cushion oxide layer of gate oxide, trenched side-wall and the bottom of some fine structures such as grid below, the substrate etc. is all done diagram and explanation among above-mentioned Fig. 1, Fig. 2 a, Fig. 2 b, Fig. 3 a, Fig. 3 b.
See also Fig. 4, LDMOS shown in Fig. 2 a is following as the principle of electrostatic preventing structure.Electrostatic charge is behind the heavily doped region 163 entering LDMOS of drain electrode, and in n trap 11 ionization because highfield can bump with p trap 12 boundaries, the hole of collision back generation arrives p type heavily doped regions 161 through p trap 12, thereby has improved the current potential of p trap 12.The current potential of p trap 12 improves makes the PN junction positively biased of source electrode 162, thereby makes among the LDMOS parasitic triode that is made up of the n trap 11 at heavily doped region 163, source electrode 162 and the raceway groove place of drain electrode (be grid 14 under n trap) open the bleed off electrostatic induced current.The heavily doped region 163 that drains in the said parasitic triode is as collector electrode, and source electrode 162 is as emitter, and p trap 11 is connected to p trap exit 161 as base stage and through an equivalent resistance substrate.
DDDMOS shown in LDMOS shown in low pressure MOS shown in Figure 1, Fig. 2 b, Fig. 3 a and Fig. 3 b, its principle as electrostatic preventing structure is all similar with the LDMOS shown in Fig. 2 a.
In side circuit; Device as electrostatic preventing structure must be triggered before inside is damaged by protective circuit; Even if otherwise itself leakage current ability also can't play the effect of protection internal circuit more by force, it is low as far as possible that this just requires that the trigger voltage (promptly wherein the conducting voltage of parasitic triode) of ESD device does.Usual way is the resistance that the length that widens source class isolation structure (promptly nestling up the isolation structure of source electrode) increases substrate, is issued to the parasitic triode conducting to be implemented in less substrate current, thereby reduces the trigger voltage of ESD device.But this method can cause the huge increase on the area undoubtedly, under the trend that whole chip area is done littler and littler, is can't be received.
Summary of the invention
Technical problem to be solved by this invention provides a kind of MOS transistor as electrostatic preventing structure, and it has less trigger voltage.For this reason, the present invention also will provide the manufacturing approach of said MOS transistor.
For solving the problems of the technologies described above; The present invention is as the MOS transistor of electrostatic preventing structure; Said MOS transistor is GGMOS; Have a field plate above the isolation structure near the source electrode of said MOS transistor, said field plate is polysilicon or metal, and said field plate is less than or equal to the size of said isolation structure on the horizontal cross-section in the size on the horizontal cross-section;
Said field plate links to each other with grid, and together through series connection one grounding through resistance;
Perhaps said field plate is through series connection one grounding through resistance, and said grid is through another grounding through resistance of series connection.
As further improvement of the present invention, said field plate and grid are same material.
The manufacturing approach of above-mentioned MOS transistor as electrostatic preventing structure, said field plate with said grid to forming with the layer of material etching.
The present invention is as the MOS transistor of electrostatic preventing structure, and when static discharge produced, its field plate that increases newly can be coupled and go up positive potential; And produce electrical potential difference with the p trap of its below; Thereby isolation structure thereunder forms depletion region down, and this can reduce the conducting area of substrate current, has increased resistance substrate; Thereby make the parasitic triode in the MOS transistor under lower voltage, to open, promptly reduced trigger voltage as the MOS transistor of electrostatic preventing structure.
Description of drawings
Fig. 1 is the existing structural representation that is used as the low pressure MOS of electrostatic preventing structure;
Fig. 2 a, Fig. 2 b are the existing structural representations that is used as the LDMOS of electrostatic preventing structure;
Fig. 3 a, Fig. 3 b are the existing structural representations that is used as the DDDMOS of electrostatic preventing structure;
Fig. 4 is the principle schematic of LDMOS shown in Fig. 2 a as electrostatic preventing structure;
Fig. 5 is the structural representation that the present invention is used as the low pressure MOS of electrostatic preventing structure;
Fig. 6 a, Fig. 6 b are the structural representations that the present invention is used as the LDMOS of electrostatic preventing structure;
Fig. 7 a, Fig. 7 b are the structural representations that the present invention is used as the DDDMOS of electrostatic preventing structure;
Fig. 8 is the principle schematic of LDMOS shown in Fig. 6 a as electrostatic preventing structure.
Description of reference numerals among the figure:
10 is p type substrate; 11 is the n trap; 12 is the p trap; 131,132,133,134 is isolation structure; 20 is polysilicon layer or metal level; 21 is depletion region.
Embodiment
The present invention is as the MOS transistor of electrostatic preventing structure; Be with the difference of tradition: have a field plate above the isolation structure near source electrode as the MOS transistor of electrostatic preventing structure; Said field plate is one deck polysilicon or metal, and the size of said field plate (on the horizontal cross-section) is less than or equal to the size (on the horizontal cross-section) of said isolation structure.
Particularly, the present invention comprises low pressure MOS, LDMOS, DDDMOS as the MOS transistor of electrostatic preventing structure.
See also Fig. 5, this is a kind of n type low pressure MOS that adopts technical scheme of the present invention.With the difference part of low pressure MOS shown in Figure 1 be: the top near second isolation structure 132 of source electrode 162 has increased a field plate 20, and the size of field plate 20 is less than or equal to the size of second isolation structure 132.When said low pressure MOS was used as the electrostatic preventing structure of semiconductor integrated circuit, field plate 20 linked to each other with grid 14, and together through series connection one grounding through resistance; Perhaps field plate 20 and grid 14 are respectively through the grounding through resistance of connecting.
See also Fig. 6 a, this is a kind of n type LDMOS that adopts technical scheme of the present invention.With the difference part of LDMOS shown in Fig. 2 a be: the top near second isolation structure 132 of source electrode 162 has increased a field plate 20, and the size of field plate 20 is less than or equal to the size of second isolation structure 132.When said LDMOS was used as the electrostatic preventing structure of semiconductor integrated circuit, field plate 20 linked to each other with grid 14, and together through series connection one grounding through resistance; Perhaps field plate 20 and grid 14 are respectively through the grounding through resistance of connecting.
See also Fig. 6 b, this is the another kind of n type LDMOS that adopts technical scheme of the present invention.With the difference part of LDMOS shown in Fig. 2 b be: the top near second isolation structure 132 of source electrode 162 has increased a field plate 20, and the size of field plate 20 is less than or equal to the size of second isolation structure 132.When said LDMOS was used as the electrostatic preventing structure of semiconductor integrated circuit, field plate 20 linked to each other with grid 14, and together through series connection one grounding through resistance; Perhaps field plate 20 and grid 14 are respectively through the grounding through resistance of connecting.
See also Fig. 7 a, this is a kind of n type DDDMOS that adopts technical scheme of the present invention.With the difference part of DDDMOS shown in Fig. 3 a be: the top near second isolation structure 132 of source electrode 162 has increased a field plate 20, and the size of field plate 20 is less than or equal to the size of second isolation structure 132.When said DDDMOS was used as the electrostatic preventing structure of semiconductor integrated circuit, field plate 20 linked to each other with grid 14, and together through series connection one grounding through resistance; Perhaps field plate 20 and grid 14 are respectively through the grounding through resistance of connecting.
See also Fig. 7 b, this is the another kind of n type DDDMOS that adopts technical scheme of the present invention.With the difference part of DDDMOS shown in Fig. 3 b be: the top near second isolation structure 132 of source electrode 162 has increased a field plate 20, and the size of field plate 20 is less than or equal to the size of second isolation structure 132.When said DDDMOS was used as the electrostatic preventing structure of semiconductor integrated circuit, field plate 20 linked to each other with grid 14, and together through series connection one grounding through resistance; Perhaps field plate 20 and grid 14 are respectively through the grounding through resistance of connecting.
Among above-mentioned Fig. 5, Fig. 6 a, Fig. 6 b, Fig. 7 a, Fig. 7 b, for for simplicity, the epitaxial loayer that possibly exist on the cushion oxide layer of gate oxide, trenched side-wall and the bottom of some fine structures such as grid below, the substrate etc. is all done diagram and explanation.Second isolation structure 132 can be the field oxygen isolation structure that adopts oxygen (LOCOS) technology to form, and also can be the shallow groove isolation structure that adopts shallow-trench isolation (STI) technology to form, and its material can be silica (SiO
2), silicon nitride (Si
3N
4), silicon oxynitride (SiO
xN
y, x, y are natural number) etc. medium.
See also Fig. 8, LDMOS shown in Fig. 6 a is following as the principle of electrostatic preventing structure.Electrostatic charge is behind the heavily doped region 163 entering LDMOS of drain electrode, and in n trap 11 ionization because highfield can bump with p trap 12 boundaries, the hole of collision back generation arrives p type heavily doped regions 161 through p trap 12, thereby has improved the current potential of p trap 12.The current potential of p trap 12 improves makes the PN junction positively biased of source electrode 162, thereby makes among the LDMOS parasitic triode that is made up of the n trap 11 at heavily doped region 163, source electrode 162 and the raceway groove place of drain electrode (be grid 14 under n trap) open the bleed off electrostatic induced current.The heavily doped region 163 that drains in the said parasitic triode is as collector electrode, and source electrode 162 is as emitter, and p trap 11 is connected to p trap exit 161 as base stage and through an equivalent resistance substrate.
Because the field plate 20 that increases newly links to each other with grid 14 and through series connection one grounding through resistance, owing to there is RC effect (resistance capacitance coupling effect), field plate 20 can be coupled a positive potential when static discharge takes place, and with its below p trap 12 generation electrical potential differences.So the part near second isolation structure, 132 bottoms can produce repulsion and form a depletion region 21 hole in the p trap 12 below field plate 20.Depletion region 21 will suppress passing through of hole current; Cause p trap resistance substrate (being the resistance that links to each other with the parasitic triode base stage shown in Fig. 8) to rise; Make parasitic triode to be issued to required cut-in voltage at littler substrate current, promptly reduced trigger voltage as the LDMOS of electrostatic preventing structure.
DDDMOS shown in LDMOS shown in low pressure MOS shown in Figure 5, Fig. 6 b, Fig. 7 a and Fig. 7 b, its principle as electrostatic preventing structure is all similar with the LDMOS shown in Fig. 6 a.
The manufacturing approach of the LDMOS of n type shown in Fig. 6 a comprises the steps:
In the 1st step, the ion that on p type substrate 10, carries out n type impurity injects, thereby forms n trap 11 on the surface of p type substrate 10.N type impurity commonly used such as phosphorus, arsenic, antimony.
This step also can become: epitaxial growth one deck p type epitaxial loayer on p type substrate, the ion that on p type epitaxial loayer, carries out n type impurity injects, thereby forms n trap 11 on the surface of p type epitaxial loayer.
In the 2nd step, the ion that in n trap 11, carries out p type impurity injects, thereby forms p trap 12 on the surface of n trap 11.P type impurity commonly used is boron for example.
In the 3rd step, four grooves of etching are filled medium in each groove in n trap 11 and/or p trap 12, form first isolation structure 131, second isolation structure 132, the 3rd isolation structure 133, the 4th isolation structure 134.Usually first deposit one deck silica before the deposit medium in groove is as cushion oxide layer covering groove sidewall and bottom.First isolation structure 131 is in n trap 11 and/or p trap 12.Second isolation structure 132 is in p trap 12.The 3rd isolation structure 133 and the 4th isolation structure 134 are in n trap 11.
The 4th step at silicon chip surface deposit one deck grid material, was generally polysilicon or high k (dielectric constant) metal, and this one deck grid material is simultaneously also as a panel material.Form grid 14 and field plate 20 after the etching.One side of grid 14 is on p trap 12, and opposite side is on the 3rd isolation structure 133.Field plate 20 is on second isolation structure 132, and cross-sectional area is littler than second isolation structure 132.Usually first deposit one deck silica before the deposit grid material forms grid 14 and gate oxide simultaneously after the etching.
The 5th step at silicon chip surface deposit one deck medium, anti-carved this layer medium until etching into grid 14 upper surfaces and/or p trap 11 upper surfaces, thereby formed side wall 15 in the both sides of grid 14.
In the 6th step, the ion that between isolation structure 131 and 132, carries out p type impurity injects, thereby in p trap 12, forms p type heavily doped region 161, as the exit of p trap 12.
The ion that between a side of second isolation structure 132 and side wall 15, carries out n type impurity injects, thereby in p trap 12, forms n type heavily doped region 162, as the source electrode of DDDMOS.
The ion that between the 3rd isolation structure 133, the 4th isolation structure 134, carries out n type impurity injects, thereby in n trap 11, forms n type heavily doped region 163, as the drain electrode of DDDMOS.
The 4th step of said method is equally applicable to make the DDDMOS shown in the LDMOS shown in low pressure MOS shown in Figure 5, Fig. 6 b, Fig. 7 a and Fig. 7 b.
Under preferable case, the present invention is as in the MOS transistor of electrostatic preventing structure, and field plate 20 is a same material with grid 14.And at the deposit grid material, the grid material of institute's deposit also is a panel material simultaneously in the step of etching grid 14, etches grid 14 and field plate 20 during etching together.Like this; The present invention has identical processing step as the manufacturing approach of the MOS transistor of electrostatic preventing structure with existing MOS transistor manufacturing approach as electrostatic preventing structure; Do not introduce extra processing step, thus have make easy, with the advantage of original process compatible.
Claims (8)
1. MOS transistor as electrostatic preventing structure; Said MOS transistor is GGMOS; It is characterized in that; Have a field plate above the isolation structure near the source electrode of said MOS transistor, said field plate is one deck polysilicon or metal, and said field plate is less than or equal to the size of said isolation structure on the horizontal cross-section in the size on the horizontal cross-section;
Said field plate links to each other with grid, and together through series connection one grounding through resistance;
Perhaps said field plate is through series connection one grounding through resistance, and said grid is through another grounding through resistance of series connection.
2. the MOS transistor as electrostatic preventing structure according to claim 1 is characterized in that said MOS transistor is low pressure MOS, goes up at p type substrate (10) to be p trap (12); First isolation structure (131) is arranged in the p trap (12), near second isolation structure (132), the 3rd isolation structure (133) of the source electrode of said MOS transistor; On second isolation structure (132) field plate (20); On the p trap (12) grid (14); Grid (14) both sides are side wall (15); P trap (12) has p type heavily doped region (161), as the exit of p trap (12); P trap (12) has n type heavily doped region (162), as source electrode; P trap (12) has n type heavily doped region (163), as drain electrode;
When said low pressure MOS is used as the electrostatic preventing structure of semiconductor integrated circuit, p type heavily doped region (161) and source electrode (162) ground connection, grid (14) and field plate (20) are through series connection one grounding through resistance, and drain electrode (163) connects static.
3. the MOS transistor as electrostatic preventing structure according to claim 1 is characterized in that said MOS transistor is LDMOS, goes up at p type substrate (10) to be n trap (11); P trap (12) is arranged in the n trap (11); Four isolation structures (131,132,133,134) are arranged in n trap (11) and p trap (12); Wherein in n trap (11) and/or p trap (12), first isolation structure (131) is arranged; In p trap (12), also has second isolation structure (132) near the source electrode of said MOS transistor; In n trap (11), also have the 3rd isolation structure (133) and the 4th isolation structure (134); On second isolation structure (132) field plate (20); On the n trap (11) grid (14); Grid (14) both sides are side wall (15); P type heavily doped region (161) is arranged, as the exit of p trap (12) in the p trap (12); N type heavily doped region (162) is arranged, as source electrode in the p trap (12); N type heavily doped region (163) is arranged, as drain electrode in the n trap (11);
When said LDMOS is used as the electrostatic preventing structure of semiconductor integrated circuit, p type heavily doped region (161) and source electrode (162) ground connection, grid (14) and field plate (20) are through series connection one grounding through resistance, and drain electrode (163) connects static.
4. the MOS transistor as electrostatic preventing structure according to claim 1 is characterized in that said MOS transistor is LDMOS, goes up at p type substrate (10) to be p trap (12); N trap (11) is arranged in the p trap (12); Four isolation structures (131,132,133,134) are arranged in p trap (12) and the n trap (11); First isolation structure (131) is wherein arranged and near second isolation structure (132) of the source electrode of said MOS transistor in p trap (12); In n trap (11), also has the 3rd isolation structure (133); In n trap (11) and/or p trap (12), also has the 4th isolation structure (134); On second isolation structure (132) field plate (20); On the p trap (12) grid (14); Grid (14) both sides are side wall 15; P type heavily doped region (161) is arranged, as the exit of p trap (12) in the p trap (12); N type heavily doped region (162) is arranged, as source electrode in the p trap (12); N type heavily doped region (163) is arranged, as drain electrode in the n trap (11);
When said LDMOS is used as the electrostatic preventing structure of semiconductor integrated circuit, p type heavily doped region (161) and source electrode (162) ground connection, grid (14) and field plate (20) are through series connection one grounding through resistance, and drain electrode (163) connects static.
5. the MOS transistor as electrostatic preventing structure according to claim 1 is characterized in that said MOS transistor is DDDMOS, goes up at p type substrate (10) to be n trap (11); P trap (12) is arranged in the n trap (11); Three isolation structures (131,132,133) are arranged in n trap (11) and p trap (12); Wherein in n trap (11) and/or p trap (12), first isolation structure (131) is arranged; In p trap (12), also has second isolation structure (132) near the source electrode of said MOS transistor; In n trap (11), also has the 3rd isolation structure (133); On second isolation structure (132) field plate (20); On the n trap (11) grid (14); Grid (14) both sides are side wall (15); P type heavily doped region (161) is arranged, as the exit of p trap (12) in the p trap (12); N type heavily doped region (162) is arranged, as source electrode in the p trap (12); N type heavily doped region (163) is arranged, as drain electrode in the n trap (11);
When said DDDMOS is used as the electrostatic preventing structure of semiconductor integrated circuit, p type heavily doped region (161) and source electrode (162) ground connection, grid (14) and field plate (20) are through series connection one grounding through resistance, and drain electrode (163) connects static.
6. the MOS transistor as electrostatic preventing structure according to claim 1 is characterized in that said MOS transistor is DDDMOS, goes up at p type substrate (10) to be p trap (12); N trap (11) is arranged in the p trap (12); Three isolation structures (131,132,133) are arranged in p trap (12) and the n trap (11); First isolation structure (131) is wherein arranged and near second isolation structure (132) of the source electrode of said MOS transistor in p trap (12); In n trap (11) and/or p trap (12), also has the 3rd isolation structure (133); On second isolation structure (132) field plate (20); On the p trap (12) grid (14); Grid (14) both sides are side wall 15; P type heavily doped region (161) is arranged, as the exit of p trap (12) in the p trap (12); N type heavily doped region (162) is arranged, as source electrode in the p trap (12); N type heavily doped region (163) is arranged, as drain electrode in the n trap (11);
When said DDDMOS is used as the electrostatic preventing structure of semiconductor integrated circuit, p type heavily doped region (161) and source electrode (162) ground connection, grid (14) and field plate (20) are through series connection one grounding through resistance, and drain electrode (163) connects static.
7. the MOS transistor as electrostatic preventing structure according to claim 1 is characterized in that said field plate and grid are same material.
8. like the manufacturing approach of the said MOS transistor as electrostatic preventing structure of claim 7, it is characterized in that, said field plate with said grid to forming with the layer of material etching.
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| CN103811483B (en) * | 2012-11-15 | 2016-06-08 | 上海华虹宏力半导体制造有限公司 | Electrostatic preventing structure |
| CN104269402B (en) * | 2014-09-04 | 2017-05-10 | 电子科技大学 | High-voltage ESD protective circuit with stacked SCR-LDMOS |
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| US10211290B2 (en) * | 2016-03-10 | 2019-02-19 | Nxp B.V. | Electrostatic discharge protection |
| US10290714B2 (en) * | 2016-05-31 | 2019-05-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Transistor structure with field plate for reducing area thereof |
| CN108063134B (en) * | 2017-12-01 | 2021-02-05 | 中国科学院上海微系统与信息技术研究所 | NMOS device based on SOI technology and electrostatic protection circuit formed by NMOS device |
| CN115497830A (en) * | 2022-11-21 | 2022-12-20 | 广州粤芯半导体技术有限公司 | Method for manufacturing semiconductor device and semiconductor device |
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| US6949797B2 (en) * | 2001-07-31 | 2005-09-27 | Infineon Technologies Ag | Semiconductor structure comprising a magnetoresistor |
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