CN103094272B - For the groove-shaped isolated gate FET structure of electrostatic protection - Google Patents
For the groove-shaped isolated gate FET structure of electrostatic protection Download PDFInfo
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- CN103094272B CN103094272B CN201110340523.7A CN201110340523A CN103094272B CN 103094272 B CN103094272 B CN 103094272B CN 201110340523 A CN201110340523 A CN 201110340523A CN 103094272 B CN103094272 B CN 103094272B
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Abstract
The invention discloses a kind of groove-shaped isolated gate FET structure for electrostatic protection, comprise a N-type epitaxy layer, the top of N-type epitaxy layer is formed with multiple P type trap, mutually isolated between multiple P type trap; Have two N-type active areas respectively in each P type trap, two N-type active areas are by a P type active area isolation; Grid is provided with between each P type trap; Two mutual short circuits in N-type active area in described each P type trap, and be connected with the P type active area in this P type trap; Each grid short circuit mutually; N-type active area in one of them P type trap is connected with grid, and is connected with earth terminal through a resistance; N-type active area in other P type trap is directly connected with earth terminal.The present invention, by carrying out optimum organization to the construction unit of existing groove-shaped isolated gate FET from circuit, increases grid capacitance coupling circuit, can reach and reduce field effect transistor cut-in voltage, the object of boost device leakage current ability.
Description
Technical field
The present invention relates to a kind of groove-shaped isolated gate FET, be specifically related to a kind of groove-shaped isolated gate FET structure for electrostatic protection.
Background technology
Existing groove-shaped isolated gate FET (IGBT) unit as shown in Figure 1, comprises a N-type epitaxy layer, and the top of N-type epitaxy layer is formed with multiple P type trap, respectively by trench isolations between multiple P type trap; Be formed with gate oxide in groove, in gate oxide, be filled with polysilicon gate, form the grid of field effect transistor; A N-type active area is had respectively as the source electrode of field effect transistor in the P type trap of groove both sides; In P type trap adjacent with N-type active area also have a P type active area to be used as P type trap pick out end, be connected with source electrode in outside; There is one deck P type implanted layer at the back side of N-type epitaxy layer, as the drain terminal of field effect transistor.
For electrostatic protection device, require that its trigger voltage should be less than the damage voltage (damage voltage is generally the puncture voltage of grid oxygen Gate Oxide puncture voltage or device source and drain) of inner protected device.And existing groove-shaped isolated gate FET device is when for electrostatic protection, its trigger voltage is not less than the puncture voltage of N-type extension and P type trap, and therefore its puncture voltage is higher, and is difficult to adjustment by the restriction of technique itself.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of groove-shaped isolated gate FET structure for electrostatic protection, and it can solve IGBT device too high for trigger voltage during electrostatic protection so that cannot protect the problem of internal circuit.
For solving the problems of the technologies described above, the technical solution that the present invention is used for the groove-shaped isolated gate FET structure of electrostatic protection is:
Comprise a N-type epitaxy layer, the top of N-type epitaxy layer is formed with multiple P type trap, mutually isolated between multiple P type trap; Have two N-type active areas respectively as the source electrode of field effect transistor in each P type trap, two N-type active areas in P type trap are by a P type active area isolation; There is one deck P type implanted layer at the back side of N-type epitaxy layer as the drain terminal of field effect transistor; Grid is provided with between each P type trap; Two mutual short circuits in N-type active area in described each P type trap, and be connected with the P type active area in this P type trap; Each grid short circuit mutually; N-type active area in one of them P type trap is connected with grid, and is connected with earth terminal through a resistance; N-type active area in other P type trap is directly connected with earth terminal.
Mutually isolated by groove between described multiple P type trap; Be formed with gate oxide in each groove, be filled with polysilicon gate in gate oxide, the gate oxide in each groove and polysilicon gate form described grid.
Mutually isolated by N-type epitaxy layer between described multiple P type trap; There is gate oxide the top of each isolated area, and there is polysilicon gate the top of gate oxide, and the gate oxide above each isolated area and polysilicon gate form described grid.
The technique effect that the present invention can reach is:
The present invention, by carrying out optimum organization to the construction unit of existing groove-shaped isolated gate FET from circuit, increases grid capacitance coupling circuit, can reach and reduce field effect transistor cut-in voltage, the object of boost device leakage current ability.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the schematic diagram of existing groove-shaped isolated gate FET;
Fig. 2 is the schematic diagram of the present invention for the groove-shaped isolated gate FET structure of electrostatic protection;
Fig. 3 is the schematic diagram of another embodiment of the present invention;
Fig. 4 is equivalent circuit diagram of the present invention.
Fig. 5 adopts circuit diagram of the present invention.
Embodiment
Be illustrated in figure 2 first embodiment of the present invention for the groove-shaped isolated gate FET structure of electrostatic protection, comprise a N-type epitaxy layer, the top of N-type epitaxy layer is formed with multiple P type trap, respectively by trench isolations between multiple P type trap; Be formed with gate oxide in each groove, be filled with polysilicon gate in gate oxide, the gate oxide in each groove and polysilicon gate form the grid of field effect transistor; Two N-type active areas adjacent with groove are had respectively as the source electrode of field effect transistor in each P type trap; Two N-type active areas in P type trap are by a P type active area isolation, and what P type active area was used as P type trap picks out end, is connected with source electrode in outside; There is one deck P type implanted layer at the back side of N-type epitaxy layer, as the drain terminal of field effect transistor; This field effect transistor is longitudinal groove type isolated gate FET;
Two mutual short circuits in N-type active area in each P type trap, and be connected with the P type active area in this P type trap; Each grid short circuit mutually; N-type active area in one of them P type trap is connected with grid, and is connected with earth terminal through a resistance; N-type active area in other P type trap is directly connected with earth terminal.
Be illustrated in figure 3 second embodiment of the present invention for the groove-shaped isolated gate FET structure of electrostatic protection, comprise a N-type epitaxy layer, the top of N-type epitaxy layer is formed with multiple P type trap, isolates between multiple P type trap respectively by N-type epitaxy layer; There is gate oxide the top of each isolated area, and there is polysilicon gate the top of gate oxide, and the gate oxide above each isolated area and polysilicon gate form the grid of field effect transistor; Two N-type active areas are had respectively as the source electrode of field effect transistor in each P type trap; Two N-type active areas in P type trap are by a P type active area isolation, and what P type active area was used as P type trap picks out end, is connected with source electrode in outside; There is one deck P type implanted layer at the back side of N-type epitaxy layer, as the drain terminal of field effect transistor; This field effect transistor is lateral trench type isolated gate FET;
Two mutual short circuits in N-type active area in each P type trap, and be connected with the P type active area in this P type trap; Each grid short circuit mutually; N-type active area in one of them P type trap is connected with grid, and is connected with earth terminal through a resistance; N-type active area in other P type trap is directly connected with earth terminal.
Equivalent circuit diagram of the present invention as shown in Figure 4.
In order to reduce the trigger voltage of isolated gate FET, the present invention adopts grid capacitance coupling circuit to be optimized it, selects one group of field effect transistor unit as equivalent capacity.As shown in Figure 5, when there being electrostatic to enter from electrostatic end, simultaneously can on polysilicon gate couple current, this electric current through outer meeting resistance to earth terminal, can be coupled coating-forming voltage on polysilicon gate, cause the raceway groove of the field effect transistor unit for discharging to be opened and form electric current, and then trigger NPN parasitic in IGBT and PNP triode unlatching leakage current.Rise time due to electrostatic is in nanosecond (ns) level, and the rise time of normal working voltage is millisecond (ms) level, slow compared with the rise time of electrostatic a lot, also coupled voltages on polysilicon gate is not easy, therefore use the mode that this capacitive coupling triggers, IGBT device can not be caused under normal working voltage by false triggering.
Claims (3)
1. for a groove-shaped isolated gate FET structure for electrostatic protection, comprise a N-type epitaxy layer, the top of N-type epitaxy layer is formed with multiple P type trap, mutually isolated between multiple P type trap; Have two N-type active areas respectively as the source electrode of field effect transistor in each P type trap, two N-type active areas in P type trap are by a P type active area isolation; There is one deck P type implanted layer at the back side of N-type epitaxy layer as the drain terminal of field effect transistor; Grid is provided with between each P type trap; It is characterized in that: two mutual short circuits in N-type active area in described each P type trap, and be connected with the P type active area in this P type trap; Each grid short circuit mutually; N-type active area in one of them P type trap is connected with grid, and is connected with earth terminal through a resistance; N-type active area in other P type trap is directly connected with earth terminal.
2. the groove-shaped isolated gate FET structure for electrostatic protection according to claim 1, is characterized in that: mutually isolated by groove between described multiple P type trap; Be formed with gate oxide in each groove, be filled with polysilicon gate in gate oxide, the gate oxide in each groove and polysilicon gate form described grid.
3. the groove-shaped isolated gate FET structure for electrostatic protection according to claim 1, is characterized in that: mutually isolated by N-type epitaxy layer between described multiple P type trap; There is gate oxide the top of each isolated area, and there is polysilicon gate the top of gate oxide, and the gate oxide above each isolated area and polysilicon gate form described grid.
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| CN201110340523.7A CN103094272B (en) | 2011-11-01 | 2011-11-01 | For the groove-shaped isolated gate FET structure of electrostatic protection |
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| CN201110340523.7A CN103094272B (en) | 2011-11-01 | 2011-11-01 | For the groove-shaped isolated gate FET structure of electrostatic protection |
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| CN103094272B true CN103094272B (en) | 2015-08-19 |
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| CN109979932B (en) * | 2017-12-28 | 2020-11-10 | 无锡华润上华科技有限公司 | Electrostatic discharge protection device |
| CN112271136A (en) * | 2020-10-14 | 2021-01-26 | 上海维安半导体有限公司 | Preparation method of trigger type silicon controlled rectifier device and rectifying device |
| CN116779662A (en) * | 2023-08-22 | 2023-09-19 | 深圳芯能半导体技术有限公司 | Antistatic IGBT chip and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1794451A (en) * | 2004-11-15 | 2006-06-28 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
| CN102054865A (en) * | 2009-11-05 | 2011-05-11 | 上海华虹Nec电子有限公司 | MOS (Metal Oxide Semiconductor) transistor used as electrostatic protection structure and manufacturing method thereof |
| CN102097431A (en) * | 2009-12-10 | 2011-06-15 | 新唐科技股份有限公司 | Chip and electro-static discharge (ESD) protection element thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1794451A (en) * | 2004-11-15 | 2006-06-28 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
| CN102054865A (en) * | 2009-11-05 | 2011-05-11 | 上海华虹Nec电子有限公司 | MOS (Metal Oxide Semiconductor) transistor used as electrostatic protection structure and manufacturing method thereof |
| CN102097431A (en) * | 2009-12-10 | 2011-06-15 | 新唐科技股份有限公司 | Chip and electro-static discharge (ESD) protection element thereof |
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