CN102983136A - Longitudinal NPN triggered high-voltage ESD protective device with high maintaining voltage - Google Patents
Longitudinal NPN triggered high-voltage ESD protective device with high maintaining voltage Download PDFInfo
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- CN102983136A CN102983136A CN2012105492253A CN201210549225A CN102983136A CN 102983136 A CN102983136 A CN 102983136A CN 2012105492253 A CN2012105492253 A CN 2012105492253A CN 201210549225 A CN201210549225 A CN 201210549225A CN 102983136 A CN102983136 A CN 102983136A
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Abstract
The invention discloses a longitudinal NPN triggered high-voltage ESD (Electronic Static Discharge) protective device with high maintaining voltage. The protective device can be used for an on-chip IC (Integrated Circuit) high-voltage ESD protective circuit and mainly comprises a substrate Psub, an N buried layer, P epitaxy, an N sink, a high-voltage deep N well, a first N+ injection region, a first P+ injection region, a second N+ injection region, a third N+ injection region, a polysilicon gate, thin gate oxide and a plurality of field oxide isolation regions. A reverse PN junction of an internal longitudinal NPN structure of the protective device is triggered and switched on under a high-voltage ESD pulse action to form a plurality of ESD current discharge paths connected in parallel, so that secondary breakdown current of the device can be raised, the switch-on resistance can be reduced, and the robustness of the device can be improved. The current path of the device after triggering and switch-on is extended by extending the length of the polysilicon gate of an LDMOS (laterally diffused metal oxide semiconductor) device, increasing the base width of the NPN structure, and employing the N buried layer and the N sink, the electric field distribution in the device is changed, and the voltage endurance capability and maintaining voltage of the device are improved and increased.
Description
Technical field
The invention belongs to the electrostatic protection field of integrated circuit, relate to a kind of high pressure esd protection device, be specifically related to a kind of high pressure esd protection device of high maintenance voltage of vertical NPN triggering, can be used for improving the reliability of IC high pressure esd protection on the sheet.
Background technology
LDMOS and VDMOS Power Field-Effect Device are the New Type Power Devices that develops rapidly last century end, and along with power, the capacity of power semiconductor constantly increases and the improving constantly of performance, its range of application is also in continuous expansion.At high-voltage DC power supply, the low-frequency high-power fields such as motor driven, power device is indispensable important semiconductor device especially.Yet, in the engineering application process, usually can cause circuit function to lose efficacy or damage because of some " chance " factors.Through investigation, outside the failure factor that dividing circuit component ageing and short circuit, open circuit etc. easily repaired, also exist some to be difficult for the fault that known static discharge (ESD) produces, i.e. " chance " inefficacy.Get rid of these potential failure factors, need to adopt suitable electrostatic defending measure at power device and circuit port.
Over nearly 20 years, people utilize the large electric current of power device, high voltage bearing characteristic, often adopt horizontal double diffusion isolated gate FET (LDMOS) at the output port of intelligent power IC both with the rate of doing work pipe of tending to act, again as the ESD protective device.Yet, facts have proved in the ESD security application, the esd protection poor-performing of LDMOS device, minority LDMOS device is low because of its grid oxygen breakdown characteristics, does not resist the impact of high pressure esd pulse and damaged.Even most LDMOS are by field plate techniques or reduce surface field (RESURF) technology, improved the grid oxygen breakdown characteristics of device, but, most of LDMOS device is still under the effect of high pressure esd pulse, stagnate in case trigger back, device is just damaged, robustness a little less than, the electronic product that does not reach national regulation requires manikin to be not less than the electrostatic defending standard of 2000V.Although the someone has proposed the high pressure esd protection device that a kind of SCR-LDMOS two structures combine in recent years; the robustness of this device is compared with the robustness of single structure LDMOS; though be largely increased; but it is still on the low side to keep voltage, still has high trigger voltage, low keeps voltage, enters the risk of latch mode easily.Especially drive chip for some high drive chips such as three-phase motor forward and backward, there is forward and reverse voltage in its high-voltage driving circuit, for these special high drive chips, not only need the forward esd pulse of high-voltage driving circuit is released, and require also can release to reverse ESD high-voltage pulse, thereby really reduce positive and negative bi-directional ESD pulse causes disabler to high-voltage driving circuit risk.The invention provides a kind of new technical scheme, can improve the voltage endurance capability of device and keep voltage, can improve secondary breakdown current again, strengthen its robustness.
Summary of the invention
For the existing above-mentioned technological deficiency of prior art; example design of the present invention the high pressure esd protection device of the high maintenance voltage that triggers of a kind of vertical NPN; both take full advantage of the LDMOS device and can bear high-voltage breakdown; and the characteristics of NPN device high maintenance voltage; utilized again SCR device low on-resistance; the characteristics of large current drain ability; by utilizing N sinking trap; the N buried regions; the particular design of P extension and high pressure N trap domain level; make device under the effect of high pressure esd pulse; vertically the reverse PN junction in the NPN structure is breakdown, forms many ESD current drain paths.And the domain level of above-mentioned particular design has prolonged the current lead-through path after device triggers, and has changed the Electric Field Distribution of device inside, is conducive to improve the voltage endurance capability of device and keeps voltage, increases secondary breakdown current.Can realize high pressure resistant, high maintenance voltage, the esd protection performances such as low on-resistance, strong robustness.
The present invention is achieved through the following technical solutions:
The high pressure esd protection device of the high maintenance voltage that a kind of vertical NPN triggers, it comprises forward and reverse high pressure ESD current drain path, to improve secondary breakdown current, reduces conducting resistance.It is characterized in that: mainly by substrate Psub, the N buried regions, the P extension, a N sinking trap, the dark N trap of high pressure, the 2nd N sinking trap, the one N+ injection region, a P+ injection region, the 2nd N+ injection region, the 3rd N+ injection region, the grid thin oxide layer of first oxygen isolated area, second oxygen isolated area, the 3rd oxygen isolated area, the 4th oxygen isolated area, the 5th oxygen isolated area and polysilicon gate and covering thereof consists of;
Described N buried regions is on the surface of described substrate Psub;
Described P extension is on described N buried regions;
From left to right be provided with successively described first oxygen isolated area, a described N sinking trap, the dark N trap of described high pressure and described the 2nd N sinking trap and described the 5th oxygen isolated area on the described P extension;
A described N sinking trap is provided with a described N+ injection region, and described first oxygen isolated area is connected with a described N+ injection region;
From left to right be provided with successively a described P+ injection region, described the 3rd oxygen isolated area and described the 2nd N+ injection region on the dark N trap of described high pressure;
Be provided with described second oxygen isolated area between a described N+ injection region and the described P+ injection region;
Described the 2nd N sinking trap is provided with described the 3rd N+ injection region;
Be provided with described the 4th oxygen isolated area, described polysilicon gate and described grid thin oxide layer between described the 2nd N+ injection region and described the 3rd N+ injection region, described the 4th oxygen isolated area left-half is positioned on the surface portion zone of the dark N trap of described high pressure, described the 4th oxygen isolated area right half part is positioned on the surface portion zone of described polysilicon gate, described polysilicon has covered whole described grid thin oxide layers, and described grid thin oxide layer is across the zone of the surface portion on the dark N trap of described high pressure and described P extension;
A described N+ injection region, described the 3rd N+ injection region are connected with the first metal layer 1 respectively, and described the first metal layer 1 is connected with the first metal layer 2, and draws an electrode from described the first metal layer 2, as the negative electrode of device;
Described polysilicon gate is connected with the second metal level 1, and draws an electrode from described the second metal level 1, as the grid of device;
A described P+ injection region, described the 2nd N+ injection region are connected with the 3rd metal level 1 respectively, and described the 3rd metal level 1 is connected with the second metal level 2, and draw an electrode from described the second metal level 2, as the anode of device.
Useful technique effect of the present invention is:
(1) example device of the present invention take full advantage of that the SCR opening speed is fast, the advantage of secondary breakdown current large (strong robustness), conducting resistance is little and NPN high maintenance voltage high pressure resistant with LDMOS, take full advantage of the not high characteristics of concentration impurity ion in described high pressure N trap and the described P epi region, can improve the high-voltage resistance capability of device.
(2) particular design of the described N sinking trap of example devices use of the present invention, described the 2nd N sinking trap, described N buried regions, described P extension domain level, can consist of vertical NPN structure, can improve voltage endurance capability, the RESURF of device, can also prolong the ESD current drain path after the device triggering and conducting, improve and keep voltage.
(3) compared with prior art, example device of the present invention not only can reduce conducting resistance, strengthen ESD current drain ability, can also realize the two-way prevention of forward and reverse esd pulse voltage.Corrected in the past that LDMOS high voltage protective device robustness is weak, response speed slowly, can not in time open and the shortcoming such as unidirectional esd protection, can realize the esd protection demand of high maintenance voltage, strong robustness.
Description of drawings
Fig. 1 is the internal structure generalized section of the embodiment of the invention;
Fig. 2 is the circuit connection diagram that example of the present invention is used for the high pressure esd protection;
Fig. 3 is the equivalent electric circuit under the effect of forward esd pulse and ESD current drain path thereof in the example of the present invention;
Fig. 4 is equivalent electric circuit and the ESD current drain path thereof under the reverse esd pulse effect in the example of the present invention.
Embodiment
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Example design of the present invention the high pressure esd protection device of the high maintenance voltage that triggers of a kind of vertical NPN; the characteristics of the high pressure resistant and NPN device high maintenance voltage of LDMOS device had both been taken full advantage of; the characteristics of SCR device low on-resistance, large current drain ability have been utilized again; by using N-type sinking trap, n type buried layer, P type epitaxial loayer and the dark N trap of high pressure; consist of in vertical NPN structure oppositely the PN junction esd protection device of conducting that is triggered, and prolonged the current lead-through path after device triggers.By elongating the length of polysilicon gate, improve the voltage endurance capability of device and keep voltage, increase secondary breakdown current, reduce conducting resistance.
The profile of example device inside structure of the present invention as shown in Figure 1, the high pressure esd protection device of the high maintenance voltage that a kind of vertical NPN triggers, it comprises forward and reverse high pressure ESD current drain path, to improve secondary breakdown current, reduces conducting resistance.It is characterized in that: mainly by substrate Psub 101, N buried regions 102, P extension 103, the one N sinking trap 104, the dark N trap 105 of high pressure, the 2nd N sinking trap 106, the one N+ injection regions 107, a P+ injection region 108, the 2nd N+ injection region 109,110, the first the oxygen isolated areas 111 in the 3rd N+ injection region, second oxygen isolated area 112, the 3rd oxygen isolated area 113, the 4th oxygen isolated area 114, the 5th oxygen isolated area 117 and polysilicon gate 115 and the grid thin oxide layer 116 that covers thereof consist of.
Described N buried regions 102 is on the surface of described substrate Psub 101, form by the large N-type doping ion that injects on described Psub 101, its N-type concentration impurity ion is only second to the N-type concentration impurity ion in a described N+ injection region 107, described the 2nd N+ injection region 109, described the 3rd N+ injection region 110, be conducive to the device inside transverse electric field is become longitudinal electric field, improve the voltage endurance capability of device.
Described P extension 103 is the P type epitaxial loayer of 8～10 μ m in described N buried regions 102 growth a layer thickness on described N buried regions 102, rationally controls the thickness of described P extension 103, prevents from causing because of the base break-through esd protection performance failure of device; The p type impurity ion concentration a little more than described substrate Psub 101, far below p type impurity ion concentration in the described P+ injection region 108, helps to improve the voltage endurance capability of device thus in the described P extension 103 in the element layout level of P-type conduction type.
From left to right be provided with successively described first oxygen isolated area 111, a described N sinking trap 104, the dark N trap 105 of described high pressure and described the 2nd N sinking trap 106 and described the 5th oxygen isolated area 117 on the described P extension 103.
A described N sinking trap 104 is on described N buried regions 102, form by the large injection N-type of high-energy doping ion in the surface portion zone of described P extension 103, the N-type concentration impurity ion is only second to described N buried regions 102 in the described N sinking trap 104 in the domain level of N-type conduction type; A described N sinking trap 104 is provided with a described N+ injection region 107, and described first oxygen isolated area 111 is connected with a described N+ injection region 107.
The dark N trap 105 of described high pressure is on described P extension 103, macro-energy is injected the formation of N-type doping ion in the surface portion zone of described P extension 103, N-type concentration impurity ion in the dark N trap 105 of described high pressure is minimum in the domain level of N-type conduction type, can improve thus the voltage endurance capability of device; From left to right be provided with successively a described P+ injection region 108, described the 3rd oxygen isolated area 113 and described the 2nd N+ injection region 109 on the dark N trap 105 of described high pressure.
Be provided with described second oxygen isolated area 112 between a described N+ injection region 107 and the described P+ injection region 108, distance between the left side edge of the dark N trap 105 of described high pressure and the described P+ injection region 108 is about half of described second oxygen isolated area 112 length, the lateral length of described second oxygen isolated area 112 is larger, guarantees the base break-through can not occur between a described N sinking trap 104, described P extension 103 and the dark N trap 105 of described high pressure.
Described the 2nd N sinking trap 106 adopts same mask plate with a described N sinking trap 104, and Implantation Energy, injection length and N-type concentration impurity ion are identical, and described the 2nd N sinking trap 106 is provided with described the 3rd N+ injection region 110.
Be provided with described the 4th oxygen isolated area 114 between described the 2nd N+ injection region 109 and described the 3rd N+ injection region 110, described polysilicon gate 115 and described grid thin oxide layer 116, described the 4th oxygen isolated area 114 left-half are positioned on the surface portion zone of the dark N trap 105 of described high pressure, described the 4th oxygen isolated area 114 right half parts are positioned on the surface portion zone of described polysilicon gate 115, described polysilicon 115 has covered whole described grid thin oxide layers 116, and described grid thin oxide layer 116 is across on the surface portion zone of the dark N trap 105 of described high pressure and described P extension 103; The length of described polysilicon gate 115 is larger, the one, help to prevent to occur between the dark N trap 105 of described high pressure, described P extension 103 and described the 2nd N sinking trap 106 the base break-through, the 2nd, help to increase the base width of NPN structure, prolong ESD current drain path, improve and keep voltage.
As shown in Figure 2, a described N+ injection region 107 is connected with 218,224 of metal level 1 respectively with described the 3rd N+ injection region 110,218,224 of described metal level 1 is connected with 225 of metal level 2, and draws an electrode 226 from 225 of described metal level 2, as the negative electrode of device; Described polysilicon gate 115 is connected with (223) of metal level 1 and draws an electrode (227) from (223) of described metal level 1, as the grid of device; A described P+ injection region 108, described the 2nd N+ injection region 109 are connected with 219,220 of metal level 1 respectively, 219,220 of described metal level 1 is connected with 221 of metal level 2, and draw an electrode 222 from 221 of described metal level 2, as the anode of device.
As shown in Figure 3, connect the high potential of high pressure esd pulse when the described anode of device, when described negative electrode and described grounded-grid, the dark N trap 105 of described high pressure, described P extension 103, described N buried regions 102 can consist of a vertical NPN structure, when the high pressure esd pulse surpasses the dark N trap 105 of described high pressure and described P extension 103 at the interface oppositely during the puncture voltage of PN junction, T1 among Fig. 3 in the dotted ellipse frame, T2, the collector junction of T3 parasitic transistor is breakdown, the device conducting that is triggered, form the ESD current path of three band arrows among Fig. 3, namely form LDMOS, the ESD current lead-through path that SCR and BJT three structures are opened simultaneously, can improve secondary breakdown current and keep voltage, reduce conducting resistance.
As shown in Figure 4, connect the high potential of high pressure esd pulse when the described negative electrode of device, when described anode and described grounded-grid, when the high pressure esd pulse is higher than the puncture voltage of described N buried regions 102 and described P extension 103 reverse PN junction at the interface, T4 among Fig. 4 in the dotted ellipse frame, the conducting that is triggered of T5 transistor collector junction, formation is by a described N sinking trap 104, described the 2nd N sinking trap 106, described N buried regions 102, the dark N trap 105 of described P extension 103 and described high pressure consists of the ESD current drain path of NPN two interdigital structures, can improve the secondary breakdown current of device reverse impulse, reduce conducting resistance, have strong robustness.
Utilize a described N sinking trap 104, described the 2nd N sinking trap 106, described N buried regions 102, described P extension 103 and the dark N trap 105 of described high pressure; consisted of an esd protection device with longer guiding path vertical structure; reduced surface field, can improve the high-voltage resistance capability of device and keep voltage.
By elongating the lateral length of described polysilicon gate 115, increase the base width of the NPN structure that is consisted of by the dark N trap 105 of described high pressure, described P extension 103 and described N buried regions 102, improve the voltage of keeping of device.
Example device of the present invention adopts the BCD high-pressure process of 0.35 μ m, the thickness of P extension 103 described in the example device of the present invention is 8～10 μ m, both can prevent thus that depletion region and the depletion region between described P extension 103 and the described N buried regions 102 between the dark N trap 105 of described high pressure and the described P extension 103 were overlapping, be that the base break-through does not occur the NPN structure, can guarantee that again device comes interim in time unlatching at esd pulse.
Explanation is at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although with reference to preferred embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from aim and the scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (4)
1. the high pressure esd protection device of the high maintenance voltage that triggers of a vertical NPN, it is characterized in that: mainly by substrate Psub (101), N buried regions (102), P extension (103), the one N sinking trap (104), the dark N trap of high pressure (105), the 2nd N sinking trap (106), the one N+ injection region (107), the one P+ injection region (108), the 2nd N+ injection region (109), the 3rd N+ injection region (110), first oxygen isolated area (111), second oxygen isolated area (112), the 3rd oxygen isolated area (113), the 4th oxygen isolated area (114), the 5th oxygen isolated area (117) and polysilicon gate (115) and the grid thin oxide layer (116) that covers thereof consist of;
Described N buried regions (102) is on the surface of described substrate Psub (101);
Described P extension (103) is on described N buried regions (102);
From left to right be provided with successively described first oxygen isolated area (111), a described N sinking trap (104), the dark N trap of described high pressure (105) and described the 2nd N sinking trap (106) and described the 5th oxygen isolated area (117) on the described P extension (103);
A described N sinking trap (104) is provided with a described N+ injection region (107), and described first oxygen isolated area (111) is connected with a described N+ injection region (107);
From left to right be provided with successively a described P+ injection region (108), described the 3rd oxygen isolated area (113) and described the 2nd N+ injection region (113) on the dark N trap of described high pressure (105);
Be provided with described second oxygen isolated area (112) between a described N+ injection region (107) and the described P+ injection region (108);
Described the 2nd N sinking trap (106) is provided with described the 3rd N+ injection region (110);
Be provided with described the 4th oxygen isolated area (114) between described the 2nd N+ injection region (109) and described the 3rd N+ injection region (110), described polysilicon gate (115) and described grid thin oxide layer (116), described the 4th oxygen isolated area (114) left-half is positioned on the surface portion zone of the dark N trap of described high pressure (105), described the 4th oxygen isolated area (114) right half part is positioned on the surface portion zone of described polysilicon gate (115), described polysilicon (115) has covered whole described grid thin oxide layers (116), and described grid thin oxide layer (116) is across on the surface portion zone of the dark N trap of described high pressure (105) and described P extension (103);
A described N+ injection region (107) is connected with (218) (224) of metal level 1 respectively with described the 3rd N+ injection region (110), (218) (224) of described metal level 1 are connected with (225) of metal level 2, and draw an electrode (226) from (225) of described metal level 2, as the negative electrode of device;
Described polysilicon gate (115) is connected with (223) of metal level 1, and draws an electrode (227) from (223) of described metal level 1, as the grid of device;
A described P+ injection region (108), described the 2nd N+ injection region (109) are connected with (219) (220) of metal level 1 respectively, (219) (220) of described metal level 1 are connected with (221) of metal level 2, and draw an electrode (222) from (221) of described metal level 2, as the anode of device;
Connect the high potential of high pressure esd pulse when the described anode of device, when described negative electrode and described grounded-grid, the dark N trap of described high pressure (105), described P extension (103), described N buried regions (102) can consist of a vertical NPN structure, can bear high-voltage pulse impacts, can form again the ESD current lead-through path of LDMOS, SCR and BJT three structures after being triggered, to improve secondary breakdown current and to keep voltage, reduce conducting resistance;
Connect the high potential of high pressure esd pulse when the described negative electrode of device, when described anode and described grounded-grid, a described N sinking trap (104), described the 2nd N sinking trap (106), described N buried regions (102), described P extension (103) and the dark N trap of described high pressure (105) form the ESD current drain path of NPN two interdigital structures, with secondary breakdown current, the reduction conducting resistance that improves device under the reverse impulse effect.
2. the high pressure esd protection device of the high maintenance voltage that triggers of vertical NPN as claimed in claim 1; it is characterized in that: utilize a described N sinking trap (104), described the 2nd N sinking trap (106), described N buried regions (102), described P extension (103) and the dark N trap of described high pressure (105); consisted of an esd protection device with the vertical NPN structure of longer guiding path; with RESURF, improve the high-voltage resistance capability of device and keep voltage.
3. the high pressure esd protection device of the high maintenance voltage that triggers of vertical NPN as claimed in claim 1; it is characterized in that: example device of the present invention adopts the BCD high-pressure process of 0.35 μ m; the thickness of described P type extension (103) is 8～10 μ m; both can prevent thus that depletion region and the depletion region between described P extension (103) and the described N buried regions (102) between the dark N trap of described high pressure (105) and the described P extension (103) were overlapping; be that the base break-through does not occur the NPN structure, can guarantee that again device comes interim in time unlatching at esd pulse.
4. the high pressure esd protection device of the high maintenance voltage that triggers of vertical NPN as claimed in claim 1; it is characterized in that: can be by elongating the length of described polysilicon gate (115); increase is by the base width of vertical NPN structure of the dark N trap of described high pressure (105), described P extension (103) and described N buried regions (102) formation, to improve the voltage of keeping of device.
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Cited By (5)
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| CN104600068A (en) * | 2015-01-20 | 2015-05-06 | 湖州迈康电子科技有限公司 | High-voltage bidirectional ESD protective device based on longitudinal NPN structure |
| CN103617996B (en) * | 2013-12-09 | 2016-03-02 | 江南大学 | A kind of ESD protective device with the annular V DMOS structure of high maintenance electric current |
| CN108352384A (en) * | 2015-10-01 | 2018-07-31 | 德州仪器公司 | High voltage dipolar configuration for improving pulse width scalability |
| CN111430306A (en) * | 2020-03-31 | 2020-07-17 | 中国电子科技集团公司第五十八研究所 | GGNMOS device preparation process for thin epitaxial process ESD protection and GGNMOS device |
| CN113257889A (en) * | 2020-04-16 | 2021-08-13 | 成都芯源系统有限公司 | LDMOS device and method for forming LDMOS device |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103617996B (en) * | 2013-12-09 | 2016-03-02 | 江南大学 | A kind of ESD protective device with the annular V DMOS structure of high maintenance electric current |
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| CN111430306A (en) * | 2020-03-31 | 2020-07-17 | 中国电子科技集团公司第五十八研究所 | GGNMOS device preparation process for thin epitaxial process ESD protection and GGNMOS device |
| CN111430306B (en) * | 2020-03-31 | 2022-08-12 | 中国电子科技集团公司第五十八研究所 | GGNMOS device preparation process for thin epitaxial process ESD protection and GGNMOS device |
| CN113257889A (en) * | 2020-04-16 | 2021-08-13 | 成都芯源系统有限公司 | LDMOS device and method for forming LDMOS device |
| CN113257889B (en) * | 2020-04-16 | 2022-10-21 | 成都芯源系统有限公司 | LDMOS device and method for forming LDMOS device |
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| CN102983136B (en) | 2014-12-24 |
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