CN111430306B - GGNMOS device preparation process for thin epitaxial process ESD protection and GGNMOS device - Google Patents
GGNMOS device preparation process for thin epitaxial process ESD protection and GGNMOS device Download PDFInfo
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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Abstract
The invention discloses a GGNMOS device and a preparation process thereof for thin epitaxial process ESD protection, and belongs to the technical field of electrostatic discharge protection of very large scale integrated circuits. According to the invention, the trigger voltage of the GGNMOS device is effectively reduced through P-type ESD injection, and the body resistance value of the GGNMOS device is improved by introducing the deep N well layer, so that the problem of uneven triggering of the GGNMOS device in a thin epitaxial process is solved; meanwhile, the deep N well layer, the P well region and the N + heavily doped region form a longitudinal NPN tube, and a current discharge channel is increased. The GGNMOS device preparation method is compatible with the existing thin epitaxy process, and improves the ESD resistance of the circuit with the minimum cost.
Description
Technical Field
The invention relates to the technical field of electrostatic discharge protection of a super-large-scale integrated circuit, in particular to a GGNMOS device and a preparation process thereof for thin epitaxial process ESD protection.
Background
An Electro-Static discharge (ESD) protection device is the most core minimum unit in a chip ESD protection design, and whether a single device is successfully designed directly relates to the smooth completion of the whole chip protection design. When an ESD event occurs, the ESD protection device for protection is subjected to a large current and a high voltage, and the operation mode of the semiconductor device is greatly changed under the conditions of the large current and the high voltage. The ESD event is a large current discharge event in a short time, so it is necessary to study the operation mechanism of the ESD single device under the condition. Conventional ESD protection devices include diodes, BJT transistors, Grounded Gate NMOS (GGNMOS), silicon controlled SCR, and other types, and different ESD protection devices can be selected according to application conditions, and in a CMOS process, a GGNMOS device is generally used as an ESD protection device.
The source electrode, the gate electrode, the body electrode and the ground are in short circuit on the basis of a common NMOS, the protection direction of the source electrode, the gate electrode, the body electrode and the ground is from drain to source, when the drain end bears ESD stress, the NMOS is in a closed state due to grounding of the gate, and the reverse PN junction of the drain region and the P well bears most ESD voltage. When the reverse voltage born by the P-well reaches the reverse breakdown voltage of the PN junction, a small amount of current passes through the P-well, and when the potential of the body potential of the P-well is 0.7V greater than the forward starting voltage of the PN junction, the P-well is conducted with the source electrode, so that the whole NMOS tube is conducted, the drain-source voltage is clamped in a certain voltage range, and the ESD current can enter the GND through the conducted NMOS, so that the purpose of protecting an internal circuit is achieved.
As the scale of circuit integration increases, the circuit resistance to single event latch-up (SEL) problems becomes more severe. The P-epitaxial layer with a certain thickness and low doping concentration is epitaxially grown on the P-type silicon single crystal with high doping concentration P +, so that the lateral resistance of the parasitic NPN can be reduced, the parasitic thyristor effect in the CMOS integrated circuit is inhibited, and the single-particle latch-up resistance is improved.
The thin epitaxial material is adopted, so that the single event latch-up (SEL) resistance of the circuit can be effectively improved, but the substrate resistance is reduced, so that the triggering of all the interdigital of the GGNMOS is not uniform, the ESD protection capability of the conventional GGNMOS device with the ESD protection structure is reduced, and the chip prepared on the thin epitaxial material cannot meet the ESD index requirement.
Disclosure of Invention
The invention aims to provide a GGNMOS device preparation process for thin epitaxial process ESD protection and a GGNMOS device, and aims to solve the problem that a chip prepared on the existing thin epitaxial layer material cannot meet the ESD index requirement.
In order to solve the technical problem, the invention provides a preparation process of a GGNMOS device for thin epitaxial process ESD protection, which comprises the following steps:
step 1, preparing a P-type epitaxial material sheet comprising a P-type silicon substrate and a P-epitaxial layer, injecting phosphorus ions, and annealing to form a deep N well layer;
step 4, removing the residual photoresist I, filling the STI groove, removing the hard mask layer and the thin oxidation buffer layer, and forming an STI isolation layer;
step 5, coating a second photoresist on the surface, performing P well region photoetching, and injecting boron ions to form a P well region;
step 6, removing the residual second photoresist, recoating the third photoresist on the surface, carrying out N well region photoetching, and injecting phosphorus ions to form an N well region;
and 11, removing the residual photoresist seven, recoating the photoresist eight on the surface, carrying out photoetching on a P + region, an N + region and a grid electrode, depositing metal, removing the surface metal and the residual photoresist eight, and finishing the preparation of a metal electrode region.
Optionally, the thickness of the P-epitaxial layer is 1.8-3.2 μm.
Optionally, the thickness of the deep N well layer is 0.8-1.5 μm.
Optionally, the doping concentration of the deep N-well layer is greater than the doping concentration of the N-well region.
Optionally, the doping concentration of the N + heavily doped region is greater than the doping concentration of the N-well region.
Optionally, the doping concentration of the P + heavily doped region is greater than that of the P-well region.
The invention also provides a GGNMOS device for thin epitaxial process ESD protection, which comprises a P-type silicon substrate and a P-epitaxial layer on the surface of the P-type silicon substrate,
the device also comprises a deep N well layer, a PED layer, a P well region, an N + heavily doped region, a P + heavily doped region, an STI isolation layer and a grid region; wherein the content of the first and second substances,
the deep N well layer is positioned in the P-epitaxial layer, and meanwhile, the deep N well layer, the P well region and the N + heavily doped region form a longitudinal NPN tube, so that a current discharge channel is increased;
the PED layer is positioned below the N + heavily doped region and is in contact with the N + heavily doped region;
and the concentration of the P-type impurities is improved below the N + heavily doped region through P-type ESD injection.
Optionally, the doping concentration of the P-type ESD implanted region is greater than the doping concentration of the P-well region.
The invention provides a GGNMOS device preparation process for thin epitaxial process ESD protection and a GGNMOS device, wherein the trigger voltage of the GGNMOS device is effectively reduced by P-type ESD injection, and the problem of uneven triggering of the GGNMOS device in the thin epitaxial process is solved by introducing a deep N-well layer to improve the body resistance value of the GGNMOS device; meanwhile, the deep N well layer, the P well region and the N + heavily doped region form a longitudinal NPN tube, and a current discharge channel is increased. The GGNMOS device preparation method is compatible with the existing thin epitaxy process, and improves the ESD resistance of the circuit with the minimum cost.
Drawings
FIG. 1 is a schematic diagram of the implantation of phosphorus ions in a P-epitaxial layer to form a deep N-well layer;
FIG. 2 is a schematic diagram of the formation of a thin oxide buffer layer and a hard mask layer on a P-epitaxial layer;
FIG. 3 is a schematic diagram of STI shallow trench isolation to form an active region;
FIG. 4 is a schematic diagram of forming an STI isolation layer;
FIG. 5 is a schematic view of a P-well region formed by implanting boron ions into a P-epitaxial layer;
FIG. 6 is a schematic diagram of implanting phosphorus ions to form an N-well region;
FIG. 7 is a schematic diagram of forming a gate region;
FIG. 8 is a schematic diagram of implanting boron ions to form P + heavily doped regions;
FIG. 9 is a schematic diagram of forming an N + heavily doped region;
fig. 10 is a schematic diagram of forming a PED layer;
fig. 11 is a schematic view of the completion of the preparation of a metal electrode region;
fig. 12 is a schematic diagram of a GGNMOS device for thin epitaxial process ESD protection provided by the present invention.
Detailed Description
The following provides a further detailed description of the GGNMOS device and its manufacturing process for thin epitaxial ESD protection, which is provided by the present invention, with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a GGNMOS device preparation process for thin epitaxial process ESD protection, which comprises the following steps:
preparing a P-type epitaxial material sheet, wherein the P-type epitaxial material sheet comprises a P-type silicon substrate 1 and a P-epitaxial layer 2, and the thickness of the P-epitaxial layer 2 is 1.8-3.2 mu m; implanting phosphorus ions into the P-epitaxial layer 2 by a high-energy ion implanter, and annealing to form a deep N well layer 3, as shown in FIG. 1; wherein the thickness of the deep N well layer 3 is 0.8-1.5 μm;
performing primary oxidation on the P-epitaxial layer 2 to form a thin oxide buffer layer 4, and then depositing silicon nitride to form a hard mask layer 5, as shown in FIG. 2;
as shown in fig. 3, coating a first photoresist 61 on the surface of the hard mask layer 5, performing active area lithography, and completing STI shallow trench isolation after etching the first photoresist 61, the hard mask layer 5, the thin oxide buffer layer 4 and the P-epitaxial layer 2 to form an active area;
removing the residual photoresist 61, filling the STI shallow trench by High Density Plasma deposition (HDP), and removing the hard mask layer 5 and the thin oxide buffer layer 4 by Chemical Mechanical Polishing (CMP) planarization to form an STI isolation layer 7, as shown in fig. 4;
coating a second photoresist 62 on the surface of the P-epitaxial layer 2, performing P well region photoetching, and injecting boron ions to form a P well region 8, as shown in FIG. 5;
removing the residual second photoresist 62, recoating the third photoresist 63 on the surface, performing N well region lithography, and implanting phosphorus ions to form an N well region 9, as shown in FIG. 6; the doping concentration of the N-well region 9 is less than the doping concentration of the deep N-well layer 3;
referring to fig. 7, the remaining photoresist three 63 is removed, a poly gate is deposited, the surface is coated with photoresist four 64 again, and photolithography is performed to etch away the poly outside the gate, thereby forming a gate region 10;
removing the remaining photoresist IV 64, recoating the photoresist V65 on the surface, performing P + region lithography, and implanting boron ions to form a P + heavily doped region 11, as shown in FIG. 8; the doping concentration of the P + heavily doped region 11 is greater than that of the P-well region 8;
removing the residual photoresist five 65, recoating the photoresist six 66 on the surface, performing N + region lithography, and implanting phosphorus ions to form an N + heavily doped region 12, as shown in fig. 9; the doping concentration of the N + heavily doped region 12 is greater than that of the N well region 9;
removing the residual photoresist six 66, recoating the photoresist seven 67 on the surface, performing PED region photoetching, and implanting boron ions to form a PED layer 13, as shown in FIG. 10;
removing the residual photoresist seven 67, recoating the photoresist eight on the surface (not shown in the figure), performing P + region, N + region and gate photoetching, depositing metal, flattening by chemical mechanical polishing, removing the surface metal and the residual photoresist eight, and completing the preparation of the metal electrode region 14, as shown in fig. 11.
Example two
The invention provides a GGNMOS device for thin epitaxial process ESD protection, the structure of which is shown in figure 12, comprising a P-type silicon substrate and a P-epitaxial layer on the surface of the P-type silicon substrate,
the device also comprises a deep N well layer, a PED layer, a P well region, an N + heavily doped region, a P + heavily doped region, an STI isolation layer and a grid region; wherein the content of the first and second substances,
the deep N well layer is positioned in the P-epitaxial layer, so that heavy doping ions in the P-type silicon substrate are effectively prevented from diffusing into the P well region, the problem of reduction of the resistance of the P well body is solved, and meanwhile, the deep N well layer, the P well region and the N + heavy doping region form a longitudinal NPN tube to increase a current discharge channel;
the PED layer is positioned below the N + heavily doped region and is in contact with the N + heavily doped region;
the concentration of P-type impurities below the N + heavily doped region is increased through P-type ESD injection, and as the reverse breakdown voltage of the N + heavily doped region and the PED layer is smaller than that of the N + heavily doped region and the P-well region, the trigger voltage of the GGNMOS device can be effectively reduced, and the improvement of the ESD resistance of the circuit in the thin epitaxial process is realized; the doping concentration of the P-type ESD injection region is greater than that of the P-well region.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (6)
1. A GGNMOS device preparation process for thin epitaxial process ESD protection is characterized by comprising the following steps:
step 1, preparing a P-type epitaxial material sheet comprising a P-type silicon substrate and a P-epitaxial layer, injecting phosphorus ions, and annealing to form a deep N well layer;
step 2, carrying out primary oxidation on the P-epitaxial layer to form a thin oxidation buffer layer, and then depositing silicon nitride to form a hard mask layer;
step 3, coating a first photoresist on the surface, performing active area photoetching, and etching to complete STI shallow trench isolation to form an active area;
step 4, removing the residual photoresist I, filling the STI groove, removing the hard mask layer and the thin oxidation buffer layer, and forming an STI isolation layer;
step 5, coating a second photoresist on the surface, performing P-well region photoetching, and injecting boron ions to form a P-well region;
step 6, removing the residual second photoresist, recoating the third photoresist on the surface, carrying out N well region photoetching, and injecting phosphorus ions to form an N well region;
step 7, removing the residual photoresist III, depositing a polycrystalline grid, coating the photoresist IV on the surface again, carrying out photoetching, and etching off the part of the polycrystalline outside the grid to form a grid region;
step 8, removing the residual photoresist IV, recoating the photoresist V on the surface, carrying out P + region photoetching, and injecting boron ions to form a P + heavily doped region;
step 9, removing the residual photoresist V, recoating the photoresist VI on the surface, carrying out N + region photoetching, and injecting phosphorus ions to form an N + heavily doped region;
step 10, removing the residual photoresist six, recoating the photoresist seven on the surface, carrying out PED area photoetching, and injecting boron ions to form a PED layer;
and 11, removing the residual photoresist seven, recoating the photoresist eight on the surface, carrying out photoetching on a P + region, an N + region and a grid electrode, depositing metal, removing the surface metal and the residual photoresist eight, and finishing the preparation of a metal electrode region.
2. The process for preparing a GGNMOS device for thin epitaxial process ESD protection according to claim 1, wherein the thickness of the P-epitaxial layer is 1.8-3.2 μm.
3. The GGNMOS device preparation process for thin epitaxial process ESD protection according to claim 1, wherein the thickness of the deep N-well layer is 0.8-1.5 μm.
4. The GGNMOS device fabrication process for thin epitaxial process ESD protection of claim 1, wherein the deep N-well layer has a doping concentration greater than the doping concentration of the N-well region.
5. The GGNMOS device fabrication process for thin epitaxial process ESD protection of claim 1, wherein the N + heavily doped region has a doping concentration greater than that of the N-well region.
6. The GGNMOS device fabrication process for thin epitaxial process ESD protection of claim 1, wherein the P + heavily doped region has a doping concentration greater than that of the P-well region.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102983136A (en) * | 2012-12-18 | 2013-03-20 | 江南大学 | Longitudinal NPN triggered high-voltage ESD protective device with high maintaining voltage |
| CN104269400A (en) * | 2014-08-30 | 2015-01-07 | 电子科技大学 | Novel gate-grounded NMOS structure ESD protective device and manufacturing method thereof |
| CN106876369A (en) * | 2017-03-01 | 2017-06-20 | 中国电子科技集团公司第五十八研究所 | For the silicon controlled rectifier (SCR) and preparation method of thin epitaxy technique electrostatic discharge (ESD) protection |
| CN108039390A (en) * | 2017-11-22 | 2018-05-15 | 天津大学 | Contactless protection ring single-photon avalanche diode and preparation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102983136A (en) * | 2012-12-18 | 2013-03-20 | 江南大学 | Longitudinal NPN triggered high-voltage ESD protective device with high maintaining voltage |
| CN104269400A (en) * | 2014-08-30 | 2015-01-07 | 电子科技大学 | Novel gate-grounded NMOS structure ESD protective device and manufacturing method thereof |
| CN106876369A (en) * | 2017-03-01 | 2017-06-20 | 中国电子科技集团公司第五十八研究所 | For the silicon controlled rectifier (SCR) and preparation method of thin epitaxy technique electrostatic discharge (ESD) protection |
| CN108039390A (en) * | 2017-11-22 | 2018-05-15 | 天津大学 | Contactless protection ring single-photon avalanche diode and preparation method |
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