JP2617226B2 - Method for manufacturing CMOS device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to CMOS integrated circuit technology.

The problem identified with both short-channel and high-voltage MOS technology is the impact ionization phenomenon at the boundary between the drain and the channel (impact ionization).
Is what happens. This usually results in the injection of photocarriers into the gate oxide when a high peak electric field is created at this boundary (shifting to the device threshold according to the operating process of the device) and lowering the avalanche breakdown voltage and lowering the parasitic capacitance. This is for increasing the substrate current. The creation of an electric field by the gate increases the likelihood of electron avalanche and flowing into the boundaries of the drain. This problem is especially acute where the drain boundary is usually very close to the edge of the gate where the gate field is highest. All these effects are especially true for N-channel devices in CMOS technology when using high voltages (eg, 5 volts and 1 micron channel length) with small geometric dimensions (eg, 20 volts and 4 micron channel length). It becomes a problem when making.

In digital CMOS circuits, the N-channel and P-channel devices carry parasitic substrate currents due to impact ionization during the transient period to switch when both are turned on. This causes a "substrate bounce" at the floating node, which may cause a latch or bias removal or discharge. (This is the reason for using the epi layer on the P + substrate.) In analog circuits, the N-channel source follower configuration is biased so that significant parasitic substrate currents flow constantly. Possibilities are even more serious. Perhaps the most significant effect of all the problems is related to the implantation of hot carriers into the gate oxide, which can change the threshold over time and cause a reduction in transconductance. Of course, all of these problems are even more serious when the gate oxide is designed so that the supply voltage is kept constant.

Since the coefficient of impact ionization is almost proportional to the amount of electrons larger than holes, the N-channel device has a limit in realizing a short-channel device using a high supply voltage. The present invention is a "hot carrier resistant" CMOS
Provide CMOS technology to make N-channel device in process. In these techniques, a lightly doped N region is formed between the channel and the N + source / drain region. This structure allows the high electric field in the drain pinch-off region to extend into the N-extension region, thereby increasing the drain breakdown voltage and reducing impact ionization, and thus reducing the emission of high energy expending electrons. . These advantageous configurations are obtained by performing a limb blanket implant at a low level dose and do not require additional masking steps.

Considerable development efforts have been devoted to problems with such properties in the prior art of NMOS devices. For example, U.S. Pat.
No. 0 indicates the use of a third wall oxide of the gate to reduce the overlap between the gate and the drain or to protrude from under the gate / drain. Ogura et al. (1980) IEEE Journal of Solid State Circuits, SC-15, pp. 424 et seq., "Lowly Doped Drain / Source (LD
The article "D) Insulated Gate Field Effect Transistor" and all references cited therein disclose a configuration having a lightly doped drain region and explain the advantages of this configuration. Another technique specifically describes the process of forming a lightly doped drain region formed by performing a reach-through implant with sidewall oxide partially interrupting the implant.

There are a number of special problems associated with including a lightly doped drain configuration in a CMOS process, and it is an object of the present invention to solve these special problems.

In particular, it is an object of the present invention to provide a method for forming a lightly doped drain extension region (called LDD region) in a CMOS process.

A second object of the present invention is to provide a method for forming an LDD region in a CMOS process without requiring an additional mask adding process.

As described above, a particular problem with CMOS technology is that the N-channel device alone has an LDD region at the boundary of the drain because the impact ionization coefficient for holes is smaller than the coefficient of electrons as described above. It is necessary to make

Therefore, an object of the present invention is to provide a method of manufacturing a CMOS device in which an LDD region is formed only in an N-channel device without forming an LDD region in a P-channel device.

It is another object of the present invention to form a lightly doped drain region only in N-channel devices except P-channel devices without the need for an additional masking step.
A method for manufacturing a CMOS device is provided.

Another problem with using a lightly doped drain region is that it degrades device characteristics in various ways. In particular, the series resistance of the device can be significantly increased and the transconductance of the device can be reduced. Both of these relate to the length of the LDD region, that is, it is desirable that the LDD extension region is not made too long longer than necessary in consideration of the operating voltage of the device. In particular, if the LDD region is not self-aligned with the gate and source / drain regions, it must have at least two alignment tolerance widths. Otherwise, normal alignment errors will create some devices that do not have an LDD area. Such a device does not operate and thus reduces the yield. Therefore, it is highly desirable that the lightly doped drain extension region be formed self-aligned with the gate and also with the source / drain region.

It is an object of the present invention to provide a CMOS process technology in which a lightly doped drain extension region is self-aligned to both gate and source / drain regions.

It is another object of the present invention that the lowly doped drain extension region is self-aligned to both the gate region and the source / drain region only in an N-channel device without any additional masking steps, The purpose of the present invention is to provide a CMOS technology which does not have such a function in the P-channel device.

The above problems are particularly acute in high voltage devices. High voltage CMOS devices are desirable in a number of applications, including consumer devices, control devices, and devices used in very noisy electrical environments. However, it is very difficult to increase the geometric dimensions of the high-voltage CMOS process to a geometric level suitable for LSI level integration. further,
Unless the multiplied cost per chip manufactured for yield shows an unacceptably low total cost value, chips that are technically feasible can also be useless long, so they are used in high-voltage CMOS processes. The number of masks to be performed must be strictly controlled. In other words, the feature that must be observed for high-voltage CMOS applications is that the number of masks is small,
This is a combination of small geometric dimensions.

It is therefore an object of the present invention to provide a high voltage CMOS technology with a small number of masks and relatively small geometric dimensions.

The length of the LDD region can be particularly problematic in high voltage CMOS processes. This is because in very high voltage application processes, low dopant concentrations are typically used to form the LDD regions so that the necessary step doping distribution is created at the boundary between the channel and the LDD regions. The use of such a low dopant concentration inevitably results in a very high resistance inside the LDD region itself, and therefore the series resistance of the device increases significantly as the length of the LDD region increases. . On the other hand, it is necessary to keep the LDD region in the high voltage device from becoming too short, since the desired skewed dopant distribution will result in a lack of tips. That is,
Increasing the effective overall width of the source and drain side LDD regions increases the series resistance in the device, but this value is the required resistance even if the width of the LDD regions on both sides is simply minimized. Due to much higher values, the use of non-self-aligned LDD regions is most suitable for high voltage processes.

The present invention provides a CMO having an N-channel transistor in an LDD region using a side wall spacer provided on a gate electrode.
The present invention relates to an invention for securing a threshold voltage of a P-channel transistor, which is particularly problematic in a method of manufacturing S.
Therefore, the gist of the present invention is to implant a P-type impurity over the entire surface.

Description of the Preferred Embodiment The present invention describes a high voltage CMOS process that is optimal for devices operating at 18 volts with a channel length of 4 microns. However, the process of the present invention is relatively scalable to suit high and low operating voltages. That is, the high voltage CMOS process, which is the preferred embodiment of the present invention, is operated at 10 volts and the channel can be easily scaled to a 2 micron process or a 14 volt 3 micron process as described below. is there. Further, the exact sequence of process steps in which the N-type and P-type source / drain regions and LDD extension regions are formed can be inserted into other high voltage CMOS processes. That is, it is preferable to use an epitaxial twin-tub process with a shallow highly doped tank, but this feature is not absolutely necessary.

A series of process steps for forming source and drain regions and LDD extension regions according to the present invention will be described first, followed by a general high voltage CMOS process flow envisioned as a preferred embodiment described herein. explain.

As a step leading to FIG. 1, a P- type epi layer 2 is formed on a P + type substrate 1, and a P type well 4 and an N type tank 5 are selectively diffused in a moat surrounded by a thick field oxide 3. Formed by A gate oxide layer 6 and a polysilicon gate layer 7 are formed by a resist 8 in the moat portion.

In the present embodiment, the flow of the process of the present invention up to the pattern formation of the polysilicon gate layer 6 is described in U.S. Pat. No. 344,588 filed on Feb. 1, 1982 (Japanese Patent Application Laid-Open No. 58-169928, This is essentially the same as that described herein for reference).

After the polysilicon gate layer 6 is patterned,
A thin gate oxide (not shown) exposed as a lightly doped drain implant (LDD implant) is performed as a reach-through implant through the gate oxide,
Preferably, it is not removed. (The reason why the gate oxide is not removed is to maintain the state when the gate oxide was formed.) However, this is not so important here.

After patterning the polysilicon, the photoresist layer on the poly layer is left in place, and the exposed gate oxide is etched away. Low level phosphorous or arsenic implants, for example, at a concentration of 8 × 12 ¹² / cm ² at 60 KeV
Is performed using This implant is self-aligned to the end of the poly gate as shown in FIG.

Since phosphorus has a higher diffusivity and shows a doping concentration distribution that changes with a gentle gradient at the junction of the channel / LDD region, it is considered that phosphorus is slightly preferable to arsenic for low-level doped drain implantation. Have been.

The use of an LDD implant containing both arsenic and phosphorus is another embodiment of the present invention. This embodiment also shows a doping level change which shows an even gentler slope at the LDD / channel boundary. That is, since phosphorus has a higher diffusivity than arsenic, the region containing only phosphorus is formed to extend slightly outside the periphery of the region containing both phosphorus and arsenic. Again, this causes the region where the potential difference exists to expand and the peak electric field to decrease.

In general, the depth and amount of the LDD implantation are set so that the implantation region can be formed at a position somewhat lower than the depth of the source region in the LDD region and at a dopant concentration lower than the dopant concentration generally used for forming the source / drain. Selected. In this example, using a 4 micron device used for example at 18 volt operation, the dopant concentration in the lightly doped drain region is approximately 1 × 10 ¹⁷ / cm ³
And the depth of the lightly doped drain region is approximately 0.15-0.2 microns. A deep LDD region can also be used very well (unless the depth of the LDD region becomes deeper than the depth of the source / drain region). It becomes difficult to control diffusion.

Structurally lightly doped drain regions perform these functions essentially. First, the change in dopant concentration at the boundary between the channel and the LDD region must be gentle. As described above, when the distribution of doping changes gradually, the potential also changes little by little, so that the peak electric field can be reduced. Second, the heavily doped drain is physically removed from the end of the gate, so that the electric field due to the gate voltage appearing at the end of the drain is much lower. That is, the transient up to the heavily doped (typically 1 × 10 ¹⁹ / cm ³ ) drain region is the largest gate induced field (at the edge of the gate) when the LDD region is not used. The physical separation of the LDD and the drain boundary between the high and low doping sections is very effective in that it is physically very close to the location where the LDD is formed. Third, doping is at a low level so that the LDD region itself typically creates a slight IR voltage ramp between the channel and the drain. This drop in voltage reduces the performance of the device, but slightly reduces the voltage drop that occurs at the boundary between the LDD and the channel (eg, approximately 1
Volts) to reduce. Fourth, if the source and the drain are physically separated from each other by a wide distance, the punch-through voltage slightly increases. Fifth, the LDD region tends to reduce the capacitive load induced by the gate and increase operating speed.

If a double implant is used, the respective energies are preferably selected such that the implants are performed to the same distance for the phosphorus and arsenic implants. In this case, the total dopant concentration in the LDD region can be selected to be within or outside 1 × 10 ¹⁸ / cm ³ . However, as described, the resistance (dopant concentration) of the LDD region can be varied to adapt the present invention to particular circuit constraints. That is, LDD implantation at a low dose can produce a smoother gradient dopant distribution at the LDD / channel boundary, thus producing a lower peak electric field at this boundary, but at the expense of transconductance and series resistance. The value goes down.

When double injection (phosphorus and arsenic) is used, these effects are more preferably exhibited as described above.
Undesired side effects in the LDD region can be reduced. That is, if phosphorus and arsenic implants are used to form the LDD region, a slightly higher overall dopant concentration is used in the LDD region than the level used when performing only phosphorus implants. , LDD with high resistance
The area can be minimized, so that the series resistance can be reduced.

After a blanket (global) LDD implant has been performed as in FIG. 1, a thin oxide layer is deposited generally isotropically, for example by plasma or low pressure chemical vapor deposition. In the preferred embodiment, a 300 nm thick oxide layer is deposited, but this thickness need not be critical.
However, it is desirable that the thickness of the deposited oxide be strictly controlled because it is related to the width of the sidewall oxide formed as described below. After the oxide 10 is formed at a predetermined position, a mask 11 for performing P + source / drain implantation is provided on the P well 4. The jetted isotropic deposition oxide 10 is removed by etching, and then, for example, at 67 KeV, as shown in FIG.
P + source / drain implant is performed on N- tank 5 using boron difluoride implantation step at a concentration of × 10 / cm ^2.
(See source / drain 24 in FIG. 3) The photoresist 11 used to mask the P-type source / drain implanted regions is now removed and the P-well 4 is removed.
An isotropic deposition oxide 10 covering the top NMOS device area.
Is partially etched away, leaving the narrow portion 20 on the side wall of the gate. Further, a mask layer for N-type implantation
21 is formed. Not all of these steps need to be performed strictly, that is, the mask forming step for N + implantation can be moved before the oxide etching is performed. However, the parameters for oxide etching are important. (See FIG. 3.) Since the polysilicon gate layer 7 needs to be patterned leaving a substantially vertical sidewall, a highly anisotropic polysilicon etching method must be used. Many such etching methods are known in the art. For example, polysilicon is etched in Freon-11.

A series of vertical sidewalls along the polysilicon gate line means that some oxide 20 remains on the gate sidewalls after the oxide has been removed from the whole. . That is, if the 300 nm oxide was removed by etching after the 300 nm oxide was isotropically deposited, the gate and gate insulator were added with approximately the same width as the initially formed oxide thickness. An oxide deposit of the same height as the thickness will still remain on the gate wall. Preferably, the walls are etched slightly more than required for removal of the insulator layer, for example with 50% overetching. As a result, the remaining oxides that are not desired to be left, such as oxides on the field oxide, are not left, and a certain amount of the sidewall oxide 20 is still left on the gate wall. (A typical LOCOS process field oxide is
It should be noted that the process is considerably inferior in forming the oxide vertically, as compared with the process shown here, which has been integrated to reduce the size. Naturally, the present invention can be applied to a wide variety of insulating layer formations, and is not limited to application to the LOCOS process.

If the isotropic deposition oxide 10 is over-etched beyond a desired amount, the highest portions of the sidewall oxide 20 are removed and their thickness is reduced slightly. However, in this preferred embodiment of the present invention, precise control of the height of the sidewall oxide 20 is appropriate because the reach-through implant through the sidewall oxide 20 is not used. Not less than 4 times the thickness of the sheet). Furthermore, as is well known in the art, the width of the sidewalls is only slightly affected by overetching, so that it is necessary to precisely control the etching period or the thickness of the initially formed isotropic deposition oxide. Due to the absence, the width of the LDD region changes only slightly.

Therefore, the source / drain implantation of arsenic is performed last, for example, at a value of 1 × 10 ¹⁶ / cm ^{2 at} 100 Kev.
22 and an LDD region 23 are formed.

The high voltage CMOS process in which the preferred embodiment of the present invention is used is described in detail below. The formation of the LDD region according to the present invention can be used in other high-voltage CMOS processes, but according to the present invention.
The combination of the LDD forming process and the high voltage process described below can be applied very advantageously. In particular, the invention can further increase the density of the device at the same operating voltage and at the same density.

Note that by using the LDD extension area, the channel length can be shortened while other operational parameters remain unchanged. That is, parameters related to P + injection for providing an interval at the end of the tank 5 are not affected by the diffusion of the LDD extension region.

The present invention will be described in connection with a process that is primarily operating at 18 volts in its embodiment, and thus is optimal for devices requiring breakdown voltages and threshold voltages of 20 volts or more. In this preferred embodiment, a 4 micron design method is used. However, the invention can be scaled proportionally to operate at, for example, 15 volts, have a geometry of 3 microns, and have lower geometries with lower operating voltages.

The present invention preferably uses a structure in which a P- layer is provided on a P + substrate (P-on P + structure). In the P-epitaxial layer, both a P-type well and an N-type tank are formed by injection.

According to the present invention, a double poly layer process can be performed using a positive resist with a nine-step mask and using a negative resist (since a two-step mask is used to form an electrode layer) with a ten-step mask. Become. Algorithmically creating a mask can reduce the number of patterning layers to eight layers, make contact to tanks made using N + source / drain implants, and use P + source / drain implants. A contact can be made to the P-well that has been made. The N + and P + S / D masks are both created from the N + / P + mask and the tank mask. The single poly layer process according to the present invention uses only eight masks, and using source / drain counter doping requires only a total of seven masks. About 10
^The starting material is a P + substrate doped to about 10 ¹⁸ / cm ^3, on which a 16 micron thick P-type epitaxial layer doped to ¹⁵ / cm ³ is formed. Evaluation of the anti-ratch performance using the process of the present invention has shown that the use of a 16 micron epilayer can provide a suitable latch protection function for internal circuit 15 volt operation. For an I / O circuit, the protection function can be further enhanced by adding a guard ring formed by the N + source / drain injection layer implantation step. This requires the use of a metal jumper in the I / O circuit to allow the polysilicon lines to cross between the P and N channel devices, but only uses 1% of the chip size and thus takes up space. The above drawbacks are very slight.
Only in I / O circuits that are susceptible to externally generated high-voltage transients, forming a guard ring configuration can severely complicate the process or significantly reduce the efficiency of the area. Instead, high durability against high voltage transients can be achieved.

Two polysilicon layers and a regrown gate oxide are used. The first polysilicon layer is doped by ion implantation, thus forming a lower electrode of the capacitive element and a transistor having a normal threshold. in addition,
A resistance element is formed in the first polysilicon layer. In the second polysilicon layer, normal gates and interconnects are formed. This layer is preferably silicided by a mixed deposition of titanium and silicon, effectively reducing the sheet resistance of the second poly layer to approximately 5 ohms / square. This avoids a difficult compromise between resistance and other required etching characteristics. When using POCl ₃ to dope polysilicon below about 50Ω / □, a large amount of polysilicon is removed as a result of the plasma etching selectively proceeding along the grain boundaries. Polysilicon having a sheet resistance of 50 Ω / □ is inferior for designing a circuit, but the poly layer portion has a high sheet resistance due to P-type source / drain implantation. By changing the second poly layer to silicide, the problem relating to sheet resistance can be eliminated and the process is not substantially complicated by depositing titanium and silicon simultaneously.

The final P channel (N tank) surface concentration is about 10
¹⁶ / cm ³ and the tank depth is about 4 microns.
For a 70 nm thick gate oxide, the resulting substrate effect is about 1.4 V ^1/2 and the Kp is 5 μA / V ² .
In most circuit designs, the N-tank can always be connected to the source, so high P-channel body effect is not a problem.

The final N-channel (P-well) surface concentration is
Approximately 2 × 10 ¹⁵ / cm ³ resulting in a substrate effect of 0.4 V ^1/2
Kp indicates 16 μA / V ² .

V _TN (NMOS threshold voltage) and V _TP (PMOS threshold voltage) simultaneously
To set in and out of 1.5 volts, a blanket boron implant is used. This blanket boron is used to set only one voltage level so that the threshold voltages of the PMOS and the NMOS are symmetrical, and to set the values of ± 1.5 volts appropriately by specifying the process parameters. Infusion is used.

Both the PMOS and NMOS field thresholds are approximately 20
Set to more than bolt. This can be achieved by making a 1.1 micron field oxide and performing a blanket boron field threshold adjustment implant. The first field threshold in the PMOS region is higher than required, and the dose of the threshold adjustment implant is such that the field threshold in the PMOS region is
It is selected to be equal to the threshold value of the field portion in the NMOS region. With the doping levels described above, the field threshold levels are set to equal values near 22 to 25 volts. Therefore, the step of adding a mask is not required for adjusting the field portion threshold.

In the PMOS source / drain, boron is implanted and the NMOS
Arsenic / phosphorus implantation is performed on the source / drain to approximately 0.5
A junction with a junction breakdown voltage of 23 volts is formed at a depth of a micron.

 The set of masks in the preferred embodiment is as follows.

The sample process of the high voltage CMOS process is described below. The starting material is a P + substrate doped to about 10 ¹⁸ / cm ³ with a 16 micron epitaxial P-type layer doped to about 10 ¹⁵ / cm ³ . The thickness of the epitaxial layer is governed by the following general factors. That is, first of all, as the layer becomes thicker, the efficiency of suppressing the latch-up decreases. Second, N tank is V _DD (+ 15V)
The minimum value of the epi layer thickness is determined by the supply voltage so that the depletion region extending from the tank when the P-type substrate (epi layer) is at 0 volt does not reach the P + substrate.
This minimizes the depletion layer that extends into the tank, thus increasing the P + punch-through voltage, and lowering the voltage on the P + substrate causes breakdown due to the high electric field, but does not diminish this voltage. You can do so. Further, as the layers become thinner, the leakage current increases and becomes charge coupled into the substrate.

Since the gain (β) product of the parasitic transistor formed in the process of this embodiment is higher than the unit gain, it does not reach the required injection current, so that the rattling can be prevented. This is avoided by allowing current to leak through the substrate. If the resistance of the path of the leakage current is reduced, the current that has increased sharply will cause more shunts. If the horizontal spacing required to completely avoid latch-up is 5 microns at 15V, then 5 microns from the tank to the N + region and 7 microns from the tank to the P + region. These values can be adapted to the geometry of the device.

An initial oxide layer of 50 nm thickness is grown and 140 nm of silicon nitride is deposited. The implantation is performed using a resist having a complement of the image of these layer tanks, e.g. 80
Pour 5 × 10 ¹² / cm ² phosphorus with KeV and inject N-tank.

For example, a 530 nm oxide layer is grown in the N tank region, which serves as a mask for subsequent P-well implants and serves as an alignment for aligning subsequently formed layers. P-well region is then for example in 60KeV 4 × 10 ¹¹ /
An implantation of cm ² of boron is performed.

The tank oxide is removed and a drive-in of the N tank and P-well injection is performed. Standard (e.g. 50
The thickness of the nm) pad oxide is grown and the nitride is deposited. The moat complement is removed from the nitride / oxide stack and a blanket boron implant for channel stop is performed, for example, at 90 KeV and at a concentration of 1.2 × 10 ¹³ / c.
It is performed using m ^2.

Next, the photoresist is removed and a field oxide growth step is performed to grow the oxide to a thickness of about 1.2 microns. The nitride / oxide stack covering the moat region is then removed. A blanket channel stop implant of boron can be used to increase the electric field threshold of the N channel without excessively lowering the electric field threshold of the P channel due to the desired effects of the side effects in the field oxide process. This is because most of the boron in the P-well enters the oxide during the field oxide formation step, while the concentration of phosphorus in the N tank increases at the surface. Furthermore, in the P-channel device,
Q _SS (charge accumulated in the oxide), which always shows a positive value,
Raise the electric field threshold. Since the voltage generated by the accumulated charges in the oxide is represented by V _SS = Q _SS / C _OX , this effect is necessary for a thick oxide layer that requires a small value of the oxide capacitance C _OX. Is particularly preferred.

Next, a 25 nm pre-gate oxide is formed to prevent the "Kouy effect" and the pre-gate oxide is etched. Next, a first gate oxide is grown to a thickness of 70 nm. Optionally, the first electrode pattern can also be etched at this time. An additional 500 nm thick first poly layer is deposited, for example 5 × 10 5 at 85 KeV.
^The doping is performed by phosphorus implantation using a concentration of ¹⁵ / cm ² . The first poly layer is used to constitute a lower electrode for a capacitance element (poly-to-poly capacitance element) composed of a precision poly layer and a poly layer required for analog signal processing. This is also used to form normal threshold transistors, where the final sheet resistance inside the N tank is approximately 150Ω / □ and outside the tank is about 40Ω / □, so for very short interconnects Can be used.
(The difference between the inside and the outside of the tank is due to the counter doping of the boron source / drain implant.) If a first electrode layer is required, the difference between the moat and the first and poly layers It may be formed.

The first poly layer is then patterned and plasma etched, and the exposed portion of the gate oxide is wet etched. Also, a 70 nm thick second gate oxide is grown in an O ₂ substrate containing 5% HCl. At the same time, an insulating layer on the first poly layer is formed on the exposed portion of the first polysilicon region to increase the thickness. Blanket implantation is performed by implanting boron of 5 × 10 ¹¹ / cm ² at 40 KeV, and the threshold values of the N-channel device and the P-channel device are adjusted.

In telecommunication circuits that require a depletion load circuit selectively (eg, for a source follower circuit), depletion (phosphorous)
At this point, a masking step can be added to form the injection layer.

Here, a 300 nm thick second poly layer is deposited and doped. 200 nm of TiSi ₂ is deposited by mixed deposition of titanium and silicon. Preferably, the deposition is performed by simultaneous electron beam mixed deposition of titanium and silicon. A method of selectively performing mixed sputtering or a direct reaction can also be used. Next, the titanium silicide is annealed and the second poly layer is patterned. (Wet etching should not be performed after silicide is deposited) silicide,
The polysilicon and exposed portions of the gate oxide are removed by plasma etching. If two poly layers are not required, the second layer is not formed and the first poly layer is silicided and used as a gate.

At this point, the above-described process steps of forming a lightly doped drain extension region in the N-channel transistor are performed. That is, LDD implantation is performed entirely, P-type source / drain regions are implanted,
N-type source / drain implantation is performed using a mask such that the N-type source / drain implant region is offset from the channel of the high voltage N-type transistor. It must be remembered that the order of performing the LDD implant, the P + source / drain implant and the N + source / drain implant must not be disrupted. However, it does not matter when the sidewall oxide is formed as shown below.

It should be noted that the step of forming a lightly doped extension region according to the invention is not feasible when source / drain counter doping is used. If source / drain counter doping is performed, this is possible because the unpatterned P-type source / drain implant is compensated for by the patterned N-type source / drain implant. However, since the LDD region is not affected by the N-type source / drain implantation, the P-type source / drain implantation must be formed in a pattern for protecting the LDD region.

Next, if a negative resist is used, the second electrode layer is patterned using a two-step resist coating. Wet etching is performed to a thickness of about 500 nm, and the remainder is removed by plasma etching. PS
Since the etching rates of G and the plasma oxide are different, it is necessary to perform the plasma etching.

Finally, 40 nm of plasma polysilicon is deposited, followed by 1200 nm of aluminum. The aluminum is then patterned, etched,
Sintered. A 300 nm plasma nitride is then deposited. A protective overcoat (POR) pattern is further formed and the nitride is etched.

The invention has mainly been described with reference to an epitaxial structure having a double well. However, it is clear to one skilled in the art that the present invention can be applied to devices in which various latch protection means are used. For example, about 10 ¹⁶ cm 2 × a doped N-well to ^-3 10 ¹⁵ cm
It can be used in P-type substrates doped to a concentration of ^-3 . In this case, a guard ring is used, while the invention can be implemented in other aspects and in the manner described above.

The present invention can also be applied to an N-on-N + (N-epi layer structure on an N + substrate) CMOS process. In this case LDD
An area will be created in the NMOS device in the tank.

Another alternative technique similar to that described above is to form a sidewall oxide along the edge of the gate of the P-channel before the P + source / drain implant is performed. In this case, the P-channel device must be masked (using a conventional N + source / drain mask) before the arsenic LDD implant occurs, so that the LDD implant does not penetrate the P-channel source / drain regions. After the mask is applied and the LDD implant is performed, the sidewall oxide is deposited and etched for gate oxide under the sidewall oxide in both P-type and N-type devices. Then P + source / drain layer is implanted BF ² is patterned is end and self-aligned sidewall oxide because performed. No P-type LDD implantation or reach-through implantation is performed. Boron is diffused relatively wide in the horizontal direction so that the P + source / drain is aligned with the edge of the gate at the end of the process. The N + source / drain layers are further patterned and a high concentration arsenic N + implant is performed. Thereafter, the process is continued as usual.

It should be noted that this method requires an extra masking process step to prevent the LDD implant from penetrating into the P-channel source / drain regions. Similar results can be obtained with boron source / drain implants that do counter-doping of arsenic LDD implants by skipping this masking step and diffusing horizontally during subsequent heat treatments. Dose can make a huge difference. That is, arsenic LDD implantation uses approximately 1 × 10 ¹³ / cm ^2, and boron P + source / drain implantation approximately 2 × 10 ¹⁵ / c
using the numerical value of m ^2.

Obviously, the sidewall oxide technique allows for control of the properties and the N-extended region can be considerably shortened.
The results of the measurements indicate that when the sidewall oxide technique was employed, the substrate current caused by impact ionization was reduced by a factor of 10. All N-channel transistors can form an LDD as they are.

Thus, the present invention is applicable to high voltage techniques as well as techniques for minimizing small geometric dimensions, and can be widely modified and modified as will be appreciated by those skilled in the art.

In the main embodiment described above for the process of forming the lightly doped drain extension region (LDD), the sidewall oxide covers the N-channel device,
The channel device is left in an unobstructed position.
However, it is desirable to keep the lightly doped drain region from entering the P-channel device, but the sidewall oxide formed near the gate of the P-channel device also improves the planarity of the device. This is a desirable point in making it possible.

The preferred embodiment of the present invention is performed by performing the step of forming the sidewall oxide at a different point in time from the sequence of masking and implanting that must be adhered to as described above. That is, in this embodiment,
After all process steps for patterning the polysilicon gate layer are completed, an LDD implant is performed with a blanket implant. Next, a photoresist is patterned according to the P-type source / drain mask, and P + source / drain implantation is performed. The P + source / drain photoresist is then stripped and an isotropic etch is performed to deposit an overall isotropic deposition oxide and leave the sidewall oxide on both the N and P channel devices. . Next, an N + source / drain photoresist layer is patterned and N + source / drain implantation is performed. This sequence of steps forms a short, lightly doped extension region that does not extend over the source / drain regions of the N-type device but only over the P-type device. However, sidewall oxide is formed both on N-type devices and on P-type devices. This configuration is slightly preferable because the planar shape is improved by the side wall. That is, the problem of step coverage at the end of the first poly layer in the PMOS region is reduced.

The invention is particularly applicable to VLSI processes, for example, VLSI processes where the channel length is less than 2 microns. like this
In the VLSI process, the present invention changes the conventional technique only by forming a source / drain region in a series of process steps. That is, since the important point of the present invention is to form a source / drain region (and a lightly doped drain extension region), the present invention can be combined with any CMOS process. The present invention reduces the substrate current and does not otherwise alter the parameters of the VLSI process. Thus, as is well known to those skilled in the art, the dose and energy of the implantation process used in conventional process steps according to any one of a number of widely known series of VLSI, CMOS processes are:
It is considerably reduced.

As described above, the present invention has advanced in forming a source / drain region applicable to any series of CMOS processes. Therefore, the present invention may be variously modified or modified and implemented as will be understood by those skilled in the art.

[Brief description of the drawings]

FIGS. 1 to 4 are diagrams for explaining a technique related to the present invention, and FIG. 5 is a diagram showing an embodiment of the present invention.

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Claims (5)

(57) [Claims] 1. A method of manufacturing a CMOS device, comprising: (a) both an N-type portion and a P-type portion on the surface for securing at least a threshold voltage of a P-channel transistor formed in at least an N-type portion; (B) forming a polycrystalline silicon gate layer on each of the P-channel and N-channel device regions on the semiconductor substrate; and (c) forming a polycrystalline silicon gate layer on the semiconductor substrate. Implanting N-type impurities at a low level in the region of the N-channel device using a polycrystalline silicon gate layer as a mask; and (d) forming sidewall oxide on side surfaces of the gate layer for the P-channel and N-channel devices. (E) masking the region of the N-channel device, and using the gate layer and the sidewall oxide of the P-channel device region as a mask to form a P-type impurity in the P-channel device; Type, and then to diffuse the impurity in the regions under the sidewall oxide P ⁺
(F) masking the P-channel device region and introducing an N-type impurity into the N-channel device using the gate layer and the sidewall oxide of the N-channel device region as a mask; And N ⁺ type source / drain regions other than under the sidewall oxide,
Forming an N ⁻ -type source / drain diffusion region under the sidewall oxide. 2. The method according to claim 1, wherein the respective gate electrodes are formed simultaneously. 3. The step (e) of implanting a P-type impurity includes the step of
The method according to claim 1, wherein the step (f) of introducing the type impurity is performed before the step (f). 4. The step (e) of implanting a P-type impurity comprises the step of
2. The method according to claim 1, wherein the step (c) is performed after the step (c) of introducing a mold impurity. 5. The step (a) of implanting a P-type impurity comprises the step of
2. The method according to claim 1, wherein the step (c) and the step (f) for introducing the type impurity are performed before any of the steps.