JPH02125465A - Manufacture of cmos device - Google Patents

Abstract

PURPOSE: To form a drain extension region doped to a low level within a CMOS process by using a gate electrode of p-type portion of the substrate and a nearby side wall spacer as a mask and by selectively driving first and second doses of n-type impurities. CONSTITUTION: After the pattern of a polysilicon gate layer 6 is formed, drain injection doped to a low level is performed as a reach-through injection through gate oxide. After forming an oxide 10 at a predetermined position, a mask 11 is provided on a P well 4. The exposed equi-directional deposition oxide 10 is etched and removed, and P<+> source/drain injection is performed for N-tank 5. A photoresist 11 is removed here, the equi-directional deposition oxide 10 covering an NMOS device region on P well 4 is partly etched and removed, leaving a thin thread portion 20 at the gate side wall. Moreover, a mask layer 21 for N-type injection is formed. Source/drain injection of arsenic is performed in the last stage and then the source/drain 22 and LDD region 23 is formed.

Description

[Detailed description of the invention] The present invention relates to CMO3 integrated circuit technology.

A recognized problem with both short-channel and high-voltage MO8 technologies is impact ionization at the drain-channel interface.
is what happens. This is because the normally high peak electric field at this boundary injects hot carriers into the gate oxide (which causes a shift in the device threshold according to the operating process) and lowers the avalanche breakdown voltage. This is to increase the raw substrate current. The electric field created by the gate increases the problem of electron avalanches flowing into the drain boundary. This problem is particularly acute when the drain boundary is typically formed very close to the edge of the gate where the gate electric field is highest. All these effects are especially noticeable when using high 741N with small geometric dimensions (e.g. 1 micron channel length at 5 volts) and high 741 (e.g. 4 micron channel length at 20 volts) in 100 MO3 technology. This is a problem when creating channel devices.

In the digital 0M08 circuit, the N-channel and P-channel devices conduct parasitic substrate ti currents due to impact ionization during the transition period for switching when both are turned on. This causes "substrate bounce" which can cause latch-up, bias removal, or discharge at the floating node. (This is the reason for using a shrimp layer on the P-board.) In analog circuits, N-channel source follower configurations are biased so that significant parasitic board currents flow continuously. The situation is potentially even more serious. Perhaps the most important weW behind all the problems is,
It concerns the injection of hot carriers into the gate oxide which can change the threshold over time and cause low transconductance. Naturally, all these problems become even more serious when the gate oxide is designed such that the supply voltage remains constant.

Since the coefficient of impact ionization is approximately proportional to the number of electrons encountered in excess of holes, N-channel devices have limitations in practical construction of short channel devices using high supply voltages. The present invention is based on “J 0M that is strong against hot carriers”.
We provide an 0MO8 technology for making N-channel devices using an 08 process. These techniques form a lightly doped N region between the channel and the N+ source/drain region. This structure allows the high electric field in the drain bound-off region to extend into the N-extended region, thereby raising the drain breakdown voltage and reducing impact ionization and thus the emission of high-energy electrons. . These advantageous configurations are obtained by performing phosphorus blanket implants at low doses and do not require additional masking steps.

Significant development efforts have been devoted to addressing problems related to these properties in the prior art of NMO8 devices. For example, 4.3 for the US patent, which is used as a reference in this
No. 56.040 shows the use of a third wall oxide on the gate to reduce overlap between the gate and drain, or to extend from below the gate/drain.

Ogura and others (1980>IEEE Journal Op Solids Dating Circuit, Volume 5C-15, 42
The paper ``Lowly Doped Drain/Source (LDD) Insulated Gate Field-Effect Transistors'' appearing on pages 4 and below and all references cited therein are We will show a configuration with , and explain the advantages of this configuration. Another technique is specifically described with reference to the formation of a lightly doped drain region formed by a reach-through implant with a sidewall oxide partially blocking the implant.

There are some special problems associated with including a lightly doped drain configuration in the OMO8 process, and it is an object of the present invention to solve these special problems.

In particular, the object of the present invention is to provide a low level doped drain extension region (referred to as LDD region) within the OMO3 process.
Provides a method for forming.

A second object of the present invention is to provide a method for forming DD regions within an 0MO8 process without requiring an additional mask addition process.

As explained above, a particular problem with 0MO8 technology is that, as shown in 1 above, the impact ionization coefficient for holes is much smaller than that for electrons, so only N-channel devices require an LDD region at the drain boundary. This is something that needs to be created.

Therefore, it is an object of the present invention to provide a method for manufacturing an 0MO8 device in which an LDD region is not formed in a P-channel device, but an LDD region is formed only in an N-channel device.

Another object of the present invention is to form lightly doped drain regions only in N-channel devices but not in P-channel devices without the need for additional masking steps.
A method of manufacturing an MO8 device is provided.

Another problem with using a lightly doped drain region is that this region degrades the performance of the device in various ways. In particular, aa
The series resistance of the device can increase considerably and the transconductance of the device can also decrease. Both of these are related to the length of the LDD region, ie, it is desirable that the LDD extension region is not much longer than necessary considering the operating voltage of the device. In particular, if the LDD region is not self-aligned with the gate and source/train regions, it must have an alignment tolerance width of at least two. Because otherwise the normal alignment error is L
This is because some devices will end up having no DD area at all. Such equipment slows yields because it does not work. Therefore, it is highly desirable to form a lightly doped drain extension region self-aligned to the gate and also to the source/drain region.

Another object of the present invention is to provide an 0MO8 process technology in which a lightly doped drain extension region self-lines both the gate and source/train regions.

Another object of the present invention is that the lightly doped drain extension region can be formed in the gate region and source/source region only in the N-channel device without any additional masking steps.
The objective is to provide an 0MO8 technology that provides a self-line in both train regions, which is not the case with P-channel devices.

The above problem is particularly acute in high voltage equipment. High voltage 0MO8 devices are desired in numerous applications including consumer equipment, control equipment, equipment used in electrically noisy environments, and the like. However, it is extremely difficult to increase the geometrical dimensions of the high voltage 0MO9 process to a geometrical dimension level suitable for LSI level integration.

Furthermore, unless the yield multiplied by the cost per manufactured chip shows an acceptably low total cost, even technically possible chips will become useless, so high-voltage 0MO8 process The number of masks used for
must be strictly controlled. That is, high voltage CMO
A characteristic that must be observed for the application of No. 8 is the combination of a small number of masks and a small geometric unity modulus.

It is therefore an object of the present invention to provide a high voltage 0MO8 technology with a small number of masks and relatively small geometric dimensions.

The length of the LDD region is particularly problematic in high voltage 0MO8 processes. This means that in application processes at very high voltages,
Although low dopant concentrations are typically used in DD region formation to allow for the necessary graded doping distribution at the channel and LDD region interfaces, such low dopant concentrations can cause problems in the LDDI region itself. This is because the inside inevitably has a very high resistance, and therefore, as the length of the DD region increases, the series resistance of the device also becomes extremely high. On the other hand, it is necessary to ensure that the LDD region in high voltage devices does not become too short, since the desired graded dopant profile would therefore be truncated. That is, as the actual overall width of the LDD fa regions on the source and drain sides increases, the series resistance within the device increases, but this value is not necessary even assuming that the widths of the LDD regions on both sides are simply minimized. The use of non-self-lined LDDI areas is most suitable for high-voltage processes because the resistance is significantly higher than that of the LDDI area.

According to the invention: providing a semi-dedicated substrate; defining a moat region on a surface of the substrate and implanting two N-type impurities into selected portions of the substrate to form a plurality of N-type tank regions; ! ! forming an insulated conductive gate layer over a portion of the board to define a predetermined plurality of device locations within the moat region, the device locations including both N-channel device locations and P-channel device locations: (a ) introducing a generally low dose of N-type dopant to a shallow depth of the substrate surface, including both the desired location of the lightly doped drain extension region and other locations; (b) providing a patterned masking layer covering the locations of the N-channel devices and removing the isotropic oxide not covered by the masking layer to remove a high dose of the isotropic oxide; Introducing P-type impurities to form P-type source/drain regions at predetermined positions where the surface of the substrate is exposed;
(c) depositing a patterned mask layer over the plurality of P-channel device locations, leaving a sidewall oxide on the sidewalls of the gate overlying the N-type device regions; The isotropic oxide overlying the type device region is anisotropically etched and a high dose of N-type impurity is implanted to form an N-type source and drain, thereby forming the N-channel device from the respective source/drain. having a lightly doped drain extension region separating a region from said channel region; and connecting said respective source/drain and gate to provide a desired functionality. be done.

In the above method, all steps of step (a) are replaced by step (b).
) and all steps in step (B) are performed before step (c).
is carried out before.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is described in terms of a high voltage 0MO8 process that is suitable for devices operating at 18 volts with a channel length of 4 microns. However, the process of the present invention is relatively scalable to suit higher or lower operating voltages. That is, the preferred embodiment of the present invention, the 'IX Voltage CMO8 process, is operated at 10 volts and the channels are operated at 2 micron processes or 14 volts and 3
Proportional scaling can be easily done in micron steps. Additionally, N-type and P-type source/drain regions and LDD
The exact series of process steps in which the extension region is formed can be inserted into other high voltage 0MO8 processes. Thus, although it is preferred to use an epitaxial twin tap process with a shallow, highly doped tank, this feature is not absolutely required.

The series of process steps for forming source and drain regions and LDD extension regions in accordance with the present invention will first be described, followed by a general high voltage CMO8 process flow envisaged as the preferred embodiment described herein. .

As a process leading to FIG. 1, a P-type shrimp layer 2 is formed on a P-type substrate 1, and a P-type well 4 and an N-type tank 5 are selected in the moat portion recessed in the thick field oxide 3. Formed by diffusion. A gate oxide layer 6 and a polysilicon gate layer 7 are formed using a resist 8 in the moat portion.

The process flow of the present invention up to the pattern formation of the polysilicon gate layer 6 is described in U.S. Patent Application No. 344.588 (H.
8-169928r High Voltage CMO8 Process", which is incorporated herein by reference).

After the polysilicon gate layer 6 is patterned, a lightly doped drain implant (LDD implant) is performed as a reach-through implant through the gate oxide so that the thin gate oxide is exposed (not shown). teeth,
It is preferable not to remove it. (The reason for not removing the gate oxide is to preserve the state in which the gate oxide was formed.) However, this is not very important here.

After patterning the polysilicon, the exposed gate oxide is etched away, leaving the photoresist layer over the poly layer in place. A low level phosphorus or arsenic implant is carried out using 60 KeV at a concentration of 8 x 1212/c2, for example. This implant is self-lined to the edge of the poly gate as shown in FIG.

Since phosphorus has a higher diffusivity and exhibits a doping concentration distribution that changes with a gentle slope depending on the junction of the channel/LDD region, it is considered that it is slightly more preferable to use phosphorus than arsenic for drain implantation, which is doped at a low level. It is being

The use of LDD implants containing both arsenic and phosphorous is another embodiment of the invention. This embodiment also exhibits a doping level change exhibiting an even more gradual slope at the LDD/channel boundary. In other words, since phosphorus has a higher diffusivity than arsenic, a region containing only phosphorus is formed to extend slightly outside the region containing both phosphorus and arsenic, which again creates a region where a potential difference exists. The electric field at the broadening peak becomes lower.

In general, the depth and implantation amount for LDD implantation are as follows: LDD(i
n! The implant region is selected to have a dopant concentration somewhat shallower than the depth of the source region within the dopant, with a dopant concentration much lower than that typically used for source/drain formation. For example, 4 used for operation at 18 volts.
In this example using a micron device, the dopant concentration in the lightly doped drain region is approximately 1
x 1017/cm3 and the depth of the lightly doped drain region is approximately 0.15-0.2 microns. Deeper LDD regions can also be used very well (unless the depth of the LDD regions is much deeper than the depth of the source/drain regions);
Forming the m-region makes it difficult to control the lateral diffusion of the LDD implant.

The structurally "lowly doped" drain region essentially performs these functions. First, the dopant concentration must change smoothly at the boundary between the channel and the LDDm region.

As explained above, if the doping distribution changes gradually, the potential also changes little by little, so the peak electric field can be lowered. Second, the highly doped drain is physically removed from the edge of the gate, so the electric field due to the gate voltage at the edge of the drain is much lower.

i.e. doped to n level (typically lX1
019/α3) The transition part up to the drain region is L
When the DD region is not used, the junction between the high and low doping regions of the LDD and drain interface is created in close physical proximity to the location of the largest gate induced electric field (at the edge of the gate). Simply physically separating the two is a valid point in itself. Third, the LDI region itself is typically doped at a low level to create a slight IR drop between the channel and drain. This voltage drop reduces the performance of the device, but reduces the voltage drop that occurs at the LDD-to-channel interface by a small amount (eg, approximately 1 volt). Fourth, if the source and drain are physically separated by a wide gap, the punch-through voltage will also increase slightly. Fifth
In addition, the LDD region tends to reduce the capacitive load induced by the gate, increasing the operating speed.

If dual implants are used, the energies of each are preferably chosen to implant to the same distance for the phosphorus and arsenic implants. In this case, the total dopant concentration in the LDD region can be chosen to be around 1x1018/c113.

However, as explained, the resistance of the LDD region (1 degree dopant) can be modified to specifically adapt the invention to the constraints of the desired circuit. That is, a lower dose DD implant produces a smoother slope of the dopant distribution in L.
can be created at the D D /channel boundary, thus creating a lower peak electric field at this boundary, but at the cost of lower transconductance and series resistance values.

These effects are even more favorable when double injection (phosphorus and arsenic) is used, as explained above. Undesirable LDD region side effects can be reduced. That is, when a phosphorous and arsenic implant is used to form the LDD region, a slightly higher overall dopant concentration is used in the LDD region than the level used when performing a phosphorus-only implant. Since the LDD region with high resistance can be minimized, the series resistance can be lowered.

After the blanket (global') LDD implant is performed as in FIG. 1, a thin oxide layer is deposited globally isodirectionally, for example by plasma or low pressure chemical vapor deposition. In the preferred embodiment, a 300 n1ll thick oxide layer is deposited, but this thickness need not be critical. However, it is desirable to tightly control the thickness of the oxide deposited as it is related to the width of the sidewall oxide formed as explained below. After the oxide 10 is formed in place, the P-well 4
Mask 11 for P+ source/drain implants over
is provided. Exposed iso-directionally deposited oxide 1
0 is etched away and then a P+ source/drain implant is made into the N- tank 5 using a single boron difluoride implant step of 8 x 10/cab2 at 67 KeV, for example, as shown in Figure 2. It will be done. (See source/drain 24 in Figure 3) The photoresist 11 used to mask the P-type source/drain implant regions is now removed and the P-well 4
The isotropically deposited oxide 10 covering the upper NMO8 device area is partially etched away leaving a shaft-like portion 20 on the sidewalls of the gate. Furthermore, a mask layer 21 for N-type implantation is formed. It is not necessary to carry out all of these steps strictly, ie, the mask forming step for the N implantation can be moved before the oxide etching is performed. However, the parameters associated with oxide etching are important. (See FIG. 3) Since the polysilicon gate layer 7 needs to be patterned leaving nearly vertical sidewalls, a highly anisotropic polysilicon etching method must be used. Many such etching methods are known in the art. For example, polysilicon is etched in Freon-11.

The fact that the vertical sidewalls are continuous along the polysilicon gate line means that even after the oxide is removed from the entire area, some oxide 20 remains in the form of a phase system on the sidewalls of the gate. Become. That is, if 30 Qnm of oxide is deposited isodirectionally and then 300 tv of oxide is etched away, the thickness of the gate plus gate insulator is approximately the same width as the initially formed oxide bank. An oxide deposit of the same height will still remain on the gate wall. Preferably, the walls are etched slightly more than required to remove the insulator layer, for example with a 50% overetch. Due to this, I do not want to leave any other residue.
The Mide leaves no oxide, such as on the field oxide, and still leaves some sidewall oxide 20 on the gate walls. (Note that the field oxide of the typical LOGO3 process is significantly inferior in terms of vertical oxide formation to the process shown here, which is more integrated for miniaturization. This can be implemented in a wide variety of insulating layer formation techniques, and is not meant to be applied only to the LOGO8 process.

If the iso-directionally deposited oxide 10 is overetched beyond the desired height, the highest portions of the sidewall oxide 20 will be removed and lowered and their thickness will be slightly thinner. However, in this preferred embodiment of the invention, reach-through implantation through the sidewall oxide 20 is not used, so precise control of the height of the sidewall oxide 20 is important (e.g., gate oxide 6 (at least 4 times the thickness of Furthermore, as is well known in the art, sidewall width is only slightly affected by overetching, requiring precise control of the etch duration or the initial iso-deposited oxide thickness. The width of the LDD region changes only slightly due to its absence.

Therefore, source/drain implantation of arsenic is, for example, 100Ke.
The source/drain 22 and the LDD region 23 are formed after a value Tia of 1×10 16 /α 2 at v.

The high voltage 0MO8 process in which the preferred embodiment of the invention is used is detailed below. Although the formation of the LDD region according to the invention can be used with other high voltage OMO8 processes, the combination of the LDD formation process according to the invention with the n-voltage process described below is very advantageously applicable. In particular, the invention allows for further increases in device density at the same operating voltage and at the same density.

Note that by using the LDD extension region, the channel length can be reduced while other operational parameters remain the same. That is, the parameters related to P injection to provide a spacing at the end of the tank 5 are not affected by the diffusion of the LDD expansion region.

The invention is described in its embodiment with reference to a process that operates primarily at 18 volts and is therefore suitable for devices where a breakdown voltage of 20 volts or more and a threshold r1 voltage are required. In this preferred embodiment, a 4 micron design method is used. However, the present invention is proportionally adaptable to scales with lower operating voltages and smaller geometrical applications, such as operating at 15 volts and having a geometric dimension of 3 microns. .

The present invention preferably uses a structure in which a 1]-layer is provided on a P-on substrate (P-on 1]-layer structure).

Within the P-epitaxial layer, both a P-type well and an N-type tank are formed by implantation.

In the present invention, a double poly layer process is possible using a 9-step mask when using a positive resist, and a 10-step mask when using a negative resist (because a 2-step mask is used to form the electrode layer). Become. Algorithmically creating masks reduces the number of patterned layers to 8M and allows contacts to be made to tanks made using N+ source/drain implants, while using P+ source/drain implants. A contact can be made to the P-well created by the P-well. Both the N+ and P+S/D masks are created from the N+/P+ mask and the tank mask. A single poly layer process according to the present invention uses only 8 masks, and using source/drain counterdoping requires only 7 masks total. A 16 micron thick P-type epitaxial layer doped to about 1015/13 is formed thereon.
A P0 substrate doped to 18/cm3 is the starting material. After evaluating the latch-up performance using the process of the present invention, it has been determined that a 16 micron strip layer can provide adequate latch-up protection for 15 volt operation of internal circuits. For 110 circuits, N
The protection function can be further enhanced by adding a guard ring formed by the +source/drain implantation step. For this, the polysilicon line is P
It is necessary to use some metal jumpers in the 110 circuit to be able to cross between and . By forming guard ring configurations only in 110 circuits that are often subject to externally generated high voltage transients, high voltage It can have strong durability against voltage transient phenomena.

A two-phase polysilicon layer and regrown gate oxide are used. The first polysilicon layer is doped by ion implantation and thus forms the lower electrode of the capacitive element and a transistor with a conventional threshold. Additionally, a resistive element is formed within this first polysilicon layer.

In the second polysilicon layer, conventional gates and interconnects are formed. This layer is preferably silicided by a mixed deposition of titanium and silicon, effectively increasing the sheet resistance of the second poly layer to approximately 5 ohms per mouth. This eliminates the need to make difficult compromises between resistance values and other required etching characteristics. When using PoCl3 to dope the polysilicon to less than about 50 Ω/hole, plasma etching proceeds selectively along the grain boundaries, resulting in a large amount of polysilicon being removed. Polysilicon, which has a sheet resistance of 50 Ω/hole, is poor for designing circuits, but the poly layer has a higher sheet resistance because P-type source/drain implants are performed. . By converting the second poly layer to a silicide, sheet resistance problems can be overcome, and titanium and silicon can be deposited simultaneously with little process complexity.

The final P channel (N tank) surface concentration is approximately 1016/α3 and the tank depth is approximately 4 microns. For a gate oxide thickness of 7Qrv, the resulting body effect is approximately 1.4v1/2;
Kp is 5μA/v2. In the design of most circuits,
Since the N tank can always be connected to the source, high P channel substrate effects are not a problem.

The final surface concentration of the N channel (P-well) is approximately 2×10 15 /cII 3 , resulting in a substrate effect of 0,4v 1/2 and a Kp of 16 μA/×2.

V (NMO8liHttlJI),! =V,,(P
A blanket (global) boron implant is used to set the MO8IIN value voltage to and from 1.5 volts simultaneously. P
l of MO8 and NMO8! This blanket boron implantation is performed to ensure that the lWi voltage is symmetrical so that only one voltage level is taken, and that the process parameters are specified to set the appropriate value of plus or minus 1.5 volts. used.

The field darkness values of PMO8 and NMO8 are both set to approximately 20 volts or more. This can be accomplished by performing a blanket BON field threshold adjustment implant that creates a 1.1 micron field oxide.

The initial field lkl value in the PMO8 region is higher than the required value, and the dose of the threshold adjustment implant is selected such that the field wA value in the PMO8 region is equal to the field threshold in the NMO8 region. At the doping level explained above, the field part lIl value level is 2
Set to equal values around 2 to 25 volts. Therefore, no step of adding a mask is required for adjusting the field threshold.

Boron implantation is performed on the PMOS source drain and N
The MOS source/drain is implanted with arsenic/phosphorous to create a junction approximately 0.5 microns deep with a junction breakdown voltage of 23 volts.

The preferred embodiment mask set is as follows.

Table 1 Twin tub, 15V, 2fl poly CHHO8 mask set Mask name Function 1, tank
Defines the P-channel region and is used in the construction of the resistive element.

2. Moat Define the moat pattern for the N+ guard ring for the active device and 110 circuit.

3. Poly N1 Used for the phase U connection of the lower N bridge of precision capacitive elements and transistors with normal thresholds.

4. Polilil! 12 Conventional transistors, used for the upper electrode and interconnection of the tF.

5, N+S/D N-type channel source/drain,
Make the guard ring and tank electrode for the 110 circuit.

6. Make P+S/D P channel source/drain, local P type root electrode.

7. Electrodes for all CrOR poly gates and moats 8. A sample process for the Netal Full Level Interconnect 9, POR Protection Overcoat High Voltage 0MO8 process is described below.

The starting material is P doped to about 1018/13
The daughter substrate is a 16 micron epitaxial pF8 doped to approximately 1015/13! m is formed. The thickness of the epitaxial layer is governed by the general factors listed below.

1a] First of all, as the layer becomes thicker, the efficiency of suppressing latch-up becomes worse. Second, N tank has vDO (+1
The minimum value of the depth of the shrimp layer is determined by the supply voltage so that the depletion region extending from the tank when the P-type substrate (shrimp layer) is at O volts (5V) does not reach the P-type substrate. This minimizes the depletion layer that extends into the tank, thus increasing the P+ punch-through voltage, and preventing the voltage from dropping at all, which will cause breakdown due to the large electric field when the voltage drops on the P-substrate. It can be done. Furthermore, as the layer is warped, the leakage current increases and becomes charge coupled into the substrate.

Since the gain (β) product of the parasitic transistor formed in the process of this embodiment is higher than the unity gain, the injection current does not reach the required injection current, so latch-up can be prevented. This can be avoided by leaking current through the substrate. If the resistance of the path for this leakage g flow is lowered, a large amount of the rapidly increased 'R flow will be shunted. In the case of 15V and 5 microns, the required horizontal spacing to completely avoid latch-up is 5 microns from the tank to the N region and 7 microns from the tank to the P1 region. These values can be adapted to the geometric dimensions of the device.

A first oxide layer of 5Qni thickness is grown, 140n
11 silicon nitride is deposited. Implantation is carried out using a resist with an auxiliary image of these layer tanks, for example, by implanting phosphorus at 5.times.10@12 /C@-2 at 80 KeV, and the N-tank is implanted.

For example, a 530 nil oxide layer is grown in the N tank region, which acts as a mask for the subsequent P-well implant and as an alignment to align subsequently formed layers. The P-well region is then implanted with boron of 4.times.10@11 /C@-2 in, for example, 60 keys.

The tank oxide is removed and the drive-in N tank and P well injections are performed. A sub-IIA (eg 5 Qrv thick) pad oxide is grown and the nitride is deposited. The part that corresponds to the auxiliary equipment of the mote is made of nitride/
The FiI compound stack is removed and a blanket boron implant for channel stop is performed using a concentration of 1.2 x 1013/Cm2 at eg 90 KeV.

The photoresist is then stripped and a field oxide growth step is performed to grow the oxide to a thickness of about 1.2 microns. The nitride/oxide stack overlying the moat area is then removed. A blanket channel-stop implant of boron can be used to increase the N-channel electric field all value without lowering the P-channel electric field threshold too much due to the desirable influence of side effects in the field oxide process. This is because most of the boron in the P-well gets into the oxide during the field oxide formation process, whereas the concentration of phosphorus in the N-tank is higher at the surface. Furthermore, in P-channel devices, Qss (charge stored in the oxide), which is always positive, increases the electric field threshold. This effect is particularly favorable in thick oxide layers, where the oxide capacitance C needs to be small, since the voltage generated by the charge accumulated in the oxide is expressed as Qss/Cox. .

A 250- pregate oxide is then formed to prevent the "Cooey effect" and a pregate oxide etch is performed. Next, a first gate oxide is grown to a thickness of 7Q nm. Optionally, the first bridge pattern can also be etched at this point. Another 5000
- a first poly layer of thickness is deposited, e.g.
Doping is carried out by phosphorous implantation using a concentration of 5×10 15 /C2 at Kev. This first poly layer is
The first purpose is to constitute a lower electrode for a capacitive element (poly-to-poly capacitive element) consisting of precision poly layers and poly layers required for analog signal processing. It is also used to form regular mWl transistors, and the final sheet resistance inside the N tank is approximately 150 ohms/port and outside the tank is approximately 400 ohms/port, so it can also be used for very short interconnections. can be used. (The difference between inside and outside the tank is caused by the counterdoping effect of the boron source/drain implant.) If a first field layer is required, it is formed between the moat and the first poly layer. You may.

The first poly layer is then patterned and plasma etched, and the exposed portions of the gate oxide are wet etched. A second gate oxide with a thickness of 7Qna+ is also grown in a zero layer gas containing 5% HCj. At the same time, an insulating layer over the first poly layer is formed and increased in thickness over the exposed portion of the first polysilicon region. Blanket implantation of 5×10 11 /C 12 boron at 40 Ke ■ is performed to match the threshold values of the N-channel device and the P-channel device.

In telecommunications circuits where depletion load circuits are optionally required (eg, for source follower circuits), a masking step can be added at this point to form a depletion (phosphorus) injection layer.

A second poly layer 3000 m thick is now deposited and doped. 2000s of Ti512 is deposited by co-deposition of titanium and silicon. Preferably, this deposition is performed by simultaneous e-beam mixed deposition of titanium and silicon. Selective mixed sputtering and direct reaction methods can also be used. The titanium silicide is then annealed and a second
The poly layer is patterned. (Do not perform a wet etch after the silicide is deposited.) The silicide, polysilicon, and exposed portions of the gate oxide are removed with a plasma etch. If two poly layers are not required, the second layer is not formed and the first poly layer is silicided and used as the gate.

At this point, the process steps described above for forming a lightly doped drain extension region in the N-channel transistor are performed. That is, the LDD implant is performed globally, the P-type source/train region implant is performed,
N-type source/drain implants are performed using a mask that allows the N-type source/drain implant regions to be offset from the channel of the N-type transistor. It must be remembered that the order in which the LDD implants, P+ source/drain implants and N+ source/drain implants are performed must never be disturbed. However, as shown below, it does not matter when the sidewall oxide is formed.

It must be noted that the process of forming a lightly doped extension region according to the invention becomes infeasible when -source/drain counterdoping is used. If source/drain counter-doping is performed, this doping is applied to the patterned N
This is possible because the unpatterned P-type source/drain implants are compensated for by the P-type source/drain implants. However, since the LDDR region is not affected by the N-type source/drain implant, the P-type source/drain implant must be patterned to protect the LDDfI4 region.

A second electrode layer is then patterned using a two-step resist coating if a negative resist is used. Wet etching is performed to a thickness of approximately 5 () Onll, and the remaining portion is removed by plasma etching. Since the etching rates of PSG and plasma oxide are different, it is necessary to perform plasma etching.

Finally, 4Qnm plasma polysilicon is deposited followed by 1200nm aluminum. The aluminum is then patterned, etched, and sintered.

A 3000-degree plasma nitride is then deposited.

A protective overcoat (POR) pattern is further formed and the nitride is etched.

The invention has been described primarily with respect to epitaxial structures with double wells. However, it will be clear to those skilled in the art that the invention can be applied to devices in which various latch-up protection measures are used. For example, an N-well doped to about 1016 cm-”
X 1015 cm-3 [P- doped to 1 degree
It can be used on shaped substrates. Although in this case a guard ring is used, the invention can also be implemented in other embodiments and in the manner described in section 1 above.

The present invention can also be applied to the N-on-N+ (N-layer structure on N+ substrate >0MO3 process. In this case, the LDDI region will be created in the NMO8& place in the tank.

Another alternative technique, similar to that described above, is to form sidewall oxide along the edge of the P channel gate before the P+ source/drain implant is performed. In this case, the P-channel device must be masked (using a normal N+ source/drain mask) before the arsenic LDD implant is performed so that the LDD implant does not penetrate into the P-channel source/drain region. After the mask is applied and the LDD implant is performed, sidewall oxide is deposited and P
The gate oxide is etched below the sidewall oxide in both type and N-type devices. Then P
+The source/drain layers are patterned and BF2 implanted so that they are self-lined with the edges of the sidewall oxide. P-type LDD implants or reach-through implants are not performed. Boron is diffused relatively widely in the horizontal direction so that the P+ source/drain is aligned with the edge of the gate at the end of the process.

The N+ source/drain layer is further patterned and a high temperature arsenic N+ implant is performed. From then on, the process continues as usual.

It should be noted that this method requires an extra masking process step to prevent the LDD implant from penetrating into the P-channel source/drain regions. Similar results can be obtained with boron source/drain implants that omit this masking step and counter-dope the arsenic LDD implant by horizontally diffusing φ during a subsequent heat treatment. There is a considerable difference in dose. That is, the arsenic LDD implantation is approximately 1×1013
Boron P+ source/drain implant using /C12 uses a value of 2×10 15 /cm”.

Clearly, sidewall oxide technology allows for control of properties and allows for significantly shorter N-extension regions. The results of the measurements show that when sidewall oxide technology is employed, the groups produced by impact ionization! 1 current is reduced by a factor of 10. All N-channel transistors can be used as is to form an LDD.

Thus, the invention is applicable not only to small geometric dimension minimization techniques, but also to high voltage techniques, and is susceptible to wide variations and modifications as will be recognized by those skilled in the art.

In the main embodiment of the lightly doped drain extension region (LDD) formation process described above, the sidewall oxide covers the N-channel device;
The channel device is left in an uncovered position.

However, it is desirable to prevent the lightly doped drain region from penetrating into the P-channel device; however, sidewall oxides may also be formed close to the gate of the P-channel device to improve planform effectiveness. This is a desirable point.

A preferred embodiment of the invention is performed by performing the step of forming the sidewall oxide at a different point in the sequence of masking and implantation that must be strictly adhered to as described above.

That is, in this embodiment, the LDD implant is performed in a blanket implant after all process steps for patterning the polysilicon gate layer are completed. The photoresist is then patterned according to the P-type source/drain mask.
A P+ source/drain implant is performed. The P+ source/drain photoresist is then stripped and isodirectionally deposited oxide is deposited over both the N-channel and 1-channel devices to form sidewall III.
(Anisotropic etching is performed to leave things.
A + source/drain photoresist layer is patterned and an N+ source/drain implant is performed. This sequence of steps forms a loose, lightly doped extension region that extends only above the source/bilene region of the N-type stomach and does not extend above the P-type device. However, sidewall oxides are formed on both T-type devices and P-type G devices. This configuration is somewhat preferable because the side walls make the planar shape more oriented. That is, P.M.O.
Step coverage problems at the ends of the first poly layer within the three regions are reduced.

The present invention is particularly applicable to VLSI processes, for example, when the channel length is 2.
It can be applied to VLSI processes shorter than microns. In such a VLSI process, the present invention modifies the conventional technology only by forming the source/train region in a series of process steps. That is, since the important point of the fourth invention is to form the source/drain region (and the lightly doped drain extension region), the present invention can be combined with any 0MO8 process.The present invention reduces the substrate current and does not otherwise change the parameters of the VLSI process.Thus, as is well known to those skilled in the art, any of the widely known series of VLSI, 0MO8 processes, of which there are many The dose and energy of the implantation process used in one conventional process step is significantly reduced.

As described above, the present invention is advanced in forming source/drain regions that can be applied to any series of OMO3 processes. Therefore, the present invention can be practiced with various modifications and variations as will be apparent to those skilled in the art.

[Brief explanation of the drawing]

Claims (7)

[Claims] (1) When forming the source/drain and lightly doped drain portions of the n-channel transistor in the n-type portion of the semiconductor surface, the gate electrode in the p-type portion of the substrate and the sidewall spacer adjacent thereto are used as masks. , a method for manufacturing an integrated circuit in which first and second doses of n-type impurities are selectively implanted, the method comprising the following steps: (a) a device formed in an n-type portion of the surface; A process of implanting p-type impurities into the entire surface in order to ensure at least a threshold voltage. (b) forming gate electrodes on each of the n-type and p-type portions of the surface and forming sidewall spacers adjacent to the sides of the electrodes; (c) selectively implanting p-type impurities into said surface, where a gate electrode on said n-type portion of said surface and sidewall spacers adjacent thereto substantially block the implant impurities; (d) implanting; Diffusing p-type impurities under sidewall spacers proximate the gate electrode on the n-type portion of the surface. (2) The manufacturing method according to claim (1), wherein each of the gate electrodes is formed at the same time. (3) The step of implanting the P-type impurity is the second step of implanting the n-type impurity.
2. The manufacturing method according to claim 1, wherein the method is carried out prior to the implantation of the dose. (4) The step of implanting the p-type impurity is the first step of implanting the n-type impurity.
The manufacturing method according to claim 1, wherein the manufacturing method is carried out after implanting a dose of. (5) The step of implanting the P-type impurity is the first step of implanting the n-type impurity.
2. The manufacturing method according to claim 1, wherein the method is performed before any of the second and second doses. (6) The manufacturing method according to claim (1), wherein the second dose of n-type impurity is higher than the first dose of n-type impurity. (7) The p-type impurity for ensuring the threshold value is boron (
1) The manufacturing method described.