CN114446944A - Semiconductor electrostatic protection device - Google Patents
Semiconductor electrostatic protection device Download PDFInfo
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- CN114446944A CN114446944A CN202011184992.XA CN202011184992A CN114446944A CN 114446944 A CN114446944 A CN 114446944A CN 202011184992 A CN202011184992 A CN 202011184992A CN 114446944 A CN114446944 A CN 114446944A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
- H01L27/0277—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
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Abstract
The invention relates to a semiconductor electrostatic protection device, comprising: a substrate on which a well region is formed; an electrostatic protection assembly is formed in the well region, the electrostatic protection assembly comprises a first doping region, a second doping region and a fourth doping region, the first doping region and the second doping region are both doping regions of a first conductivity type, a gate layer is formed on the substrate between the first doping region and the second doping region, and the fourth doping region is a doping region of a second conductivity type; the well region further comprises a third doped region, and the third doped region is located between the second doped region and the gate layer. The third doped region is arranged, so that on one hand, the distance between the second doped region and the grid layer is increased, and the maintaining voltage of a transmission line pulse curve is improved; on the other hand, the third doped region can absorb the hole current when the hole current reaches a certain threshold value, so that the effect of improving the holding voltage of the transmission line pulse curve is further achieved, and the semiconductor electrostatic protection device can meet the requirement of improving the chip function.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor electrostatic protection device.
Background
Protection of each voltage level in the current power management chip or other DC-DC converter, or AC-DC converter is generally implemented by using ESD protection devices corresponding to the voltage level, taking 5V ESD protection devices as an example, which are usually 5V GGNMOS (Gate group NMOS) and 5V GDPMOS (Gate VDD PMOS), and 5V GGNMOS is most commonly used.
In the conventional 0.18um conventional process, DCG (Distance from drain Contact to Gate poly) is often used to improve the electrostatic protection capability, but the sustain voltage Vh in the transmission line pulse curve always restricts the characteristics of the ESD protection device. The holding voltage of a typical 5V ESD protection device is around 5.5V in a 0.18um process, and although the holding voltage can be raised by adjusting the channel length, the amount of raising is limited, and generally does not exceed 7V. However, as the demand of consumer electronics is higher and higher, the operating voltage of a 5V chip exceeds 7V or higher, which requires a higher holding voltage for the ESD protection device, however, the holding voltage of the existing ESD protection device cannot meet the demand of chip function improvement.
Disclosure of Invention
In view of the above, it is necessary to provide a semiconductor electrostatic protection device in order to solve the above technical problems. The chip has the beneficial effect of being capable of providing higher maintaining voltage so as to meet the requirement of improving the functions of the chip.
A semiconductor electrostatic protection device, comprising:
the semiconductor device comprises a substrate, wherein a well region is formed on the substrate;
the grid layer is positioned on the upper surface of the well region;
the first doping area is positioned in the well area on one side of the grid layer;
the second doping area is positioned in the well region on the other side of the grid layer, and a third doping area is further formed in the well region between the second doping area and the grid layer;
and the fourth doped region is positioned in the well region on the side, far away from the gate layer, of the second doped region, the first doped region and the second doped region are both doped regions of the first conductivity type, and the third doped region and the fourth doped region are doped regions of the second conductivity type.
Through the technical scheme, after the current enters the semiconductor electrostatic protection region, a large number of holes generated after the current reaches the trigger voltage move to the position of the fourth doping region, when the holes flow to the fourth doping region through the well region, the well region below the second doping region generates a pressure difference to the fourth doping region, and when the pressure difference is larger than 0.7V, a parasitic NPN is formed, so that the current is discharged. The third doped region is arranged, so that on one hand, the distance between the second doped region and the grid layer is increased, and the ESD resistance is improved; on the other hand, the third doped region enables NPN leakage current to be transferred into the body from the surface, and higher voltage is needed to maintain under the same leakage current, so that the maintaining voltage is increased, the effect of maintaining the voltage is improved, and the semiconductor electrostatic protection device can meet the requirement that the common working voltage of the chip function is improved. And the third doped region can be completely and synchronously formed in the fourth doped region, and the structure of the third doped region is not changed too much, so that the cost is greatly reduced.
In one embodiment, the length of the third doped region along the direction from the first doped region to the second doped region is positively correlated to the sustain voltage of the electrostatic protection device.
In one embodiment, a first blocking layer is formed on the upper surface of the third doped region, and the first blocking layer completely covers the upper surface of the third doped region;
the second doped region is adjacent to the third doped region, and the first barrier layer extends to the upper surface of the second doped region.
In one embodiment, the semiconductor device further includes a second blocking layer, the second blocking layer is located on the upper surface of the gate layer, and a projection of the second blocking layer on the upper surface of the substrate is adjacent to a projection of the first blocking layer on the upper surface of the substrate.
In one embodiment, the gate layer, the first doped region, the second doped region, the third doped region and the fourth doped region constitute an electrostatic protection unit, and the well region includes at least two electrostatic protection units.
In one embodiment, at least two of the electrostatic protection units share the same first doped region in the same well region.
In one embodiment, the first doped region is externally connected to a first voltage, and the gate layer, the second doped region and the fourth doped region are externally connected to a second voltage.
In one embodiment, the first voltage is an input/output voltage and the second voltage is a ground voltage.
In one embodiment, an insulating barrier layer is formed on the first doped region, a through hole is formed through the insulating barrier layer, and the first doped region is externally connected with the first voltage through the through hole.
In one embodiment, a shallow trench isolation structure is formed between the second doped region and the fourth doped region.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor electrostatic protection device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of potential connections of a semiconductor ESD protection device in accordance with an embodiment of the present invention;
fig. 3 is a transmission line pulse plot for a semiconductor electrostatic protection device having third doped regions of different sizes in accordance with an embodiment of the present invention.
Reference numerals: 10. a substrate; 11. a well region; 12. a first doped region; 13. a second doped region; 14. a fourth doped region; 15. a third doped region; 16. a gate layer; 161. a gate conductive layer; 162. a gate oxide layer; 17. a first barrier layer; 18. a second barrier layer; 19. an insulating barrier layer; 20. a shallow trench isolation structure; 21. and a through hole.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on methods or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
Protection of each voltage level in a current power management chip or other DC-DC converter, or AC-DC converter, generally uses an ESD protection device corresponding to the voltage level, taking 5V ESD protection devices as an example, usually 5V GGNMOS (Gate group NMOS) and 5V GDPMOS (Gate VDD PMOS), and 5V GGNMOS is most commonly used.
In the conventional 0.18um conventional process, DCG is often used to improve the electrostatic protection capability, but the maintaining voltage Vh thereof always restricts the characteristics of the ESD protection device, and the maintaining voltage of the ESD protection device of 5V is about 5.5V in the 0.18um process, and although the maintaining voltage can be raised by adjusting the channel length, the raising amount is limited, and generally does not exceed 7V. However, as the demand for consumer electronics is higher, the operating voltage of 5V chips will exceed 7V or higher, which requires higher holding voltage for ESD devices.
In order to provide a higher sustain voltage and thus satisfy the improvement of chip function, as shown in fig. 1, the present application provides a semiconductor electrostatic protection device, including: a substrate 10, wherein a well region 11 is formed on the substrate 10; a gate layer 16 located on the upper surface of the well region 11; a first doped region 12 located in the well region 11 on one side of the gate layer 16; the second doped region 13 is positioned in the well region 11 at the other side of the gate layer 16, and a third doped region 15 is further formed in the well region 11 between the second doped region 13 and the gate layer 16; and a fourth doped region 14 located in the well region 11 on a side of the second doped region 13 away from the gate layer 16, wherein the first doped region 12 and the second doped region 13 are both doped regions of the first conductivity type, and the third doped region 15 and the fourth doped region 14 are both doped regions of the second conductivity type.
Through the technical scheme, after the current enters the semiconductor electrostatic protection region, a large number of holes generated after reaching the trigger voltage move to the position of the fourth doping region 14, when the holes flow to the fourth doping region 14 through the well region 11, a pressure difference is generated from the well region 11 to the fourth doping region 14 below the second doping region 13, and when the pressure difference is larger than 0.7V, a parasitic NPN is formed so as to discharge the current. The third doped region 15 is added, so that on one hand, the distance between the second doped region 13 and the gate layer 16 is increased, and the ESD resistance is improved; on the other hand, the third doped region 15 allows the NPN leakage current to be transferred from the surface into the body, and a higher voltage is required to maintain under the same leakage current, which will make the maintenance voltage higher, thereby improving the effect of maintaining the voltage, and enabling the semiconductor electrostatic protection device to meet the requirement of improving the working voltage of the chip function. And the third doped region 15 can be completely formed synchronously with the fourth doped region 14 without making excessive changes on the structure thereof, thereby greatly reducing the cost.
In an alternative embodiment, the material of the substrate 10 may be silicon, germanium, GaAs (gallium arsenide), InP (indium phosphide), GaN (gallium nitride), or the like, i.e., the substrate 10 may be a silicon substrate, a germanium substrate, a GaAs substrate, an InP substrate, a GaN substrate, or the like; in this embodiment, the substrate 10 may be a silicon substrate. Well regions 11 may be formed in the substrate 10 by ion implantation, and the well regions 11 may be P-type well regions.
In an alternative embodiment, the first conductivity type is N-type, and the second conductivity type is P-type, that is, in this embodiment, the first doping region 12 and the second doping region 13 are N-type doping regions, and the fourth doping region 14 and the third doping region 15 are P-type doping regions. And in an alternative embodiment, the first doped region 12 and the second doped region 13 are heavily doped N-type regions, and the fourth doped region 14 and the third doped region 15 are heavily doped P-type regions. The first doped region 12, the second doped region 13, the fourth doped region 14 and the third doped region 15 may be formed in the well region 11 by an ion implantation process, and the region to be ion implanted may be defined by forming a patterned mask layer on the surface of the substrate 10.
The length of the third doped region 15 along the direction from the first doped region 12 to the second doped region 13 is positively correlated to the sustain voltage of the esd protection device. Taking a 5V semiconductor electrostatic protection device in 0.18um process as an example, as shown in fig. 2, the length of the third doped region 15 along the direction from the first doped region 12 to the second doped region 13 is denoted by a, and the four curves in fig. 3 represent the Transmission Line Pulse (TLP) curves of the semiconductor electrostatic protection device when the standard tube without the third doped region 15, a is 0.4um, a is 0.6um, and a is 1um, respectively. It can be seen from the figure that as the value of a increases, the holding voltage also increases, which can reach more than 7V or higher 8V, and the bottleneck that the chip function cannot be improved due to insufficient holding voltage of the semiconductor electrostatic protection device is well solved.
In an alternative embodiment, the first barrier layer 17 is formed on the upper surface of the third doped region 15, and the first barrier layer 17 completely covers the upper surface of the third doped region 15. The material of the first barrier layer 17 may be silicide, such as silicon nitride, silicon carbide, etc. The first barrier layer 17 can prevent the second doped region 13 and the third doped region 15 from being directly connected through a metal layer in a subsequent process of forming the metal layer.
In an alternative embodiment, the second doped region 13 is adjacent to the third doped region 15, and the first barrier layer 17 extends to the upper surface of the second doped region 13. The third doped region 15 is adjacent to the second doped region 13, so that the well region 11 between the second doped region 13 and the gate layer 16 can be made into a P-type heavily doped region to the maximum extent, thereby absorbing the hole current to the maximum extent in practical application. In practical production, the boundary of the first blocking layer 17 is inevitably arranged to fluctuate, and it may occur that the boundary of the first blocking layer 17 on the surface of the third doped region 15 near one side of the second doped region 13 does not completely cover the third doped region 15, so that a metal layer formed subsequently directly connects the second doped region 13 with the third doped region 15. By extending the first barrier layer 17 from the upper surface of the third doped region 15 to cover the border region where the second doped region 13 adjoins the third doped region 15, a space for tolerance is reserved for fluctuations that may occur in actual production, reducing the possibility that the first barrier layer 17 fails to cover the border of the third doped region 15 adjoining the second doped region 13.
In an alternative embodiment, the method further includes a second blocking layer 18, the second blocking layer 18 is located on the upper surface of the gate layer 16, and a projection of the second blocking layer 18 on the upper surface of the substrate 10 is adjacent to a projection of the first blocking layer 17 on the upper surface of the substrate 10. Specifically, the gate layer 16 includes a gate conductive layer 161 and a gate oxide layer 162; the material of the gate conductive layer 161 may be heavily doped polysilicon or metal, such as tungsten, titanium, etc., and the gate oxide layer 162 is made of oxide, including silicon dioxide, etc. The vertical projection of the third doped region 15 on the upper surface of the substrate 10 is adjacent to the vertical projection of the gate layer 16 on the upper surface of the substrate 10, so that the well region 11 between the second doped region 13 and the gate layer 16 is made into a P-type heavily doped region to the maximum extent, and therefore, the hole current collection capacity is larger. The second blocking layer 18 can reduce the possibility of such errors, because the forming position of the first blocking layer 17 may deviate in real production, so that the part of the third doped region 15 close to the gate layer 16 is not completely covered.
In an alternative embodiment, the well region 11 includes at least one esd protection unit, and the esd protection unit includes two esd protection components. The two electrostatic protection devices are arranged in the well 11 in a mirror image manner with the first doped region 12 as a center, and the two electrostatic protection devices in the same electrostatic protection unit share the same first doped region 12.
In an alternative embodiment, as shown in fig. 2, the first doped region 12 is externally connected to a first voltage, and the gate layer 16, the second doped region 13 and the fourth doped region 14 are externally connected to a second voltage. The first voltage is an input/output terminal voltage, and the second voltage is a ground terminal voltage.
In an alternative embodiment, an insulating barrier layer 19 is formed on the first doped region 12, a through hole 21 is formed through the insulating barrier layer 19, and the first doped region 12 is externally connected to the first voltage through the through hole 21. The material of the insulating barrier layer 19 may be silicide, such as silicon nitride or silicon carbide, and may be identical to the first barrier layer 17 and the second barrier layer 18. The insulating barrier layer 19 may be formed on the first barrier layer 17 and the second barrier layer 18 in the same process, and specifically includes the following steps: depositing a photoresist layer on the upper surface of the substrate 10 and the upper surface of the gate layer 16; carrying out graphical processing on the photoresist layer by exposure and development; the photoresist layer after the patterning process covers all the areas except the area where the third doped region 15 is located, the boundary area of the second doped region 13 close to the third doped region 15, the boundary area of the gate layer 16 close to the third doped region 15 and the areas outside the two side areas of the first doped region 12; depositing a barrier material layer which can be a silicon nitride layer or a silicon carbide layer; and removing the barrier material layer on the upper surface of the photoresist layer and removing the photoresist layer.
In an alternative embodiment, the insulating barrier layer 19 is also formed on the gate layer 16 near the boundary region of the first doped region 12 to reduce the production error that may occur in the actual production process.
In an alternative embodiment, a shallow trench isolation structure 20 is formed between the second doped region 13 and the fourth doped region 14. The shallow trench isolation structure 20 can effectively isolate the second doped region 13 from the fourth doped region 14, and reduce the mutual influence between the two regions. The specific forming process comprises the following steps: forming a patterned mask layer on the upper surface of the substrate 10, wherein the patterned mask layer exposes the well region 11 between the second doped region 13 and the fourth doped region 14; etching the well region 11 by adopting a dry etching or wet etching process so as to form a groove; depositing an isolation structure material layer in the groove and on the upper surface of the patterned mask layer, wherein the isolation structure material layer can be an oxide layer or an isolation structure material layer formed by oxidation in other implementations; and grinding to remove the isolation structure material layer on the upper surface of the patterned grinding layer and removing the patterned mask layer to form the shallow trench isolation structure 20.
Through the above technical solution, after the first doped region 12 is connected to the input/output voltage, a large number of holes generated in the well region 11 move to the position of the fourth doped region 14, when the holes flow to the fourth doped region 14 through the well region 11, a voltage difference is generated from the well region 11 to the fourth doped region 14 under the second doped region 13, and when the voltage difference is greater than 0.7V, a parasitic NPN is formed to discharge the current. The third doped region 15 is added, so that on one hand, the distance between the second doped region 13 and the gate layer 16 is increased, and the ESD resistance is improved; on the other hand, the third doped region 15 allows the NPN leakage current to be transferred from the surface into the body, and a higher voltage is required to maintain under the same leakage current, which will make the maintenance voltage higher, thereby improving the effect of maintaining the voltage, and enabling the semiconductor electrostatic protection device to meet the requirement of improving the common working voltage of the chip function. And the third doped region 15 can be completely formed synchronously with the fourth doped region 14 without making excessive changes on the structure thereof, thereby greatly reducing the cost.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A semiconductor electrostatic protection device, comprising:
the semiconductor device comprises a substrate, a first semiconductor layer and a second semiconductor layer, wherein a well region is formed on the substrate;
the grid layer is positioned on the upper surface of the well region;
the first doping area is positioned in the well area on one side of the grid layer;
the second doping area is positioned in the well region on the other side of the grid layer, and a third doping area is further formed in the well region between the second doping area and the grid layer;
and the fourth doped region is positioned in the well region on the side, far away from the gate layer, of the second doped region, the first doped region and the second doped region are both doped regions of the first conductivity type, and the third doped region and the fourth doped region are doped regions of the second conductivity type.
2. The semiconductor electrostatic protection device of claim 1, wherein a length of the third doped region along a direction from the first doped region to the second doped region is positively correlated to a sustain voltage of the electrostatic protection component.
3. The electrostatic protection device for semiconductor of claim 1, wherein a first barrier layer is formed on the upper surface of the third doped region, and the first barrier layer completely covers the upper surface of the third doped region;
the second doped region is adjacent to the third doped region, and the first barrier layer extends to the upper surface of the second doped region.
4. The semiconductor electrostatic protection device according to claim 3, further comprising a second barrier layer, wherein the second barrier layer is located on the upper surface of the gate layer, and a projection of the second barrier layer on the upper surface of the substrate is adjacent to a projection of the first barrier layer on the upper surface of the substrate.
5. The semiconductor electrostatic protection device according to claim 1, wherein the gate layer, the first doped region, the second doped region, the third doped region and the fourth doped region constitute an electrostatic protection unit, and at least two electrostatic protection units are included in the well region.
6. The semiconductor electrostatic protection device according to claim 5, wherein at least two electrostatic protection units in the same well region share the same first doped region.
7. The device of claim 1, wherein the first doped region is externally coupled to a first voltage, and the gate layer, the second doped region and the fourth doped region are externally coupled to a second voltage.
8. The semiconductor electrostatic protection device according to claim 7, wherein the first voltage is an input/output voltage, and the second voltage is a ground voltage.
9. The semiconductor electrostatic protection device according to claim 7, wherein an insulating barrier layer is formed on the first doped region, a through hole is formed through the insulating barrier layer, and the first doped region is externally connected to the first voltage through the through hole.
10. The electrostatic protection device for semiconductor of claim 1, wherein a shallow trench isolation structure is formed between the second doped region and the fourth doped region.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011184992.XA CN114446944A (en) | 2020-10-30 | 2020-10-30 | Semiconductor electrostatic protection device |
| PCT/CN2021/088109 WO2022088619A1 (en) | 2020-10-30 | 2021-04-19 | Semiconductor electrostatic protection device |
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| CN202011184992.XA CN114446944A (en) | 2020-10-30 | 2020-10-30 | Semiconductor electrostatic protection device |
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| KR101146217B1 (en) * | 2005-06-30 | 2012-05-25 | 매그나칩 반도체 유한회사 | Semiconductor device |
| KR101091126B1 (en) * | 2009-07-20 | 2011-12-09 | 주식회사 바우압텍 | Electro-Static Discharge Protection Device for high voltage operation |
| CN106298777B (en) * | 2016-09-27 | 2019-06-04 | 上海华力微电子有限公司 | A kind of GGNMOS device and preparation method thereof as ESD protection |
| KR20200074581A (en) * | 2018-12-17 | 2020-06-25 | 에스케이하이닉스 주식회사 | Electrostatic Discharge Protection Device |
| CN111430306B (en) * | 2020-03-31 | 2022-08-12 | 中国电子科技集团公司第五十八研究所 | GGNMOS device preparation process for thin epitaxial process ESD protection and GGNMOS device |
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