CN108364945B - Double-gate-controlled electrostatic discharge device for improving holding voltage and manufacturing method thereof - Google Patents
Double-gate-controlled electrostatic discharge device for improving holding voltage and manufacturing method thereof Download PDFInfo
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
- H01L27/0274—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the field effect transistor, e.g. gate coupled transistors
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Abstract
The invention discloses a double-grid-control electrostatic discharge device for improving a holding voltage, which comprises a substrate, wherein an HVNW (high voltage-nitride-field-effect transistor) region is arranged in the substrate, a P-body region and an NDD (non-grid-drive) region are arranged in the HVNW region, a first P + injection region, a first N + injection region, a first polysilicon grid and a second N + injection region are arranged in the P-body region, a second polysilicon grid stretches across between the HVNW region and the P-body region, and a third N + injection region is arranged in the NDD region, wherein the first N + injection region, the first polysilicon grid, the second N + injection region, the second polysilicon grid and the third N + injection region form a double-grid MOSFET (metal-oxide-semiconductor field effect transistor) structure.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a double-gate-controlled electrostatic discharge device for improving a holding voltage and a manufacturing method thereof.
Background
In the past decades, electronic technology has developed at a high speed, electronic products have become indispensable parts in people's lives, and integrated circuits are applied to the aspects of people's lives, thereby greatly improving the quality of life and the standard of life of people. The development of integrated circuits still follows the direction guided by moore's law, i.e., higher integration of devices, larger scale, smaller size, etc.
Electrostatic discharge (ESD) is a fatal cause of failure of integrated circuits, and with the progress of semiconductor process level, ESD protection is more and more emphasized, and according to statistics of related data, in the microelectronic field, the failure of integrated circuits caused by ESD phenomenon is about 58%, and the data also fully illustrates the importance of ESD protection in the microelectronic field, and a good ESD protection can effectively improve the reliability of products. In high-voltage application, the factors of high voltage, large current, strong electromagnetic interference and the like bring great inconvenience to the design of ESD protection, and the factors of small occupied area and strong discharge capacity are the difficulties which need to be overcome by designers of the current integrated circuits.
The traditional L DMOS structure device is named as a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), is used for an ESD protection device of a high-voltage process and has strong ESD resistance, the traditional L DMOS structure is the most widely applied ESD protection device in the high-voltage field, and various modified L DMOS structure electrostatic protection devices are widely applied to various high-voltage environments.
The cross-sectional view and equivalent circuit of a conventional ESD protection device of L DMOS structure are shown in fig. 1, L DMOS structure is a forward-conducting diode characteristic when working in reverse, the reverse-discharging ESD pulse capability is very strong, when L DMOS structure works in forward, when the voltage difference between the anode and the cathode reaches the turn-on voltage of the device, avalanche breakdown occurs between HVNW and P-body, and multiplied avalanche carriers are generated, a large number of avalanche multiplied carriers flow through the parasitic resistance Rp of P-body to generate voltage drop, and when the voltage drop reaches the BE junction turn-on voltage of parasitic NPN triode structure, the NPN is turned on, thereby discharging ESD current, at this time, the voltage is stagnated to the holding voltage, the L DMOS structure works in the low-resistance region, when the current finally increases to cause thermal failure of the device, secondary breakdown occurs, and at this time, the ESD protection device of L DMOS structure is completely failed.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a dual-gate electrostatic discharge device with a simple structure and capable of increasing a sustain voltage, and a method for manufacturing the same.
The technical scheme for solving the problems is as follows: a double-grid-control electrostatic discharge device for improving the holding voltage comprises a substrate, an HVNW region, a P-body region, an NDD region, a first P + injection region, a first N + injection region, a second N + injection region, a third N + injection region, a first polysilicon grid and a second polysilicon grid, wherein the substrate is internally provided with the HVNW region, the HVNW region is internally provided with the P-body region and the NDD region from left to right in sequence, the P-body region is internally provided with the first P + injection region, the first N + injection region, the first polysilicon grid and the second N + injection region from left to right in sequence, the second polysilicon grid stretches across between the HVNW region and the P-body region, and the NDD region is internally provided with the third N + injection region; the first N + injection region, the first polysilicon gate, the second N + injection region, the second polysilicon gate and the third N + injection region form a double-gate MOSFET (metal-oxide-semiconductor field effect transistor) structure.
In the double-gate electrostatic discharge device for improving the holding voltage, the left side of the P-body region is connected with the left side edge of the HVNW region, the left side of the first P + injection region is connected with the left side edge of the P-body region, the right side of the first P + injection region is connected with the left side of the first N + injection region, the right side of the first N + injection region is connected with the left side of the first polysilicon gate, the right side of the first polysilicon gate is connected with the left side of the second N + injection region, the right side of the second N + injection region is connected with the left side of the second polysilicon gate, the right side of the second polysilicon gate is connected with the left side edge of the NDD region, the right side of the NDD region is connected with the right side edge of the HVNW region, and the right side of the third N + injection region is connected with the right side edge of the NDD region.
In the double-gate-controlled electrostatic discharge device for improving the holding voltage, the first P + injection region, the first N + injection region and the first polysilicon gate are connected together and used as the cathode of the device; the second polysilicon gate is used as a control gate of the device; the third N + injection region serves as an anode of the device.
In the double-gate-controlled electrostatic discharge device for improving the holding voltage, the left half part of the first P + injection region is located on the surface of the P-body region, and the right half part of the first P + injection region is completely located in the P-body region; the left half of the third N + implant region is located entirely within the NDD region and the right half of the third N + implant region is located at a surface of the NDD region.
When the high-voltage pulse of the ESD is applied to the anode of the device and the cathode of the device is at the ground potential, the first N + injection region, the P-body region and the HVNW region form a longitudinal NPN triode structure, the base of the longitudinal NPN triode structure is connected with the parasitic resistor of the P-body region, namely the longitudinal NPN triode structure forms a BJT transistor structure.
When the ESD high-voltage pulse falls to the anode of the device and the cathode of the device is at the ground potential, the first polysilicon gate is at the ground potential, a forward voltage is applied to the second polysilicon gate structure, the HVNW region and the P-body region are subjected to avalanche breakdown, and the double-gate MOSFET structure after the device is triggered is equivalent to a variable resistor connected in series on the collector of a parasitic NPN triode structure.
A manufacturing method of a double-gate-control electrostatic discharge device for improving the holding voltage comprises the following steps:
the method comprises the following steps: forming an HVNW region in a substrate;
step two: forming a P-body region and an NDD region in the HVNW region, wherein the P-body region is located on the left side of the NDD region;
step three: annealing the HVNW region, the P-body region and the NDD region to eliminate impurity diffusion;
step four: depositing a first polysilicon gate on the P-body region, and depositing a second polysilicon gate at the junction of the P-body region and the HVNW region;
step five: forming a first P + injection region, a first N + injection region and a second N + injection region in the P-body region, wherein the first P + injection region, the first N + injection region, the first polysilicon gate, the second N + injection region and the second polysilicon gate are sequentially connected, and forming a third N + injection region in the NDD region;
step six: annealing the first P + injection region, the first N + injection region, the second N + injection region and the third N + injection region to eliminate the migration of impurities in the injection regions;
step seven: connecting the first P + injection region, the first N + injection region and the first polysilicon gate together and using the first P + injection region, the first N + injection region and the first polysilicon gate as a cathode of the device; taking the second polysilicon gate as a control gate of the device; the third N + implant region serves as the anode of the device.
The manufacturing method of the double-gate-controlled electrostatic discharge device for improving the holding voltage further comprises the following steps before the first step: forming a layer of silicon dioxide film on a substrate, and then depositing a layer of silicon nitride; coating a photoresist layer on a wafer, and exposing and developing the photoresist to form an isolation shallow groove; and etching the silicon nitride, the silicon dioxide and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then polishing by a chemical machine until reaching the silicon nitride layer to remove the silicon nitride layer.
In the manufacturing method of the double-gate-controlled electrostatic discharge device for improving the holding voltage, the left half part of the first P + injection region is located on the surface of the P-body region, and the right half part of the first P + injection region is completely located in the P-body region; the left half of the third N + implant region is located entirely within the NDD region and the right half of the third N + implant region is located at a surface of the NDD region.
In the third step, an RTP process is adopted to eliminate the diffusion of impurities; in the sixth step, an RTP process is adopted to eliminate the migration of impurities in the injection region.
The invention has the beneficial effects that:
1. the electrostatic discharge device adopts a double-gate MOSFET structure, an avalanche breakdown path of a traditional L DMOS structure is not changed, the trigger voltage of the electrostatic discharge device is still the trigger voltage of a traditional L DMOS device, namely avalanche breakdown occurs in the HVNW region and the P-body region, and the avalanche breakdown path is not changed, so that the trigger voltage is not improved.
2. The electrostatic discharge device adopts a double-grid MOSFET (metal oxide semiconductor field effect transistor) structure, a first polysilicon grid structure is grounded, a forward voltage is applied to a second polysilicon grid structure, the double-grid MOSFET structure after the electrostatic discharge device is triggered is equivalent to a variable resistor connected in series on a collector of a parasitic NPN triode structure at the moment, due to the existence of the variable resistor, the collector current of the parasitic NPN triode structure is reduced, the emitter current of the parasitic NPN triode structure is reduced, the current amplification coefficient of the parasitic NPN triode structure is reduced, the maintaining voltage of an L DMOS device is directly improved due to the reduction of the current amplification coefficient, the phenomenon of uneven conduction of a L DMOS device is inhibited, the integral secondary breakdown current of the DMOS L DMOS device is improved, and meanwhile, the maintaining voltage of the L DMOS structure can be directly adjusted according to the applied forward voltage by applying the forward voltage to the second polysilicon grid structure.
3. The manufactured double-gate-controlled L DMOS electrostatic discharge device structure does not violate the rule of layout design, and does not use the process except the standard CMOS process, so that the L DMOS can be applied to the ESD protection design, the internal chip is effectively protected, and the ESD robustness of the device is improved.
Drawings
Fig. 1 is a cross-sectional view and a schematic parasitic structure of a conventional L DMOS structure.
Fig. 2 is a schematic structural diagram of an electrostatic discharge device of the present invention.
Fig. 3 is a schematic diagram of a three-dimensional parasitic structure of the electrostatic discharge device of the present invention.
Fig. 4 is a schematic diagram of an ESD current discharge path of the ESD discharging device of the present invention.
Fig. 5 is a top view of the electrostatic discharge device structure of the present invention.
Detailed Description
The invention is further described below with reference to the figures and examples.
As shown in fig. 2 and 3, a double-gate-controlled electrostatic discharge device for increasing a sustain voltage includes a substrate P-SUB101, an HVNW region 102, a P-body region 103, an NDD region 104, a first P + implantation region 105, a first N + implantation region 106, a second N + implantation region 107, a third N + implantation region 108, a first polysilicon gate 201, and a second polysilicon gate 202, wherein the substrate P-SUB101 has the HVNW region 102, the HVNW region 102 has the P-body region 103 and the NDD region 104 arranged from left to right, the P-body region 103 has the first P + implantation region 105, the first N + implantation region 106, the first polysilicon gate 201, the second N + implantation region 107 arranged from left to right, the second polysilicon gate 202 spans between the HVNW region 102 and the P-body region 103, and the NDD region 104 has the third N + implantation region 108 arranged therein; the first N + implantation region 106, the first polysilicon gate 201, the second N + implantation region 107, the second polysilicon gate 202, and the third N + implantation region 108 form a dual-gate MOSFET field effect transistor structure, which can improve the holding voltage of the device structure to enhance the ESD robustness of the device.
The left side of the P-body region 103 is connected to the left edge of the HVNW region 102, the left side of the first P + implantation region 105 is connected to the left edge of the P-body region 103, the right side of the first P + implantation region 105 is connected to the left side of the first N + implantation region 106, the right side of the first N + implantation region 106 is connected to the left side of the first polysilicon gate 201, the right side of the first polysilicon gate 201 is connected to the left side of the second N + implantation region 107, the right side of the second N + implantation region 107 is connected to the left side of the second polysilicon gate 202, the right side of the second polysilicon gate 202 is connected to the left edge of the NDD region 104, the right side of the hvndd region 104 is connected to the right edge of the HVNW region 102, and the right side of the third N + implantation region 108 is connected to the right edge of the NDD region 104.
The first P + injection region 105 is connected with the first metal layer 203 through a contact hole, the first N + injection region 106 is connected with the second metal layer 204 through a contact hole, the first polysilicon gate 201 is connected with the third metal layer 205 through a contact hole, a metal through hole 301 is formed in the sixth metal layer 302, and the first metal layer 203, the second metal layer 204 and the third metal layer 205 are all connected with the sixth metal layer 302 through the metal through hole 301 and used as a cathode of a device.
The second polysilicon gate 202 is connected to the fourth metal layer 206 through a contact hole, a metal through hole 303 is formed in the seventh metal layer 304, and the fourth metal layer 206 is connected to the seventh metal layer 304 through the metal through hole 303 and serves as a control gate of a device.
The third N + injection region 108 is connected to the fifth metal layer 207 through a contact hole, a metal through hole 305 is formed in the eighth metal layer 306, and the fifth metal layer 207 is connected to the eighth metal layer 306 through the metal through hole 305 and serves as an anode of a device.
The left half of the first P + implant region 105 is located on the surface of the P-body region 103, and the right half of the first P + implant region 105 is located entirely in the P-body region 103; the left half of the third N + implant region 108 is located entirely within the NDD region 104, and the right half of the third N + implant region 108 is located at the surface of the NDD region 104.
When the ESD high voltage pulse arrives at the anode of the device and the cathode of the device is grounded, the first N + injection region 106, the P-body region 103 and the HVNW region 102 form a vertical NPN transistor structure, and the base of the vertical NPN transistor structure is connected to the parasitic resistance of the P-body region 103, i.e., the vertical NPN transistor structure forms a BJT transistor structure.
When the ESD high voltage pulse reaches the anode of the device and the cathode of the device is at the ground potential, the first polysilicon gate 201 is at the ground potential, and a forward voltage is applied to the second polysilicon gate 202 structure, so that the HVNW region 102 and the P-body region 103 are subjected to avalanche breakdown, and the double-gate MOSFET field effect transistor structure after the device is triggered is equivalent to a variable resistor connected in series to the collector of the parasitic NPN triode structure.
The electrostatic discharge device adopts a double-gate MOSFET structure, an avalanche breakdown path of a traditional L DMOS structure is not changed, the trigger voltage of the device is still the trigger voltage of a traditional L DMOS device, namely avalanche breakdown occurs in the HVNW region 102 and the P-body region 103, the trigger voltage is not improved because the avalanche breakdown path is not changed, the double-gate MOSFET structure after the device triggering is equivalent to a variable resistor connected in series with a collector of a parasitic NPN triode structure due to embedding the double-gate MOSFET structure in the L DMOS structure, grounding a first polysilicon gate 201 structure, applying forward voltage to a second polysilicon gate 202 structure, reducing a collector current of the parasitic NPN triode structure due to the existence of the variable resistor, reducing an emitter current of the parasitic NPN triode structure, reducing a current amplification coefficient of the parasitic NPN triode structure, directly increasing a maintenance voltage of the L DMOS device, inhibiting an uneven conduction phenomenon of an L device, increasing L of the device, and controlling the overall secondary current breakdown of the parasitic NPN triode structure through the parasitic current amplification factor, so that the parasitic NPN transistor structure is embedded in a parasitic triode structure, the parasitic triode structure is not influenced by the parasitic current amplification angle of the parasitic DMOS 355635, and the parasitic triode structure is proved to be capable of controlling the parasitic triode structure, so that the parasitic triode structure is not increased, the parasitic triode structure, so that the parasitic triode structure is improved.
A double-grid-control L DMOS electrostatic discharge device structure for improving holding voltage is disclosed, for formula (1), Ic is collector current, β is current amplification factor, I isBIs the base current.
Ic＝β*IB(1)
IE＝IB+IC＝(1+β)*IB(2)
From the formula, it can be found that when β is constant, the collector current ICWill follow the base current IBThe change of the voltage is changed, and at the moment, in the double-grid-control L DMOS electrostatic discharge device structure, through the double-grid MOSFET field effect tube structure, the equivalent is that a variable resistor is connected in series on the collector of the parasitic NPN triode, so that the collector current is controlled through the magnitude of the external voltage, and the formula (2) shows that I isEFor the emitter current, the collector current Ic is reduced by controlling the collector current of the parasitic NPN triode, resulting in a reduction of the emitter current IEThe current amplification factor of the parasitic NPN transistor is reduced, so that it is proved from the viewpoint of the current amplification factor that the sustain voltage of the L DMOS structure can be improved.
The emission efficiency of the parasitic NPN transistor can be adjusted by adjusting the voltage of the second polysilicon gate 202 of the dual-gate MOSFET fet structure, so as to control the magnitude of the holding voltage of the L DMOS structure, thereby enabling the device structure to generate the holding voltage required for the actual ESD window.
A manufacturing method of a double-gate-control electrostatic discharge device for improving the holding voltage comprises the following steps:
the method comprises the following steps: and forming a silicon dioxide film on the substrate P-SUB101 by thermal oxidation to relieve the stress of silicon nitride formed in the subsequent steps on the silicon substrate, and then depositing a layer of silicon nitride by Chemical Vapor Deposition (CVD) to be used as a stop layer for the subsequent CMP.
A photoresist layer is coated on the wafer, and the photoresist is exposed and developed for the definition of the isolation shallow trench. Etching the silicon nitride, the silicon dioxide and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide by using Chemical Vapor Deposition (CVD), then polishing by using a chemical machine until reaching the silicon nitride layer, and removing the silicon nitride layer by using hot phosphoric acid wet etching.
Step two: HVNW region 102 is formed in substrate P-SUB 101. Photoresist is coated on a wafer and used for defining the HVNW region 102, high-energy phosphorus ions are implanted twice to form a local N-type region, and the photoresist layer is removed to form the HVNW region 102.
Step three, forming a P-body area 103 and an NDD area 104 in the HVNW area 102, wherein the P-body area 103 is positioned at the left side of the NDD area 104, coating photoresist on the wafer for defining the P-body area 103 (the P-body is the general name of L VPW and HVPW), then implanting high-energy boron ions to form a local P-type area, removing the photoresist to form the P-body area 103, coating the photoresist on the wafer for defining the NDD area 104, then implanting high-energy phosphorus ions to form a local N-type area, removing the photoresist layer to form the NDD area 104.
Step four: annealing treatment is performed on the HVNW region 102, the P-body region 103 and the NDD region 104 to repair damage of silicon surface crystals caused by ion implantation, activation of implanted impurities, and elimination of diffusion of impurities by an RTP process.
Step five: a first polysilicon gate 201 is deposited over the P-body region 103 and a second polysilicon gate 202 is deposited at the intersection of the P-body region 103 and the HVNW region 102. The sacrificial oxide layer grows to trap silicon surface defects. The gate oxide layer grows to be used as a gate insulating layer of a transistor, the first polysilicon gate 201 and the second polysilicon gate 202 are deposited by Chemical Vapor Deposition (CVD), photoresist is formed, polysilicon etching is performed, the specific shape of polysilicon must be accurately obtained from the photoresist, and the photoresist layer is removed. And oxidizing the polysilicon to buffer and isolate the polysilicon and the silicon nitride formed in the subsequent step. And depositing a layer of silicon nitride by using Chemical Vapor Deposition (CVD), etching the silicon nitride, leaving the isolation side wall, and accurately positioning the ion implantation of the source region and the drain region of the transistor.
Step six: a first P + implantation region 105, a first N + implantation region 106 and a second N + implantation region 107 are formed in the P-body region 103, and the first P + implantation region 105, the first N + implantation region 106, the first polysilicon gate 201, the second N + implantation region 107 and the second polysilicon gate 202 are sequentially connected to form a third N + implantation region 108 in the NDD region 104.
And forming photoresist for controlling ion implantation, implanting shallow-depth and heavily-doped boron ions, and removing the photoresist layer to form the first P + implantation region 105. And forming photoresist, wherein the photoresist is used for controlling ion implantation, implanting arsenic ions with shallow depth and heavy doping, removing the photoresist layer, and forming the first N + implantation region 106, the second N + implantation region 107 and the third N + implantation region 108. The left half of the first P + implant region 105 is located on the surface of the P-body region 103, and the right half of the first P + implant region 105 is located entirely in the P-body region 103; the left half of the third N + implant region 108 is located entirely within the NDD region 104, and the right half of the third N + implant region 108 is located at the surface of the NDD region 104.
Step seven: annealing treatment is performed on the first P + implantation region 105, the first N + implantation region 106, the second N + implantation region 107 and the third N + implantation region 108, and migration of impurities in the implantation regions is eliminated by an RTP process.
Step eight: connecting the first P + implantation region 105, the first N + implantation region 106 and the first polysilicon gate 201 together and serving as a cathode of the device; the second polysilicon gate 202 is used as a control gate of the device; the third N + implant region 108 serves as the anode of the device.
The manufacturing method of the electrostatic discharge device is simple in process and convenient to operate, the manufactured double-gate-controlled L DMOS electrostatic discharge device does not violate the rule of layout design, and processes except a standard CMOS process are not used, so that L DMOS can be applied to ESD protection design, an internal chip is effectively protected, and the ESD robustness of the device is improved.
Claims (8)
1. A double-grid control electrostatic discharge device for improving the holding voltage is characterized in that: the HVNW/NDD/P + dual-gate structure comprises a substrate, an HVNW area, a P-body area, an NDD area, a first P + injection area, a first N + injection area, a second N + injection area, a third N + injection area, a first polysilicon gate and a second polysilicon gate, wherein the substrate is provided with the HVNW area, the P-body area and the NDD area are sequentially arranged in the HVNW area from left to right, the P-body area is sequentially provided with the first P + injection area, the first N + injection area, the first polysilicon gate and the second N + injection area from left to right, the second polysilicon gate stretches across between the HVNW area and the P-body area, and the NDD area is provided with the third N + injection area; the first N + injection region, the first polysilicon gate, the second N + injection region, the second polysilicon gate and the third N + injection region form a double-gate MOSFET (metal-oxide-semiconductor field effect transistor) structure;
the left side of the P-body region is connected with the left side edge of the HVNW region, the left side of the first P + injection region is connected with the left side edge of the P-body region, the right side of the first P + injection region is connected with the left side of the first N + injection region, the right side of the first N + injection region is connected with the left side of the first polysilicon gate, the right side of the first polysilicon gate is connected with the left side of the second N + injection region, the right side of the second N + injection region is connected with the left side of the second polysilicon gate, the right side of the second polysilicon gate is connected with the left side edge of the NDD region, the right side of the NDD region is connected with the right side edge of the HVNW region, and the right side of the third N + injection region is connected with the right side edge of the NDD region;
the first P + injection region, the first N + injection region and the first polysilicon gate are connected together and used as a cathode of the device; the second polysilicon gate is used as a control gate of the device; the third N + injection region serves as an anode of the device.
2. The double-gate-controlled electrostatic discharge device for increasing the sustaining voltage according to claim 1, wherein: the left half part of the first P + injection region is positioned on the surface of the P-body region, and the right half part of the first P + injection region is completely positioned in the P-body region; the left half of the third N + implant region is located entirely within the NDD region and the right half of the third N + implant region is located at a surface of the NDD region.
3. The double-gate-controlled electrostatic discharge device for increasing the sustaining voltage according to claim 1, wherein: when the ESD high-voltage pulse arrives at the anode of the device and the cathode of the device is grounded, the first N + injection region, the P-body region and the HVNW region form a longitudinal NPN triode structure, the base of the longitudinal NPN triode structure is connected with the parasitic resistor of the P-body region, namely the longitudinal NPN triode structure forms a BJT transistor structure.
4. The double-gate-controlled electrostatic discharge device for increasing the sustaining voltage according to claim 3, wherein: when the ESD high-voltage pulse reaches the anode of the device and the cathode of the device is at the ground potential, the first polysilicon gate is at the ground potential, a forward voltage is applied to the second polysilicon gate structure, the HVNW region and the P-body region are subjected to avalanche breakdown, and the double-gate MOSFET structure after the device is triggered is equivalent to a variable resistor which is connected in series on the collector of a parasitic NPN triode structure.
5. A method for manufacturing the double-gate-controlled electrostatic discharge device for improving the holding voltage according to any one of claims 1 to 4, comprising the following steps:
the method comprises the following steps: forming an HVNW region in a substrate;
step two: forming a P-body region and an NDD region in the HVNW region, wherein the P-body region is located on the left side of the NDD region;
step three: annealing the HVNW region, the P-body region and the NDD region to eliminate impurity diffusion;
step four: depositing a first polysilicon gate on the P-body region, and depositing a second polysilicon gate at the junction of the P-body region and the HVNW region;
step five: forming a first P + injection region, a first N + injection region and a second N + injection region in the P-body region, wherein the first P + injection region, the first N + injection region, the first polysilicon gate, the second N + injection region and the second polysilicon gate are sequentially connected, and forming a third N + injection region in the NDD region;
step six: annealing the first P + injection region, the first N + injection region, the second N + injection region and the third N + injection region to eliminate the migration of impurities in the injection regions;
step seven: connecting the first P + injection region, the first N + injection region and the first polysilicon gate together and using the first P + injection region, the first N + injection region and the first polysilicon gate as a cathode of the device; taking the second polysilicon gate as a control gate of the device; the third N + implant region serves as the anode of the device.
6. The method as claimed in claim 5, further comprising a step a before the step one: forming a layer of silicon dioxide film on a substrate, and then depositing a layer of silicon nitride; coating a photoresist layer on a wafer, and exposing and developing the photoresist to form an isolation shallow groove; and etching the silicon nitride, the silicon dioxide and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then polishing by a chemical machine until reaching the silicon nitride layer to remove the silicon nitride layer.
7. The method of claim 6, wherein the method comprises: the left half part of the first P + injection region is positioned on the surface of the P-body region, and the right half part of the first P + injection region is completely positioned in the P-body region; the left half of the third N + implant region is located entirely within the NDD region and the right half of the third N + implant region is located at a surface of the NDD region.
8. The method of claim 5, wherein the method comprises: in the third step, an RTP process is adopted to eliminate the diffusion of impurities; in the sixth step, an RTP process is adopted to eliminate the migration of impurities in the injection region.
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| CN105390491A (en) * | 2015-12-17 | 2016-03-09 | 江南大学 | LDMOS-SCR device with source-end embedded finger NMOS |
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| US6413806B1 (en) * | 2000-02-23 | 2002-07-02 | Motorola, Inc. | Semiconductor device and method for protecting such device from a reversed drain voltage |
| TWI231035B (en) * | 2004-02-13 | 2005-04-11 | Vanguard Int Semiconduct Corp | High voltage ESD protection device having gap structure |
| KR102374203B1 (en) * | 2015-08-31 | 2022-03-15 | 삼성전자주식회사 | Electrostatic discharge protection device and electronic device having the same |
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| CN101034671A (en) * | 2006-03-02 | 2007-09-12 | 沃特拉半导体公司 | Lateral double-diffused mosfet (ldmos) transistor and a method of fabricating the same |
| CN105390491A (en) * | 2015-12-17 | 2016-03-09 | 江南大学 | LDMOS-SCR device with source-end embedded finger NMOS |
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