CN214848631U - Low-voltage grid unidirectional silicon controlled electrostatic protection device - Google Patents
Low-voltage grid unidirectional silicon controlled electrostatic protection device Download PDFInfo
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Abstract
The embodiment of the utility model provides a low pressure area bars one-way silicon controlled rectifier electrostatic protection device, include: a P-type substrate; an N-type buried layer, an N-type deep well region and a P-type deep well region are arranged in the P-type substrate; the N-type deep well comprises a first N-well, the P-type deep well comprises a second P-well, the N-type deep well and the first N-well are not of equal width, and the P-type deep well and the second P-well are not of equal width; the first N trap is provided with a first N + injection, a second P + injection and a third N + injection; a fourth P + injection is arranged on the N-type deep well; a second P well is arranged on the P type deep well; the left part of the fifth N + injection is arranged on the N-type deep well, and the right part of the fifth N + injection is arranged on the P-type deep well and the second P well; the left part of the sixth N + injection is arranged on the second P well, and the right part of the sixth N + injection is arranged on the P-type deep well; a seventh P + injection is arranged on the P-type deep well; the polysilicon gate is arranged on the second P well; two electrodes of the P-type deep well and a grid electrode on the second P well are connected together and used as a cathode of the device, and two electrodes in the first N well are connected together and used as an anode of the device.
Description
Technical Field
The utility model relates to an electrostatic protection field especially relates to a low pressure area bars one-way silicon controlled rectifier electrostatic protection device.
Background
With the progress of semiconductor manufacturing processes, the failure of integrated circuit chips and electronic products caused by ESD is becoming more serious. ESD protection of electronic products and integrated circuit chips has become one of the major challenges facing product engineers.
The modes of ESD induced failure are hard failure, soft failure, and latent failure, respectively. The causes of these failures can be further divided into electrical failures and thermal failures. The thermal failure means that when an ESD pulse comes, a current of several amperes to several tens of amperes is generated locally on the chip, the duration is short, but a large amount of heat is generated, so that local metal wires are melted or a chip is hot-spotted, and secondary breakdown is caused. Electrical failure means that the voltage applied to the gate oxide layer creates an electric field with a strength greater than the dielectric strength, causing a surface breakdown or dielectric breakdown. Because the threat of ESD to chips is getting more and more serious, the research on the physical mechanism is getting more and more attention.
Compared with other ESD devices, the traditional silicon controlled device has a double-conductance modulation mechanism, high unit area discharge efficiency, small unit parasitic capacitance and best robustness. However, since the trigger voltage is high, the latch-up is easily caused by the low holding voltage, and the design is important.
The cross-sectional view of the conventional low-voltage thyristor electrostatic discharge protection device is shown in fig. 1, and the equivalent circuit diagram thereof is shown in fig. 2. When an ESD pulse is applied to the SCR anode, the N + injection and the P well form a reverse biased PN junction. When the pulse voltage is higher than the avalanche breakdown voltage of the PN junction, a large amount of avalanche current is generated in the device, and the current flows through the P trap and flows to the cathode through the parasitic resistance. The voltage drop of the two ends of the parasitic resistor of the P trap is equivalent to the base voltage drop of the NPN transistor, and when the voltage is higher than the forward conducting voltage of the longitudinal NPN transistor, the transistor is turned on. After the triode is switched on, base current is provided for the vertical PNP triode, and after the vertical PNP triode is also switched on, base current is further provided for the transverse NPN triode, so that a positive feedback mechanism is formed, and the SCR path is completely switched on. Therefore, even if there is no avalanche current after the current is discharged, a large current can be discharged because the transistor is turned on. The low-voltage unidirectional silicon controlled rectifier can provide electrostatic protection for a circuit with working signals only having positive voltage, and the protection capability of the low-voltage unidirectional silicon controlled rectifier electrostatic device is greatly reduced due to the fact that large current passes through a surface path of the device and is particularly easy to cause thermal failure of the device.
SUMMERY OF THE UTILITY MODEL
The utility model provides a simple structure's one-way silicon controlled rectifier electrostatic protection device of low pressure area bars.
In order to achieve the above object, the embodiment of the present invention provides a technical solution that:
the embodiment of the utility model provides a pair of low pressure area bars one-way silicon controlled rectifier electrostatic protection device, include:
a P-type substrate; an N-type buried layer is arranged in the P-type substrate; an N-type deep well region and a P-type deep well region are arranged above the N-type buried layer;
the N-type deep well comprises a first N-well, the P-type deep well comprises a second P-well, the N-type deep well and the first N-well are not equal in width, and the P-type deep well and the second P-well are not equal in width; the first N trap is provided with a first N + injection, a second P + injection and a third N + injection; a fourth P + injection is formed on the N-type deep well;
a second P well is arranged on the P-type deep well; the left part of the fifth N + injection is arranged on the N-type deep well, and the right part of the fifth N + injection is arranged on the P-type deep well and the second P well; the left part of the sixth N + injection is arranged on the second P well, and the right part of the sixth N + injection is arranged on the P-type deep well; a seventh P + injection is formed on the P-type deep well; a polysilicon gate on the second P well;
two electrodes of the P-type deep well and one grid electrode on the second P well are connected together and used as a cathode of the device, and two electrodes in the first N well are connected together and used as an anode of the device.
Wherein, the device comprises five field oxide isolation regions; wherein a first field oxide isolation region is to the left of the first N + implant, a second field oxide isolation region is between the first N + implant and the second P + implant, a third field oxide isolation region is between the third N + implant and the fourth P + implant, a fourth field oxide isolation region is between the sixth N + implant and the seventh P + implant, and a fifth field oxide isolation region is to the right of the seventh P + implant.
Wherein the left side of the first field oxide isolation region is positioned on the surface of the P-type substrate, and the right side of the first field oxide isolation region is positioned on the surface of the N-type deep well; the second field oxide isolation region is arranged on the surface of the first N well; the left side of the third field oxide isolation region is positioned on the surface of the first N-type well, and the right side of the third field oxide isolation region is positioned on the surface of the N-type deep well; the fourth field oxide isolation region is arranged on the surface of the P-type deep well; the fifth field oxygen is arranged on the surface of the P type deep well on the left side and on the surface of the P type substrate on the right side.
When an ESD pulse reaches an anode of the device, and a cathode of the device is connected to a low potential, the second P + injection, the first N well/the N-type deep well, and the P-type deep well form a vertical parasitic triode PNP1, the first N well/the N-type deep well, the P-type deep well/the second P well, and the sixth N + injection form a lateral parasitic triode NPN1, the first N well/the N-type deep well/the N-type buried layer, the P-type deep well/the second P well, and the sixth N + injection form a vertical parasitic triode NPN2, and when the PNP1, the NPN1, and the NPN2 are turned on, a forward SCR path is formed, and a breakdown surface of the forward parasitic triode PNP is a reverse PN junction formed by the fifth N + injection and the second P well.
Wherein a fourth P + implant is implanted between the third field oxide isolation region and the fifth N + implant.
Wherein a third N + implant is implanted between the third field oxide isolation region and the second P + implant.
The embodiment of the utility model provides a low pressure area bars one-way silicon controlled rectifier electrostatic protection device, beneficial effect lies in:
1. in order to reduce the trigger voltage of the device and improve the maintaining voltage, a first P trap is implanted into the P type deep trap, the doping concentration of the region is increased, the trigger voltage is reduced, and meanwhile, the base region carrier concentration of a parasitic triode NPN1 is increased, so that the current gain of the parasitic triode is reduced, the positive feedback effect of the triode is weakened, and the maintaining voltage is improved.
2. In order to better exert the performance of the low-voltage grid unidirectional silicon controlled rectifier, the utility model introduces a grid and is connected with the cathode, and the cathode polysilicon grid can generate vertical upward electric field force to promote current carriers to move in the P wells of the positive electrode and the negative electrode so as to reduce the on-resistance;
3. the utility model discloses fifth N + pours into and second P trap overlap area' S distance S2, and forward trigger voltage is adjusted to S2, and when the distance increased, device trigger voltage increased.
4. The width S1 of the polysilicon gate of the utility model is adjustable, when S1 is increased, the width of the electric field under the gate is increased, and the number of the active carriers is increased; s1 increases and the device on-resistance decreases.
5. In order to further improve the maintaining voltage of the device, a floating third N + injection and a floating fourth P + injection are implanted, the implanted floating third N + injection is compounded with holes in anode current, the concentration of the holes flowing into a first N well is reduced, therefore, the carrier injection efficiency of an emitter of a parasitic triode PNP1 is reduced, and the maintaining voltage is increased; and a fourth P + injection is implanted between the third field oxide isolation region and the fifth N + injection to increase the hole concentration near the region, block the surface path of current, enable the current to flow through the deep layer of the device and increase the holding voltage of the device.
Drawings
FIG. 1 is a cross-sectional view of a presently known unidirectional LVTSCR electrostatic protection device;
FIG. 2 is an equivalent circuit diagram of a prior art unidirectional LVTSCR electrostatic protection device;
fig. 3 is a cross-sectional view of a low-voltage gate unidirectional silicon controlled rectifier electrostatic protection device according to an embodiment of the present invention;
fig. 4 is an equivalent circuit diagram of the low-voltage gate unidirectional silicon controlled rectifier electrostatic protection device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
As shown in fig. 3, a low voltage gated one-way thyristor electrostatic discharge protection device includes a P-type substrate 101; an N-type buried layer 201 is arranged in the substrate; an N-type deep well region 301 and a P-type deep well region 302 are arranged above the N-type buried layer 201; the N-type deep well 301 comprises a first N-well 401; the P-type deep well 302 comprises a second P-well 402; the N-type deep well 301 and the first N well 401 are not equal in width; the P-type deep well 302 and the first P-well 402 are not as wide; a first N + implant 501, a second P + implant 502, and a third N + implant 503 are disposed on the first N well 401; a fourth P + implant 504 is formed on the N-type deep well 301; a sixth N + implant 506 and a seventh P + implant 507 are formed on the P-type deep well 302; a second P well 402 is arranged on the P-type deep well 302; the left part of the fifth N + implant 505 is on the N-type deep well 301 and the right part is on the P-type deep well 302; the gate 701 is on the second P-well 402;
the low-voltage unidirectional silicon controlled rectifier electrostatic protection device with the grid is provided with five field oxide isolation regions; the first field oxide isolation region 601 is on the left of the first N + implant 501, the second field oxide isolation region 602 is between the first N + implant 501 and the second P + implant 502, the third field oxide isolation region 603 is between the third N + implant 503 and the fourth P + implant 504, the fourth field oxide isolation region 604 is between the sixth N + implant 506 and the seventh P + implant 507, and the fifth field oxide isolation region 605 is on the right of the seventh P + implant 507;
the left part of the first field oxide isolation region 601 is positioned on the surface of the P-type substrate 101, and the right part of the first field oxide isolation region is positioned on the surface of the N-type deep well 301; the second field oxide isolation region 602 is on the surface of the first N well 401; the left part of the third field oxide isolation region 603 is positioned on the surface of the first N well 401, and the right part is positioned on the surface of the N-type deep well 301; the fourth field oxide isolation region 604 is on the surface of the P-type deep well 302; the left part of the fifth field oxide isolation region 605 is on the surface of the P-type deep well 302, and the right part is on the surface of the P-type substrate 101;
as shown in fig. 4, when the ESD pulse reaches the anode of the device and the cathode of the device is connected to the low potential, the second P + implant 502, the first N well 401/N type deep well 301, and the P type deep well 302 form a vertical parasitic transistor PNP1, the first N well 401/N type deep well 301, the P type deep well 302/second P well 402, and the sixth N + implant 506 form a lateral parasitic transistor NPN1, the first N well 401/N type deep well 301/N type buried layer 201, the P type deep well 302/second P well 402, and the sixth N + implant 506 form a vertical parasitic transistor NPN2, and when the PNP1, the NPN1, and the NPN2 are turned on, a forward SCR path is formed, and the breakdown plane is a reverse PN junction formed by the fifth N + implant 505 and the second P well 402.
The device can adjust the forward trigger voltage by controlling the distances S2 and S2 of the overlapping region of the second P trap 402 and the fifth N + injection 505 according to the requirements of ESD design windows under different application scenes, and when the distance increases, the trigger voltage of the device increases. The width S1 of the polysilicon gate is adjustable, and when S1 is increased, the width of an electric field under the gate is increased, so that the number of active carriers is increased; s1 increases and the device on-resistance decreases.
Here, when the ESD pulse reaches the anode of the device and the cathode of the device is at ground potential, the fifth N + implant 505 of the drain of the embedded GGNMOS and the second P-well 402 form a reverse biased PN junction to generate avalanche breakdown, so that the parasitic triode is turned on, and currents flow through the first N-well 401, the N-type deep well 301, the second P-well 402 and the P-type deep well 302, when well resistors Rnw1 and Rpw1 on the first N-well 401, the N-type deep well 301 and the P-type deep well 302 generate a voltage drop of 0.7V, the parasitic triodes PNP1, NPN1 and NPN2 are turned on, and at this time, the main bleeder path P1 is formed by the SCR formed by the PNP1 and the NPN1, the on resistance is large, and since the current amplification factor of the parasitic triode NPN1 is larger than the parasitic triode 2, after the parasitic triode is completely turned on, the main bleeder path P2 is formed by the SCR formed by the PNP1 and the NPN2, and the on resistance is small.
Here, the distances S2, S2 between the second P well 402 and the N-type deep well 301 adjust the trigger voltage, and as the distance increases, the device trigger voltage increases.
Here, the width S1 of the polysilicon gate is adjustable, and when S1 is increased, the width of the electric field under the gate is increased, and the number of mobile effective carriers is increased; s1 increases and the device on-resistance decreases.
Here, the fourth P + implant is implanted between the third field oxide isolation region and the fifth N + implant 505 to increase the hole concentration near this region, block the surface path of the current, allow the current to flow through the deep layer of the device, and increase the holding voltage of the device.
Here, a third N + implant is implanted between the third field oxide isolation region and the anode second P + implant 502, and the third N + implant will recombine with minority carrier holes of the anode second P + implant 502, reducing the concentration of holes flowing into the first N-well 401, thereby reducing the carrier injection efficiency of the emitter of the parasitic triode PNP1 and maintaining the voltage increase.
Here, the first P well is implanted into the P-type deep well 302, the doping concentration of this region is increased, and the breakdown voltage of the backward diode constituted by the fifth N + implant 505 and the second P well 402 is lowered.
The embodiment of the utility model provides a still provide a manufacturing method of low pressure area bars unidirectional silicon controlled rectifier electrostatic protection device, including following step:
the method comprises the following steps: forming an N-type buried layer in a P-type substrate;
step two: generating an N-type deep well and a P-type deep well above the N-type buried layer;
step three: generating a first N well in the N-type deep well, and generating a second P well in the P-type deep well;
step four: forming a first N + injection region, a second P + injection region, a third N + injection region and a fourth P + injection region on the first N well, and generating a fifth N + injection region on the N-type deep well, the P-type deep well and the second P well; forming a polysilicon gate on the second P well; forming a sixth P + injection on the second P well and the P-type deep well; generating a seventh P + injection region on the P-type deep well;
step five: forming a first field oxide isolation region on the P-type substrate and the N-type deep well, forming a second field oxide isolation region between a first N + injection and a second P + injection on the first N well, forming a third field oxide isolation region between a third N + injection and a fourth P + injection on the first N well, forming a second field oxide isolation region between a first N + injection and a second P + injection on the first N well by generating a fourth field oxide between a sixth N + injection and a seventh P + injection on the P-type deep well, and generating a fifth field oxide isolation region on the P-type deep well and the P-type substrate;
step six: annealing all the injection regions to eliminate the migration of impurities in the injection regions;
step seven: and connecting the sixth N + injection and the seventh P + injection with the polysilicon grid and using the sixth N + injection and the seventh P + injection as a cathode of the device, and connecting the first N + injection and the second P + injection together and using the first N + injection and the second P + injection as an anode of the device.
In one embodiment, the first step further comprises the following steps: growing a silicon dioxide film on a P-type substrate, and then depositing a silicon nitride film; spin-coating a photoresist layer on a wafer, and adding a mask plate to expose and develop the wafer to form an isolation shallow slot; and etching the silicon dioxide, the silicon nitride and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is removed.
The utility model discloses the manufacturing method process of low pressure area bars unidirectional silicon controlled rectifier electrostatic protection device in the above-mentioned embodiment is simple, convenient operation. The utility model discloses a size of puncture face, the trigger voltage of adjusting device are adjusted. The trigger voltage is reduced and the maintaining voltage is increased by implanting a second P well. And implanting a third N + implantation and a fourth P + implantation to further improve the maintaining voltage of the device. The utility model discloses the example device adopts 0.25 mu m's BCDMOS technology.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (6)
1. The utility model provides a low pressure area bars unidirectional silicon controlled rectifier electrostatic discharge protection device which characterized in that includes:
a P-type substrate; an N-type buried layer is arranged in the P-type substrate; an N-type deep well region and a P-type deep well region are arranged above the N-type buried layer;
the N-type deep well comprises a first N-well, the P-type deep well comprises a second P-well, the N-type deep well and the first N-well are not equal in width, and the P-type deep well and the second P-well are not equal in width; the first N trap is provided with a first N + injection, a second P + injection and a third N + injection; a fourth P + injection is formed on the N-type deep well;
a second P well is arranged on the P-type deep well; the left part of the fifth N + injection is arranged on the N-type deep well, and the right part of the fifth N + injection is arranged on the P-type deep well and the second P well; the left part of the sixth N + injection is arranged on the second P well, and the right part of the sixth N + injection is arranged on the P-type deep well; a seventh P + injection is formed on the P-type deep well; a polysilicon gate on the second P well;
two electrodes of the P-type deep well and one grid electrode on the second P well are connected together and used as a cathode of the device, and two electrodes in the first N well are connected together and used as an anode of the device.
2. The low-voltage gated thyristor electrostatic discharge protection device of claim 1, comprising five field oxide isolation regions; wherein a first field oxide isolation region is to the left of the first N + implant, a second field oxide isolation region is between the first N + implant and the second P + implant, a third field oxide isolation region is between the third N + implant and the fourth P + implant, a fourth field oxide isolation region is between the sixth N + implant and the seventh P + implant, and a fifth field oxide isolation region is to the right of the seventh P + implant.
3. The low-voltage gated thyristor electrostatic discharge protection device of claim 2, wherein the first field oxide isolation region is located on the P-type substrate surface on the left side and on the N-type deep well surface on the right side; the second field oxide isolation region is arranged on the surface of the first N well; the left side of the third field oxide isolation region is positioned on the surface of the first N-type well, and the right side of the third field oxide isolation region is positioned on the surface of the N-type deep well; the fourth field oxide isolation region is arranged on the surface of the P-type deep well; the fifth field oxygen is arranged on the surface of the P type deep well on the left side and on the surface of the P type substrate on the right side.
4. The low-voltage gated SCR ESD device of claim 1, when the ESD pulse reaches the anode of the device and the cathode of the device is connected with low potential, the second P + injection, the first N well/the N-type deep well and the P-type deep well form a longitudinal parasitic triode PNP1, the first/N-well, the P-well, the second P-well, and the sixth N + implant form a lateral parasitic transistor NPN1, the first N well/the N-type deep well/the N-type buried layer, the P-type deep well/the second P well, and the sixth N + implant form a vertical parasitic transistor NPN2, when the PNP1, the NPN1, and the NPN2 are turned on, a forward SCR path is formed, and a breakdown plane of the forward SCR path is a reverse PN junction formed by the fifth N + injection and the second P-well.
5. The low-voltage gated triac electrostatic protection device of claim 2, wherein a fourth P + implant is implanted between said third field oxide isolation region and said fifth N + implant.
6. The low-voltage gated triac electrostatic protection device of claim 2, wherein a third N + implant is implanted between said third field oxide isolation region and said second P + implant.
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| WO2023098174A1 (en) * | 2021-11-30 | 2023-06-08 | 无锡华润上华科技有限公司 | Electrostatic discharge protection structure |
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| WO2023098174A1 (en) * | 2021-11-30 | 2023-06-08 | 无锡华润上华科技有限公司 | Electrostatic discharge protection structure |
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