CN115513201A - High-maintenance low-resistance uniform-conduction bidirectional silicon controlled electrostatic protection device and manufacturing method thereof - Google Patents
High-maintenance low-resistance uniform-conduction bidirectional silicon controlled electrostatic protection device and manufacturing method thereof Download PDFInfo
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
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- 239000000377 silicon dioxide Substances 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
- H01L29/66386—Bidirectional thyristors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/747—Bidirectional devices, e.g. triacs
Abstract
The embodiment of the invention provides a high-maintenance low-resistance uniform-conduction bidirectional controllable silicon electrostatic protection device and a manufacturing method thereof, wherein a first P + injection region, a first N + injection region, a second N + injection region and a third N + injection region are directly connected through a lead to serve as an anode of the device, and a second P + injection region, a fourth N + injection region, a fifth N + injection region and a sixth N + injection region are directly connected through leads to serve as a cathode of the device; the first floating P + injection region is arranged on the right side of the third N + injection region in the first P well, and the fourth floating P + injection region is arranged on the left side of the fourth N + injection region in the second P well; an N-type trap is arranged between the first P trap and the second P trap, a floating N + injection region is arranged in the middle of the N-type trap, a second floating P + injection region and a third floating P + injection region are arranged to stretch over the middle of the first P trap, the N-type trap and the second P trap respectively, a first grid is arranged between the second floating P + injection region and the floating N + injection region, and a second grid is arranged between the third floating P + injection region and the floating N + injection region.
Description
Technical Field
The invention relates to the field of electrostatic protection, in particular to a high-maintenance low-resistance uniform-conduction bidirectional thyristor electrostatic protection device and a manufacturing method thereof.
Background
With the progress of semiconductor manufacturing processes, the failure of integrated circuit chips and electronic products caused by electrostatic discharge (ESD) is becoming more serious. ESD protection of electronic products and integrated circuit chips has become one of the major challenges facing product engineers.
Compared with other ESD devices, the traditional Silicon Controlled Rectifier (SCR) device has the advantages of being provided with a double-conductance modulation mechanism, high in unit area discharge efficiency, small in unit parasitic capacitance, capable of achieving very high robustness with a small area and the like. However, the traditional silicon controlled rectifier device has the defects of over-high trigger voltage, over-low maintaining voltage after the device is triggered and the like, the protection device cannot timely protect the core circuit due to the over-high trigger voltage, and latch-up effect of the device is caused due to the over-low maintaining voltage, so that the ESD protection device cannot normally play a role, and the integrity of signals transmitted by an I/O port cannot be ensured.
The bidirectional thyristor is improved on the basis of the traditional thyristor, has symmetrical structural layout, has the same working principle as the traditional unidirectional thyristor, and can clamp voltage in positive and negative directions respectively. The cross-sectional view of the conventional triac ESD device is shown in FIG. 1, and the equivalent circuit diagram thereof is shown in FIG. 2. When the ESD pulse is applied to the anode of the bidirectional SCR, the N-type trap and the third floating P + injection region form a reverse bias PN node. When the pulse voltage is higher than the avalanche breakdown voltage of the PN junction, a large amount of avalanche current is generated in the device, and the current flow path is to flow to the other end, namely the cathode, through the second P-well parasitic resistor. When the voltage across the parasitic well resistor is higher than the forward conduction voltage of the NPN transistor, the transistor turns on. After the triode is switched on, base current is provided for the transverse PNP triode, and after the transverse PNP triode is also switched on, base current is also provided for the longitudinal NPN triode, so that a positive feedback loop is formed. When the two parasitic triodes are completely started, the low-resistance SCR path is also completely started and participates in discharging ESD current. The bidirectional SCR is of a symmetrical structure, and when an ESD pulse occurs at the cathode, PN junction avalanche breakdown is generated between the N-type deep well and the second P + injection region, so that the PNP triode and the NPN triode are sequentially conducted to discharge static electricity. However, the conventional SCR has the disadvantages of high trigger voltage, high on-resistance and low holding voltage, which cause the device to easily exceed the design window, and the holding voltage is low and latch-up is easily caused.
Disclosure of Invention
The invention provides a high-maintenance low-resistance uniform-conduction bidirectional controllable silicon electrostatic protection device with a simple structure and a manufacturing method thereof.
In order to achieve the above purpose, the technical solution of the embodiment of the present invention is implemented as follows:
the embodiment of the invention provides a high-maintenance low-resistance uniform-conduction bidirectional controllable silicon electrostatic protection device, which comprises a P-type substrate;
an N-type buried layer is arranged in the P-type substrate;
an N-type trap is arranged in the middle above the N-type buried layer;
a first P well is arranged on the left side of the N-type buried layer, and a second P well is arranged on the right side of the N-type buried layer;
a first P + injection region, the first N + injection region, a second N + injection region and a third N + injection region are arranged in the first P well, wherein the first P + injection region is positioned on the left side of the first P well, the first N + injection region is positioned on the right side of the first P + injection region and is attached together, the second N + injection region is positioned on the right side of the first N + injection region, and the third N + injection region is positioned on the right side of the second N + injection region;
a second P + injection region, a fourth N + injection region, a fifth N + injection region and a sixth N + injection region are arranged in the second P well, wherein the second P + injection region is located on the right side of the second P well, the sixth N + injection region is located on the left side of the second P + injection region and is bonded together, the fifth N + injection region is located on the left side of the sixth N + injection region, and the fourth N + injection region is located on the left side of the fifth N + injection region;
an N-type well is arranged between the first P well and the second P well, a floating N + injection region is arranged in the middle of the N-type well, meanwhile, the second floating P + injection region spans between the first P well and the N well, and a third floating P + injection region spans between the N well and the second P well; the first grid and the second grid are respectively arranged on two sides above the N well;
a first high-voltage N well and a second high-voltage N well are respectively arranged on the left side and the right side above the N-type buried layer;
the first P + injection region and the first N + injection region, the second N + injection region and the third N + injection region are connected together and used as an anode of the device, and the fourth N + injection region and the fifth N + injection region and the sixth N + injection region and the second P + injection region are connected together and used as a cathode of the device.
Wherein the left side of the first field oxide isolation region is in contact with the edge of the left side of the P-type substrate, the right side of the first field oxide isolation region is in contact with the left side of the first P + implantation region, the right side of the first P + implantation region is connected with the left side of the first N + implantation region, the right side of the first N + implantation region is in contact with the left side of the second field oxide isolation region, the right side of the second N + implantation region is in contact with the left side of the second N + implantation region, the right side of the second N + implantation region is in contact with the left side of the third field oxide isolation region, the right side of the third N + implantation region is in contact with the left side of the fourth field oxide isolation region, the right side of the fourth field oxide isolation region is in contact with the left side of the first floating P + implantation region, the right side of the first floating P + implantation region is in contact with the left side of the fifth field oxide isolation region, the right side of the fifth field oxide isolation region is in contact with the left side of the second floating P + implantation region, and the second floating P + implantation region crosses the N-type substrate; the right side of the second floating P + injection region is in contact with the left side of the first grid electrode, the right side of the first grid electrode is in contact with the left side of the floating N + injection region, the right side of the floating N + injection region is in contact with the left side of the second grid electrode, the right side of the second grid electrode is in contact with the left side of a third floating P + injection region, and the third floating P + injection region spans between the N well and the second P well; the third floating P + injection region right side is in contact with the sixth field oxygen isolation region left side, the sixth field oxygen isolation region right side is in contact with the fourth floating P + injection region left side, the fourth floating P + injection region right side is in contact with the seventh field oxygen isolation region left side, the seventh field oxygen isolation region right side is connected with the fourth N + injection region left side, the fourth N + injection region right side is in contact with the eighth field oxygen isolation region left side, the eighth field oxygen isolation region right side is in contact with the fifth N + injection region left side, the fifth N + injection region right side is in contact with the ninth field oxygen isolation region left side, the ninth field oxygen isolation region right side is in contact with the sixth N + injection region left side, the sixth N + injection region right side is connected with the second P + injection region left side, and the tenth field oxygen isolation region right side is in contact with the P type substrate right side edge.
The left part of the first field oxide isolation region is positioned on the surface of the P-type substrate, and the right part of the first field oxide isolation region is positioned on the surface of the first P well; the left part of the tenth field oxide isolation region is positioned on the surface of the second P well, and the right part of the tenth field oxide isolation region is positioned on the surface of the P-type substrate; the second field oxygen isolation region, the third field oxygen isolation region, the fourth field oxygen isolation region and the fifth field oxygen isolation region are located on the surface of the first P well, and the sixth field oxygen isolation region, the seventh field oxygen isolation region, the eighth field oxygen isolation region and the ninth field oxygen isolation region are located on the surface of the second P well.
When a high-voltage ESD pulse reaches the anode of the device, and the cathode of the device is connected with a low potential, the first N + injection region, the first P trap and the N trap form a longitudinal NPN type triode, the first P trap, the N trap and the second P trap form a transverse PNP type triode structure, the second N + injection region, the second P trap and the N trap form a longitudinal NPN type triode, and the first P trap, the N type buried layer and the second P trap form a transverse PNP type triode.
When the ESD pulse reaches the anode of the device, the cathode of the device is connected with a low potential, ESD current flows into the first P well, the N well, the second P well and then the second P + injection region along the first P + injection region, when the ESD current is increased to a certain value, a reverse PN junction formed by the N well and the third floating P + injection region is subjected to avalanche breakdown, the ESD current flows into the second P well through the third floating P + injection region in a large amount, a voltage drop is formed on an equivalent resistor of the second P well, when the voltage drop reaches 0.7V, the right-side longitudinal NPN triode is conducted, base current is provided for the left-side transverse PNP triode to further promote the conduction of the right-side longitudinal NPN triode, and a positive feedback effect is formed, and at the moment, the device is successfully triggered.
The embodiment of the invention also provides a manufacturing method of the high-maintenance low-resistance uniform conduction bidirectional controllable silicon electrostatic protection device, which comprises the following steps:
the method comprises the following steps: forming an N-type buried layer in a P-type substrate;
step two: generating an N-type trap in the middle above the N-type buried layer;
step three: sequentially generating a first field oxygen isolation region, a second field oxygen isolation region, a third field oxygen isolation region, a fourth field oxygen isolation region, a fifth field oxygen isolation region, a sixth field oxygen isolation region, a seventh field oxygen isolation region, an eighth field oxygen isolation region, a ninth field oxygen isolation region and a tenth field oxygen isolation region in the P-type substrate from left to right;
step four: respectively generating a first high-voltage N well, a second high-voltage N well, a first P well and a second P well on two sides above the N-type buried layer;
step five: respectively generating a first grid and a second grid on two sides above the N-type well;
step six: sequentially forming a first P + injection region, a first N + injection region, a second N + injection region, a third N + injection region, a first floating P + injection region and a second floating P + injection region from left to right in the first P well, wherein the second floating P + injection region spans between the first P well and the N well, the second floating P + injection region, the floating N + injection region and the third floating P + injection region are sequentially formed in the N well from left to right, the third floating P + injection region spans between the N well and the second P well, the third floating P + injection region, the fourth N + injection region, the fifth N + injection region, the sixth N + injection region and the second P + injection region are sequentially formed in the second P well from left to right, and simultaneously forming a floating N + injection region in the N well; the left side of the first field oxide isolation region is in contact with the edge of the left side of the P-type substrate, the right side of the first field oxide isolation region is in contact with the left side of the first P + injection region, the right side of the first P + injection region is connected with the left side of the first N + injection region, the right side of the first N + injection region is in contact with the left side of the second field oxide isolation region, the right side of the second N + injection region is in contact with the left side of the third field oxide isolation region, the right side of the third field oxide isolation region is in contact with the left side of the third N + injection region, the right side of the third N + injection region is in contact with the left side of the fourth field oxide isolation region, the right side of the fourth field oxide isolation region is in contact with the left side of the first floating P + injection region, the right side of the first floating P + injection region is in contact with the left side of the fifth field oxide isolation region, the right side of the fifth field oxide isolation region is in contact with the left side of the second floating P + injection region, and the second floating P + injection region crosses the first N well; the right side of the second floating P + injection region is in contact with the left side of the first grid, the right side of the first grid is in contact with the left side of the floating N + injection region, the right side of the floating N + injection region is in contact with the left side of the second grid, the right side of the second grid is in contact with the left side of a third floating P + injection region, and the third floating P + injection region spans between the N well and the second P well; the right side of the third floating P + injection region is in contact with the left side of the sixth field oxygen isolation region, the right side of the sixth field oxygen isolation region is in contact with the left side of the fourth floating P + injection region, the right side of the fourth floating P + injection region is in contact with the left side of the seventh field oxygen isolation region, the right side of the seventh field oxygen isolation region is connected with the left side of the fourth N + injection region, the right side of the fourth N + injection region is in contact with the left side of the eighth field oxygen isolation region, the right side of the eighth field oxygen isolation region is in contact with the left side of the fifth N + injection region, the right side of the fifth N + injection region is in contact with the left side of the ninth field oxygen isolation region, the right side of the ninth field oxygen isolation region is in contact with the left side of the sixth N + injection region, the right side of the sixth N + injection region is connected with the left side of the second P + injection region, and the right side of the tenth field oxygen isolation region is in contact with the edge of the right side of the P-type substrate;
step seven: annealing the first P + injection region, the first N + injection region, the second N + injection region, the third N + injection region and the first floating P + injection region, the second floating P + injection region crossing between the first P well and the N well, the floating N + injection region in the N well, the third floating P + injection region crossing between the N well and the second P well, the fourth floating P + injection region and the fourth N + injection region, the fifth N + injection region, the sixth N + injection region and the second P + injection region to eliminate the migration of impurities in the injection regions;
step eight: and connecting the first P + injection region and the first N + injection region, and connecting the second N + injection region and the third N + injection region together to serve as an anode of the device, and connecting the fourth N + injection region and the fifth N + injection region together with the sixth N + injection region and the second P + injection region to serve as a cathode of the device.
Wherein, the method also comprises the following steps:
growing a silicon dioxide film on the P-type substrate, and then depositing a silicon nitride film; spin-coating a photoresist layer on a wafer, and adding a mask plate to expose and develop the wafer to form an isolation shallow slot; and etching the silicon dioxide, the silicon nitride and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is removed.
The embodiment of the invention provides a high-maintenance low-resistance uniform-conduction bidirectional controllable silicon electrostatic protection device and a manufacturing method thereof, and the bidirectional controllable silicon electrostatic protection device has the beneficial effects that:
1. the invention can realize the purposes of reducing trigger voltage and on-resistance and improving the maintaining voltage by changing the internal structure levels of the device and the wiring without increasing the layout area of the device, wherein a first P + injection region, a first N + injection region, a second N + injection region and a third N + injection region are directly connected with each other through a lead and are used as the anode of the device, and a second P + injection region, a fourth N + injection region, a fifth N + injection region and a sixth N + injection region are directly connected with each other through a lead and are used as the cathode of the device; the first floating P + injection region is arranged on the right side of the third N + injection region in the first P well, the fourth floating P + injection region is arranged on the left side of the fourth N + injection region in the second P well, and the floating P + injection is designed to improve the holding voltage.
2. According to the invention, the N-type well is arranged between the first P well and the second P well, the floating N + injection region is arranged in the middle of the N-type well, meanwhile, the second floating P + injection region and the third floating P + injection region are respectively arranged to cross the middle positions of the first P well, the N-type well and the second P well, the first grid electrode is arranged between the second floating P + injection region and the floating N + injection region, and the second grid electrode is arranged between the third floating P + injection region and the floating N + injection region.
3. According to the invention, the sizes S2 of the second field oxide isolation region, the third field oxide isolation region, the eighth field oxide isolation region and the ninth field oxide isolation region of the second P well in the first P well are adjustable, and when the sizes S2 are increased, the width of the base electrode of the parasitic triode is increased, so that the amplification factor of the parasitic triode is reduced, the positive feedback of the SCR is weakened, and the maintaining voltage of the device is increased. Meanwhile, with the increase of S2, the area of the device is increased, so that the heat dissipation capacity of the device is increased, and the failure current of the device is increased.
Drawings
FIG. 1 is a cross-sectional view of a conventional bi-directional SCR ESD device;
FIG. 2 is an equivalent circuit diagram of a conventional bidirectional SCR ESD protection device;
FIG. 3 is a cross-sectional view of a high-maintenance low-resistance uniform turn-on triac electrostatic protection device in accordance with an embodiment of the present invention;
fig. 4 is an equivalent circuit diagram of a high-maintenance low-resistance uniform-conduction bidirectional thyristor electrostatic protection device according to an embodiment of the invention;
fig. 5 is a simulation diagram of the total current density distribution of the high-maintenance low-resistance uniform-conduction triac electrostatic protection device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below with reference to the drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
As shown in fig. 3, a high-maintenance low-resistance uniform-conduction bidirectional thyristor electrostatic protection device comprises a P-type substrate 101; an N-type buried layer 201 is arranged in the P-type substrate 101; an N-type trap 301 is arranged in the middle above the N-type buried layer 201; a first P well 401 is arranged on the left side of the N-type buried layer 201, and a second P well 402 is arranged on the right side of the N-type buried layer 201; a first P + injection region 601, a first N + injection region 602, a second N + injection region 603 and a third N + injection region 604 are arranged in the first P well 401, wherein the first P + injection region 601 is located on the left side of the first P well 401, the first N + injection region 602 is located on the right side of the first P + injection region 601 and is attached together, the second N + injection region 603 is located on the right side of the first N + injection region 602, and the third N + injection region 604 is located on the right side of the second N + injection region 603;
a second P + injection region 613, a fourth N + injection region 610, a fifth N + injection region 611 and a sixth N + injection region 612 are disposed in the second P well 402, wherein the second P + injection region 613 is located at the right side of the second P well 402, the sixth N + injection region 612 is located at the left side of the second P + injection region 613 and is bonded together, the fifth N + injection region 611 is located at the left side of the sixth N + injection region 612, the fourth N + injection region 610 is located at the left side of the fifth N + injection region 611, and meanwhile, the third N + injection region 604 and the second N + injection region 603 are directly connected through a metal wire;
an N-type well 301 is arranged between the first P-well 401 and the second P-well 402, a floating N + injection region 607 is arranged in the middle of the N-type well 301, meanwhile, the first floating P + injection region 605 is arranged on the right side of a third N + injection region 604 in the first P-well 401, and a fourth floating P + injection region 609 is arranged on the left side of a fourth N + injection region 610 in the second P-well 402; the second floating P + injection region 606 and the third floating P + injection region 608 are respectively arranged across the middle positions of the first P well 401, the N-type well 301 and the second P well 402;
a first high-voltage N well 501 and a second high-voltage N well 502 are respectively arranged on the left side and the right side above the N-type buried layer 201;
a first gate 701 is arranged between the second floating P + injection region 606 and the floating N + injection region 607, and a second gate 702 is arranged between the third floating P + injection region 608 and the floating N + injection region 607;
the first P + implantation region 601, the first N + implantation region 602, the second N + implantation region 603, and the third N + implantation region 604 are directly connected by a wire and serve as an anode of the device, and the second P + implantation region 613, the fourth N + implantation region 610, the fifth N + implantation region 611, and the sixth N + implantation region 612 are directly connected by a wire and serve as a cathode of the device.
A first field oxide isolation region 801 is arranged between the left side of the first P + injection region 601 and the left side edge of the P-type substrate 101, the right side of the first P + injection region 601 is connected with the left side of the first N + injection region 602, a second field oxide isolation region 802 is arranged between the right side of the first N + injection region 602 and the left side of the second N + injection region 603, and a third field oxide isolation region 803 is arranged between the right side of the second N + injection region 603 and the left side of the third N + injection region 604; a tenth field oxide isolation region 810 is arranged between the left side of the second P + implantation region 613 and the edge of the right side of the P-type substrate 101, the left side of the second P + implantation region 613 is connected with the right side of the sixth N + implantation region 612, a ninth field oxide isolation region 809 is arranged between the left side of the sixth N + implantation region 612 and the right side of the fifth N + implantation region 611, and an eighth field oxide isolation region 808 is arranged between the left side of the fifth N + implantation region 611 and the right side of the fourth N + implantation region 610; a fourth field oxide isolation region 804 is disposed on the right side of the third N + implantation region 604 and the left side of the first floating P + implantation region 605; a fifth field oxide isolation region 805 is arranged on the right side of the first floating P + injection region 605 and the left side of the second floating P + injection region 606; a seventh field oxide isolation region 807 is disposed on the left side of the fourth N + implantation region 610 and the right side of the fourth floating P + implantation region 609; a sixth field oxide isolation region 806 is disposed on the left side of the fourth floating P + implant region 609 and the right side of the third floating P + implant region 608.
The left part of the first field oxide isolation region 801 is positioned on the surface of the P-type substrate 101, and the right part of the first field oxide isolation region 801 is positioned on the surface of the first P-well 401; the left part of the tenth field oxide isolation region 810 is positioned on the surface of the second P well 402, and the right part of the tenth field oxide isolation region 810 is positioned on the surface of the P-type substrate 101; the second field oxide isolation region 802, the third field oxide isolation region 803, the fourth field oxide isolation region 804 and the fifth field oxide isolation region 805 are located on the surface of the first P well 401, and the ninth field oxide isolation region 809, the eighth field oxide isolation region 808, the seventh field oxide isolation region 807 and the sixth field oxide isolation region 806 are located on the surface of the second P well 402.
As shown in fig. 4, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first N + injection region 602, the first P well 401, and the N well 301 form a vertical NPN transistor, the second N + injection region 603, the first P well 401, and the N well 301 form a vertical NPN transistor, the third N + injection region 604, the first P well 401, and the N well 301 form a vertical NPN transistor, the fourth N + injection region 610, the second P well 402, and the N well 301 form a vertical NPN transistor, the fifth N + injection region 611, the second P well 402, and the N well 301 form a vertical NPN transistor, the first P well 401, the N well 301, and the second P well 402 form a horizontal PNP triode structure, the sixth N + injection region 612, the second P well 402, and the N well 301 form a vertical NPN transistor, and the first P well 401, the N well 402, and the second P well 402 form a horizontal PNP triode structure, and the sixth N well 201 form a horizontal PNP triode structure. The longitudinal parasitic NPN transistor in the first P well 401 and the longitudinal parasitic longitudinal NPN transistor in the second P well 402 may be combined in pairs to form a bidirectional SCR structure with the lateral PNP transistor.
When a high-voltage ESD pulse reaches the anode of the device, the cathode of the device is connected to a low potential, an ESD current flows into the first P well 401, the N well, the second P well 402 and then to the second P + injection region 613 along the first P + injection region 601, when the ESD current increases to a certain value, an avalanche breakdown occurs at a reverse PN junction formed by the N well and the third floating P + injection region 608, and the ESD current flows into the second P well 402 through the third floating P + injection region 608 in a large amount, as can be seen from the equivalent circuit diagram of fig. 4, when a voltage drop generated by the avalanche current on the parasitic resistance of the second P well 402 is large enough, the parasitic triode T5 is turned on, and after the parasitic triode T5 is turned on, a current is provided for the base of the parasitic triode T2, which form a positive feedback loop, and the forward SCR structure is turned on to discharge static electricity. As can be seen from the simulation diagram of total current density distribution of the device shown in fig. 5, the current density distribution below the first P + injection region 601 and the fourth N + injection region 610 is the most dense, which indicates that the path is a main leakage path, and meanwhile, the current is also dense in the N-type buried layer 201, and the leakage path can guide the current to flow to the deep part of the device, so that the sustain voltage and the failure current of the device can be effectively increased. Similarly, when a positive ESD pulse occurs at the cathode, avalanche breakdown occurs at a reverse PN junction formed by the N-well and the second floating P + injection region 606, and an avalanche current flows through the parasitic resistor of the first P-well 401 and flows into the anode, as can be seen from the equivalent circuit diagram of fig. 4, when a voltage drop generated by the avalanche current on the parasitic resistor of the first P-well 401 is large enough, the parasitic triode T3 is turned on, and the parasitic triode T3 provides a current for the base of the parasitic triode T2 after being turned on, so that the parasitic triode T3 and the base form a positive feedback loop, and the reverse SCR structure is turned on to discharge static electricity.
Compared with the traditional bidirectional silicon controlled rectifier electrostatic protection device, the device changes the trigger path of the traditional silicon controlled rectifier, the parasitic resistance of a metal conducting wire path which is passed by an ESD pulse in the stage of triggering the device is very small, the on-resistance of the device can be effectively reduced, the N trap and the third floating P + injection region 608, and the reverse bias PN junction formed by the N trap and the second floating P + injection region 606 enable the device to have lower trigger voltage, meanwhile, the middle floating N + injection region 607 can improve the doping concentration of the middle N trap 301, the base region concentration of a parasitic PNP triode on the silicon controlled rectifier path of the device is increased, and further the maintaining voltage of the device is improved.
The first floating layer P + and the fourth floating layer P + can increase the distance between the cathode and the anode of the device, the holding voltage of the device can be effectively improved, the main structure of the controlled silicon can be completely isolated from the P-type substrate 101 by the N-type buried layer 201, and the anti-leakage capacity of the device is effectively improved.
The sizes S2 of the second field oxide isolation region 802 and the third field oxide isolation region 803 in the first P well 401 and the eighth field oxide isolation region 808 and the ninth field oxide isolation region 809 in the second P well 402 are adjustable, and when S2 is increased, as shown in fig. 4, the widths of the bases of the parasitic triode T2, the parasitic triode T3, the parasitic triode T5, and the parasitic triode T6 are increased, so that the amplification factor of the parasitic triode is reduced, the positive feedback of the SCR is weakened, and the holding voltage of the device is increased. Meanwhile, with the increase of S2, the area of the device is increased, so that the heat dissipation capacity of the device is increased, and the failure current of the device is increased.
The embodiment of the invention also provides a manufacturing method of the high-maintenance low-resistance uniform conduction bidirectional controllable silicon electrostatic protection device, which comprises the following steps:
the method comprises the following steps: forming an N-type buried layer 201 in a P-type substrate 101;
step two: generating an N-type well 301 in the middle above the N-type buried layer 201;
step three: a first field oxide isolation region 801, a second field oxide isolation region 802, a third field oxide isolation region 803, a fourth field oxide isolation region 804, a fifth field oxide isolation region 805, a sixth field oxide isolation region 806, a seventh field oxide isolation region 807, an eighth field oxide isolation region 808, a ninth field oxide isolation region 809 and a tenth field oxide isolation region 810 are sequentially formed in the P-type substrate 101 from left to right;
step four: a first high-voltage N well 501, a second high-voltage N well 502, a first P well 401 and a second P well 402 are respectively generated on two sides above the N-type buried layer 201;
step five: generating a first gate 701 and a second gate 702 on two sides above the N-type well 301 respectively;
step six: a first P + injection region 601, a first N + injection region 602, a second N + injection region 603, a third N + injection region 604, a first floating P + injection region 605 and a second floating P + injection region 606 are sequentially formed in the first P well 401 from left to right, the second floating P + injection region 606 spans between the first P well 401 and the N well 301, the second floating P + injection region 606, the floating N + injection region 607 and a third floating P + injection region 608 are sequentially formed in the N well 301 from left to right, the third floating P + injection region 608 spans between the N well 301 and the second P well 402, the third floating P + injection region 608, the fourth floating P + injection region 609, the fourth N + injection region 610, the fifth N + injection region, the sixth N + injection region 301, the second P + injection region 613, and the N + injection region 610 are sequentially formed in the second P well 402 from left to right, and the floating P + injection regions are simultaneously formed in the N well 301; the left side of the first field oxide isolation region 801 is in contact with the edge of the left side of the P-type substrate 101, the right side of the first field oxide isolation region 801 is in contact with the left side of the first P + injection region 601, the right side of the first P + injection region 601 is connected with the left side of the first N + injection region 602, the right side of the first N + injection region 602 is in contact with the left side of the second field oxide isolation region 802, the right side of the second field oxide isolation region 802 is in contact with the left side of the second N + injection region 603, the right side of the second N + injection region 603 is in contact with the left side of the third field oxide isolation region 803, the right side of the third field oxide isolation region 803 is in contact with the left side of the third N + injection region 604, the right side of the third N + injection region 604 is in contact with the left side of the fourth field oxide isolation region 804, the right side of the fourth field oxide isolation region 804 is in contact with the left side of the first floating P + injection region 605, the right side of the first floating P + injection region 605 is in contact with the left side of the fifth field oxide isolation region 805, the second floating P + injection region 401, and the second floating P + injection region 401; the right side of the second floating P + implant region 606 is in contact with the left side of the first gate 701, the right side of the first gate 701 is in contact with the left side of the floating N + implant region 607, the right side of the floating N + implant region 607 is in contact with the left side of the second gate 702, the right side of the second gate 702 is in contact with the left side of a third floating P + implant region 608, and the third floating P + implant region 608 spans between the N-well 301 and the second P-well 402; the right side of the third floating P + implant region 608 is in contact with the left side of the sixth field oxide isolation region 806, the right side of the sixth field oxide isolation region 806 is in contact with the left side of the fourth floating P + implant region 609, the right side of the fourth floating P + implant region 609 is in contact with the left side of the seventh field oxide isolation region 807, the right side of the seventh field oxide isolation region 807 is in contact with the left side of the fourth N + implant region 610, the right side of the fourth N + implant region 610 is in contact with the left side of the eighth field oxide isolation region 808, the right side of the eighth field oxide isolation region 808 is in contact with the left side of the fifth N + implant region 611, the right side of the fifth N + implant region 611 is in contact with the left side of the ninth field oxide isolation region 809, the right side of the ninth field oxide isolation region 809 is in contact with the left side of the sixth N + implant region 612, the right side of the sixth N + implant region 612 is in contact with the left side of the second P + implant region 613, and the right side of the tenth field oxide isolation region 810 is in contact with the edge of the P-type substrate 101;
step seven: annealing the first P + implantation region 601, the first N + implantation region 602, the second N + implantation region 603, the third N + implantation region 604 and the first floating P + implantation region 605, the second floating P + implantation region 606 crossing between the first P well 401 and the N well 301, the floating N + implantation region 607 in the N well 301, the third floating P + implantation region 608 crossing between the N well 301 and the second P well 402, the fourth floating P + implantation region 609 and the fourth N + implantation region 610, the fifth N + implantation region 611, the sixth N + implantation region 612 and the second P + implantation region 613 to eliminate the migration of impurities in the implantation regions;
step eight: the first P + implantation region 601 and the first N + implantation region 602, the second N + implantation region 603 and the third N + implantation region 604 are connected together and serve as an anode of the device, and the fourth N + implantation region 610, the fifth N + implantation region 611 and the sixth N + implantation region 612 and the second P + implantation region 613 are connected together and serve as a cathode of the device.
Optionally, the method further comprises:
growing a silicon dioxide film on the P-type substrate 101, and then depositing a silicon nitride film; spin-coating a photoresist layer on a wafer, and adding a mask plate to expose and develop the wafer to form an isolation shallow slot; and etching the silicon dioxide, the silicon nitride and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is removed.
The manufacturing method of the high-maintenance low-resistance uniform conduction bidirectional controllable silicon electrostatic protection device is simple in process and convenient to operate. The manufactured bidirectional thyristor electrostatic protection device structure has a reverse avalanche breakdown surface with lower breakdown voltage, can effectively reduce the trigger voltage of the device, has a trigger path with lower parasitic resistance, and can effectively reduce the on-resistance of the device. Meanwhile, the addition of floating N + injection can effectively improve the holding voltage of the device. The device can adjust the trigger voltage of the device by controlling the size of the N + injection region of the breakdown surface according to the requirements of ESD design windows under different application scenes. The device can be applied to an ESD protection design, effectively protects an internal chip and is far away from the risk of latch-up. The device of the embodiment of the invention adopts a BCDMOS process with the thickness of 0.25 mu m.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (7)
1. A high-maintenance low-resistance uniform-conduction bidirectional controllable silicon electrostatic protection device is characterized by comprising a P-type substrate; an N-type buried layer is arranged in the P-type substrate; an N-type trap is arranged in the middle above the N-type buried layer; a first P well is arranged on the left side of the N-type buried layer, and a second P well is arranged on the right side of the N-type buried layer; a first P + injection region, a first N + injection region, a second N + injection region and a third N + injection region are arranged in the first P well, wherein the first P + injection region is positioned on the left side of the first P well, the first N + injection region is positioned on the right side of the first P + injection region and is attached together, the second N + injection region is positioned on the right side of the first N + injection region, and the third N + injection region is positioned on the right side of the second N + injection region;
a second P + injection region, a fourth N + injection region, a fifth N + injection region and a sixth N + injection region are arranged in the second P well, wherein the second P + injection region is positioned on the right side of the second P well, the sixth N + injection region is positioned on the left side of the second P + injection region and bonded together, the fifth N + injection region is positioned on the left side of the sixth N + injection region, the fourth N + injection region is positioned on the left side of the fifth N + injection region, and meanwhile, the third N + injection region is directly connected with the second N + injection region through a metal wire;
an N-type well is arranged between the first P well and the second P well, a floating N + injection region is arranged in the middle of the N-type well, meanwhile, the first floating P + injection region is arranged on the right side of a third N + injection region in the first P well, and a fourth floating P + injection region is arranged on the left side of a fourth N + injection region in the second P well; the second floating P + injection region and the third floating P + injection region are respectively arranged at the middle positions of the first P well, the N-type well and the second P well in a spanning manner;
a first high-voltage N well and a second high-voltage N well are respectively arranged on the left side and the right side above the N-type buried layer;
a first grid electrode is arranged between the second floating P + injection region and the floating N + injection region, and a second grid electrode is arranged between the third floating P + injection region and the floating N + injection region;
the first P + injection region, the first N + injection region, the second N + injection region and the third N + injection region are directly connected through leads and serve as anodes of the devices, and the second P + injection region, the fourth N + injection region, the fifth N + injection region and the sixth N + injection region are directly connected through leads and serve as cathodes of the devices.
2. The high-maintenance low-resistance uniform-conduction triac electrostatic protection device according to claim 1, wherein a first field oxide isolation region is arranged between the left side of the first P + implantation region and the left edge of the P-type substrate, the right side of the first P + implantation region is connected with the left side of the first N + implantation region, a second field oxide isolation region is arranged between the right side of the first N + implantation region and the left side of the second N + implantation region, and a third field oxide isolation region is arranged between the right side of the second N + implantation region and the left side of the third N + implantation region; a tenth field oxide isolation region is arranged between the left side of the second P + injection region and the edge of the right side of the P-type substrate, the left side of the second P + injection region is connected with the right side of the sixth N + injection region, a ninth field oxide isolation region is arranged between the left side of the sixth N + injection region and the right side of the fifth N + injection region, and an eighth field oxide isolation region is arranged between the left side of the fifth N + injection region and the right side of the fourth N + injection region; a fourth field oxide isolation region is arranged on the right side of the third N + injection region and the left side of the first floating P + injection region; a fifth field oxygen isolation region is arranged on the right side of the first floating P + injection region and the left side of the second floating P + injection region; a seventh field oxide isolation region is arranged on the left side of the fourth N + injection region and the right side of the fourth floating P + injection region; and a sixth field oxygen isolation region is arranged on the left side of the fourth floating P + injection region and the right side of the third floating P + injection region.
3. The high-maintenance low-resistance uniform-conduction triac electrostatic protection device according to claim 2, wherein said first field oxide isolation region is located at the left of said P-type substrate surface and said first field oxide isolation region is located at the right of said first P-well surface; the left part of the tenth field oxygen isolation region is positioned on the surface of the second P well, and the right part of the tenth field oxygen isolation region is positioned on the surface of the P-type substrate; the second field oxygen isolation region, the third field oxygen isolation region, the fourth field oxygen isolation region and the fifth field oxygen isolation region are located on the surface of the first P well, and the ninth field oxygen isolation region, the eighth field oxygen isolation region, the seventh field oxygen isolation region and the sixth field oxygen isolation region are located on the surface of the second P well.
4. The high-maintenance low-resistance uniform-conduction triac electrostatic protection device according to claim 2, wherein when a high-voltage ESD pulse reaches an anode of the device and a cathode of the device is connected to a low potential, the first N + injection region, the first P well and the N well constitute a vertical NPN type triode, the second N + injection region, the first P well and the N well constitute a vertical NPN type triode, the third N + injection region, the first P well and the N well constitute a vertical NPN type triode, the fourth N + injection region, the second P well and the N well constitute a vertical NPN type triode, the fifth N + injection region, the second P well and the N well constitute a vertical NPN type triode, the first P well, the N well and the second P well constitute a lateral PNP type triode structure, the sixth N + injection region, the second P well and the N well constitute a vertical NPN type triode, and the first P well, the N well and the second P well constitute a lateral PNP type triode structure.
5. The high-maintenance low-resistance uniform-conduction triac electrostatic protection device as claimed in claim 1, wherein when a high-voltage ESD pulse reaches the anode of the device, the cathode of the device is connected to a low potential, ESD current flows into said first P well, said N well, said second P well and then to said second P + injection region along said first P + injection region, when the ESD current increases to a certain value, a reverse PN junction formed by said N well and said third floating P + injection region is avalanche-broken, the ESD current flows into said second P well in a large amount through said third floating P + injection region, and forms a voltage drop on the equivalent resistance of said second P well, when the voltage drop reaches 0.7V, the right-side vertical NPN transistor is turned on and provides a base current for the left-side lateral transistor to promote the turn-on thereof, and a positive feedback effect is formed, and the device is successfully triggered.
6. A manufacturing method of a high-maintenance low-resistance uniform-conduction bidirectional controllable silicon electrostatic protection device is characterized by comprising the following steps:
the method comprises the following steps: forming an N-type buried layer in a P-type substrate;
step two: generating an N-type trap in the middle above the N-type buried layer;
step three: sequentially generating a first field oxygen isolation region, a second field oxygen isolation region, a third field oxygen isolation region, a fourth field oxygen isolation region, a fifth field oxygen isolation region, a sixth field oxygen isolation region, a seventh field oxygen isolation region, an eighth field oxygen isolation region, a ninth field oxygen isolation region and a tenth field oxygen isolation region in the P-type substrate from left to right;
step four: respectively generating a first high-voltage N well, a second high-voltage N well, a first P well and a second P well on two sides above the N-type buried layer;
step five: respectively generating a first grid and a second grid on two sides above the N-type well;
step six: sequentially forming a first P + injection region, a first N + injection region, a second N + injection region, a third N + injection region, a first floating P + injection region and a second floating P + injection region from left to right in the first P well, wherein the second floating P + injection region spans between the first P well and the N well, the second floating P + injection region, the floating N + injection region and the third floating P + injection region are sequentially formed in the N well from left to right, the third floating P + injection region spans between the N well and the second P well, the third floating P + injection region, the fourth N + injection region, the fifth N + injection region, the sixth N + injection region and the second P + injection region are sequentially formed in the second P well from left to right, and simultaneously forming a floating N + injection region in the N well; the left side of the first field oxygen isolation region is in contact with the edge of the left side of the P-type substrate, the right side of the first field oxygen isolation region is in contact with the left side of the first P + injection region, the right side of the first P + injection region is connected with the left side of the first N + injection region, the right side of the first N + injection region is in contact with the left side of the second field oxygen isolation region, the right side of the second N + injection region is in contact with the left side of the second N + injection region, the right side of the second N + injection region is in contact with the left side of the third field oxygen isolation region, the right side of the third N + injection region is in contact with the left side of the fourth field oxygen isolation region, the right side of the fourth field oxygen isolation region is in contact with the left side of the first floating P + injection region, the right side of the first floating P + injection region is in contact with the left side of the fifth field oxygen isolation region, the right side of the fifth field oxygen isolation region is in contact with the left side of the second floating P + injection region, and the second floating P + injection region crosses between the first floating P well and the N-type substrate; the right side of the second floating P + injection region is in contact with the left side of the first grid, the right side of the first grid is in contact with the left side of the floating N + injection region, the right side of the floating N + injection region is in contact with the left side of the second grid, the right side of the second grid is in contact with the left side of a third floating P + injection region, and the third floating P + injection region spans between the N well and the second P well; the right side of the third floating P + injection region is in contact with the left side of the sixth field oxygen isolation region, the right side of the sixth field oxygen isolation region is in contact with the left side of the fourth floating P + injection region, the right side of the fourth floating P + injection region is in contact with the left side of the seventh field oxygen isolation region, the right side of the seventh field oxygen isolation region is connected with the left side of the fourth N + injection region, the right side of the fourth N + injection region is in contact with the left side of the eighth field oxygen isolation region, the right side of the eighth field oxygen isolation region is in contact with the left side of the fifth N + injection region, the right side of the fifth N + injection region is in contact with the left side of the ninth field oxygen isolation region, the right side of the ninth field oxygen isolation region is in contact with the left side of the sixth N + injection region, the right side of the sixth N + injection region is connected with the left side of the second P + injection region, and the right side of the tenth field oxygen isolation region is in contact with the edge of the right side of the P-type substrate;
step seven: annealing the first P + injection region, the first N + injection region, the second N + injection region, the third N + injection region and the first floating P + injection region, the second floating P + injection region crossing between the first P well and the N well, the floating N + injection region in the N well, the third floating P + injection region crossing between the N well and the second P well, the fourth floating P + injection region and the fourth N + injection region, the fifth N + injection region, the sixth N + injection region and the second P + injection region to eliminate the migration of impurities in the injection regions;
step eight: and connecting the first P + injection region and the first N + injection region, and connecting the second N + injection region and the third N + injection region together to serve as an anode of the device, and connecting the fourth N + injection region and the fifth N + injection region together with the sixth N + injection region and the second P + injection region to serve as a cathode of the device.
7. The method for manufacturing the high-maintenance low-resistance uniform-conduction bidirectional triode thyristor electrostatic discharge protection device according to claim 6, wherein the method further comprises the following steps:
growing a silicon dioxide film on the P-type substrate, and then depositing a silicon nitride film; spin-coating a photoresist layer on the wafer, and adding a mask plate to expose and develop the wafer to form the shallow isolation trench; and etching the silicon dioxide, the silicon nitride and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is removed.
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| CN116314277A (en) * | 2023-05-15 | 2023-06-23 | 微龛(广州)半导体有限公司 | SCR (selective catalytic reduction) type ESD (electro-static discharge) protection device, electronic device and preparation method |
-
2022
- 2022-10-26 CN CN202211324316.7A patent/CN115513201A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116314277A (en) * | 2023-05-15 | 2023-06-23 | 微龛(广州)半导体有限公司 | SCR (selective catalytic reduction) type ESD (electro-static discharge) protection device, electronic device and preparation method |
| CN116314277B (en) * | 2023-05-15 | 2023-08-22 | 微龛(广州)半导体有限公司 | SCR (selective catalytic reduction) type ESD (electro-static discharge) protection device, electronic device and preparation method |
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