CN111799258A - Interdigital asymmetric bidirectional silicon controlled rectifier electrostatic discharge device and manufacturing method thereof - Google Patents
Interdigital asymmetric bidirectional silicon controlled rectifier electrostatic discharge device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses an interdigital asymmetric bidirectional silicon controlled rectifier electrostatic discharge device. Firstly, the invention selects an asymmetric silicon controlled structure, and uses the path of the protection ring as a temporary discharge path of the negative pulse, thereby avoiding the problem of the parasitic path of the protection ring of the traditional device; secondly, the novel interdigital mode can control the protection level of the device according to the increase and decrease of the number of the cathodes. If the device protection level is high, the number of cathodes is increased; if the protection level of the device is low, the number of cathodes is reduced, and the area of a layout is saved. By floating the P + of the inner interdigital, the parasitic NPN base resistance of the inner interdigital is increased, and the opening of the outer interdigital is assisted, so that the conduction speed of the device is increased and the current distribution is more uniform; finally, the maintaining voltage of the whole device is generally determined by the innermost interdigital, so that the problem that the maintaining voltage of the device in the traditional interdigital mode is reduced along with the increase of the number of the interdigital is avoided.
Description
Technical Field
The invention relates to the field of electrostatic protection, in particular to an interdigital asymmetric bidirectional silicon controlled rectifier electrostatic discharge device and a manufacturing method thereof.
Background
With the progress of semiconductor process, the feature size of the device is continuously reduced and the integration degree is continuously improved, the design window of the SD device is smaller and larger, the difficulty is larger and larger, an ESD protection device which occupies a small chip area and has good electrostatic discharge capability is needed, and the ESD protection device becomes one of the main problems faced by product engineers.
A Silicon Controlled Rectifier (SCR) is a conventional device structure for ESD protection in a chip. Compared with a diode, a triode and a field effect transistor, the semiconductor device has the advantages of high unit area discharge efficiency, strong robustness and high protection level due to a self positive feedback mechanism, and can achieve a high electrostatic protection level with a small chip area on a semiconductor plane process. A Bidirectional SCR (BSCR) is a compact ESD protection device that can clamp a voltage in both forward and reverse directions. It can be used for electrostatic protection of input/output (I/O) pins that transmit signals above or below ground level, for example, data buses of communication chips.
When the asymmetric bidirectional SCR device is applied to some special ports on a chip, the problems of device maintenance voltage and failure current need to be considered. The asymmetric bidirectional SCR device is switched on to enable the maintaining voltage to be very low due to strong switching-on, and the circuit cannot be switched off after being switched on due to static electricity when the circuit works normally, so that a very low voltage is maintained at a circuit port, and the operation of an inner core circuit is influenced. In general, a pair of irreconcilable contradictions is observed between high holding voltage and high failure current. The sustain voltage is typically boosted at the expense of the failure current. Fig. 1 is a cross-sectional view of a typical asymmetric bidirectional SCR, and an equivalent circuit diagram thereof is shown in fig. 2, which is symmetrical. Applying a positive electrostatic pulse to the anode (positive direction) and a negative electrostatic pulse to the anode (negative direction) the ESD characteristics are the same in both cases.
From the above analysis, when the asymmetric device is applied to some special ports on a chip, the problems of low holding voltage and low failure current of the electrostatic protection device are to be solved, so as to prevent the latch-up problem after the discharge device is turned on and the device fails prematurely.
Disclosure of Invention
In order to solve the technical problems, the invention provides an interdigital asymmetric bidirectional thyristor electrostatic discharge device with simple structure, high maintenance voltage and high failure current, and a manufacturing method thereof.
The technical scheme for solving the problems is as follows: an interdigital asymmetric bidirectional controllable silicon electrostatic discharge device comprises a P-type substrate;
a P-type epitaxial layer is arranged above the P-type substrate, and an N-type buried layer is arranged between the P-type substrate and the P-type epitaxial layer;
a first high-voltage N well, a second high-voltage N well and a third high-voltage N well are sequentially arranged in the P-type epitaxial layer from left to right;
a first deep N well is arranged in the first high-voltage N well, a second deep N well is arranged in the second high-voltage N well, the left side of the second deep N well is wider than the second high-voltage N well, a third deep N well is arranged in the third high-voltage N well, and the left side of the third deep N well is wider than the third high-voltage N well;
a first shallow N well is arranged above the left side of the second deep N well, and a second shallow N well is arranged above the left side of the third deep N well;
a first deep P well is arranged on the left side of the first deep N well, a second deep P well and a third deep P well are sequentially arranged between the first deep N well and the second deep N well from left to right, a fourth deep P well and a fifth deep P well are sequentially arranged between the second deep N well and the third deep N well from left to right, and a sixth deep P well is arranged on the right side of the third deep N well;
a first shallow P well to a sixth shallow P well are sequentially arranged in the first deep P well to the sixth deep P well;
a first P + injection region is arranged in the first shallow P well; a second P + injection region and a first N + injection region are sequentially arranged in the second shallow P well from left to right; a fourth P + injection region and a second N + injection region are sequentially arranged in the third shallow P well from left to right; a third P + injection region is bridged between the second shallow P well and the third shallow P well; a fifth P + injection region and a third N + injection region are sequentially arranged in the fourth shallow P well from left to right; a seventh P + injection region and a fourth N + injection region are sequentially arranged in the fifth shallow P well from left to right; a sixth P + injection region is bridged between the fourth shallow P well and the fifth shallow P well; an eighth P + injection region is arranged in the sixth shallow P well;
the fifth P + injection region, the third N + injection region and the fourth N + injection region are connected together and used as an anode of the device; the first P + injection region, the second P + injection region, the first N + injection region, the second N + injection region and the eighth P + injection region are connected together and serve as a cathode of the device.
In the interdigital asymmetric bidirectional silicon controlled electrostatic discharge device, a first field oxide isolation region is arranged between the left side of the first P + injection region and the left side edge of the P-type epitaxial layer, a second field oxide isolation region is arranged between the right side of the first P + injection region and the left side of the second P + injection region, a third field oxide isolation region is arranged between the right side of the second P + injection region and the left side of the first N + injection region, a fourth field oxide isolation region is arranged between the right side of the first N + injection region and the left side of the third P + injection region, a fifth field oxide isolation region is arranged between the right side of the third P + injection region and the left side of the fourth P + injection region, a sixth field oxide isolation region is arranged between the right side of the fourth P + injection region and the left side of the second N + injection region, a seventh field oxide isolation region is arranged between the right side of the second N + injection region and the left side of the fifth P + injection region, and an eighth field oxide isolation region is arranged between the right side of the fifth P, a ninth field oxygen isolation region is arranged between the right side of the third N + injection region and the left side of the sixth P + injection region, a tenth field oxygen isolation region is arranged between the right side of the sixth P + injection region and the left side of the seventh P + injection region, an eleventh field oxygen isolation region is arranged between the right side of the seventh P + injection region and the left side of the fourth N + injection region, a twelfth field oxygen isolation region is arranged between the right side of the fourth N + injection region and the left side of the eighth P + injection region, and a thirteenth field oxygen isolation region is arranged between the right side of the eighth P + injection region and the edge of the right side of the P-type epitaxial layer.
The equivalent circuit of the asymmetric bidirectional thyristor electrostatic discharge device in the interdigital mode comprises:
the second shallow N well, the third deep N well and the third high-voltage N well are used as a base electrode of the first PNP type transistor, and the fifth shallow P well and the fifth deep P well are used as a collector electrode of the first PNP type transistor;
the second shallow N well, the third deep N well and the third high-voltage N well are used as collectors of the first NPN transistor, the fifth shallow P well and the fifth deep P well are used as bases of the first NPN transistor, and the fourth N + injection region is used as an emitter of the first NPN transistor;
the second NPN transistor, wherein the second shallow N well, the third deep N well and the third high-voltage N well are used as a collector of the second NPN transistor, the fifth shallow P well and the fifth deep P well are used as a base of the second NPN transistor, and the third N + injection region is used as an emitter of the second NPN transistor;
the first PNP type transistor comprises a first shallow P well, a first high-voltage N well, a first PNP type transistor, a second PNP type transistor, a third shallow P well and a third deep P well, wherein the first shallow P well and the second deep P well are used as emitting electrodes of the first PNP type transistor;
the first shallow N well, the second deep N well and the second high-voltage N well are used as collectors of the third NPN transistor, the third shallow P well and the third deep P well are used as bases of the third NPN transistor, and the second N + injection region is used as an emitter of the third NPN transistor;
the first shallow N well, the second deep N well and the second high-voltage N well are used as collectors of the fourth NPN transistor, the third shallow P well and the third deep P well are used as bases of the fourth NPN transistor, and the first N + injection region is used as an emitter of the fourth NPN transistor;
the sixth shallow P well and the sixth deep P well are integrally formed into a first P well parasitic resistor;
a second P well parasitic resistor is formed among the fourth shallow P well, the fourth deep P well, the fifth shallow P well and the fifth deep P well;
a third P well parasitic resistor is integrally formed on the right side of the fourth shallow P well and the fourth deep P well;
a fourth P well parasitic resistor is integrally formed on the left side of the fourth shallow P well and the fourth deep P well;
a fifth P well parasitic resistor is formed among the second shallow P well, the second deep P well, the third shallow P well and the third deep P well;
the second shallow P-well and the second deep P-well form a sixth P-well parasitic resistor.
In the equivalent circuit of the asymmetric bidirectional triode thyristor electrostatic discharge device in the interdigital mode, one end of the fourth P trap parasitic resistor is connected to the fifth P + injection region, the other end of the fourth P trap parasitic resistor is connected with the emitter of the second PNP transistor, the base of the second PNP transistor, the collector of the third NPN transistor and the collector of the fourth NPN transistor are connected together, the base electrode of the third NPN transistor is connected with one end of a fifth P well parasitic resistor, the other end of the fifth P well parasitic resistor is connected with the base electrode of the fourth NPN transistor, the collector electrode of the second PNP transistor and one end of a sixth P well parasitic resistor, the emitter electrode of the third NPN transistor is connected with the second N + injection region, the emitter electrode of the fourth NPN transistor is connected with the first N + injection region, and the other end of the sixth P well parasitic resistor is connected with the second P + injection region; the fourth P well parasitic resistor, the second PNP transistor, the third NPN transistor, the fourth NPN transistor, the fifth P well parasitic resistor and the sixth P well parasitic resistor jointly form a forward SCR current leakage path;
one end of the first P well parasitic resistor is connected to the eighth P + injection region, the other end of the first P well parasitic resistor is connected with the emitter of the first PNP transistor, the base of the first PNP transistor, the collector of the first NPN transistor and the collector of the second NPN transistor are connected together, the base of the first NPN transistor and one end of the second P well parasitic resistor are connected together, the other end of the second P well parasitic resistor is connected with the base of the second NPN transistor, the collector of the first PNP transistor and one end of the third P well parasitic resistor, the emitter of the first NPN transistor and the fourth N + injection region are connected together, the emitter of the second NPN transistor and the third N + injection region are connected together, and the other end of the third P well parasitic resistor and the fifth P + injection region are connected together; the first P well parasitic resistor, the first PNP transistor, the first NPN transistor, the second P well parasitic resistor and the third P well parasitic resistor jointly form a reverse SCR current leakage path.
In the interdigital asymmetric bidirectional triode thyristor electrostatic discharge device, when an ESD high-voltage pulse comes to the anode of the device and the cathode of the device is grounded, the first shallow N well, the second deep N well, the second high-voltage N well, the P-type epitaxial layer, the third shallow P well and the third deep P well are subjected to avalanche breakdown, avalanche carriers flow through the fifth P well parasitic resistor and the sixth P well parasitic resistor, when the voltage drop between the two ends of the fifth P well parasitic resistor and the sixth P well parasitic resistor is greater than 0.7V, the third NPN transistor is started first, so that the base electrode of the second PNP transistor is started when the base electrode potential of the second PNP transistor is reduced, the fourth NPN transistor is started when the current is gradually increased and the voltage between the two ends of the sixth P well parasitic resistor is also greater than 0.7V, finally the second PNP transistor, the third NPN transistor and the fourth NPN transistor form positive feedback, the positive SCR path starts the leakage current, and the SCR path ratio of the inner side is formed first, the maintaining voltage is mainly determined by the maintaining voltage of the inner SCR and cannot be reduced due to the increase of the interdigital;
and similarly, when a negative ESD high-voltage pulse comes to the anode of the device and the cathode of the device is grounded, finally the first PNP transistor, the first NPN transistor and the second NPN transistor form positive feedback, the reverse SCR path starts the leakage current, and the reverse maintaining voltage is only dependent on the SCR path of the inner interdigital of the reverse phase.
According to the asymmetric bidirectional silicon controlled rectifier electrostatic discharge device in the interdigital mode, an asymmetric silicon controlled rectifier structure is adopted as the electrostatic discharge device, and the path of the protection ring is used as a temporary discharge path of negative pulses.
According to the asymmetric bidirectional silicon controlled rectifier electrostatic discharge device in the interdigital mode, the protection grade of the device can be controlled according to the increase and decrease of the number of cathodes in the interdigital mode; the P + of the inner interdigital floats.
A manufacturing method of an interdigital asymmetric bidirectional silicon controlled rectifier electrostatic discharge device comprises the following steps:
the method comprises the following steps: forming a P-type epitaxial layer in a P-type substrate;
step two: forming an N-type buried layer at the junction of the P-type substrate and the P-type epitaxial layer;
step three: sequentially generating a first high-voltage N well, a second high-voltage N well and a third high-voltage N well from left to right above the N-type buried layer;
step four: generating a first deep N well in the first high-voltage N well, generating a second deep N well in the second high-voltage N well, wherein the left side of the second deep N well exceeds the second high-voltage N well, and generating a third deep N well in the third high-voltage N well, wherein the left side of the third deep N well exceeds the third high-voltage N well;
step five: generating a first shallow N well at the upper left of the second deep N well, and generating a second shallow N well at the upper left of the third deep N well;
step six: a first deep P well is generated on the left side of the first deep N well, a second deep P well and a third deep P well are sequentially generated between the first deep N well and the second deep N well from left to right, a fourth deep P well and a fifth deep P well are sequentially generated between the second deep N well and the third deep N well from left to right, and a sixth deep P well is generated on the right side of the third deep N well;
step seven: sequentially generating a first shallow P well to a sixth shallow P well in the first deep P well to the sixth deep P well;
step eight: generating a first P + injection region in a first shallow P well, sequentially generating a second P + injection region and a first N + injection region in a second shallow P well from left to right, sequentially generating a fourth P + injection region and a second N + injection region in a third shallow P well from left to right, generating a third P + injection region between the second shallow P well and the third shallow P well, sequentially generating a fifth P + injection region and a third N + injection region in a fourth shallow P well from left to right, sequentially generating a seventh P + injection region and a fourth N + injection region in the fifth shallow P well from left to right, generating a sixth P + injection region between the fourth shallow P well and the fifth shallow P well, and generating an eighth P + injection region in the sixth shallow P well;
step nine: a first field oxide isolation region is generated between the left side of the first P + injection region and the left side edge of the P-type epitaxial layer, a second field oxide isolation region is generated between the right side of the first P + injection region and the left side of the second P + injection region, a third field oxide isolation region is generated between the right side of the second P + injection region and the left side of the first N + injection region, a fourth field oxide isolation region is generated between the right side of the first N + injection region and the left side of the third P + injection region, a fifth field oxide isolation region is generated between the right side of the third P + injection region and the left side of the fourth P + injection region, a sixth field oxide isolation region is generated between the right side of the fourth P + injection region and the left side of the second N + injection region, a seventh field oxide isolation region is generated between the right side of the second N + injection region and the left side of the fifth P + injection region, an eighth field oxide isolation region is generated between the right side of the fifth P + injection region and the left side of the third N + injection region, and a ninth field oxide isolation region are, a tenth field oxygen isolation region is formed between the right side of the sixth P + injection region and the left side of the seventh P + injection region, an eleventh field oxygen isolation region is formed between the right side of the seventh P + injection region and the left side of the fourth N + injection region, a twelfth field oxygen isolation region is formed between the right side of the fourth N + injection region and the left side of the eighth P + injection region, and a thirteenth field oxygen isolation region is formed between the right side of the eighth P + injection region and the right edge of the P-type epitaxial layer;
step ten: annealing the first P + injection region to the eighth P + injection region and the first N + injection region to the fourth N + injection region to eliminate the migration of impurities in the injection regions;
step eleven: and connecting the fifth P + injection region, the third N + injection region and the fourth N + injection region together to serve as an anode of the device, and connecting the first P + injection region, the second P + injection region, the first N + injection region, the second N + injection region and the eighth P + injection region together to serve as a cathode of the device.
The manufacturing method of the asymmetric bidirectional thyristor electrostatic discharge device in the interdigital mode further comprises the following steps before the first step: growing a silicon dioxide film on a P-type substrate, and then depositing a silicon nitride film; spin-coating a photoresist layer on a wafer, and adding a mask plate to expose and develop the wafer to form an isolation shallow slot; and etching the silicon dioxide, the silicon nitride and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is removed.
The invention has the beneficial effects that: firstly, the invention selects an asymmetric silicon controlled structure, and uses the path of the protection ring as a temporary discharge path of the negative pulse, thereby avoiding the problem of the parasitic path of the protection ring of the traditional device; secondly, the number of cathodes can be increased or decreased in the novel interdigital mode according to different protection grades, parasitic NPN base resistance of the inner-side interdigital is increased by floating P + of the inner-side interdigital, and meanwhile, the outer-side interdigital is assisted to be started, so that the conduction speed of a device is increased, and the current distribution is more uniform; finally, the maintaining voltage of the whole device is generally determined by the innermost interdigital, so that the problem that the maintaining voltage of the device in the traditional interdigital mode is reduced along with the increase of the number of the interdigital is avoided. The silicon controlled rectifier electrostatic discharge device has the characteristics of high holding voltage and high failure current, and can realize high protection level while effectively avoiding latch-up effect.
Drawings
Fig. 1 is a cross-sectional view of a prior art asymmetric DDSCR electrostatic protection device.
Fig. 2 is a forward and reverse equivalent circuit diagram of a conventional asymmetric DDSCR electrostatic protection device.
Fig. 3 is a cross-sectional view of the present invention.
Fig. 4 is a forward and reverse equivalent circuit diagram of the present invention.
Detailed Description
The invention is further described below with reference to the figures and examples.
As shown in fig. 3, an asymmetric bidirectional thyristor electrostatic discharge device in an interdigital manner includes a P-type substrate 101; a P-type epitaxial layer 301 is arranged above the P-type substrate 101, and an N-type buried layer 201 is arranged between the P-type substrate 101 and the P-type epitaxial layer 301;
a first high-voltage N well 401, a second high-voltage N well 402 and a third high-voltage N well 403 are sequentially arranged in the P-type epitaxial layer 301 from left to right;
a first deep N well 501 is arranged in the first high-voltage N well 401, a second deep N well 502 is arranged in the second high-voltage N well 402, the left side of the second deep N well 502 is wider than the second high-voltage N well 402, a third deep N well 503 is arranged in the third high-voltage N well 403, and the left side of the third deep N well 503 is wider than the third high-voltage N well 403;
a first shallow N well 704 is arranged above the left side of the second deep N well 502, and a second shallow N well 707 is arranged above the left side of the third deep N well 503;
a first deep P well 601 is arranged on the left side of the first deep N well 501, a second deep P well 602 and a third deep P well 603 are sequentially arranged between the first deep N well 501 and the second deep N well 502 from left to right, a fourth deep P well 604 and a fifth deep P well 605 are sequentially arranged between the second deep N well 502 and the third deep N well 503 from left to right, and a sixth deep P well 606 is arranged on the right side of the third deep N well 403;
a first shallow P well 701 to a sixth shallow P well 708 are sequentially arranged in the first deep P well 601 to the sixth deep P well 606;
a first P + injection region 801 is arranged in the first shallow P well 701; a second P + injection region 802 and a first N + injection region 803 are sequentially arranged in the second shallow P well 702 from left to right; a fourth P + injection region 805 and a second N + injection region 806 are sequentially arranged in the third shallow P well 703 from left to right; a third P + injection region 804 is bridged between the second shallow P well 702 and the third shallow P well 703; a fifth P + injection region 807 and a third N + injection region 808 are sequentially arranged in the fourth shallow P well 705 from left to right; a seventh P + injection region 810 and a fourth N + injection region 811 are sequentially arranged in the fourth shallow P well 706 from left to right; a sixth P + implantation region 809 is bridged between the fourth shallow P well 604 and the fifth shallow P well 605; an eighth P + implantation region 812 is disposed in the sixth shallow P well 606;
the fifth P + implant region 807, the third N + implant region 808, and the fourth N + implant region 811 are connected together and serve as the anode of the device; the first P + implant region 801, the second P + implant region 802, the first N + implant region 803, the second N + implant region 806, and the eighth P + implant region 812 are connected together and serve as the cathode of the device.
A first field oxide isolation region 901 is arranged between the left side of the first P + injection region 801 and the left side edge of the P-type epitaxial layer 301, a second field oxide isolation region 902 is arranged between the right side of the first P + injection region 801 and the left side of the second P + injection region 802, a third field oxide isolation region 903 is arranged between the right side of the second P + injection region 802 and the left side of the first N + injection region 803, a fourth field oxide isolation region 904 is arranged between the right side of the first N + injection region 803 and the left side of the third P + injection region 804, a fifth field oxide isolation region 905 is arranged between the right side of the third P + injection region 804 and the left side of the fourth P + injection region 805, a sixth field oxide isolation region 906 is arranged between the right side of the fourth P + injection region 805 and the left side of the second N + injection region 806, a seventh field oxide isolation region 907 is arranged between the right side of the second N + injection region 806 and the left side of the fifth P + injection region 807, and an eighth field oxide isolation region 908 is arranged between the right side of the fifth P +, a ninth field oxide isolation region 909 is arranged between the right side of the third N + injection region 808 and the left side of the sixth P + injection region 809, a tenth field oxide isolation region 910 is arranged between the right side of the sixth P + injection region 809 and the left side of the seventh P + injection region 810, an eleventh field oxide isolation region 911 is arranged between the right side of the seventh P + injection region 810 and the left side of the fourth N + injection region 811, a twelfth field oxide isolation region 912 is arranged between the right side of the fourth N + injection region 811 and the left side of the eighth P + injection region 812, and a thirteenth field oxide isolation region 913 is arranged between the right side 812 of the eighth P + injection region and the edge of the right side of the P-type epitaxial layer 301.
As shown in fig. 4, the equivalent circuit of the device includes:
the first PNP type transistor PNP1, wherein the sixth shallow P-well 708 and the sixth deep P-well 607 serve as the emitter of the first PNP type transistor PNP1, the second shallow N-well 707, the third deep N-well 503, and the third high voltage N-well 403 serve as the base of the first PNP type transistor PNP1, and the fourth shallow P-well 706 and the fifth deep P-well 605 serve as the collector of the first PNP type transistor PNP 1;
a first NPN transistor NPN1, wherein the second shallow N-well 707, the third deep N-well 503, and the third high voltage N-well 403 serve as collectors of the first NPN transistor NPN1, the fourth shallow P-well 705 and the fifth deep P-well 605 serve as bases of the first NPN transistor NPN1, and the fourth N + implant 811 serves as an emitter of the first NPN transistor NPN 1;
a second NPN transistor NPN2, wherein the second shallow N-well 707, the third deep N-well 503, and the third high voltage N-well 403 serve as collectors of the second NPN transistor NPN2, the fourth shallow P-well 705 and the fifth deep P-well 605 serve as bases of the second NPN transistor NPN2, and the third N + implant region 808 serves as an emitter of the second NPN transistor NPN 2;
a second PNP type transistor PNP2 wherein the fourth shallow P-well 705 and the fourth deep P-well 604 serve as the emitter of the second PNP type transistor PNP2, the first shallow N-well 704, the second deep N-well 502, and the second high voltage N-well 402 serve as the base of the second PNP type transistor PNP2, and the third shallow P-well 703 and the third deep P-well 603 serve as the collector of the second PNP type transistor PNP 2;
a third NPN transistor NPN3, wherein the first shallow N-well 704, the second deep N-well 502, and the second high voltage N-well 402 serve as a collector of the third NPN transistor NPN3, the third shallow P-well 703 and the third deep P-well 603 serve as a base of the third NPN transistor NPN3, and the second N + implant 806 serves as an emitter of the third NPN transistor NPN 3;
a fourth NPN transistor NPN4, wherein the first shallow N well 704, the second deep N well 502, and the second high voltage N well 402 serve as collectors of the fourth NPN transistor NPN4, the third shallow P well 703 and the third deep P well 603 serve as bases of the fourth NPN transistor NPN4, and the first N + implant 803 serves as an emitter of the fourth NPN transistor NPN 4;
the sixth shallow P-well 708 and the sixth deep P-well 606 integrally form a first P-well parasitic resistance R1;
a second P-well parasitic resistor R2 is formed between the fourth shallow P-well 705 and the fourth deep P-well 604 and the fifth shallow P-well 706 and the fifth deep P-well 605;
the fourth shallow P-well 705 and the right side of the fourth deep P-well 604 form a third P-well parasitic resistor R3 integrally;
a fourth P-well parasitic resistor R4 is integrally formed on the left side of the fourth shallow P-well 705 and the fourth deep P-well 604;
a fifth P-well parasitic resistor R5 is formed among the second shallow P-well 702, the second deep P-well 602, the third shallow P-well 703 and the third deep P-well 603;
the second shallow P-well 702 and the second deep P-well 602 form a sixth P-well parasitic resistance R6 integrally.
In the equivalent circuit, one end of the fourth P-well parasitic resistor R4 is connected to the fifth P + injection region 807, the other end of the fourth P-well parasitic resistor R4 is connected to the emitter of the second PNP transistor PNP2, the base of the second PNP transistor PNP2, the collector of the third NPN transistor NPN3 and the collector of the fourth NPN transistor NPN4 are connected together, the base of the third NPN transistor NPN3 and one end of the fifth P-well parasitic resistor R5 are connected together, the other end of the fifth P-well parasitic resistor R5 is connected together with the base of the fourth NPN transistor NPN4, the collector of the second PNP transistor PNP2, and one end of the sixth P-well parasitic resistor R6, the emitter of the third NPN transistor NPN3 and the second N + injection region 806 are connected together, the emitter of the fourth NPN transistor NPN4 and the first N + injection region 803 are connected together, and the other end of the sixth P-well parasitic resistor R6 and the second P + injection region 802 are connected together. The fourth P-well parasitic resistor R4, the second PNP transistor PNP2, the third NPN transistor NPN3, the fourth NPN transistor NPN4, the fifth P-well parasitic resistor R5 and the sixth P-well parasitic resistor R6 jointly form a forward SCR current leakage path;
one end of the first P-well parasitic resistor R1 is connected to the eighth P + injection region 812, the other end of the first P-well parasitic resistor R1 is connected to the emitter of the first PNP transistor PNP1, the base of the first PNP transistor PNP1, the collector of the first NPN transistor NPN1 and the collector of the second NPN transistor NPN2 are connected together, the base of the first NPN transistor NPN1 and one end of the second P-well parasitic resistor R2 are connected together, the other end of the second P-well parasitic resistor R2 is connected together with the base of the second NPN transistor NPN2, the collector of the first PNP transistor PNP1, and one end of the third P-well parasitic resistor R3, the emitter of the first NPN transistor NPN1 and the fourth N + injection region 811 are connected together, the emitter of the second NPN transistor NPN2 and the third N + injection region 808 are connected together, and the other end of the third P-well parasitic resistor R3 and the fifth P + injection region 807 are connected together. The first P well parasitic resistor R1, the first PNP transistor PNP1, the first NPN transistor NPN1, the second NPN transistor NPN2, the second P well parasitic resistor R2 and the third P well parasitic resistor R3 jointly form a reverse SCR current leakage path;
when an ESD high voltage pulse comes to the anode of the device and the cathode of the device is at ground potential, the first shallow N well 704, the second deep N well 502, the second high voltage N well 402, the P-type epitaxial layer 301, the third shallow P well 703, and the third deep P well 603 undergo avalanche breakdown, avalanche carriers flow through the fifth P well parasitic resistor R5 and the sixth P well parasitic resistor R6, when a voltage drop across the fifth P well parasitic resistor R5 and the sixth P well parasitic resistor R6 is greater than 0.7V, the third NPN transistor NPN3 is turned on first, so that the base potential of the second PNP transistor PNP2 is decreased and turned on, and as the current gradually increases, the voltage across the sixth P well parasitic resistor R6 is also greater than 0.7V, the fourth NPN transistor 4 is turned on, and finally the second PNP transistor PNP2, the third NPN transistor 3, and the fourth NPN transistor 4 form a positive feedback, and the SCR path on the positive feedback current is firstly formed, the maintaining voltage is mainly determined by the maintaining voltage of the inner SCR and cannot be reduced due to the increase of the interdigital;
in a similar way, when a negative ESD high-voltage pulse comes to the anode of the device and the cathode of the device is grounded, the first PNP transistor PNP1, the first NPN transistor NPN1 and the second NPN transistor NPN2 finally form positive feedback, the reverse SCR path starts the leakage current, and the reverse maintaining voltage is only dependent on the SCR path of the reverse inner side interdigital;
the working principle of the invention is as follows: firstly, the invention selects an asymmetric silicon controlled structure, and uses the path of the protection ring as a temporary discharge path of the negative pulse, thereby avoiding the problem of the parasitic path of the protection ring of the traditional device; secondly, the novel interdigital mode can increase and decrease the number of cathodes according to different protection grades. By floating the P + of the inner interdigital, the parasitic NPN base resistance of the inner interdigital is increased, and the opening of the outer interdigital is assisted, so that the conduction speed of the device is increased and the current distribution is more uniform; finally, the maintaining voltage of the whole device is generally determined by the innermost interdigital, so that the problem that the maintaining voltage of the device in the traditional interdigital mode is reduced along with the increase of the number of the interdigital is avoided. The silicon controlled rectifier electrostatic discharge device has the characteristics of high holding voltage and high failure current, and can realize high protection level while effectively avoiding latch-up effect.
The manufacturing method of the asymmetric bidirectional controllable silicon electrostatic discharge device in the interdigital mode comprises the following steps:
the method comprises the following steps: forming a P-type epitaxial layer 301 in a P-type substrate 101;
step two: forming an N-type buried layer 201 at the boundary of the P-type substrate 101 and the P-type epitaxial layer 301;
step three: a first high-voltage N well 401, a second high-voltage N well 402 and a third high-voltage N well 403 are sequentially generated from left to right above the N-type buried layer 201;
step four: a first deep N-well 501 is generated in the first high-voltage N-well 401, a second deep N-well 502 is generated in the second high-voltage N-well 402, the left side of the second deep N-well 502 exceeds the second high-voltage N-well 402, a third deep N-well 503 is generated in the third high-voltage N-well 403, and the left side of the third deep N-well 503 exceeds the third high-voltage N-well 403;
step five: a first shallow N-well 704 is generated above and to the left of the second deep N-well 502, and a second shallow N-well 707 is generated above and to the left of the third deep N-well 503;
step six: a first deep P well 601 is generated on the left side of the first deep N well 501, a second deep P well 602 and a third deep P well 603 are sequentially generated between the first deep N well 501 and the second deep N well 502 from left to right, a fourth deep P well 604 and a fifth deep P well 605 are sequentially generated between the second deep N well 502 and the third deep N well 503 from left to right, and a sixth deep P well 606 is generated on the right side of the third deep N well 503;
step seven: sequentially generating a first shallow P well 701 to a sixth shallow P well 708 in the first deep P well 601 to the sixth deep P well 606;
step eight: a first P + injection region 801 is generated in the first shallow P well 701, a second P + injection region 802 and a first N + injection region 803 are sequentially generated in the second shallow P well 702 from left to right, a fourth P + injection region 805 and a second N + injection region 806 are sequentially generated in the third shallow P well 603 from left to right, a third P + injection region 804 is generated between the second shallow P well 702 and the third shallow P well 703, a fifth P + injection region 807 and a third N + injection region 808 are sequentially generated in the fourth shallow P well 705 from left to right, a seventh P + injection region 810 and a fourth N + injection region 811 are sequentially generated in the fifth shallow P well 706 from left to right, a sixth P + injection region 809 is generated between the fourth shallow P well 705 and the fifth shallow P well 706, and an eighth P + injection region 812 is generated in the sixth shallow P well 708;
step nine: a first field oxide isolation region 901 is formed between the left side of the first P + implantation region 801 and the left side edge of the P-type epitaxial layer 301, a second field oxide isolation region 902 is formed between the right side of the first P + implantation region 801 and the left side of the second P + implantation region 802, a third field oxide isolation region 903 is formed between the right side of the second P + implantation region 802 and the left side of the first N + implantation region 803, a fourth field oxide isolation region 904 is formed between the right side of the first N + implantation region 803 and the left side of the third P + implantation region 804, a fifth field oxide isolation region 905 is formed between the right side of the third P + implantation region 804 and the left side of the fourth P + implantation region 805, a sixth field oxide isolation region 906 is formed between the right side of the fourth P + implantation region 805 and the left side of the second N + implantation region 806, a seventh field oxide isolation region 907 is formed between the right side of the second N + implantation region 806 and the left side of the fifth P + implantation region 807, and an eighth field oxide isolation region 908 is formed between the right side of the fifth P +, a ninth field oxide isolation region 909 is formed between the right side of the third N + injection region 808 and the left side of the sixth P + injection region 809, a tenth field oxide isolation region 910 is formed between the right side of the sixth P + injection region 809 and the left side of the seventh P + injection region 810, an eleventh field oxide isolation region 911 is formed between the right side of the seventh P + injection region 810 and the left side of the fourth N + injection region 811, a twelfth field oxide isolation region 912 is formed between the right side of the fourth N + injection region 811 and the left side of the eighth P + injection region 812, and a thirteenth field oxide isolation region 913 is formed between the right side of the eighth P + injection region 812 and the edge of the right side of the P-type epitaxial layer 301;
step ten: annealing the first P + implantation region 801 to the eighth P + implantation region 812 and the first N + implantation region 803 to the fourth N + implantation region 811 to eliminate the migration of impurities in the implantation regions;
step eleven: the fifth P + implant region 807, the third N + implant region 808, and the fourth N + implant region 811 are connected together and serve as the anode of the device, and the first P + implant region 801, the second P + implant region 802, the first N + implant region 803, the second N + implant region 806, and the eighth P + implant region 812 are connected together and serve as the cathode of the device.
The first step also comprises the following steps: growing a silicon dioxide film on a P-type substrate 101, and then depositing a silicon nitride film; spin-coating a photoresist layer on a wafer, and adding a mask plate to expose and develop the wafer to form an isolation shallow slot; and etching the silicon dioxide, the silicon nitride and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is removed.
The novel asymmetric electrostatic protection structure with the interdigital mode, which is manufactured by the invention, can not violate layout design rules and can not utilize layers beyond the standard BCD process, so that the bidirectional SCR can be applied to ESD protection design, an internal chip can be effectively protected, and the risk of latch-up is kept away while high protection level is ensured.
Compared with the asymmetric DDSCR device shown in FIG. 1, the device has the advantages of faster starting, higher holding voltage and failure current, and effectively avoiding latch-up effect.
Claims (9)
1. An asymmetric bidirectional controllable silicon electrostatic discharge device of interdigital mode which characterized in that: comprises a P-type substrate;
a P-type epitaxial layer is arranged above the P-type substrate, and an N-type buried layer is arranged between the P-type substrate and the P-type epitaxial layer;
a first high-voltage N well, a second high-voltage N well and a third high-voltage N well are sequentially arranged in the P-type epitaxial layer from left to right;
a first deep N well is arranged in the first high-voltage N well, a second deep N well is arranged in the second high-voltage N well, the left side of the second deep N well is wider than the second high-voltage N well, a third deep N well is arranged in the third high-voltage N well, and the left side of the third deep N well is wider than the third high-voltage N well;
a first shallow N well is arranged above the left side of the second deep N well, and a second shallow N well is arranged above the left side of the third deep N well;
a first deep P well is arranged on the left side of the first deep N well, a second deep P well and a third deep P well are sequentially arranged between the first deep N well and the second deep N well from left to right, a fourth deep P well and a fifth deep P well are sequentially arranged between the second deep N well and the third deep N well from left to right, and a sixth deep P well is arranged on the right side of the third deep N well;
a first shallow P well to a sixth shallow P well are sequentially arranged in the first deep P well to the sixth deep P well;
a first P + injection region is arranged in the first shallow P well; a second P + injection region and a first N + injection region are sequentially arranged in the second shallow P well from left to right; a fourth P + injection region and a second N + injection region are sequentially arranged in the third shallow P well from left to right; a third P + injection region is bridged between the second shallow P well and the third shallow P well; a fifth P + injection region and a third N + injection region are sequentially arranged in the fourth shallow P well from left to right; a seventh P + injection region and a fourth N + injection region are sequentially arranged in the fifth shallow P well from left to right; a sixth P + injection region is bridged between the fourth shallow P well and the fifth shallow P well; an eighth P + injection region is arranged in the sixth shallow P well;
the fifth P + injection region, the third N + injection region and the fourth N + injection region are connected together and used as an anode of the device; the first P + injection region, the second P + injection region, the first N + injection region, the second N + injection region and the eighth P + injection region are connected together and serve as a cathode of the device.
2. The interdigital asymmetric bidirectional thyristor electrostatic discharge device of claim 1, wherein: a first field oxygen isolation region is arranged between the left side of the first P + injection region and the left side edge of the P-type epitaxial layer, a second field oxygen isolation region is arranged between the right side of the first P + injection region and the left side of the second P + injection region, a third field oxygen isolation region is arranged between the right side of the second P + injection region and the left side of the first N + injection region, a fourth field oxygen isolation region is arranged between the right side of the first N + injection region and the left side of the third P + injection region, a fifth field oxygen isolation region is arranged between the right side of the third P + injection region and the left side of the fourth P + injection region, a sixth field oxygen isolation region is arranged between the right side of the fourth P + injection region and the left side of the second N + injection region, a seventh field oxygen isolation region is arranged between the right side of the second N + injection region and the left side of the fifth P + injection region, an eighth field oxygen isolation region is arranged between the right side of the fifth P + injection region and the left side of the third N + injection region, and a ninth field oxygen isolation region are, a tenth field oxygen isolation region is arranged between the right side of the sixth P + injection region and the left side of the seventh P + injection region, an eleventh field oxygen isolation region is arranged between the right side of the seventh P + injection region and the left side of the fourth N + injection region, a twelfth field oxygen isolation region is arranged between the right side of the fourth N + injection region and the left side of the eighth P + injection region, and a thirteenth field oxygen isolation region is arranged between the right side of the eighth P + injection region and the edge of the right side of the P-type epitaxial layer.
3. The device of claim 1, wherein the equivalent circuit comprises:
the second shallow N well, the third deep N well and the third high-voltage N well are used as a base electrode of the first PNP type transistor, and the fifth shallow P well and the fifth deep P well are used as a collector electrode of the first PNP type transistor;
the second shallow N well, the third deep N well and the third high-voltage N well are used as collectors of the first NPN transistor, the fifth shallow P well and the fifth deep P well are used as bases of the first NPN transistor, and the fourth N + injection region is used as an emitter of the first NPN transistor;
the second NPN transistor, wherein the second shallow N well, the third deep N well and the third high-voltage N well are used as a collector of the second NPN transistor, the fifth shallow P well and the fifth deep P well are used as a base of the second NPN transistor, and the third N + injection region is used as an emitter of the second NPN transistor;
the first PNP type transistor comprises a first shallow P well, a first high-voltage N well, a first PNP type transistor, a second PNP type transistor, a third shallow P well and a third deep P well, wherein the first shallow P well and the second deep P well are used as emitting electrodes of the first PNP type transistor;
the first shallow N well, the second deep N well and the second high-voltage N well are used as collectors of the third NPN transistor, the third shallow P well and the third deep P well are used as bases of the third NPN transistor, and the second N + injection region is used as an emitter of the third NPN transistor;
the first shallow N well, the second deep N well and the second high-voltage N well are used as collectors of the fourth NPN transistor, the third shallow P well and the third deep P well are used as bases of the fourth NPN transistor, and the first N + injection region is used as an emitter of the fourth NPN transistor;
the sixth shallow P well and the sixth deep P well are integrally formed into a first P well parasitic resistor;
a second P well parasitic resistor is formed among the fourth shallow P well, the fourth deep P well, the fifth shallow P well and the fifth deep P well;
a third P well parasitic resistor is integrally formed on the right side of the fourth shallow P well and the fourth deep P well;
a fourth P well parasitic resistor is integrally formed on the left side of the fourth shallow P well and the fourth deep P well;
a fifth P well parasitic resistor is formed among the second shallow P well, the second deep P well, the third shallow P well and the third deep P well;
the second shallow P-well and the second deep P-well form a sixth P-well parasitic resistor.
4. The device of claim 3, wherein in the equivalent circuit, one end of the fourth P-well parasitic resistor is connected to the fifth P + injection region, the other end of the fourth P-well parasitic resistor is connected to the emitter of the second PNP transistor, the base of the second PNP transistor, the collector of the third NPN transistor and the collector of the fourth NPN transistor are connected together, the base of the third NPN transistor and one end of the fifth P-well parasitic resistor are connected together, the other end of the fifth P-well parasitic resistor is connected to the base of the fourth NPN transistor, the collector of the second NPN transistor and one end of the sixth P-well parasitic resistor, the emitter of the third NPN transistor and the second N + injection region are connected together, and the emitter of the fourth NPN transistor and the first N + injection region are connected together, the other end of the sixth P trap parasitic resistor is connected with the second P + injection region; the fourth P well parasitic resistor, the second PNP transistor, the third NPN transistor, the fourth NPN transistor, the fifth P well parasitic resistor and the sixth P well parasitic resistor jointly form a forward SCR current leakage path;
one end of the first P well parasitic resistor is connected to the eighth P + injection region, the other end of the first P well parasitic resistor is connected with the emitter of the first PNP transistor, the base of the first PNP transistor, the collector of the first NPN transistor and the collector of the second NPN transistor are connected together, the base of the first NPN transistor and one end of the second P well parasitic resistor are connected together, the other end of the second P well parasitic resistor is connected with the base of the second NPN transistor, the collector of the first PNP transistor and one end of the third P well parasitic resistor, the emitter of the first NPN transistor and the fourth N + injection region are connected together, the emitter of the second NPN transistor and the third N + injection region are connected together, and the other end of the third P well parasitic resistor and the fifth P + injection region are connected together; the first P well parasitic resistor, the first PNP transistor, the first NPN transistor, the second P well parasitic resistor and the third P well parasitic resistor jointly form a reverse SCR current leakage path.
5. The interdigital asymmetric bidirectional thyristor electrostatic discharge device of claim 4, wherein: when an ESD high-voltage pulse comes to an anode of the device, when a cathode of the device is at a ground potential, the first shallow N well, the second deep N well, the second high-voltage N well, the P-type epitaxial layer, the third shallow P well and the third deep P well are subjected to avalanche breakdown, avalanche carriers flow through a fifth P well parasitic resistor and a sixth P well parasitic resistor, when voltage drop between the fifth P well parasitic resistor and the sixth P well parasitic resistor is more than 0.7V, the third NPN transistor is started firstly, so that a base electrode of the second PNP transistor is started when the potential is reduced, the fourth NPN transistor is also started when voltage between two ends of the sixth P well parasitic resistor is also more than 0.7V along with the gradual increase of current, and finally the second PNP transistor, the third NPN transistor and the fourth NPN transistor form positive feedback, a positive SCR path starts to discharge current, and the maintenance voltage mainly depends on the maintenance voltage of the inner side SCR due to the first formation of the SCR path, the reduction caused by the increase of the interdigital is avoided;
and similarly, when a negative ESD high-voltage pulse comes to the anode of the device and the cathode of the device is grounded, finally the first PNP transistor, the first NPN transistor and the second NPN transistor form positive feedback, the reverse SCR path starts the leakage current, and the reverse maintaining voltage is only dependent on the SCR path of the inner interdigital of the reverse phase.
6. The interdigital asymmetric bidirectional thyristor electrostatic discharge device of claim 5, wherein: the static electricity discharge device adopts an asymmetric silicon controlled structure, and a path of the protection ring is used as a temporary leakage path of the negative pulse.
7. The interdigital asymmetric bidirectional thyristor electrostatic discharge device of claim 5, wherein: the interdigital mode can control the protection level of the device according to the increase and decrease of the number of the cathodes; the P + of the inner interdigital floats.
8. A method for fabricating an interdigital asymmetric triac electrostatic discharge device as claimed in any one of claims 1-7, comprising the steps of:
the method comprises the following steps: forming a P-type epitaxial layer in a P-type substrate;
step two: forming an N-type buried layer at the junction of the P-type substrate and the P-type epitaxial layer;
step three: sequentially generating a first high-voltage N well, a second high-voltage N well and a third high-voltage N well from left to right above the N-type buried layer;
step four: generating a first deep N well in the first high-voltage N well, generating a second deep N well in the second high-voltage N well, wherein the left side of the second deep N well exceeds the second high-voltage N well, and generating a third deep N well in the third high-voltage N well, wherein the left side of the third deep N well exceeds the third high-voltage N well;
step five: generating a first shallow N well at the upper left of the second deep N well, and generating a second shallow N well at the upper left of the third deep N well;
step six: a first deep P well is generated on the left side of the first deep N well, a second deep P well and a third deep P well are sequentially generated between the first deep N well and the second deep N well from left to right, a fourth deep P well and a fifth deep P well are sequentially generated between the second deep N well and the third deep N well from left to right, and a sixth deep P well is generated on the right side of the third deep N well;
step seven: sequentially generating a first shallow P well to a sixth shallow P well in the first deep P well to the sixth deep P well;
step eight: generating a first P + injection region in a first shallow P well, sequentially generating a second P + injection region and a first N + injection region in a second shallow P well from left to right, sequentially generating a fourth P + injection region and a second N + injection region in a third shallow P well from left to right, generating a third P + injection region between the second shallow P well and the third shallow P well, sequentially generating a fifth P + injection region and a third N + injection region in a fourth shallow P well from left to right, sequentially generating a seventh P + injection region and a fourth N + injection region in the fifth shallow P well from left to right, generating a sixth P + injection region between the fourth shallow P well and the fifth shallow P well, and generating an eighth P + injection region in the sixth shallow P well;
step nine: a first field oxide isolation region is generated between the left side of the first P + injection region and the left side edge of the P-type epitaxial layer, a second field oxide isolation region is generated between the right side of the first P + injection region and the left side of the second P + injection region, a third field oxide isolation region is generated between the right side of the second P + injection region and the left side of the first N + injection region, a fourth field oxide isolation region is generated between the right side of the first N + injection region and the left side of the third P + injection region, a fifth field oxide isolation region is generated between the right side of the third P + injection region and the left side of the fourth P + injection region, a sixth field oxide isolation region is generated between the right side of the fourth P + injection region and the left side of the second N + injection region, a seventh field oxide isolation region is generated between the right side of the second N + injection region and the left side of the fifth P + injection region, an eighth field oxide isolation region is generated between the right side of the fifth P + injection region and the left side of the third N + injection region, and a ninth field oxide isolation region are, a tenth field oxygen isolation region is formed between the right side of the sixth P + injection region and the left side of the seventh P + injection region, an eleventh field oxygen isolation region is formed between the right side of the seventh P + injection region and the left side of the fourth N + injection region, a twelfth field oxygen isolation region is formed between the right side of the fourth N + injection region and the left side of the eighth P + injection region, and a thirteenth field oxygen isolation region is formed between the right side of the eighth P + injection region and the right edge of the P-type epitaxial layer;
step ten: annealing the first P + injection region to the eighth P + injection region and the first N + injection region to the fourth N + injection region to eliminate the migration of impurities in the injection regions;
step eleven: and connecting the fifth P + injection region, the third N + injection region and the fourth N + injection region together to serve as an anode of the device, and connecting the first P + injection region, the second P + injection region, the first N + injection region, the second N + injection region and the eighth P + injection region together to serve as a cathode of the device.
9. The method for manufacturing an interdigital asymmetric bidirectional triode thyristor electrostatic discharge device according to claim 8, wherein the first step further comprises the following steps: growing a silicon dioxide film on a P-type substrate, and then depositing a silicon nitride film; spin-coating a photoresist layer on a wafer, and adding a mask plate to expose and develop the wafer to form an isolation shallow slot; and etching the silicon dioxide, the silicon nitride and the isolation shallow groove, removing the photoresist layer, depositing a layer of silicon dioxide, and then performing chemical mechanical polishing until the silicon nitride layer is removed.
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