CN211654821U - Low-capacitance low-clamping voltage transient voltage suppressor - Google Patents

Abstract

The utility model relates to a low electric capacity hangs down clamping voltage transient voltage suppressor. The TVS tube with the structure of the low-capacitance low-clamping-voltage transient voltage suppressor comprises an N-sub silicon wafer of an N-type silicon substrate, a P-type trap PW, a P + region, an N + region, a medium, a ground metal layer Gnd, a TVS device connected with a power metal layer VCC, a signal end IO1 and an IO2 metal, and is characterized in that: at least a first to a fourth P-type trap PW1-4 are included on an N-sub or a grown N-epi of an N-type silicon substrate, and a TVS tube of the transistor is a bipolar transistor composed of N +/PW2/PW3/N +. The TVS tube of the low-capacitance low-clamping-voltage transient voltage suppressor structure has the bipolar transistor effect, and has the advantages of low breakdown voltage, low trigger voltage and quicker protection response; the circuit also has the characteristic of smaller on-resistance and clamping voltage, and has stronger protection capability on a post-stage integrated circuit.

Description

Low-capacitance low-clamping voltage transient voltage suppressor

Technical Field

The utility model relates to a technical field of semiconductor protection device especially relates to a low electric capacity hangs down clamp voltage transient voltage suppressor for the protection device design and the manufacturing field of high-speed signal port.

Background

The transient voltage suppressor (TVS for short) is a clamping overvoltage protection device which can fix surge voltage at a lower voltage level in a short time, so that a rear-stage integrated circuit is prevented from being impacted by over-static discharge or surge voltage and damaged.

The TVS device is mainly applied to various interface circuits, for example, a large number of TVS protection devices are arranged in a mobile phone, a flat panel, a television and a computer host, the IO end of the TVS device is usually connected with the IO end of a circuit, the grounding end is connected with the ground in the circuit, namely, the TVS device and a protected chip are in parallel connection, when electrostatic discharge or surge voltage enters from the IO end of the circuit, the TVS device can be triggered to be preferentially conducted, current is released to the ground through the TVS device, and the voltage is clamped at a lower level, so that a rear-stage integrated circuit is effectively protected.

With the rapid development of modern technologies, integrated circuits are continuously developing in the direction of low voltage, low power consumption and high-speed transmission, and higher performance requirements are also provided for corresponding TVS protection devices, which require that the clamping voltage of a TVS is as low as possible and that a capacitor is as small as possible, and are generally applied to high-speed ports such as HDMI3.0/3.1 and USB3.1, where the capacitor requirement is less than 0.5pF, and a large capacitor may cause packet loss and other abnormalities of high-frequency signals in the transmission process.

Disclosure of Invention

In order to solve the above problems, the utility model aims to solve the technical problem that: a low capacitance low clamp voltage transient voltage suppressor is provided.

The purpose of the utility model is realized through the following scheme: a transient voltage suppressor with low capacitance and low clamping voltage comprises a TVS device which comprises an N-type silicon substrate N-sub silicon chip, a P-type trap PW, a P + region, an N + region, a medium, a grounding metal layer Gnd, a power supply metal layer VCC, a signal end IO1 and an IO2 metal layer on the basis of a TVS tube structure, at least comprises a first P-type trap PW1-4, a second P-type trap PW1-4 and a third P-type trap PW1-4,

the first and fourth P-type wells PW1, 4 are lightly doped P-type wells with the same structure, and each well comprises a P + region and an N + region;

the second P-type well PW2 contains a random heavily doped N + region; and the number of the first and second groups,

the third P-type well PW3 well sequentially comprises an N + region, a P + region and light doping of the N + region, and the width of the P + region in the third P-type well PW3 is smaller than that of the N + region;

the TVS tube consists of a bipolar transistor consisting of N +/PW2/PW3/N +, a second P-type well PW2 and a third P-type well PW3 in a base region are shorted together with a collector N + of a grounding terminal through a P + lead-out; when electrostatic discharge or surge is generated, because the second P-type well PW2 is heavily doped, the breakdown voltage of N +/PW2 is lower, and after the N +/PW2 junction breaks down, current flows from the second P-type well PW2 to the third P-type well PW3 and then flows out from the P + end to the ground end; meanwhile, because the third P-type well PW3 is lightly doped, the voltage difference generated by the current from the third P-type well PW3 to P + is easily larger than 0.7V due to its higher resistance, at this time, the bipolar transistor effect is generated, the current can flow out from the P + end and also from the N + end of the ground end, and a significant negative resistance characteristic is presented, that is, the current-voltage curve is obviously snapbacked;

a P-type buried layer (P-BL) is added below the second P-type well PW2 and the third P-type well PW3 and matched with an N-type substrate to form a wider depletion region, so that the parasitic capacitance of the bottom junction of the TVS transistor is greatly reduced, and the overall capacitance of the device is remarkably reduced and is smaller than that of the device with the traditional structure by more than 10%;

the P + region is an ultra-shallow junction or has the same junction depth with the N + region, when the TVS tube is conducted, the path from the current to the base region P + from the second and third P-type wells PW2 and PW3 is lengthened, meanwhile, the width of the base region P + is narrower, the width of the base region P + is smaller than that of the N + at the two sides of the base region P +, and under the combined action of the two, the resistance on the current path is larger, so that the bipolar transistor effect can be triggered only by small current reaching the base region P +, the negative resistance snapback is generated in advance, and the clamping voltage is further reduced;

two types of diodes were formed: the first diode from the IO end to the VCC end is formed by P +/N-epi/N +, N-epi is a high resistance epitaxy, and the P + and the N-epi form a wider space charge region to reduce the capacitance of the diode; the second diode from ground (Gnd) to signal terminal IO is composed of two diodes formed by P +/PW1/N + and/or P +/PW4/N +, the first P-type well PW1 and the fourth P-type well PW4 are lightly doped, so that a wider space charge region is formed between N + and the first P-type well PW1 and the fourth P-type well PW4 to reduce the capacitance of the diode. The capacitance of the device as a whole is reduced accordingly.

Furthermore, the implanted elements PW1 and 4 of the first and fourth P-type wells are boron, and the implantation dosage is 5E 11-1E 13CM^-2The implantation energy is 60-100 KeV; the second P-type well PW2 is implanted with boron at an implant dose of 1E 14-9E 14CM^-2The implantation energy is 60-100 KeV; the third P-type well PW3 is implanted with boron at an implant dose of 1E 12-1E 14CM^-2The implantation energy is 60 to 100 KeV.

Furthermore, phosphorus or arsenic impurities are doped in the N-type epitaxial growth, the resistivity of the N-type epitaxial growth is 50-300 omega CM, and the epitaxial thickness is 3-8 mu m; p + is an ultra-shallow junction, the implantation element is boron, and the implantation dosage is 1E 15-8E 15CM^-2The implantation energy is 40-80 KeV; the N + region is heavily doped, the implantation element is phosphorus or arsenic, and the implantation dosage is 2E 15-1.2E 16 CM^-2The implantation energy is 80-150 KeV; in the diode formed by P +/N-epi/N + from the IO end to the VCC end, a smaller junction area is formed by P + and N-epi, the diode has smaller capacitance, and the capacitance of the whole device can be reduced.

On the basis of the scheme, the third P-type well PW3 and the second P-type well PW2 are arranged in a surrounding shape or a plug-finger shape, so that the current path area is further increased, and the surge peak current is improved, so that better electrostatic discharge and surge protection capability is obtained.

On the basis of the scheme, the utility model provides a TVS pipe of low clamp voltage transient voltage suppressor structure of low electric capacity, it has one deck N-type epitaxial layer and P-type buried layer P-BL to grow on the silicon substrate silicon chip of N-type, be the first P type well PW1 including P + district, N + district in proper order on N-type epitaxial layer surface from left to right, the P + district, the N + district on one side N-type epitaxial layer surface, the second P type well PW2 that has N + district, the third P type well PW3 that includes N + district, P + district and N + district in proper order, the fourth P type well PW4 including P + district, N + district, the P + district, N + district on the other side N-type epitaxial layer surface, second P type well PW2 and third P PW3 bottom connect P-type buried layer P-BL; the P + region in the first P-type well PW1 and the third P-type well PW3 are connected with a metal ground terminal; the N + region on the surface of the N-type epitaxial layer and the N + region of the second P-type well PW2 are connected with the power supply metal layer VCC; an N + region in the first P-type well PW1 and a P + region on the surface of the N-type epitaxial layer on one side are connected with a signal end IO 1; an N + region in the fourth P-type well PW4 and a P + region on the surface of the other side N-type epitaxial layer are connected with a signal terminal IO 2.

Wherein the N-substrate resistivity is 200-300 omega CM.

Further, the thickness of the P-type buried layer (P-BL) is 200-500 Å, boron or boron difluoride is ion-implanted, the implantation energy is 60-100 KeV, and the implantation dosage is 5E 11-5E 12CM^-2。

Preferably, the junction depth of the P + region is shallower than the junction depth of the N + region.

On the basis of the scheme, an N-type epitaxial layer is not grown on an N-type substrate, a P + region and an N + region originally arranged on the N-type epitaxial layer are directly arranged on the surface of the N-type substrate, and the P + region and the N + region are formed in the surface of the N-type substrate.

Furthermore, the P + region and the N + region in the N-type substrate are disposed in N-type well NW, and the shapes of second and third P-type wells PW2 and 3 are adjusted so that third P-type well PW3 surrounds second P-type well PW 2.

Further, a Deep P-region Deep P-is added at the bottom of the third P-type well PW 3.

On the basis of the scheme, a P + buried layer P + BL can be added between the upper surface of the P-type buried layer P-BL and the bottoms of the second and third P-type traps PW2 and 3.

Based on the above scheme, the utility model provides another TVS tube with low capacitance and low clamping voltage transient voltage suppressor structure, an N-type epitaxial layer and a P-type buried layer (P-BL) are grown on the N-type silicon substrate silicon chip, the bottom parts of a first P-type well PW1 comprising a P + region and an N + region, a P + region and an N + region on the surface of the N-type epitaxial layer on one side, a third P-type well PW3 comprising the N + region, the P + region and the N + region in sequence, a second P-type well PW2 comprising the N + region, a fifth P-type well PW5 comprising the N + region, the P + region and the N + region in sequence, a fourth P-type well PW4 comprising the P + region and the N + region, a P + region and an N + region on the surface of the N-type epitaxial layer on the other side, and a third P-type well PW3, a third P-type buried layer P-BL and a fifth P-type well PW 365 on the surface of the N-type epitaxial layer from left to right; a P + region in the first P-type well PW1, a third P-type well PW3 and a fifth P-type well PW5 are connected with a metal ground terminal; the N + region on the surface of the N-type epitaxial layer and the N + region of the second P-type well PW2 are connected with the power supply metal layer VCC; an N + region in the first P-type well PW1 and a P + region on the surface of the N-type epitaxial layer on one side are connected with a signal end IO 1; an N + region in the fourth P-type well PW4 and a P + region on the surface of the other side N-type epitaxial layer are connected with a signal terminal IO 2.

In order to further reduce capacitance, a lightly doped P-type well PW region is added around a P + region on the surface of the N-type epitaxial layer, a diode from an IO end to VCC is formed by P +/lightly doped PW/N-epi/N +, and the lightly doped PW and the N-epi of the N-type epitaxial layer form a wider space charge region.

The utility model provides a TVS pipe manufacturing method according to foretell low electric capacity low clamp voltage transient voltage suppressor structure, including following step:

step 1: growing a thin oxide layer on the upper surface of an N-type substrate silicon wafer, performing photoetching and ion implantation, performing thermal process propulsion to form a P-type buried layer P-BL, and removing the thin oxide layer on the surface by wet etching.

Step 2: growing an N-type epitaxial layer on the surface of the silicon wafer;

and step 3: performing PWell1 and 4 photoetching, ion implantation, second P-type well PW2 photoetching, ion implantation, PWell3 photoetching and ion implantation on the epitaxial surface of the silicon wafer in sequence, wherein the positions of the second P-type well PWell2 and the third P-type well PWell 353 correspond to the positions of the P-type buried layer P-BL, and the structures of the first P-type well PW1 and the fourth P-type well PW 384 are the same;

and 4, step 4: putting the silicon wafer into a high-temperature furnace tube, and simultaneously propelling the first to fourth P-type wells PW1-4 to ensure that the second P-type well PW2 and the third P-type well PW3 are connected with a P-type buried layer P-BL;

and 5: performing N + selective implantation on the surface, wherein the N + implantation is realized by photoetching and ion implantation processes, and the N + implantation element is phosphorus or arsenic, and then entering a furnace tube for annealing to repair implantation damage;

step 6: performing P + selective implantation on the surface, wherein the P + implantation element is boron, the distance between P + and N + in PW3 is set to be 0-5 mu m, the implantation energy is less than that of N + implantation, and then performing rapid thermal annealing to repair implantation damage;

and 7: performing medium deposition on the surface to form a medium layer, and then performing photoetching and etching to form a contact hole, wherein the medium layer is one of an oxide layer, boron-phosphorus glass or a multilayer insulating film composite layer;

and 8: and carrying out metal deposition, and then forming a front metal layer by photoetching and etching, wherein the metal layer is a pure aluminum layer, an aluminum-silicon compound layer or a metal composite layer structure.

Preferably, in step 1, the thickness of the thin oxide layer is 200-500 Å, boron or boron difluoride is ion implanted, the implantation energy is 60-100 KeV, and the implantation dosage is 5E 11-5E 12CM^-2The injection angle is 7 ℃, the hot process is pushed into a high-temperature furnace tube, the temperature is 950-1100 ℃, and the time is 60-120 minutes.

Preferably, in step 2, the N-type epitaxial growth is doped with phosphorus or arsenic impurities, the resistivity of the N-type epitaxial growth is 50-300 Ω CM, and the epitaxial thickness is 3-8 μm.

Preferably, in step 3, the implantation elements of the first and fourth P-type wells PW1, 4 are boron, and the implantation dose is 5E 11-1E 13CM^-2The implantation energy is 60 to 100KeV, and the implantation angle is 7 degrees. The second P-type well PW2 is implanted with boron at an implant dose of 1E 14-9E 14CM^-2The implantation energy is 60 to 100KeV, and the implantation angle is 7 degrees. First, theThe tri-P type well PW3 is implanted with boron at an implant dose of 1E 12-1E 14CM^-2The implantation energy is 60 to 100KeV, and the implantation angle is 7 degrees.

Preferably, in the step 4, the temperature of the furnace tube is 1000-1150 ℃ and the time is 60-120 minutes.

Preferably, in step 5, the N + implantation element is phosphorus or arsenic, and the implantation dose is 2E 15-1.2E 16 CM^-2The injection energy is 80-150 KeV, the annealing process temperature is 850-950 ℃, and the time is 30-60 minutes.

Preferably, in step 6, the P + implantation element is boron, and the implantation dose is 1E 15-8E 15CM^-2The implantation energy is 40-80 KeV; the rapid thermal annealing temperature is 950-1050 ℃, and the time is 10-30 seconds, so that the P + junction depth is obviously shallower than the N + junction depth.

Further, in step 6, the distance between the P + region and the N + region in the third P-type well PW3 is 0 μm, and the P + width in the third P-type well PW3 is set to 1-5 μm.

Furthermore, in step 6, the width of P + in the third P-type well PW3 is set to 0.5-1.5 μm.

Preferably, in step 8, the metal composite layer structure is a three-layer structure of titanium, titanium nitride and aluminum-silicon-copper in sequence from bottom to top, wherein the thickness of titanium is 200 to 500 a, the thickness of titanium nitride is 400 to 1000 a, and the thickness of aluminum-silicon-copper is 2 to 4 μm.

The utility model has the advantages that: the TVS tube of the low-capacitance low-clamping-voltage transient voltage suppressor structure has the bipolar transistor effect, and has the advantages of low breakdown voltage, low trigger voltage and quicker protection response; meanwhile, the circuit has the characteristic of smaller on-resistance and clamping voltage, and has stronger protection capability on a post-stage integrated circuit. The utility model also provides a manufacturing approach of above-mentioned TVS pipe, the yield is high.

Drawings

FIG. 1 is a schematic cross-sectional view of embodiment 1 of the present invention;

FIG. 2 is a schematic structural diagram of a silicon wafer with a P-type buried layer (P-BL) formed on an N-type substrate silicon wafer in step 1;

FIG. 3 is a schematic diagram of a silicon wafer structure for growing an N-type epitaxial layer in step 2;

FIG. 4 is a schematic structural diagram of a silicon wafer subjected to PWell1-4 implantation on the surface of an N-type epitaxial layer in step 3;

FIG. 5, step 4, the silicon wafer in step 3 is put into a high temperature furnace tube, and PWell1-4 is simultaneously pushed, so that the silicon wafer structure schematic diagram of PWell2, PWell3 and P-BL region are connected;

FIG. 6 is a schematic diagram of a silicon wafer structure in which N + selective implantation is performed on the silicon wafer to form N + junctions in step 5;

FIG. 7 is a schematic diagram of a silicon wafer structure in which P + selective implantation is performed on the surface of the silicon wafer in step 5 in step 6, and the silicon wafer structure is formed by implanting a P + junction between the N + deep junction of PWell3 and the P + junction in PWell1, N + epitaxial surface N +, PWell 4;

and 8, step 7 in the step 6, carrying out medium deposition on the upper surface of the silicon wafer, and then photoetching and etching to form a contact hole. The dielectric layer can be an oxide layer, can also be boron-phosphorus glass, and can also be a multilayer insulating film composite layer;

FIG. 9 is a schematic diagram showing the structure of P +, N + junctions of the same depth in embodiment 2;

FIG. 10 is a schematic structural view of the P + N + junction of example 3 with equal depth and without epitaxial layer growth;

fig. 11 is a schematic structural diagram of embodiment 4, where no epitaxy is grown, P + and N + in the N-type substrate are located in NWell, PWell2 is located in PWell3, and P + and N + junctions are as deep as possible, and no epitaxial layer is grown;

FIG. 12 is the structural diagram of example 5, without epitaxy, with P + and N + in the N-type substrate set in NWell, PWell2 in PWell3 and a deep P-junction below PWell 3;

fig. 13 is a schematic structural diagram of embodiment 6, which is different from embodiment 1 in that a P + type buried layer (P + BL) and a P-type buried layer (P-BL) are sequentially disposed at the bottom of PWell 2-3;

fig. 14 is a schematic structural diagram of embodiment 7, a PWell5 having the same structure as PWell3 is added to the left side of PWell2, and the bottoms of pwells 5, 2 and 3 are connected to a P-type buried layer (P-BL);

fig. 15 is a schematic structural diagram of embodiment 8, where a PWell5 having the same structure as PWell3 is added to the left side of PWell2, P + on the N-type epitaxy is PWell6, 7, and the bottoms of PWell5, PWell 382 and PWell3 are connected to the P-type buried layer (P-BL);

FIG. 16 is a schematic circuit diagram;

the reference numbers in the figures illustrate:

N-sub-N-type silicon substrate; N-epi-N-type epitaxial layer;

P-BL-P-type buried layer;

deep P-region, Deep P-;

PW-P well;

PW 1-7-first through seventh P-wells;

NW-N well;

NW1, 2-first, second N-type wells;

gnd-ground metal layer, VCC-power metal layer;

d1-4-first to fourth diodes;

1-a dielectric layer; 2-metal layer.

Detailed Description

Example 1

A TVS tube with a low-capacitance low-clamping voltage transient voltage suppressor structure is shown in figure 1 and comprises a TVS device with a P-type trap PW, a P + region, an N + region, a medium, a ground metal layer Gnd, a power metal layer VCC, a signal end IO1 and an IO2 metal, wherein on the basis of the structure of the existing TVS device, an N-type epitaxial layer N-epi and a P-type buried layer P-BL are grown on an N-type silicon substrate N-sub silicon wafer, and the TVS tube comprises:

the surface of the N-type epitaxial layer is sequentially as follows from left to right:

a first P-type well PW1 including P + region and N + region;

a P + region and an N + region on the surface of the N-type epitaxial layer on one side;

a second P-type well PW2 with an N + region;

a third P-type well PW3 sequentially including N + region, P + region and N + region;

a fourth P-type well PW4 including P + region and N + region;

a P + region and an N + region on the surface of the N-type epitaxial layer on the other side;

the bottoms of the second P-type trap PW2 and the third P-type trap PW3 are connected with a P-type buried layer P-BL; a P + region in the first P-type well PW1 and a third P-type well PW3 are connected with the ground metal layer Gnd; an N + region on the surface of the N-epi of the N-type epitaxial layer and an N + region of the second P-type well PW2 are connected with the power supply metal layer VCC; an N + region in the first P-type well PW1 and a P + region on the surface of the N-type epitaxial layer on one side are connected with a signal end IO 1; an N + region in the fourth P-type well PW4 and a P + region on the surface of the other side N-type epitaxial layer are connected with a signal terminal IO 2.

In this embodiment, the first and fourth P-type wells PW1, 4 are lightly doped P-type wells with the same structure, and each well includes a P + region and an N + region;

the second P-type well PW2 contains a random heavily doped N + region; and the number of the first and second groups,

the third P-type well PW3 well sequentially comprises an N + region, a P + region and light doping of the N + region, and the width of the P + region in the third P-type well PW3 is smaller than that of the N + region;

the TVS tube consists of a bipolar transistor consisting of N +/PW2/PW3/N +, a second P-type well PW2 and a third P-type well PW3 of a base region are shorted together with a collector N + connected with the grounded metal layer Gnd through a P + lead-out; when static electricity is released or surge is generated, because the second P-type well PW2 is heavily doped, the breakdown voltage of N +/PW2 is lower, and after the N +/PW2 junction breaks down, current flows from the second P-type well PW2 to the third P-type well PW3 and then flows out from the P + end to the ground end; meanwhile, because the third P-type well PW3 is lightly doped, the voltage difference generated by the current from the third P-type well PW3 to P + is easily larger than 0.7V due to the higher resistance of the third P-type well PW3, at this time, the bipolar transistor effect is generated, the current can flow out from the P + end and also from the collector N + of the ground end, and the current exhibits a significant negative resistance characteristic, that is, the current-voltage curve is obviously snapbacked;

a P-type buried layer P-BL is added below the second P-type well PW2 and the third P-type well PW3 and matched with an N-type substrate N-sub to form a wider depletion region, so that the parasitic capacitance of the bottom junction of the TVS tube is greatly reduced, the integral capacitance of the device is remarkably reduced, and the capacitance of the device is smaller than that of the device with a traditional structure by more than 10%;

the P + region is an ultra-shallow junction, when the TVS tube is conducted, the path from the current to the base region P + from the second P-type well PW2 and the third P-type well PW3 is lengthened, meanwhile, the width of the base region P + is set to be narrower, the width of the base region P + is smaller than that of the N + regions at two sides of the base region P +, and under the combined action of the two, the resistance on the current path is larger, so that the bipolar transistor effect can be triggered only by small current reaching the base region P +, negative resistance snapback occurs in advance, and the clamping voltage is further reduced;

two types of diodes were formed: the first diode D1 from the IO1 end to the VCC end and the third diode D3 from the IO2 end to the VCC end are formed by P +/N-epi/N + junctions, N-epi is a high resistance epitaxy, and the P + and the N-epi form a wider space charge region to reduce the capacitance of the diodes; the second diode D2 from ground (Gnd) to IO1 and the fourth diode D4 from ground Gnd to signal IO2, i.e. the second diode D2 is composed of P +/PW1/N + and the fourth diode D4 is composed of P +/PW4/N +, the first P-type well PW1 and the fourth P-type well PW4 are lightly doped, so that a wider space charge region is formed between N + and the first P-type well PW1 and the fourth P-type well PW4 to reduce the capacitance of the diodes. The capacitance of the device as a whole is reduced accordingly. The schematic diagram of the circuit is shown in fig. 16.

In this embodiment, the implantation elements of the first and fourth P-type wells PW1, 4 are boron, and the implantation dose is 5E 11-1E 13CM^-2The implantation energy is 60-100 KeV; the second P-type well PW2 is implanted with boron at an implant dose of 1E 14-9E 14CM^-2The implantation energy is 60-100 KeV; the third P-type well PW3 is implanted with boron at an implant dose of 1E 12-1E 14CM^-2The implantation energy is 60 to 100 KeV.

Phosphorus or arsenic impurities are doped in the N-epi growth of the N-type epitaxial layer, the resistivity of the N-epi growth is 50-300 omega CM, and the epitaxial thickness is 3-8 mu m; p + is an ultra-shallow junction, the implantation element is boron, and the implantation dosage is 1E 15-8E 15CM^-2The implantation energy is 40-80 KeV; the N + region is heavily doped, the implantation element is phosphorus or arsenic, and the implantation dosage is 2E 15-1.2E 16 CM^-2The implantation energy is 80-150 KeV; and in the diode formed by P +/N-epi/N + from the IO terminal to the VCC terminal, a smaller junction area is formed by P + and N-epi.

This example was made as follows:

step 1: as shown in figure 2, an N-type substrate N-sub with the resistivity of 200-300 omega CM is used, a thin oxide layer grows on the upper surface of the N-type substrate N-sub, a P-type buried layer P-BL is formed by photoetching and ion implantation in a thermal process, and then the thin oxide layer on the surface is removed in a wet etching mode.

Preferably, the N-substrate is formed by ion implantation of boron or boron difluoride into a thin oxide layer with a thickness of 200-500 Å, an implantation energy of 60-100 KeV, and an implantation dose of 5E 11-5E 12CM^-2The implantation angle was 7 degrees. And (3) pushing the thermal process into a high-temperature furnace tube at 950-1100 ℃ for 60-120 minutes to form the P-type buried layer P-BL.

Step 2: as shown in FIG. 3, N-type epitaxial growth is performed on the surface of the silicon wafer. Preferably, the N-type epitaxial layer N-epi is doped with phosphorus or arsenic impurities, has a resistivity of 50 to 300 Ω CM, and has a thickness of 3 to 8 μm.

And step 3: and sequentially carrying out photoetching and ion implantation on the first and fourth P-type wells PW1, 4, photoetching and ion implantation on the epitaxial surface of the silicon wafer, photoetching and ion implantation on the second P-type well PW2, photoetching and ion implantation on the third P-type well PW3, and forming a silicon wafer structure shown in FIG. 4.

Preferably, the PW1 implantation element is boron, and the implantation dosage is 5E 11-1E 13CM^-2The implantation energy is 60 to 100KeV, and the implantation angle is 7 degrees. The PW2 implantation element is boron, and the implantation dosage is 1E 14-9E 14CM^-2The implantation energy is 60 to 100KeV, and the implantation angle is 7 degrees. The PW3 implantation element is boron, and the implantation dosage is 1E 12-1E 14CM^-2The implantation energy is 60 to 100KeV, and the implantation angle is 7 degrees.

And 4, step 4: and (4) putting the silicon wafer obtained in the step (3) into a high-temperature furnace tube, and simultaneously pushing the first to fourth P-type wells PW1-4 so that the second and third P-type wells PW2 and 3 are connected with the P-type buried layer P-BL. As shown in FIG. 5, the temperature of the furnace tube is preferably 1000-1150 ℃ for 60-120 minutes.

And 5: and carrying out N + selective implantation on the surface, and realizing the N + selective implantation through photoetching and ion implantation processes. And then the silicon wafer is put into a furnace tube for annealing to repair the injection damage, as shown in figure 6. Preferably, the N + implantation element is phosphorus or arsenic, and the implantation dosage is 2E 15-1.2E 16 CM^-2The implantation energy is 80-150 KeV. The annealing process is carried out at the temperature of 850-950 ℃ for 30-60 minutes.

Step 6: performing P + selective implantation on the surface by photolithography and ion implantationAnd (4) realizing an injection process. And then carrying out rapid thermal annealing to repair the injection damage. In this embodiment, the P + implantation element is boron, and the implantation dose is 1E 15-8E 15CM^-2The implantation energy is 40 to 80 KeV. The rapid thermal annealing temperature is 950-1050 ℃ and the time is 10-30 seconds. Making the P + junction depth significantly shallower than the N + junction depth as shown in fig. 7.

Preferably, the P + and N + spacings in the third P-type well PW3 are set to 0-5 μm, more preferably 0 μm.

Preferably, the P + width in the third P-type well PW3 is set to 1-5 μm, more preferably 0.5-1.5 μm.

And 7: and performing dielectric deposition on the surface, and then performing photoetching and etching to form a contact hole, which is shown in figure 8. The dielectric layer 1 may be an oxide layer, or boron-phosphorus glass, or a multilayer insulating film composite layer.

And 8: and performing metal deposition, and then forming front metal by photoetching and etching to be used as power supply metal layer 2, grounding metal layer and signal terminals IO1 and IO2 respectively.

Preferably, the metal may be pure aluminum or an aluminum-silicon compound; more preferably, the composite material is a three-layer composite structure, and the three-layer structure comprises titanium, titanium nitride and aluminum-silicon-copper in sequence from bottom to top, wherein the thickness of the titanium is 200-500A, the thickness of the titanium nitride is 400-1000A, and the thickness of the aluminum-silicon-copper is 2-4 μm. The TVS transistor of the low-capacitance low-clamp voltage transient voltage suppressor structure shown in fig. 1 is completed.

Example 2

This embodiment is similar to embodiment 1, as shown in fig. 9, other structures are the same as the embodiment, and the manufacturing method is the same, except that the junction depths of the P + region and the N + region are the same or close, the TVS device includes a P-type well PW, a P + region, an N + region, a dielectric, a ground metal layer Gnd, a power metal layer VCC, a signal terminal IO1 and an IO2 metal, and on the basis of the existing TVS device structure, an N-type epitaxial layer N-epi and a P-type buried layer P-BL are grown on an N-type silicon substrate N-sub silicon wafer, wherein:

the surface of the N-type epitaxial layer is sequentially as follows from left to right:

a first P-type well PW1 including P + region and N + region;

a P + region and an N + region on the surface of the N-type epitaxial layer on one side;

a second P-type well PW2 with an N + region;

a third P-type well PW3 sequentially including N + region, P + region and N + region;

a fourth P-type well PW4 including P + region and N + region;

a P + region and an N + region on the surface of the N-type epitaxial layer on the other side;

the bottoms of the second P-type trap PW2 and the third P-type trap PW3 are connected with a P-type buried layer P-BL; a P + region in the first P-type well PW1 and a third P-type well PW3 are connected with the ground metal layer Gnd; an N + region on the surface of the N-epi of the N-type epitaxial layer and an N + region of the second P-type well PW2 are connected with the power supply metal layer VCC; an N + region in the first P-type well PW1 and a P + region on the surface of the N-type epitaxial layer on one side are connected with a signal end IO 1; an N + region in the fourth P-type well PW4 and a P + region on the surface of the other side N-type epitaxial layer are connected with a signal terminal IO 2. A TVS transistor constituting a low capacitance low clamp voltage transient voltage suppressor structure as shown in fig. 9 below.

Example 3

Similar to the structure of embodiment 1, an N-type substrate N-sub is used, no N-type epitaxial layer is grown, and no P-type buried layer is also present, as shown in fig. 10, a TVS device including a P-type well PW, a P + region, an N + region, a dielectric, a ground metal layer Gnd, a power metal layer VCC, a signal terminal IO1, and an IO2 metal is provided, where on the basis of the existing TVS device structure, the following steps are sequentially performed on the surface of the N-type silicon substrate N-sub from left to right:

a first P-type well PW1 including P + region and N + region;

a P + region and an N + region on the surface of the N-sub of the silicon substrate with the N-type on one side;

a second P-type well PW2 with an N + region;

a third P-type well PW3 sequentially including N + region, P + region and N + region;

a fourth P-type well PW4 including P + region and N + region;

a P + region and an N + region on the surface of the N-sub of the N-type silicon substrate on the other side;

a P + region in the first P-type well PW1 and a third P-type well PW3 are connected with the ground metal layer Gnd; an N + region on the surface of the N-sub silicon substrate and an N + region of the second P-type well PW2 are connected with the power supply metal layer VCC; an N + region in the first P-type well PW1 and a P + region on the surface of the N-sub of the N-type silicon substrate on one side are connected with a signal end IO 1; an N + region in the fourth P-type well PW4 and a P + region on the surface of the N-sub of the N-type silicon substrate on the other side are connected to the signal terminal IO2, so as to form a TVS transistor with a low-capacitance low-clamping voltage transient voltage suppressor structure as shown in fig. 10.

Example 4

Using an N-type substrate N-sub, not growing an N-type epitaxial layer, and adjusting the shapes of a second P-type well PW2 and a third P-type well PW3, so that the third P-type well PW3 surrounds the second P-type well PW2, and a P + region and an N + region on the N-type substrate N-sub are in the N-type well, as shown in FIG. 11, the TVS device comprises the P-type well PW, the P + region, the N + region, a medium, a ground metal layer Gnd, a power metal layer VCC, a signal terminal IO1 and an IO2 metal, and on the basis of the structure of the existing TVS device, the shapes of the N-sub surface of the N-type silicon substrate are sequentially from left to right:

a first P-type well PW1 including P + region and N + region;

a first N-type well NW1 including a P + region and an N + region;

a second P-type well PW2 with an N + region;

a third P-type well PW3 sequentially including N + region, P + region and N + region, the third P-type well PW3 surrounding the second P-type well PW 2;

a fourth P-type well PW4 including P + region and N + region;

a second N-type well NW2 including P + and N + regions;

a P + region in the first P-type well PW1 and a third P-type well PW3 are connected with the ground metal layer Gnd; an N + region in the N-type well NW and an N + region of a second P-type well PW2 are connected with the power supply metal layer VCC; an N + region in the first P-type well PW1 and a P + region in the first N-type well NW1 are connected with a signal terminal IO 1; the N + region of the fourth P-type well PW4 and the P + region of the second N-type well NW1 are connected to the signal terminal IO2, and form a TVS transistor with a low-capacitance low-clamp voltage transient voltage suppressor structure as shown in fig. 11.

Example 5

Similar to embodiment 4, except that a Deep P-region Deep P-is connected to the third P-well PW 3.

As shown in fig. 12, using an N-type substrate, without epitaxy, PW2 and PW3 were shaped such that PW3 surrounded PW2 while increasing the Deep P-region (Deep P-).

The TVS device comprises a P-type well PW, an N-type well NW, a P + region, an N + region, a medium, a grounding metal layer Gnd, a power supply metal layer VCC, a signal end IO1 and an IO2 metal, wherein on the basis of the structure of the existing TVS device, a layer of Deep P-region Deep P-is grown on the surface of an N-sub silicon substrate N-sub, and the Deep P-region Deep P-is sequentially formed from left to right:

a first P-type well PW1 including P + region and N + region;

a first N-type well NW1 including a P + region and an N + region;

a second P-type well PW2 with an N + region;

a third P-type well PW3 sequentially comprising an N + region, a P + region and an N + region, wherein the third P-type well PW3 surrounds the second P-type well PW2, and the bottom of the third P-type well is connected with a Deep P-region Deep P-;

a fourth P-type well PW4 including P + region and N + region;

a second N-type well NW2 including P + and N + regions;

a P + region in the first P-type well PW1 and a third P-type well PW3 are connected with the ground metal layer Gnd; an N + region in the N-type well NW and an N + region of a second P-type well PW2 are connected with the power supply metal layer VCC; an N + region in the first P-type well PW1 and a P + region in the first N-type well NW1 are connected with a signal terminal IO 1; the N + region of the fourth P-type well PW4 and the P + region of the second N-type well NW1 are connected to the signal terminal IO2, thereby forming a TVS transistor with a low-capacitance low-clamp voltage transient voltage suppressor structure as shown in fig. 12.

Example 6

Similar to the embodiment, the P + buried layer P + BL is added, so that the P + BL is positioned above the P-BL.

As shown in fig. 13, a TVS device including a P-type well PW, a P + region, an N + region, a dielectric, a ground metal layer Gnd, a power metal layer VCC, a signal terminal IO1 and an IO2 metal, based on the structure of the conventional TVS device,

growing a P-buried layer P-BL on an N-sub silicon wafer of an N-type silicon substrate, then growing a P + buried layer P + BL at the same position, and then growing an N-type epitaxial layer N-epi, wherein: the surface of the N-type epitaxial layer is sequentially as follows from left to right:

a first P-type well PW1 including P + region and N + region;

a P + region and an N + region on the surface of the N-type epitaxial layer on one side;

a second P-type well PW2 with an N + region;

a third P-type well PW3 sequentially including N + region, P + region and N + region;

a fourth P-type well PW4 including P + region and N + region;

a P + region and an N + region on the surface of the N-type epitaxial layer on the other side;

the P + region is an ultra-shallow junction;

the bottoms of the second P-type trap PW2 and the third P-type trap PW3 are connected with a P + buried layer P + BL; a P + region in the first P-type well PW1 and a third P-type well PW3 are connected with the ground metal layer Gnd; an N + region on the surface of the N-epi of the N-type epitaxial layer and an N + region of the second P-type well PW2 are connected with the power supply metal layer VCC; an N + region in the first P-type well PW1 and a P + region on the surface of the N-type epitaxial layer on one side are connected with a signal end IO 1; an N + region in the fourth P-type well PW4 and a P + region on the surface of the N-type epitaxial layer on the other side are connected to the signal terminal IO2, so as to form a TVS transistor with a low-capacitance low-clamp voltage transient voltage suppressor structure as shown in fig. 13.

In this embodiment, the diode from the IO terminal to the VCC terminal is formed by P +/N-epi/N +, and since P + is an ultra-shallow junction, the junction area formed by P + and N-epi is also smaller, and the diode has a smaller capacitance, so that the capacitance of the entire device can be reduced.

Example 7

Similar to embodiment 1, except that the third P-type well PW3 and the second P-type well PW2 are arranged in a ring-shaped or interdigitated structure.

As shown in fig. 14, the TVS device includes a P-type well PW, a P + region, an N + region, a dielectric, a ground metal layer Gnd, a power metal layer VCC, a signal terminal IO1, and an IO2 metal, and on the basis of the structure of the conventional TVS device, an N-type epitaxial layer N-epi and a P-type buried layer P-BL are grown on an N-type silicon substrate N-sub silicon wafer, where:

the surface of the N-type epitaxial layer is sequentially as follows from left to right:

a first P-type well PW1 including P + region and N + region;

a P + region and an N + region on the surface of the N-type epitaxial layer on one side;

a third P-type well PW3 sequentially including N + region, P + region and N + region;

a second P-type well PW2 with an N + region;

a fifth P-type well PW5 having the same structure as the third P-type well PW 3;

a fourth P-type well PW4 including P + region and N + region;

a P + region and an N + region on the surface of the N-type epitaxial layer on the other side;

the bottom of the second to the fifth P-type traps PW2-5 is connected with a P-type buried layer P-BL; the P + region in the first P-type well PW1 and the third and fifth P-type wells PW3 and 5 are connected with the ground metal layer Gnd; an N + region on the surface of the N-epi of the N-type epitaxial layer and an N + region of the second P-type well PW2 are connected with the power supply metal layer VCC; an N + region in the first P-type well PW1 and a P + region on the surface of the N-type epitaxial layer on one side are connected with a signal end IO 1; an N + region in the fourth P-type well PW4 and a P + region on the surface of the N-type epitaxial layer on the other side are connected to the signal terminal IO2, so as to form a TVS transistor with a low-capacitance low-clamp voltage transient voltage suppressor structure as shown in fig. 14.

The diode from the IO end to the VCC end is formed by P +/N-epi/N + as in embodiment 1, and since P + is an ultra-shallow junction, the junction area formed by P + and N-epi is also smaller, the diode has a smaller capacitance, and the capacitance of the whole device can be reduced.

By arranging the third P-type well PW3 and the second P-type well PW2 to be in a surrounding or inserted finger type structure, the current path area is increased, and the surge peak current is increased, so that better electrostatic discharge and surge protection capability is obtained.

Example 8

Similar to example 7, a layer of lightly doped P-type well PW is added around the P + region on the surface of N-epi of the N-type epitaxial layer.

As shown in fig. 14, the TVS device includes a P-type well PW, a P + region, an N + region, a dielectric, a ground metal layer Gnd, a power metal layer VCC, a signal terminal IO1, and an IO2 metal, and on the basis of the structure of the conventional TVS device, an N-type epitaxial layer N-epi and a P-type buried layer P-BL are grown on an N-type silicon substrate N-sub silicon wafer, where: the surface of the N-type epitaxial layer is sequentially as follows from left to right:

a first P-type well PW1 including P + region and N + region;

a P + region and an N + region on the surface of the N-type epitaxial layer on one side, wherein the periphery of the P + region is lightly doped to form a sixth P-type well PW 6;

a third P-type well PW3 sequentially including N + region, P + region and N + region;

a second P-type well PW2 with an N + region;

a fifth P-type well PW5 having the same structure as the third P-type well PW 3;

a fourth P-type well PW4 including P + region and N + region;

a P + region and an N + region on the surface of the N-type epitaxial layer on the other side, wherein a seventh P-type well PW76 is formed by light doping around the P + region;

the bottom of the second to the fifth P-type traps PW2-5 is connected with a P-type buried layer P-BL; the P + region in the first P-type well PW1 and the third and fifth P-type wells PW3 and 5 are connected with the ground metal layer Gnd; an N + region on the surface of the N-epi of the N-type epitaxial layer and an N + region of the second P-type well PW2 are connected with the power supply metal layer VCC; an N + region in the first P-type well PW1 and a P + region in the sixth P-type well PW6 are connected with a signal terminal IO 1; an N + region in the fourth P-type well PW4 and a P + region in the seventh P-type well PW7 are connected to the signal terminal IO2, so as to form a TVS transistor with a low-capacitance low-clamp voltage transient voltage suppressor structure as shown in fig. 14.

In this embodiment, a lightly doped PW4 region is added to the diode from IO terminal to VCC terminal, i.e., the diode is formed by P +/PW4/N-epi/N +, PW4 and N-epi can form a wider space charge region, so that the capacitance is further reduced.

The utility model is characterized in that:

(1) the TVS tube with the structure of the utility model is a bipolar transistor consisting of N +/PW2/PW3/N +, and the base regions PW2 and PW3 are led out through P + and are in short circuit with the collector electrode N + of the grounding end. When electrostatic discharge or surge is generated, because PW2 is heavily doped, the breakdown voltage of N +/PW2 is lower, and after the N +/PW2 junction breaks down, current flows from PW2 to PW3 and then flows out to the ground from a P + end. Meanwhile, because PW3 is lightly doped and has a high resistance, the voltage difference generated from PW3 to P + is easily greater than 0.7V, and at this time, the bipolar transistor effect is generated, and the current can flow out not only from the P + terminal, but also from the N + terminal of the ground terminal, thereby showing a significant negative resistance characteristic, i.e., the current-voltage curve is remarkably snapbacked. In conclusion, the device of the utility model not only has the advantages of low breakdown voltage and trigger voltage and faster protection response; meanwhile, the circuit has the characteristic of smaller on-resistance and clamping voltage, and has stronger protection capability on a post-stage integrated circuit.

(2) In order to reduce the device capacitance, the conventional art only considers the capacitance of the diode with small capacitance, but the parasitic capacitance of the TVS tube is neglected by the method, the utility model discloses an increase P-buried layer P-BL below the TVS tube, such as below second, three P type trap PW2, PW 3), with the collocation of N-type substrate, can form the depletion region of broad, greatly reduced the parasitic capacitance of TVS tube bottom junction. The whole capacitance of the device is remarkably reduced and is smaller than that of the device with the traditional structure by more than 10%.

(3) Embodiment 1, embodiment 6, embodiment 7 of the present invention: the P + is an ultra-shallow junction, when the TVS tube is conducted, the path from the PW2 and the PW3 to the base region P + is lengthened, meanwhile, the width of the P + is set to be narrow, and under the combined action of the PW2 and the PW3, the resistance on the current path is larger, so that the bipolar transistor effect can be triggered by only small current reaching the base region P +, the negative resistance snapback occurs in advance, and the clamping voltage is further reduced.

(4) The utility model discloses in contain two kinds of diodes: the first diode from the IO terminal to the VCC terminal is formed by P +/N-epi/N +, and since N-epi is a high resistance epitaxy, the space charge region formed by P + and P + is wider, and the capacitance of the diode is reduced. The second diode from ground (Gnd) to IO is formed by P +/PW1/N +, PW1 is lightly doped, so the space charge region formed by N + is wider, and the capacitance of the diode is also reduced. The capacitance of the device as a whole is thus reduced.

The embodiment of the utility model provides a be two IO ports, obviously can increase more IO ports or remove the IO port on this basis, this type of change is still the utility model discloses a within the protection scope.

The above description is only for the purpose of illustrating the technical idea and the technical features of the present invention, and it should be understood that the present invention is not limited to the above embodiments, and many changes, repetitions, modifications, and even equivalents may be made thereto within the spirit and scope of the present invention as defined in the claims.

Claims (14)

1. The utility model provides a low electric capacity low clamp voltage transient voltage suppressor, on TVS tube structure basis, contains the TVS device of N-sub silicon chip of the silicon substrate of N-type, P type trap PW, P + district, N + district, medium, ground metal layer Gnd, connection power metal layer VCC, signal terminal IO1 and IO2 metal layer, its characterized in that: at least one first to four P-type wells PW1-4 are included on an N-type silicon substrate N-sub or a grown N-type epitaxial layer N-epi, wherein,

the first and fourth P-type wells PW1, 4 are lightly doped P-type wells with the same structure, and each well comprises a P + region and an N + region;

the second P-type well PW2 contains a random heavily doped N + region; and the number of the first and second groups,

the third P-type well PW3 well sequentially comprises an N + region, a P + region and light doping of the N + region, and the width of the P + region in the third P-type well PW3 is smaller than that of the N + region;

the TVS tube consists of a bipolar transistor consisting of N +/PW2/PW3/N +, a second P-type well PW2 and a third P-type well PW3 in a base region are shorted together with a collector N + of a grounding end through a P + lead-out; when electrostatic discharge or surge is generated, because the second P-type well PW2 is heavily doped, the breakdown voltage of N +/PW2 is lower, and after the N +/PW2 junction breaks down, current flows from the second P-type well PW2 to the third P-type well PW3 and then flows out from the P + end to the ground end; meanwhile, because the third P-type well PW3 is lightly doped and has high resistance, the voltage difference generated by the current from the third P-type well PW3 to P + is easily larger than 0.7V, at this time, the bipolar transistor effect is generated, the current can flow out from the P + end and also from the N + end of the ground end, and a significant negative resistance characteristic is presented, that is, the current-voltage curve is obviously snapbacked;

a P-type buried layer P-BL is added below the second P-type well PW2 and the third P-type well PW3 and matched with an N-type substrate, so that a wider depletion region can be formed, and the parasitic capacitance of the bottom junction of the TVS tube is greatly reduced;

the P + region is an ultra-shallow junction or the junction depth of the P + region is the same as that of the N + region, when the TVS tube is conducted, the path from the current to the base region P + from the second P-type well PW2 and the third P-type well PW3 is lengthened, and meanwhile, the width of the base region P + is set to be narrower and is smaller than the N + on the two sides of the base region P +;

two types of diodes were formed: the first diode from the IO end to the VCC end is formed by P +/N-epi/N +, N-epi is a high resistance epitaxy, and the P + and the N-epi form a wider space charge region to reduce the capacitance of the diode; the second diode from ground Gnd to signal IO is formed by two diodes formed by P +/PW1/N + and/or P +/PW4/N +, the first P-type well PW1 and the fourth P-type well PW4 are lightly doped, so that a wider space charge region is formed between N + and the first P-type well PW1 and the fourth P-type well PW4 to reduce the capacitance of the diode.

2. The low capacitance low clamp voltage transient voltage suppressor of claim 1, wherein: the first and fourth P-type wells PW1, 4 are implanted with boron at a dose of 5E 11-1E 13CM^-2The implantation energy is 60-100 KeV; the second P-type well PW2 is implanted with boron at an implant dose of 1E 14-9E 14CM^-2The implantation energy is 60-100 KeV; the third P-type well PW3 is implanted with boron at an implant dose of 1E 12-1E 14CM^-2The implantation energy is 60 to 100 KeV.

3. The low capacitance low clamp voltage transient voltage suppressor of claim 1, wherein: the N-type epitaxial growth is doped with phosphorus or arsenic impurities, the resistivity of the N-type epitaxial growth is 50-300 omega CM, and the epitaxial thickness is 3-8 mu m; p + is an ultra-shallow junction, the implantation element is boron, and the implantation dosage is 1E 15-8E 15CM^-2The implantation energy is 40-80 KeV; the N + region is heavily doped, the implantation element is phosphorus or arsenic, and the implantation dosage is 2E 15-1.2E 16 CM^-2The implantation energy is 80-150 KeV; and in the diode formed by P +/N-epi/N + from the IO terminal to the VCC terminal, a smaller junction area is formed by P + and N-epi.

4. The low capacitance low clamp voltage transient voltage suppressor of claim 1 or 2, wherein: the third P-type well PW3 and the second P-type well PW2 are arranged in a ring shape or a finger-inserting shape.

5. A low capacitance low clamp voltage transient voltage suppressor according to any one of claims 1 to 3, wherein: an N-type epitaxial layer and a P-type buried layer (P-BL) grow on an N-type silicon substrate, a first P-type well PW1 comprising a P + region and an N + region, a P + region and an N + region on the surface of the N-type epitaxial layer on one side, a second P-type well PW2 comprising the N + region, a third P-type well PW3 comprising the N + region, the P + region and the N + region, a fourth P-type well PW4 comprising the P + region and the N + region, a P + region and an N + region on the surface of the N-type epitaxial layer on the other side, and the bottoms of the second P-type well PW2 and the third P-type well PW3 are connected with the P-type buried layer P-BL; the P + region in the first P-type well PW1 and the third P-type well PW3 are connected with a metal ground terminal; the N + region on the surface of the N-type epitaxial layer and the N + region of the second P-type well PW2 are connected with the power supply metal layer VCC; an N + region in the first P-type well PW1 and a P + region on the surface of the N-type epitaxial layer on one side are connected with a signal end IO 1; an N + region in the fourth P-type well PW4 and a P + region on the surface of the other side N-type epitaxial layer are connected with a signal terminal IO 2.

6. The low capacitance low clamp voltage transient voltage suppressor of claim 5, wherein: the N-substrate resistivity is 200-300 omega CM.

7. The transient voltage suppressor of claim 5, wherein said P-type buried layer (P-BL) has a thickness of 200-500 Å, and boron or boron difluoride is ion implanted at an energy of 60-100 KeV and a dose of 5E 11-5E 12CM^-2。

8. The low capacitance low clamp voltage transient voltage suppressor of claim 5, wherein: the junction depth of the P + region is shallower than that of the N + region.

9. The low capacitance low clamp voltage transient voltage suppressor of claim 6, wherein: and (3) not growing an N-type epitaxial layer on the N-type substrate, directly arranging a P + region and an N + region which are originally arranged on the N-type epitaxial layer on the surface of the N-type substrate, and forming the P + region and the N + region in the surface of the N-type substrate.

10. The low capacitance low clamp voltage transient voltage suppressor of claim 9, wherein: the P + region and the N + region in the N-type substrate are arranged in an N-type well NW, and the shapes of the second P-type well PW2 and the third P-type well PW3 are adjusted, so that the second P-type well PW2 is surrounded by the third P-type well PW 3.

11. The low capacitance low clamp voltage transient voltage suppressor of claim 10, wherein: deep P-region Deep P-is added at the bottom of the second and third P-type wells PW2, 3.

12. The low capacitance low clamp voltage transient voltage suppressor of claim 5, wherein: and a P + buried layer P + BL is additionally arranged between the upper surface of the P-type buried layer P-BL and the bottoms of the second P-type well PW2 and the third P-type well PW 3.

13. The low capacitance low clamp voltage transient voltage suppressor of claim 4, wherein: growing an N-type epitaxial layer and a P-type buried layer P-BL on an N-type silicon substrate, wherein a first P-type well PW1 comprising a P + region and an N + region, a P + region and an N + region on the surface of the N-type epitaxial layer on one side, a third P-type well PW3 comprising the N + region, the P + region and the N + region, a second PWell2 comprising the N + region, a fifth P-type well PW5 comprising the N + region, the P + region and the N + region, a fourth P-type well PW4 comprising the P + region and the N + region, a P + region and an N + region on the surface of the N-type epitaxial layer on the other side, a third P-type well3, a second P-type well PW2 and the bottom of the fifth P-type well PW5 are connected with the P-type buried layer P-BL; a P + region in the first P-type well PW1, a third P-type well PW3 and a fifth P-type well PW5 are connected with a metal ground terminal; an N + region on the surface of the N-type epitaxial layer and an N + region of the second PWell2 are connected with the power supply metal layer VCC; an N + region in the first PWell1 and a P + region on the surface of the N-type epitaxial layer on one side are connected with a signal end IO 1; the N + region in the fourth PWell4 and the P + region on the surface of the N-type epitaxial layer on the other side are connected with a signal terminal IO 2.

14. The low capacitance low clamp voltage transient voltage suppressor of claim 13, wherein: and a layer of lightly doped PWell area is added around the P + area on the surface of the N-type epitaxial layer, a diode from an IO end to VCC is formed by a P +/lightly doped P-type well PW/N-epi/N +, and the lightly doped P-type well PW and the N-epi of the N-type epitaxial layer form a wider space charge area so as to further reduce the capacitance.

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