KR101006768B1 - Structure of a tvs diode array and its fabrication method - Google Patents

Abstract

PURPOSE: A TVS diode array and a fabrication method thereof are provided to prevent the latch up phenomenon by forming a bonding boundary where a PN diode and a zener diode are formed in the planar structure. CONSTITUTION: A n+ buried layer(102) is locally formed on a p-type substrate(101). An n- epi layer(103) and a p++ epi layer(104) are successively formed on the p-type substrate. The n+ buried layer is bonded with the p-type substrate to perform the zener diode function. The p++ epi layer and the n- epi layer of the mesa structure form the PN diode.

Description

TVS diode array and its manufacturing method {Structure of a TVS diode array and its fabrication method}

The present invention relates to a method of manufacturing a TVS (Transient Voltage Suppressor) diode array, and more particularly, to a technology of forming a junction interface in which a PN diode and a Zener diode are formed in order to prevent a latch up phenomenon. will be.

    Transient Voltage Suppressors (TVSs) are diode arrays for protecting electronic circuits from transient voltages such as electrostatic discharge (ESD).

    FIG. 1A illustrates an input / output terminal 1 (IO Port 1) and an input / output terminal 2 (IO Port 2) in which a single Zener diode, a high side PN diode, and a low side PN diode are connected in series. Shows a TVS diode array schematic.

Here, PN diodes tend to have low capacitance values of about 1 pF as the data throughput increases, and they must satisfy the ESD (International Electromechanical Commission). In general, ESD protection devices should have a high ESD immunity value of Level 4 in the IEC61000-4-2 standard.

Here, the zener diode serves to protect the electronic circuit by clamping the transient voltage or the transient current. In order to protect the electronic circuit more safely, it is necessary to have a low clamping characteristic. For this purpose, the zener diode should have a low dynamic resistance (Rd) value of several Ohm.

FIG. 1B is a conventional technique for fabricating the TVS diode array of FIG. 1A described above. In this structure, parasitic NPN channels are formed in the main diode and parasitic PNP channels are formed in the upper diode. This can cause latch up, which damages or destabilizes the electronic circuitry, causing unwanted effects. In order to solve the latch-up problem in such a structure, a method of increasing the length of the main diode to about 100 μm may be used, but there is a problem that productivity is reduced due to an increase in chip area.

In order to solve this latch-up problem, US Patent Publication No. 2007 / 0073807A1 discloses a structure as shown in FIG. 1C. In this structure, a trench isolation is performed between the main diode and the surrounding PN diode to prevent latchup. To isolate trenches for device isolation, productivity is achieved through complex process steps, including deep trench etching of silicon, oxide film formation on silicon sidewalls, polycrystalline silicon deposition, and planarization with chemical mechanical polishing (CMP). There is a limit to increase.

Also, in this structure, since the PN junction interface is formed by ion implantation after forming a contact hole, the PN junction interface is not flat at the contact hole side and is formed into a curved surface to generate a curved effect in which an electric field is concentrated. There is a problem that the TVS is vulnerable to ESD due to the curved effect of the electric field is concentrated.

Therefore, in order to have a low capacitance value and high ESD characteristic required for high-speed data processing, the N-epit thickness of the PN diode to form IO Port 1 and IO Port 2 must be increased. However, in the NP diode formed by the side junction of the N + and P substrates, since the junction is made at the lower portion of the N + and the P body on the side, there is a problem that ESD characteristics are not improved even if the thickness of the P substrate is increased.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a TVS diode structure and a method of manufacturing the same, which suppress the latch-up phenomenon and the curved surface effect.

In addition, the device isolation of the mesa structure is used to simplify the manufacturing process, provide a highly reliable TVS diode array with high clamping resistance with low clamping voltage, and provide a TVS diode structure and a method of manufacturing the same to improve productivity. do.

In order to achieve the above object, the configuration of the TVS diode array manufacturing method according to the present invention, the first step of forming a buried layer consisting of the second conductive layer in a portion of the semiconductor substrate consisting of the first conductive layer, A second step of forming an epitaxial layer consisting of a first conductive layer and a third conductive layer on top of the buried layer and epitaxially growing a fourth conductive layer on the third conductive layer, a plurality of mesas in the fourth conductive layer on the buried layer A third step of etching the fourth conductive layer using a dry etching process by masking with a photosensitive film to form a structure, masking the buried layer region with a photosensitive film and opposite the fourth conductive layer on the exposed third conductor surface outside the buried layer region A fourth step of forming a fifth conductive layer by removing a photoresist film after performing ion implantation with a dopant and performing a heat treatment, the buried layer and the first conductive layer group A first active region consisting of a plurality of zener diodes made of a junction, a plurality of PN diodes formed of a junction of a fourth conductive layer and a third conductive layer of a mesa structure, and upper and lower NP diodes spaced at a predetermined distance from the first active region. Masking the first active region and the second active region with a photoresist film and etching the lower portion of the buried layer by dry etching to form a second active region comprising a functioning third conductive layer and a first conductive layer substrate junction. A sixth step of forming the contact holes, forming the upper metal electrodes to form the input / output terminals 1 and 2, and forming the lower metal electrode on the back surface of the substrate after applying the insulating film to the substrate on which the fifth and fifth steps of isolation are completed. Characterized in that it comprises a step.

In addition, the first conductive layer is characterized in that the silicon semiconductor doped with N-type or P-type impurities 10 ¹⁷ / cm ³ ~ 10 ²¹ / cm ³ .

The second conductive layer may be a silicon thin film doped with P-type or N-type impurities at 10 ¹⁶ / cm ³ to 10 ²⁰ / cm ³ .

The third conductive layer may be a silicon thin film doped with P-type or N-type impurities at 10 ¹⁴ / cm ³ to 10 ¹⁸ / cm ³ .

In addition, the fourth conductive layer and the fifth conductive layer is a silicon thin film doped with opposite conductivity types and doped with P-type or N-type impurities at 10 ¹⁷ / cm ³ to 10 ²¹ / cm ³ .

On the other hand, the configuration of the TVS diode array fabricated by the above-described TVS diode manufacturing method, the buried layer consisting of a second conductive layer in a portion of the semiconductor substrate composed of the first conductive layer, the third conductive layer on top of the first conductive layer and the buried layer. An epi layer of a fourth conductive layer continuously formed on the epi layer composed of a layer and the third conductive layer, a plurality of mesa structures formed on the fourth conductive layer on the buried layer, and a singular layer formed by bonding the buried layer and the first conductive layer substrate A first active region formed of a plurality of PN diodes formed by joining four zener diodes, a fourth conductive layer having a mesa structure, and a third conductive layer, and a first and second NP diodes spaced at a predetermined distance from each other. 3 Mesa structure formed by etching to the lower part of the buried layer, leaving the second active region consisting of the conductive layer and the first conductive layer substrate junction. And it characterized in that.

The present invention solves the latchup problem occurring in the conventional TVS diode array with a mesa structure, thereby eliminating a trench process, an oxide film forming process, and a planarization process, thereby simplifying the manufacturing process and improving productivity.

In addition, by solving the degradation of ESD resistance due to the curved surface effect, there is an advantage that the junction interface of the PN diode having a small capacitance value is flat to have an excellent ESD resistance compared to the existing process, thereby reducing the epitaxial thickness relatively compared to the existing process. This allows the production of mass-produced TVS diode arrays.

In addition, since device isolation is performed in a mesa shape, cross talk between input and output terminals is suppressed.

1A to 1C are cross-sectional views showing the structure of a TVS diode array fabricated by the prior art.
2A to 2E are cross-sectional views sequentially illustrating a method of manufacturing a TVS diode array according to the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. In the drawings of the present invention, the size or dimensions of the structures are shown to be enlarged or reduced than actual for clarity of the present invention is not limited to the drawings. In adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used to refer to the same components as much as possible even if displayed on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a TVS diode array according to an exemplary embodiment of the present invention.

  2A illustrates a substrate fabrication process in which an N + buried layer 102 is locally formed on a P-type substrate 101, and then an N− epilayer 103 and a P ++ epilayer 104 are sequentially formed.

The N + buried layer 102 is bonded to the P-type substrate 101 to function as a zener diode. The impurity concentration of the N + buried layer is determined by the required zener voltage and has a concentration value of approximately 10 ¹⁶ to 10 ²⁰ / cm ³ .

The P ++ epitaxial layer 104 has a thickness of approximately 10 to 500 nm and a concentration of approximately 10 ¹⁷ to 10 ²¹ / cm ³ and is in contact with the lower N- epi layer 103 to serve as a PN diode. Wherein the concentration of the N- epi layer 103 is different depending on the breakdown voltage value of the required PN diode, has a concentration of approximately 10 ¹⁴ ~ 10 ¹⁸ / cm ³ and the thickness range is approximately 0.5 ~ 20nm.

A mesa-shaped P ++ epitaxial layer 104 is formed on the N + buried layer 102 as shown in FIG. 2B by using a masking and etching process using a photosensitive film on the substrate where the process is completed. The etching process may be either wet or dry, but dry etching is preferable.

The P ++ epitaxial layer 104 of mesa structure formed in the above process and the lower N- epitaxial layer 103 form a PN diode. In order to adjust the capacitance required by the PN diode, the area of the P ++ epilayer 104 and the thickness and concentration of the N− epilayer 104 should be adjusted. In the present invention, since the PN junction interface is flat, the electric field distribution is uniformly distributed at the PN junction interface, and the PN junction ends have relatively superior ESD resistance characteristics as compared to the PN junction interface by the conventional process, which is curved by a doping profile. It has the advantage of being. Therefore, since ESD resistance per unit area is stronger than that of the existing process, the method has the advantage of reducing the area of the mesa-shaped P ++ epitaxial layer 104 to have the same capacitance value as the existing process.

Referring to FIG. 2C, the N + buried layer 102 region is masked with the photosensitive film 105 and N + ion implanted into the exposed N− epilayer 103 outside the buried layer region. N + ion implantation uses arsenic or phosphorus ions and has a concentration of approximately 10 ¹⁷ to 10 ²¹ / cm ³ .

Subsequently, the photoresist layer 105 is removed and rapid thermal treatment (RTA) forms an N ++ semiconductor layer 106.

Thereafter, a photo process using a photoresist film and a dry etching process are performed to form a first active region and a second active region as shown in FIG. 2D.

Form a first active region having a plurality of mesa structures and a second active region having upper and lower NP diode functions spaced apart from the first active region by functioning as a buried layer and functioning as a Zener diode. In addition, the first active region and the second active region are masked by the photoresist layer using a photoresist film, and the first active region and the second active region are formed as shown in FIG.

The first active region includes a plurality of PN diodes formed of a P ++ epitaxial layer 104 and an N− epilayer 103 junction, and a plurality of zener diodes composed of an N + buried layer 102 and a P-type substrate 101 junction. have. This structure has a feature that the junction interface where the PN diode and the zener diode are formed is flat.

In addition, since the thickness of the N- epi layer 103 grown after the zener diode junction interface is formed can be reduced as compared with the existing process, the epitaxial growth time can be shortened to reduce the heat treatment time applied to the zener junction interface. As a result, the doping profile is abruptly abruptly reduced at the zener junction interface, thereby reducing the dynamic resistance Rd, thereby lowering the clamping voltage of the zener diode compared to the prior art.

The second active region is composed of an NP diode composed of a junction of an N- epi layer 103 and a P-type substrate 101. Here, the bonding interface at which NP bonding is made also has the same flat characteristics as the first bonding interface.

After the insulating film 107 is coated on the substrate, the contact hole is formed and the upper metal electrode 108 is formed to form IO Port 1 and IO Port 2 as shown in FIG. 2E. 109 is formed to complete the TVS diode array fabrication process.

101: P-type substrate 102: N + buried layer
103: N- epi layer 104: P ++ epi layer
105: photosensitive film 106: N + + semiconductor layer
107: insulating film 108: upper metal electrode
109: lower metal electrode

Claims (6)

In the method of manufacturing a TVS (Transient Voltage Suppressor) diode array,
A first step of forming a buried layer composed of a second conductive layer in a portion of the semiconductor substrate composed of the first conductive layer;
A second step of forming an epitaxial layer comprising a third conductive layer on the first conductive layer and the buried layer and epitaxially growing a fourth conductive layer on the third conductive layer;
A third step of etching the fourth conductive layer using a dry etching process by masking with a photosensitive film so that a plurality of mesa structures are formed on the fourth conductive layer on the buried layer;
A fourth step of masking the buried layer region with a photoresist film, ion implanting the exposed third conductor surface outside the buried layer region with a dopant opposite to the fourth conductive layer, removing the photoresist film, and performing a heat treatment to form a fifth conductive layer;
A first active region consisting of a plurality of zener diodes comprising the buried layer and the first conductive layer substrate junction and a plurality of PN diodes formed by the junction of the fourth conductive layer and the third conductive layer having a mesa structure and the first active region and the first active region Masking the first active region and the second active region with a photosensitive film and forming a buried layer by dry etching so as to form a second active region comprising a third conductive layer and a first conductive layer substrate junction which are spaced apart and serve as upper and lower NP diode functions. A fifth step of etching the lower portion to isolate the device with a mesa structure; And
And a sixth step of forming the contact holes, forming the upper metal electrodes to form the input / output terminals 1 and 2, and forming the lower metal electrodes on the back of the substrate after applying the insulating film to the substrate on which the fifth step is completed. TVS Diode Array Manufacturing Method The method of claim 1, wherein the first conductive layer is a silicon semiconductor doped with N-type or P-type impurities at 10 ¹⁷ / cm ³ to 10 ²¹ / cm ³ .
The method of claim 1, wherein the second conductive layer is a silicon thin film doped with P-type or N-type impurities at 10 ¹⁶ / cm ³ to 10 ²⁰ / cm ³ .
The method of claim 1, wherein the third conductive layer is a silicon thin film doped with P-type or N-type impurities at 10 ¹⁴ / cm ³ to 10 ¹⁸ / cm ³ .
The method of claim 1, wherein the fourth conductive layer and the fifth conductive layer is a silicon thin film doped with opposite conductivity types and doped with P-type or N-type impurities at 10 ¹⁷ / cm ³ to 10 ²¹ / cm ³ TVS diode array manufacturing method.
In the TVS diode array manufactured by the manufacturing method of any one of claims 1 to 5,
A buried layer composed of a second conductive layer in a portion of the semiconductor substrate composed of the first conductive layer;
An epi layer of an epi layer composed of a third conductive layer on the first conductive layer and the buried layer and a fourth conductive layer continuously formed on the third conductive layer;
A plurality of mesa structures formed in a fourth conductive layer above the buried layer;
A fifth conductive layer formed of a dopant opposite to the fourth conductive layer on the exposed third conductor surface outside the buried layer region; And
A first active region comprising a plurality of zener diodes comprising the buried layer and the first conductive layer substrate junction, and a plurality of PN diodes formed by the junction of the fourth conductive layer and the third conductive layer having a mesa structure, and the first active region and the first active region. A mesa structure formed by etching to a lower portion of the buried layer, leaving a second active region consisting of a third conductive layer and a first conductive layer substrate junction spaced apart from each other to function as upper and lower NP diodes.

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