CN210167361U - Trench MOSFET integrated ESD protection - Google Patents
Trench MOSFET integrated ESD protection Download PDFInfo
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- CN210167361U CN210167361U CN201921656756.6U CN201921656756U CN210167361U CN 210167361 U CN210167361 U CN 210167361U CN 201921656756 U CN201921656756 U CN 201921656756U CN 210167361 U CN210167361 U CN 210167361U
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Abstract
The utility model discloses a more superior integrated ESD protected slot MOSFET, its integrated ESD protected slot MOSFET, between MOSFET's grid and source electrode, include the zener diode that positive, reverse PN junction series connection constitutes, zener diode's one end is connected MOSFET's grid, and the other end is connected MOSFET's source electrode; and a voltage stabilizing diode formed by connecting forward and reverse PN junctions in series is arranged between the grid electrode and the drain electrode of the MOSFET, one end of the voltage stabilizing diode is connected with the grid electrode of the MOSFET, and the other end of the voltage stabilizing diode is connected with the drain electrode of the MOSFET.
Description
Technical Field
The utility model relates to a semiconductor device makes technical field, especially relates to a slot MOSFET of integrated ESD protection.
Background
The MOSFET chips are classified according to structures and comprise two major categories of planar MOSFETs and trench MOSFETs, wherein the trench MOSFETs are dominant in medium-low voltage MOSFETs due to higher current density; MOSFET chips are classified by conduction, including N-type MOSFETs, which are more widely used because of their higher current density, and P-type MOSFETs. MOSFET chips all contain 3 ports for source, gate and drain, typically with the source and gate on the front side of the chip and the drain on the back side of the chip.
A thin gate oxide layer is arranged between a grid electrode and a source electrode and a drain electrode of the MOSFET chip, and the thin gate oxide layer can be broken down and damaged and can not recover when being impacted by external unexpected high voltage. It is therefore necessary in some practical applications to provide electrostatic discharge (ESD) protection to the gate of a MOSFET chip. Generally, a group of voltage stabilizing diodes are connected in parallel between a grid electrode and a source electrode of an MOSFET chip, the reverse breakdown voltage of the voltage stabilizing diodes is lower than the bearable voltage of a grid oxide layer, when the voltage generated by electrostatic discharge (ESD) is higher than the reverse breakdown voltage of the voltage stabilizing diodes, the voltage stabilizing diodes are broken down, the voltage is clamped by the voltage stabilizing diodes, and electrostatic energy is discharged from the voltage stabilizing diodes, so that the grid oxide layer is prevented from being damaged, and the protection effect on the grid oxide layer is realized. In practical applications, in order to reduce the size and material cost of the circuit board, a zener diode providing ESD protection function is generally integrated into a MOSFET chip, which is called an integrated ESD protection MOSFET chip.
U.S. patent No. US8004009B2, Trench MOSFETS with Zener Diode, discloses a Trench MOSFET with ESD protection integrated inside a chip and a method for manufacturing the same, including a Cell region (Cell), a Gate (Gate) extraction region, and a Zener Diode integrated therebetween, the Zener Diode being disposed on the upper surface of a thick oxide layer, and formed by connecting a plurality of PN junctions disposed in polysilicon in series (i.e., polysilicon Diode), a Source Metal (Source Metal) connecting the Cell and one end of the Zener Diode together, and a Gate Metal (Gate Metal) connecting the Gate and the other end of the Zener Diode together. Other solutions in the prior art are similar or similar to the solutions disclosed above, and all adopt a zener diode that provides an ESD protection function by disposing a polysilicon diode on the upper surface of a thick oxide layer.
Specifically, with respect to a trench MOSFET integrated with ESD protection in the prior art, a corresponding equivalent circuit diagram is shown in fig. 1, a diode between a drain and a source is an intrinsic parasitic diode necessary for a MOSFET chip, an integrated zener diode providing an ESD protection function is provided between a gate and the source, the zener diode is formed by connecting forward and reverse PN junctions in series, when the gate receives external forward ESD static electricity, the reverse PN junction is broken down, the forward PN junction is conducted, and energy is discharged through the zener diode formed by connecting the forward and reverse PN junctions in series; when the grid electrode receives external reverse ESD static electricity, the forward PN junction is broken down, the reverse PN junction is conducted, and energy is still discharged through the voltage stabilizing diode formed by connecting the forward PN junction and the reverse PN junction in series, namely, the voltage stabilizing diode formed by connecting the forward PN junction and the reverse PN junction in series can play a role in discharging energy and clamping voltage all the time, so that the grid oxide layer of the MOSFET is protected from being damaged by the static electricity.
With respect to the prior art, the following disadvantages exist:
1. in order to manufacture the thick oxide layer and the polysilicon diode, the process flow is more complex and the process cost is higher.
2. Due to the existence of the thick oxide layer and the polysilicon diode, the step difference on the surface of the chip is large, the process difficulty is increased, and the process stability is poor.
3. The voltage stabilizing diode adopts a polysilicon diode, and polysilicon is composed of silicon crystal grains with certain sizes, so that the stability and consistency of the voltage stabilizing diode are poorer than those of monocrystalline silicon, and the stability of ESD protection capability of the voltage stabilizing diode made of the polysilicon is poorer.
4. The zener diode is located between the gate and the source, rather than between the gate and the drain, so that ESD energy between the gate and the drain can only be discharged through a series circuit formed by the zener diode and the internal parasitic diode of the MOSFET, that is, an ESD energy discharge channel between the gate and the drain is one more internal parasitic diode than an ESD energy discharge channel between the gate and the source, thereby increasing a clamping voltage and impedance of the energy discharge channel, and generally resulting in a poorer ESD protection capability between the gate and the drain than between the gate and the source.
SUMMERY OF THE UTILITY MODEL
In view of prior art's limitation, the utility model discloses an overcome prior art not enough, adapt to reality needs, disclose a slot MOSFET of more superior integrated ESD protection, the utility model discloses the ESD protective capability of scheme is better, more stable, and technology is simpler, and process stability is better, and manufacturing cost is lower.
In order to realize the utility model discloses a purpose, the utility model discloses the technical scheme who adopts does:
the trench MOSFET integrating ESD protection comprises a voltage stabilizing diode formed by connecting a positive PN junction and a negative PN junction in series between a grid electrode and a source electrode of the MOSFET, wherein one end of the voltage stabilizing diode is connected with the grid electrode of the MOSFET, and the other end of the voltage stabilizing diode is connected with the source electrode of the MOSFET; and a voltage stabilizing diode formed by connecting forward and reverse PN junctions in series is arranged between the grid electrode and the drain electrode of the MOSFET, one end of the voltage stabilizing diode is connected with the grid electrode of the MOSFET, and the other end of the voltage stabilizing diode is connected with the drain electrode of the MOSFET.
Preferably, among the technical scheme, zener diode is the bulk silicon diode.
Preferably, in the technical solution of the present invention, the zener diode is located below the MOSFET gate and in the surrounding area of the gate; at least two grooves are arranged between the voltage stabilizing diode and the MOSFET cellular area, and at least two grooves at least comprise a first groove used for forming a MOSFET terminal area field limiting ring and a second groove used for isolating the voltage stabilizing diode and the MOSFET terminal area.
Preferably, in the technical solution of the present invention, the MOSFET is an N-type trench MOSFET or a P-type trench MOSFET.
Preferably, in the technical solution of the present invention, when the MOSFET is an N-type trench MOSFET, the zener diode between the gate and the drain is of an N/P/N-structure; when the MOSFET is a P-type groove MOSFET, the voltage stabilizing diode between the grid electrode and the drain electrode is in a P/N/P-structure.
Preferably, in the technical solution of the present invention, when the MOSFET chip is an N-type trench MOSFET, the N-type doped region of the zener diode N/P/N-between the gate and the drain is the same as the N-type source region of the MOSFET; when the MOSFET chip is a P-type groove MOSFET, the P-type doped region of the voltage stabilizing diode P/N/P-between the grid electrode and the drain electrode and the P-type source region of the MOSFET have the same doping concentration.
Preferably, in the technical solution of the present invention, when the MOSFET chip is an N-type trench MOSFET, the P-type doped region of the zener diode N/P/N-between the gate and the drain is the same as the P-type body region of the MOSFET; when the MOSFET chip is a P-type groove MOSFET, the N-type doped region of the voltage stabilizing diode P/N/P-between the grid electrode and the drain electrode and the N-type body region of the MOSFET have the same doping concentration.
Preferably, in the technical solution of the present invention, when the MOSFET chip is an N-type trench MOSFET, the N-type doped region of the zener diode N/P/N-between the gate and the drain is an N-type epitaxial layer of the MOSFET; when the MOSFET chip is a P-type groove MOSFET, the P-type doped region of the voltage stabilizing diode P/N/P-between the grid electrode and the drain electrode is the P-type epitaxial layer of the MOSFET.
Preferably, in the technical solution of the present invention, when the MOSFET chip is an N-type trench MOSFET, the zener diode between the gate and the source is of an N/P/N structure;
preferably, among the technical scheme of the utility model, when the MOSFET chip is P type slot MOSFET, zener diode between grid and the source electrode is P/N P structure.
Preferably, in the technical solution of the present invention, when the MOSFET chip is an N-type trench MOSFET, the N-type doped region of the zener diode N/P/N between the gate and the source is the same as the N-type source region of the MOSFET; when the MOSFET chip is a P-type groove MOSFET, the P-type doped region of the voltage stabilizing diode P/N/P between the grid electrode and the source electrode and the P-type source region of the MOSFET have the same doping concentration.
Preferably, in the technical solution of the present invention, when the MOSFET chip is an N-type trench MOSFET, the P-type doped region of the zener diode N/P/N between the gate and the source is the same as the P-type body region of the MOSFET; when the MOSFET chip is a P-type groove MOSFET, the N-type doped region of the voltage stabilizing diode P/N/P between the grid electrode and the source electrode and the N-type body region of the MOSFET have the same doping concentration.
The beneficial effects of the utility model reside in that:
1. the utility model discloses a slot MOSFET of integrated ESD protection, its inside integrated zener diode are the bulk silicon diode, and not polycrystalline silicon diode, and consequently zener diode's ESD release characteristic is more stable, and ESD protective capability is more stable.
2. The structure of the utility model does not adopt thick oxide layer and polysilicon diode, the structure on the surface of the chip is relatively smooth, there is no high step drop, the process difficulty is lower, the process stability is better, the manufacturing cost is lower.
3. The utility model discloses between grid and source to and between grid and drain electrode, all integrated zener diode, ESD energy between grid and the drain electrode is released and need not pass through MOSFET's internal parasitic diode, ESD energy of releasing that can be faster, therefore the ESD protective capability is better.
4. The utility model discloses an internally integrated zener diode's P type doping area and MOSFET's P type somatic region can form in step in the technology, and zener diode's N type doping area and MOSFET's N type source region can form in step in the technology to realize lower manufacturing cost.
Drawings
FIG. 1 is a schematic diagram of a prior art trench MOSFET equivalent circuit integrated with ESD protection;
FIG. 2 is a schematic diagram of the internal cross-sectional structure of a trench MOSFET integrated with ESD protection according to the present invention;
FIG. 3 is a schematic diagram of a trench MOSFET equivalent circuit integrated with ESD protection according to the present invention;
fig. 4 is a schematic structural diagram corresponding to step S1 in the method for manufacturing a trench MOSFET integrated with ESD protection according to the present invention;
fig. 5 is a schematic structural diagram corresponding to step S2 in the method for manufacturing a trench MOSFET integrated with ESD protection according to the present invention;
fig. 6 is a schematic structural diagram corresponding to step S3 in the method for manufacturing a trench MOSFET integrated with ESD protection according to the present invention;
fig. 7 is a schematic structural diagram corresponding to step S4 in the method for manufacturing a trench MOSFET integrated with ESD protection according to the present invention;
fig. 8 is a schematic structural diagram corresponding to step S5 in the method for manufacturing a trench MOSFET integrated with ESD protection according to the present invention;
fig. 9 is a schematic structural diagram corresponding to step S6 in the method for manufacturing a trench MOSFET integrated with ESD protection according to the present invention;
fig. 10 is a schematic structural diagram corresponding to step S7 in the method for manufacturing a trench MOSFET with integrated ESD protection according to the present invention;
fig. 11 is a schematic structural diagram corresponding to step S8 in the method for manufacturing a trench MOSFET integrated with ESD protection according to the present invention;
fig. 12 is a schematic structural diagram corresponding to step S9 in the method for manufacturing a trench MOSFET integrated with ESD protection according to the present invention.
In the figure:
1 is an N-type substrate (for an N-type trench MOSFET);
1 is a P-type substrate (for a P-type trench MOSFET);
2 is an N-type epitaxial layer (for an N-type trench MOSFET);
2 is a P-type epitaxial layer (for a P-type trench MOSFET);
3 is a hard mask;
4.1 is a first groove, 4.2 is a second groove, and 4.3 is a third groove;
5 is a gate oxide layer;
6 is polysilicon;
for an N-type trench MOSFET:
7.1, 7.2 and 7.3 are respectively a first P-type doped region (P-type body region), a second P-type doped region and a third P-type doped region;
8.1, 8.2 and 8.3 are respectively a first N-type doped region (N-type source region), a second N-type doped region and a third N-type doped region;
for a P-type trench MOSFET:
7.1, 7.2 and 7.3 are respectively a first N-type doped region (N-type body region), a second N-type doped region and a third N-type doped region;
8.1, 8.2 and 8.3 are respectively a first P-type doped region (P-type source region), a second P-type doped region and a third P-type doped region;
9 is a medium layer;
10.1, 10.2 and 10.3 are respectively a first lead hole, a second lead hole and a third lead hole;
11.1 and 11.2 are respectively a first metal interconnection line and a second metal interconnection line;
and 12 is a drain metal.
Detailed Description
The invention will be further described with reference to the following figures and examples:
example 1: a trench MOSFET integrated with ESD protection is disclosed, and is shown in figures 2 and 3.
The trench MOSFET integrated with ESD protection of the present invention, as shown in fig. 2, includes a zener diode formed by connecting forward and backward PN junctions in series between the gate and the source of the MOSFET, wherein one end of the zener diode is connected to the gate of the MOSFET, and the other end of the zener diode is connected to the source of the MOSFET; a voltage stabilizing diode formed by connecting forward and reverse PN junctions in series is arranged between the grid electrode and the drain electrode of the MOSFET, one end of the voltage stabilizing diode is connected with the grid electrode of the MOSFET, and the other end of the voltage stabilizing diode is connected with the drain electrode of the MOSFET; the zener diodes are all bulk silicon diodes, and the equivalent circuit diagram is shown in fig. 3.
As shown in fig. 2, the zener diode is located below the MOSFET gate and in the peripheral region of the gate, and a plurality of trenches are included between the zener diode and the MOSFET cell area, where the plurality of trenches at least include two trenches: respectively as follows: a trench (4.2 in the figure) to form a MOSFET termination field limiting ring (7.2 in the figure) and a trench (4.3 in the figure) to isolate the zener diode from the MOSFET termination region.
The utility model discloses a trench MOSFET of integrated ESD protection it is applicable to N type trench MOSFET and P type trench MOSFET, and when the MOSFET chip is N type trench MOSFET, the zener diode between grid and the drain electrode is N/P/N-structure; when the MOSFET chip is a P-type groove MOSFET, the voltage stabilizing diode between the grid electrode and the drain electrode is in a P/N/P-structure.
Further, when the MOSFET chip is an N-type trench MOSFET, the N-type doped region of the zener diode N/P/N-between the gate and the drain (i.e., N in N/P/N-, 8.2 in the figure) and the N-type source region of the MOSFET (8.1 in the figure) have the same doping concentration (the N-type doped region and the N-type source region can be formed simultaneously, which can reduce the process cost).
When the MOSFET chip is a P-type trench MOSFET, the P-type doped region of the zener diode P/N/P-between the gate and the drain (i.e., P in P/N/P, 8.2 in the figure) and the P-type source region of the MOSFET (8.1 in the figure) have the same doping concentration (the P-type doped region and the P-type source region can be formed simultaneously, which can reduce the process cost).
Further, when the MOSFET chip is an N-type trench MOSFET, the P-type doped region of the zener diode N/P/N-between the gate and the drain (i.e., P in N/P/N-, 7.3 in the figure) and the P-type body region of the MOSFET (7.1 in the figure) have the same doping concentration (i.e., can be formed simultaneously, which can reduce the process cost).
When the MOSFET chip is a P-type trench MOSFET, the N-type doped region of the zener diode P/N/P-between the gate and the drain (i.e., N in P/N/P-and 7.3 in the figure) and the N-type body region of the MOSFET (and 7.1 in the figure) have the same doping concentration (i.e., they can be formed simultaneously, which can reduce the process cost).
Further, when the MOSFET chip is an N-type trench MOSFET, the N-type doped region of the Zener diode N/P/N-between the grid and the drain (i.e. N in N/P/N-) is an N-type epitaxial layer (2 in the figure) of the MOSFET; and when the MOSFET chip is a P-type groove MOSFET, the P-type doped region (namely P in P/N/P-) of the voltage stabilizing diode P/N/P-between the grid electrode and the drain electrode is a P-type epitaxial layer (2 in the figure) of the MOSFET.
Furthermore, the trench MOSFET integrated with ESD protection of the present invention is suitable for N-type trench MOSFET and P-type trench MOSFET, and when the MOSFET chip is N-type trench MOSFET, the voltage regulator diode between the gate and the source is of N/P/N structure; and when the MOSFET chip is a P-type groove MOSFET, the voltage stabilizing diode between the grid electrode and the source electrode is in a P/N/P structure.
Further, when the MOSFET chip is an N-type trench MOSFET, the N-type doped region of the zener diode N/P/N between the gate and the source (i.e., N in N/P/N, 8.2 and 8.3 in the figure) and the N-type source region of the MOSFET (8.1 in the figure) have the same doping concentration (i.e., can be formed simultaneously, which can reduce the process cost).
When the MOSFET chip is a P-type trench MOSFET, the P-type doped region of the Zener diode P/N/P between the grid and the source (i.e. P in P/N/P, 8.2 and 8.3 in the figure) and the P-type source region of the MOSFET (8.1 in the figure) have the same doping concentration (i.e. can be formed synchronously, and the process cost can be reduced).
Further, when the MOSFET chip is an N-type trench MOSFET, the P-type doped region of the zener diode N/P/N between the gate and the source (i.e., P in N/P/N, 7.3 in the figure) and the P-type body region of the MOSFET (7.1 in the figure) have the same doping concentration (i.e., they can be formed simultaneously, which can reduce the process cost).
When the MOSFET chip is a P-type trench MOSFET, the N-type doped region of the zener diode P/N/P between the gate and the source (i.e., N in P/N/P, 7.3 in the figure) and the N-type body region of the MOSFET (7.1 in the figure) have the same doping concentration (i.e., they can be formed simultaneously, which can reduce the process cost).
As shown in fig. 3, fig. 3 is an equivalent circuit diagram corresponding to the trench MOSFET with integrated ESD protection according to the present invention.
s1, forming a lightly doped N-type epitaxial layer 2 on the top surface of the heavily doped N-type silicon substrate 1, see fig. 4.
S2, forming a hard mask 3 on the upper surface of the N-type epitaxial layer 2, wherein the material of the hard mask 3 is silicon oxide or silicon nitride, or a stacked layer formed by silicon oxide and silicon nitride, and the thickness of the hard mask 3 is 200-600nm, as shown in fig. 5.
S3, removing the hard mask in the set area (i.e. remaining the hard mask in the set area) by using a photolithography and etching process, and then removing the photoresist, see fig. 6.
S4, forming a first groove 4.1, a second groove 4.2 and a third groove 4.3 on the surface layer of the N-type epitaxial layer 2 by using the reserved hard mask 3 as a barrier layer and adopting an etching process; the first grooves 4.1 are composed of a plurality of (more than or equal to two) grooves, the second grooves 4.2 at least comprise one groove, and the third grooves 4.3 at least comprise one groove; the depth of the first groove 4.1, the second groove 4.2 and the third groove 4.3 is 0.6-3.0um, see fig. 7.
S5, removing the hard mask 3, and then growing a gate oxide layer 5 on the surfaces of the first trench 4.1, the second trench 4.2 and the third trench 4.3 by adopting a high-temperature oxidation process, wherein the thickness of the gate oxide layer 5 is 15-120nm, and because the high-temperature oxidation process has no regioselectivity, the gate oxide layer is also grown on the upper surface of the N-type epitaxial layer 2; and then, growing polycrystalline silicon 6 on the surface of the gate oxide layer by adopting a chemical vapor deposition process method, wherein the first trench 4.1, the second trench 4.2 and the third trench 4.3 are filled with the polycrystalline silicon 6, which is shown in fig. 8.
S6, removing the polysilicon outside the first, second and third trenches 4.1, 4.2, 4.3 by Chemical Mechanical Polishing (CMP) or dry etching, and only retaining the polysilicon in the first, second and third trenches 4.1, 4.2, 4.3; the upper surface of the remaining polysilicon is not higher than the upper surface of the gate oxide layer 5, see fig. 9.
S7, forming a P-type doped region on the surface layer of the N-type epitaxial layer 2 by adopting an ion implantation and annealing process, wherein the P-type doped region comprises a first P-type doped region 7.1, a second P-type doped region 7.2 and a third P-type doped region 7.3; the first P-type doped region 7.1 is located in a region between the trenches of the first trench 4.1, and the second P-type doped region 7.2 is located in a region between the first trench 4.1 and the third trench 4.3 and is separated into a plurality of sections (greater than or equal to two sections) by the second trench 4.2; the third P-type doped region 7.3 is located in the peripheral region of the third trench 4.3.
As described above, the first P-type doped region 7.1, the second P-type doped region 7.2, and the third P-type doped region 7.3 are formed by the same ion implantation and annealing process, and do not need to be formed by performing a photolithography process to perform zoning and separate ion implantation, as shown in fig. 10.
S8, forming a first N-type doped region 8.1 on the surface layer of the first P-type doped region 7.1, and forming a second N-type doped region 8.2 and a third N-type doped region 8.3 in a set region on the surface layer of the third P-type doped region 7.3 by photolithography, ion implantation, and annealing;
as described above, the first N-type doped region 8.1, the second N-type doped region 8.2, and the third N-type doped region 8.3 are formed by the same photolithography, ion implantation, and annealing process, and are formed by performing zoning and respective ion implantation without performing photolithography processes for many times;
as mentioned above, the third N-type doped region 8.3 is a ring-shaped N-type doped region surrounding one or several turns, and the second N-type doped region 8.2 is located in the central region where the ring-shaped N-type doped region is surrounded, see fig. 11.
S9, forming the dielectric layer 9, the first wire hole 10.1, the second wire hole 10.2, the third wire hole 10.3, the first metal interconnection 11.1, and the second metal interconnection 11.2 by deposition, photolithography, and etching.
The first lead hole 10.1 is located above the first N-type doped region 8.1, the second lead hole 10.2 is located above the second N-type doped region 8.2, and the third lead hole 10.3 is located above the third N-type doped region 8.3.
The first metal interconnection line 11.1 is a gate metal of the MOSFET and connects the second N-type doped region 8.2 to the gate through the second wire hole 10.2.
Wherein the second metal interconnection line 11.2 is a source metal of the MOSFET and connects the first N-doped region 8.1 and the third N-doped region 8.3 to the source through the first wire hole 10.1 and the third wire hole 10.3, see fig. 12.
So far, the main structure of the trench MOSFET integrated with ESD protection is completed, and the subsequent process steps including the back thinning, back metallization (forming the drain metal 12), and the like, all belong to the conventional process steps in the industry, and are not described herein again.
As shown in fig. 12, the first P-type doped region 7.1 constitutes a P-type body region of the MOSFET, the first N-type doped region 8.1 constitutes an N-type source region of the MOSFET, and the P-type body region 7.1, the N-type source region 8.1 and the first trench 4.1 constitute a cell region of the MOSFET.
The second P-type doped region 7.2 forms a MOSFET termination region field-limiting ring, and the field-limiting ring 7.2 and the second trench 4.2 form a MOSFET termination region.
Further, the NPN structure formed by the second N-type doped region 8.2, the third P-type doped region 7.3 and the third N-type doped region 8.3 in the trench MOSFET integrated with ESD protection of the present invention is a zener diode between the gate and the source, one end of the zener diode (the second N-type doped region 8.2) is connected to the gate 11.1, and the other end of the zener diode (the third N-type doped region 8.3) is connected to the source 11.2; the NPN structure of the voltage stabilizing diode is a forward PN junction series structure and a reverse PN junction series structure, and ESD energy discharge between the grid electrode and the source electrode can be realized.
Further, the present invention discloses an NPN-structure formed by the second N-type doped region 8.2, the third P-type doped region 7.3 and the lightly doped N-type epitaxial layer 2 in the trench MOSFET for integrated ESD protection is a zener diode between the gate and the drain, one end of the zener diode (the second N-type doped region 8.2) is connected to the gate 11.1, and the other end of the zener diode (the N-type epitaxial layer 2) is connected to the N-type substrate 1 of the MOSFET, that is, to the drain; the NPN-structure of the zener diode, i.e., the forward and reverse PN junction series structure, can achieve ESD energy discharge between the gate and the drain, as described above.
To sum up, the utility model discloses an integrated ESD protection's slot MOSFET compares with prior art and has following advantage:
the utility model discloses an its inside integrated zener diode of slot MOSFET of integrated ESD protection is the bulk silicon diode, and not polycrystalline silicon diode, and consequently zener diode's ESD discharge characteristic is more stable, and ESD protective capability is also more stable.
The structure of the utility model does not adopt thick oxide layer and polysilicon diode, the structure on the surface of the chip is relatively smooth, there is no high step drop, the process difficulty is lower, the process stability is better, the manufacturing cost is lower.
The utility model discloses between grid and source to and between grid and drain electrode, all integrated zener diode, ESD energy between grid and the drain electrode is released and need not pass through MOSFET's internal parasitic diode, ESD energy of releasing that can be faster, therefore the ESD protective capability is better.
The utility model discloses an internally integrated zener diode's P type doping area and MOSFET's P type somatic region can form in step in the technology, and zener diode's N type doping area and MOSFET's N type source region can form in step in the technology to realize lower manufacturing cost.
It should be noted that the present invention is described with reference to N-type trench MOSFET as an example, but the present invention is also applicable to P-type trench MOSFET; all trench MOSFETs with integrated ESD protection can be considered as the scope of protection of the present invention without departing from the main spirit of the present invention.
In summary, the embodiments of the present invention disclose a preferred embodiment, but not limited thereto, and those skilled in the art can easily understand the spirit of the present invention according to the above embodiments, and make different extensions and changes, but the scope of the present invention is within the scope of the present invention.
Claims (12)
1. An integrated ESD protected trench MOSFET, comprising: a voltage stabilizing diode formed by connecting forward and reverse PN junctions in series is arranged between the grid and the source of the MOSFET, one end of the voltage stabilizing diode is connected with the grid of the MOSFET, and the other end of the voltage stabilizing diode is connected with the source of the MOSFET; and a voltage stabilizing diode formed by connecting forward and reverse PN junctions in series is arranged between the grid electrode and the drain electrode of the MOSFET, one end of the voltage stabilizing diode is connected with the grid electrode of the MOSFET, and the other end of the voltage stabilizing diode is connected with the drain electrode of the MOSFET.
2. The integrated ESD protected trench MOSFET of claim 1 wherein: and the voltage stabilizing diodes are all bulk silicon diodes.
3. The integrated ESD protected trench MOSFET of claim 1 wherein: the voltage stabilizing diode is positioned below the grid electrode of the MOSFET and in the peripheral area of the grid electrode; at least two grooves are arranged between the voltage stabilizing diode and the MOSFET cellular area, and at least two grooves at least comprise a first groove used for forming a MOSFET terminal area field limiting ring and a second groove used for isolating the voltage stabilizing diode and the MOSFET terminal area.
4. The integrated ESD protected trench MOSFET of claim 1 wherein: the MOSFET is an N-type groove MOSFET or a P-type groove MOSFET.
5. The integrated ESD protected trench MOSFET of claim 4 wherein: when the MOSFET is an N-type groove MOSFET, the voltage stabilizing diode between the grid electrode and the drain electrode is of an N/P/N-structure; when the MOSFET is a P-type groove MOSFET, the voltage stabilizing diode between the grid electrode and the drain electrode is in a P/N/P-structure.
6. The integrated ESD protected trench MOSFET of claim 4 wherein: when the MOSFET chip is an N-type groove MOSFET, the N-type doping region of the voltage stabilizing diode N/P/N-between the grid electrode and the drain electrode has the same doping concentration as the N-type source region of the MOSFET; when the MOSFET chip is a P-type groove MOSFET, the P-type doped region of the voltage stabilizing diode P/N/P-between the grid electrode and the drain electrode and the P-type source region of the MOSFET have the same doping concentration.
7. The integrated ESD protected trench MOSFET of claim 4 wherein: when the MOSFET chip is an N-type groove MOSFET, the doping concentration of a P-type doping area of a voltage stabilizing diode N/P/N-between the grid electrode and the drain electrode is the same as that of a P-type body area of the MOSFET; when the MOSFET chip is a P-type groove MOSFET, the N-type doped region of the voltage stabilizing diode P/N/P-between the grid electrode and the drain electrode and the N-type body region of the MOSFET have the same doping concentration.
8. The integrated ESD protected trench MOSFET of claim 4 wherein: when the MOSFET chip is an N-type groove MOSFET, an N-type doped region of a voltage stabilizing diode N/P/N-between the grid electrode and the drain electrode is an N-type epitaxial layer of the MOSFET; when the MOSFET chip is a P-type groove MOSFET, the P-type doped region of the voltage stabilizing diode P/N/P-between the grid electrode and the drain electrode is the P-type epitaxial layer of the MOSFET.
9. The integrated ESD protected trench MOSFET of claim 4 wherein: when the MOSFET chip is an N-type groove MOSFET, the voltage stabilizing diode between the grid electrode and the source electrode is of an N/P/N structure.
10. The integrated ESD protected trench MOSFET of claim 4 wherein: when the MOSFET chip is a P-type groove MOSFET, the voltage stabilizing diode between the grid electrode and the source electrode is in a P/N/P structure.
11. The integrated ESD protected trench MOSFET of claim 4 wherein: when the MOSFET chip is an N-type groove MOSFET, the N-type doped region of the voltage stabilizing diode N/P/N between the grid electrode and the source electrode has the same doping concentration as the N-type source region of the MOSFET; when the MOSFET chip is a P-type groove MOSFET, the P-type doped region of the voltage stabilizing diode P/N/P between the grid electrode and the source electrode and the P-type source region of the MOSFET have the same doping concentration.
12. The integrated ESD protected trench MOSFET of claim 4 wherein: when the MOSFET chip is an N-type groove MOSFET, the doping concentration of a P-type doping area of a voltage stabilizing diode N/P/N between the grid electrode and the source electrode is the same as that of a P-type body area of the MOSFET; when the MOSFET chip is a P-type groove MOSFET, the N-type doped region of the voltage stabilizing diode P/N/P between the grid electrode and the source electrode and the N-type body region of the MOSFET have the same doping concentration.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110518063A (en) * | 2019-09-30 | 2019-11-29 | 深圳市芯电元科技有限公司 | The groove MOSFET and manufacturing method of integrated ESD protection |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110518063A (en) * | 2019-09-30 | 2019-11-29 | 深圳市芯电元科技有限公司 | The groove MOSFET and manufacturing method of integrated ESD protection |
| CN110518063B (en) * | 2019-09-30 | 2024-05-28 | 深圳市芯电元科技有限公司 | Trench MOSFET integrated with ESD protection and method of manufacture |
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