CN117219654B

CN117219654B - High-voltage grid driving circuit and preparation method thereof

Info

Publication number: CN117219654B
Application number: CN202311468067.3A
Authority: CN
Inventors: 姚国亮; 乔明
Original assignee: University of Electronic Science and Technology of China; Hangzhou Silan Microelectronics Co Ltd
Current assignee: University of Electronic Science and Technology of China; Hangzhou Silan Microelectronics Co Ltd
Priority date: 2023-11-07
Filing date: 2023-11-07
Publication date: 2024-02-23
Anticipated expiration: 2043-11-07
Also published as: CN117219654A

Abstract

The application discloses high-voltage gate drive circuit and preparation method thereof, high-voltage gate drive circuit includes: a substrate of a first doping type; a first buried layer of a second doping type located on the substrate; an epitaxial layer of a first doping type on the substrate and the first buried layer, the epitaxial layer including a high-side drive circuit region, a low-side drive circuit region, and a level shift circuit region, the level shift circuit region including at least a high-voltage LDMOS device; and a high-voltage isolation island and an isolation structure, the high-side drive circuit region and the low-side drive circuit region being isolated via the high-voltage isolation island, the level shift circuit region and the high-side drive circuit region being isolated via the isolation structure. The high-voltage grid driving circuit has higher breakdown voltage and isolation voltage, reduces reliability risks such as high-voltage overline and the like, requires fewer photoetching layers and simpler working procedures in the process, and reduces production cost.

Description

High-voltage grid driving circuit and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a high-voltage gate driving circuit and a preparation method thereof.

Background

BCD (Bipolar-CMOS-DMOS technology) is generally classified into high voltage BCD, high density BCD (emphasizing linewidth reduction of control logic), and high power BCD (emphasizing output large current of critical power transistors) according to industry standards. The high-voltage BCD technology is generally applied to HVICs (High Voltage Integrated Circuit, high-voltage integrated circuits), and refers to BCD technology with a withstand voltage above 100V, and is widely applied to the fields of AC-DC power supply, LED driving, high-voltage gate driving (motor driving), and the like, where the withstand voltage of a power device is generally required to reach 500V to 800V.

When the HVIC is applied to a high-voltage gate driving circuit, the HVIC is mainly used for driving a motor, a typical topological structure is half-bridge driving, the high-voltage gate driving circuit comprises a low-side driving circuit region and a high-side driving circuit region, and the high-side driving circuit region is required to realize high-side floating driving through a level shift technology. The level shift circuit region is typically implemented by a high voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor, lateral double-diffused metal oxide semiconductor) device, and a drain terminal of the high voltage LDMOS device typically requires a high voltage cross-over (HVI) to the high side driving circuit region, resulting in a high voltage cross-over problem. In order to solve this problem, three generations of technologies are mainly developed for the high voltage gate driving circuit. Fig. 1a to 1c show schematic structural diagrams of a third generation isolation structure of a high voltage gate driving circuit, wherein fig. 1a shows a schematic diagram of a first generation conventional isolation structure; FIG. 1b shows a schematic diagram of a second generation self-isolating structure; fig. 1c shows a schematic diagram of a third generation partition RESURF (Divided RESURF) isolation structure. All three isolation structures are currently in use.

However, the three isolation structures are based on the common lateral PN junction isolation of bulk silicon, and in practical application, reliability problems such as high-voltage overline and parasitic effects can be caused.

In addition, as the product iterates, the requirements on switching speed, area and efficiency are getting higher and higher, how to achieve the above objective with fewer lithography levels and lower cost, and obtaining better performance is the main trend of HVIC development.

Disclosure of Invention

In view of the above problems, the present invention aims to provide a high-voltage gate driving circuit and a manufacturing method thereof, wherein the high-voltage gate driving circuit is provided with an isolation structure with an air gap, and the isolation structure with the air gap integrates the characteristics of good isolation, small electric leakage, small area, high reliability, high breakdown voltage and the like, and plays a good role in isolation.

According to an aspect of the present invention, there is provided a high voltage gate driving circuit including: a substrate of a first doping type; a first buried layer of a second doping type located on the substrate; an epitaxial layer of a first doping type on the substrate and the first buried layer, the epitaxial layer including a high-side drive circuit region, a low-side drive circuit region, and a level shift circuit region, the level shift circuit region including at least a high-voltage LDMOS device; and a high-voltage isolation island and an isolation structure, the high-side drive circuit region and the low-side drive circuit region being isolated via the high-voltage isolation island, the level shift circuit region and the high-side drive circuit region being isolated via the isolation structure; wherein, the isolation structure includes: an isolation trench extending from a surface of the epitaxial layer to an inside of the substrate; the dielectric layer is positioned on the inner wall of the isolation groove; and an air gap inside the dielectric layer.

Optionally, the width of the isolation trench is 1.0 μm to 3.0 μm, the depth is 15 μm to 30 μm, and the width-to-depth ratio of the isolation trench is 1: 5-1: 20.

optionally, the high-voltage LDMOS device includes: the substrate of the first doping type; the first buried layer with the second doping type is positioned on the substrate; the epitaxial layer with the first doping type is positioned on the substrate and the first buried layer; a high-voltage well of a second doping type located in the epitaxial layer; a low voltage well of a first doping type located in the high voltage well; a second buried layer of the first doping type located in the high-voltage well; a field oxide layer located on the high voltage well and the low voltage well of the first doping type; an ohmic contact region of a second doping type located in the high voltage well and the low voltage well of the first doping type; an ohmic contact region of a first doping type located in the low voltage well of the first doping type; and a gate structure located on the field oxide layer, the high voltage well and the low voltage well of the first doping type; wherein the second buried layer includes: a first portion located under and in contact with the low voltage well of the first doping type; a second portion below the field oxide layer and spaced apart from the field oxide layer; and a third portion connecting the first portion and the second portion such that the second buried layer is electrically connected with the low-voltage well of the first doping type.

Optionally, the high-side driving circuit region includes at least a medium voltage NMOS device and a medium voltage PMOS device, and the medium voltage NMOS device includes: the substrate of the first doping type; the first buried layer with the second doping type is positioned on the substrate; the epitaxial layer with the first doping type is positioned on the first buried layer; the high-voltage well of the second doping type is positioned in the epitaxial layer, and the high-voltage well in the high-voltage LDMOS device and the high-voltage well in the medium-voltage NMOS device are formed at the same time; the low-voltage well of the first doping type is positioned in the epitaxial layer, and the low-voltage well of the first doping type in the high-voltage LDMOS device and the low-voltage well of the first doping type in the medium-voltage NMOS device are formed at the same time; a low voltage well of a second doping type located in the epitaxial layer and the high voltage well; the second buried layer of the first doping type is positioned below the low-voltage well of the first doping type and the low-voltage well of the second doping type in the epitaxial layer and is in contact with the low-voltage well of the first doping type and the low-voltage well of the second doping type, and the second buried layer in the high-voltage LDMOS device and the second buried layer in the medium-voltage NMOS device are formed at the same time; a field oxide layer located on the high-voltage well, the low-voltage well of the first doping type, the low-voltage well of the second doping type and the epitaxial layer, wherein the field oxide layer in the high-voltage LDMOS device and the field oxide layer in the medium-voltage NMOS device are formed at the same time; the ohmic contact region of the first doping type is positioned in the low-voltage well of the first doping type, and the ohmic contact region of the first doping type in the high-voltage LDMOS device and the ohmic contact region of the first doping type in the medium-voltage NMOS device are formed simultaneously; the ohmic contact region of the second doping type is positioned in the low-voltage well of the first doping type and the low-voltage well of the second doping type, and the ohmic contact region of the second doping type in the high-voltage LDMOS device and the ohmic contact region of the second doping type in the medium-voltage NMOS device are formed at the same time; the grid structure is positioned on the field oxide layer, the low-voltage well of the first doping type and the low-voltage well of the second doping type, and the grid structure in the high-voltage LDMOS device and the grid structure in the medium-voltage NMOS device are formed at the same time; in the medium voltage NMOS device, the high voltage well is positioned at two sides of the medium voltage NMOS device and connected with the first buried layer, and the low voltage well with the second doping type and the first buried layer are isolated through the second buried layer and the epitaxial layer.

Optionally, the method further comprises: one or more of low-voltage NMOS, low-voltage PMOS, triode, resistor and capacitor.

According to another aspect of the present invention, there is provided a method for manufacturing a high voltage gate driving circuit, comprising: forming a first buried layer of a second doping type on the substrate of the first doping type; forming an epitaxial layer of a first doping type on the substrate and the first buried layer, wherein the epitaxial layer comprises a high-side driving circuit region, a low-side driving circuit region and a level shift circuit region; forming an isolation structure; forming at least a high-voltage LDMOS device in an epitaxial layer of the level shift circuit area, wherein the level shift circuit area is isolated from the high-side driving circuit area through the isolation structure; and forming a high-voltage isolation island in the epitaxial layer, the high-side drive circuit region being isolated from the low-side drive circuit region via the high-voltage isolation island; the method for forming the isolation structure comprises the following steps: etching the epitaxial layer and part of the substrate to form an isolation trench extending from the surface of the epitaxial layer to the inside of the substrate; forming a dielectric layer on the inner wall of the isolation trench; and forming an air gap inside the dielectric layer.

optionally, the method for forming the high-voltage LDMOS device comprises the following steps: forming the first buried layer of a second doping type on the substrate of a first doping type; forming the epitaxial layer of a first doping type on the substrate and the first buried layer; forming a high-voltage well of a second doping type in the epitaxial layer; forming a low-voltage well of a first doping type in the high-voltage well; forming a second buried layer of the first doping type in the high-voltage well; forming a field oxide layer on the high voltage well and the low voltage well of the first doping type in the high voltage well; forming an ohmic contact region of a second doping type in the high-voltage well and a low-voltage well of the first doping type in the high-voltage well, and forming an ohmic contact region of the first doping type in the low-voltage well of the first doping type in the high-voltage well; and forming a gate structure on the field oxide layer, the high voltage well and the low voltage well of the first doping type in the high voltage well; wherein the second buried layer includes: a first portion located under and in contact with the low voltage well of the first doping type; a second portion below the field oxide layer and spaced apart from the field oxide layer; and a third portion connecting the first portion and the second portion such that the second buried layer is electrically connected with the low-voltage well of the first doping type.

Optionally, at least a medium voltage NMOS device and a medium voltage PMOS device are formed in the epitaxial layer of the high side driving circuit region, and the method for forming the medium voltage NMOS device includes: forming the first buried layer of a second doping type on the substrate of a first doping type; forming the epitaxial layer of the first doping type on the first buried layer; forming the high-voltage well with the second doping type in the epitaxial layer, wherein the high-voltage well in the high-voltage LDMOS device and the high-voltage well in the medium-voltage NMOS device are formed at the same time; forming a low-voltage well of the first doping type in the epitaxial layer of the medium-voltage NMOS device, wherein the low-voltage well of the first doping type in the high-voltage LDMOS device and the low-voltage well of the first doping type in the medium-voltage NMOS device are formed simultaneously; forming a low-voltage well of a second doping type in the epitaxial layer and the high-voltage well of the medium-voltage NMOS device; forming the second buried layer of a first doping type in the epitaxial layer of the medium voltage NMOS device, wherein the second buried layer is positioned below the low-voltage well of the first doping type and the low-voltage well of the second doping type in the epitaxial layer and is in contact with the low-voltage well of the first doping type and the low-voltage well of the second doping type, and the second buried layer in the high voltage LDMOS device and the second buried layer in the medium voltage NMOS device are formed simultaneously; forming the field oxide layer on the high voltage well in the epitaxial layer, the low voltage well of the first doping type in the epitaxial layer, the low voltage well of the second doping type in the epitaxial layer and the epitaxial layer of the medium voltage NMOS device, wherein the field oxide layer in the high voltage LDMOS device and the field oxide layer in the medium voltage NMOS device are formed simultaneously; forming an ohmic contact region of the first doping type in the low-voltage well of the first doping type in the epitaxial layer of the medium-voltage NMOS device, wherein the ohmic contact region of the first doping type in the high-voltage LDMOS device and the ohmic contact region of the first doping type in the medium-voltage NMOS device are formed simultaneously; forming ohmic contact regions of the second doping type in the low-voltage well of the first doping type in the epitaxial layer of the medium-voltage NMOS device and the low-voltage well of the second doping type in the epitaxial layer, wherein the ohmic contact regions of the second doping type in the high-voltage LDMOS device and the ohmic contact regions of the second doping type in the medium-voltage NMOS device are formed simultaneously; and forming the gate structure on the field oxide layer of the medium voltage NMOS device, the low voltage well of the first doping type in the epitaxial layer, the low voltage well of the second doping type in the epitaxial layer, the gate structure in the high voltage LDMOS device and the gate structure in the medium voltage NMOS device being formed simultaneously; in the medium voltage NMOS device, the high voltage well is positioned at two sides of the medium voltage NMOS device and connected with the first buried layer, and the low voltage well with the second doping type and the first buried layer are isolated through the second buried layer and the epitaxial layer.

Optionally, the method further comprises: one or more devices of low-voltage NMOS, low-voltage PMOS, triode, resistor and capacitor are formed.

The DTI isolation structure with the air gap is mainly used between the level shift circuit area and the high-side drive circuit area, so that the sensitivity of breakdown voltage and isolation voltage existing in the conventional process to the process and the layout can be effectively relieved, and the design of an isolation area between the two is simpler. The high-voltage junction isolation structure has the advantages that high breakdown voltage is achieved, meanwhile, high isolation voltage is also achieved between the level shift circuit area and the high-side drive circuit area, and the problem that isolation voltage is low due to high-voltage overline of a traditional junction isolation structure is solved. And because the dielectric constant of the air gap is far smaller than that of solid insulating materials such as polycrystal and oxide layers, the parasitic capacitance in the applied circuit is reduced, the reaction time is prolonged, and the method is more suitable for high-frequency application.

Compared with the conventional polycrystal filling DTI isolation structure (the polycrystal structure is filled in the isolation groove), in the working state, the floating polycrystal can induce electric potential, so that the two sides of the isolation groove are opened on site (carriers are induced on the two sides of the isolation groove, thereby forming conducting paths on the two sides of the isolation groove, and the field opening is caused), and lower through voltage is caused. An improvement is to etch the isolation trench so that the poly in the isolation trench is connected to the substrate at zero potential all the time, but this structure suffers from the problem of electric field concentration, eventually resulting in a reduced breakdown voltage. Another solution is to use tank bottom injection, but the high concentration of P-type impurities introduced at the tank bottom can lead to early breakdown of the tank bottom. Both methods cannot obtain a higher isolation voltage while satisfying the breakdown voltage requirement. The DTI isolation structure of the embodiment of the application can not generate the problems caused by the polycrystalline filling DTI isolation structure, and can meet the requirements of breakdown voltage and isolation voltage.

The problem of the whole-medium DTI isolation structure can be avoided, but the stress problem caused by the whole-medium DTI is easy to cause defects in the device.

The isolation voltage on two sides of the DTI isolation structure can be continuously increased along with the increase of the depth of the DTI isolation structure, and the required isolation voltage can be obtained by setting the depth of the DTI isolation structure.

The DTI isolation structure of the embodiments of the present application may also be used for isolation of other devices, such as between a high side driver circuit region and a low side driver circuit region. The parasitic triode in the circuit can be reduced in starting risk, so that the latch-up effect is relieved, the related electric leakage and reliability problems are improved, and the negative pressure problem and dV/dT problem of the inductive load in practical application are well relieved due to the isolation effect of the DTI isolation structure.

In summary, the DTI isolation structure provided by the application is used between the level shift circuit region and the high-side drive circuit region, has the characteristics of high breakdown voltage and high isolation voltage, and can effectively relieve the sensitivity of the breakdown voltage and isolation voltage existing in the conventional process to the process and the layout. The characteristics of good isolation, small electric leakage, small area, high reliability and high breakdown voltage are combined, and a good isolation effect can be achieved.

According to the high-voltage gate driving circuit, the second buried layer of the first doping type is introduced into the high-voltage well, so that in order to maintain charge balance, the concentration of impurities of the second doping type (such as N type) in the high-voltage LDMOS device is improved at the same time, and lower specific on-resistance is obtained under the same drift region length and breakdown voltage. Under the same current magnitude application requirement, the area of the high-voltage LDMOS device is smaller, the capacitance is smaller, and the high-voltage LDMOS device is more suitable for being applied to high-frequency scenes, such as the fields of LLC power supplies and the like.

Further, the second doping type impurity concentration of the drain electrode is increased by introducing the second buried layer, so that the on-state characteristic of the high-voltage LDMOS device is improved, the safe working area of the high-voltage LDMOS device is expanded, the effect of concentrating the electric field of the thin epitaxy process towards the source end is relieved, and the reliability problem caused by overlarge electric field of the beak part is reduced.

In the high-voltage LDMOS device, the second buried layer is located below the low-voltage well with the first doping type, and the concentration of the base region of the parasitic NPN triode can be improved by injecting the second buried layer with the first doping type below the low-voltage well with the first doping type, so that the difficulty of opening the parasitic NPN triode is increased, and the stability of the high-voltage LDMOS device is improved.

In the high-voltage LDMOS device, the second buried layer below the low-voltage well of the first doping type is connected with the low-voltage well of the first doping type to enable the low-voltage well to be electrically connected, so that the high-voltage LDMOS device provides a discharging passage for depletion charges in the second buried layer at the moment of switching of a switching state, and the switching speed is increased.

In addition, the conventional full-isolation (full-isolation) NMOS device needs an extra level to improve the isolation voltage between the low-voltage well of the second doping type and the first buried layer.

The full set of BCD (Bipolar, CMOS, DMOS) devices are realized by the method, only fewer photoetching and working procedures are needed, and the cost is obviously reduced.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1a shows a schematic structural diagram of a first generation conventional isolation structure;

FIG. 1b shows a schematic structural diagram of a second generation self-isolating structure;

FIG. 1c shows a schematic structure of a third generation of digital RESURF isolation structure;

fig. 2 shows an equivalent circuit diagram of a high voltage gate driving circuit;

FIG. 3a shows a top view of a conventional high voltage gate drive circuit;

FIG. 3b shows a cross-sectional view of FIG. 3a along the direction AA';

fig. 4a shows a top view of a high voltage gate drive circuit according to a first embodiment of the present application;

FIG. 4b is a cross-sectional view taken along the BB' direction in FIG. 4 a;

fig. 4c shows a schematic diagram of the connection of a second buried layer of the high voltage LDMOS device of the first embodiment of the present application;

FIG. 4d shows an enlarged view at C in FIG. 4 b;

FIG. 4e shows an enlarged view at D in FIG. 4 b;

FIG. 5a is a schematic diagram showing the simulation of the breakdown voltage and isolation voltage as a function of trench bottom implant dose for a conventional poly-filled DTI isolation structure;

fig. 5b shows a schematic simulation of breakdown voltage and isolation voltage of the DTI isolation structure according to the first embodiment of the present application as a function of the trench bottom implant dose;

fig. 6 shows a variation trend of breakdown voltage and specific on-resistance of the high-voltage LDMOS device according to the first embodiment of the present application with the implantation dosage of the second buried layer;

Fig. 7a shows a vertical isolation withstand voltage simulation diagram of a medium voltage NMOS device according to a first embodiment of the present application;

fig. 7b shows a breakdown voltage simulation diagram of a medium voltage NMOS device according to the first embodiment of the present application;

fig. 8 shows a schematic structural diagram of a high-voltage gate driving circuit according to a second embodiment of the present application;

fig. 9a to 9j are schematic structural diagrams showing various stages in the manufacturing process of the high voltage gate driving circuit according to the first embodiment of the present application.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown.

The invention may be embodied in various forms, some examples of which are described below.

Fig. 2 shows an equivalent circuit diagram of a high voltage gate drive circuit comprising a high side drive circuit region, a low side drive circuit region and a level shift circuit region, wherein the level shift circuit region comprises at least a high voltage LDMOS device, the high voltage LDMOS device performing signal transmission between the high side drive circuit region and the low side drive circuit region. The low-side driving circuit area takes the substrate potential GND as a reference, and an input signal passes through the low-side driving circuit area to drive an external power device; the small voltage of the low-side driving circuit area is output to the high-side driving circuit area through the high-voltage LDMOS device, so that enough driving voltage is generated, and finally the external power device is driven through the high-side driving circuit area.

The level shift circuit region may include one or more high-voltage LDMOS devices, a gate of each of the one or more high-voltage LDMOS devices being connected to the pulse generating circuit in the low-side driving circuit region, a source being grounded, and a drain being connected to the high-side driving circuit region. When the level shift circuit region adopts a plurality of high-voltage LDMOS devices to transmit signals from the low-side drive circuit region to the high-side drive circuit region, the plurality of high-voltage LDMOS devices alternately work, so that the effect of reducing power consumption is achieved. The high-side drive circuit region at least comprises a medium-voltage NMOS device and a medium-voltage PMOS device.

Fig. 3a shows a top view of a conventional high voltage gate drive circuit, which is a Divided RESURF structure, and fig. 3b shows a cross-sectional view along direction AA' of fig. 3 a. As shown in fig. 3a and 3b, the high-side driving circuit region, the low-side driving circuit region, and the level shift circuit region are located on the same substrate, the high-voltage isolation island isolates the high-side driving circuit region from the low-side driving circuit region, and the junction isolation structure J isolates the level shift circuit region from the high-side driving circuit region.

The second generation self-isolation structure generally causes larger electric leakage between the high-voltage LDMOS device and the high-voltage isolation island, and the third generation of the Divideo resuRF structure has larger sensitivity on the aspects of process fluctuation and layout although compared with the second generation self-isolation structure in terms of electric leakage, the isolation structure still has larger sensitivity on the aspects of process fluctuation and layout, the influence of charge balance on breakdown voltage and isolation voltage needs to be considered, and failure problem is easy to occur.

The high-voltage gate driving circuit employing the junction isolation structure J needs to consider the influence of the width of the isolation region on the breakdown voltage of the high-voltage LDMOS device and the isolation voltage between the high-voltage LDMOS device and the high-side driving circuit region. In order to obtain a better isolation effect, the width of the isolation region cannot be too small, otherwise, advanced breakdown of the high-voltage LDMOS device and the high-side driving circuit region may be caused, but the wider the isolation region is, the worse the depletion effect of the high-voltage LDMOS device and the high-side driving circuit region on the isolation region is, when impurities in a certain place in the isolation region are not depleted, advanced breakdown of the high-voltage LDMOS device is caused, and the breakdown voltage is reduced, namely, the width of the isolation region cannot be too large. Therefore, the conventional Divideo-RESURF structure needs to make a relatively complex design in an isolation region, and has certain requirements on drawing and processing of a layout. Meanwhile, due to the influence of high-voltage overwires, the junction isolation structure is easy to cause field opening on the surface of an epitaxial layer in a working state, so that isolation voltages at two sides of a high-voltage LDMOS device and a high-side driving circuit area are reduced. In the junction isolation structure J of fig. 3b, the introduction of the low voltage well 306b may alleviate the field-on effect and increase the isolation voltage, but a higher electric field peak may occur at both sides of 306b, which may lead to early breakdown of the device.

The isolation structure S can effectively relieve the problem caused by junction isolation. Fig. 4a illustrates a schematic structure of a high voltage gate driving circuit according to a first embodiment of the present application, fig. 4b is a cross-sectional view along a BB' direction in fig. 4a, fig. 4C illustrates a schematic structure of a second buried layer of a high voltage LDMOS device according to a first embodiment of the present application, fig. 4D illustrates an enlarged view at C in fig. 4b, and fig. 4e illustrates an enlarged view at D in fig. 4 b.

As shown in fig. 4a, the high-side driving circuit region, the low-side driving circuit region and the level shift circuit region are located on the same substrate, the high-voltage isolation island isolates the high-side driving circuit region from the low-side driving circuit region, and the DTI isolation structure S isolates the level shift circuit region from the high-side driving circuit region. As shown in fig. 4b, the level shift circuit region includes a high voltage LDMOS device, and the high side driver circuit region includes at least a medium voltage NMOS device and a medium voltage PMOS device. In other embodiments, two high-voltage LDMOS devices may be used in the level shift circuit region to transfer signals from the low-side driving circuit region to the high-side driving circuit region, and the two high-voltage LDMOS devices are operated alternately, so as to achieve the effect of reducing power consumption.

With continued reference to fig. 4b, the high voltage gate drive circuit includes a substrate 301 of a first doping type, a first buried layer 302 of a second doping type, an epitaxial layer 303 of the first doping type, and a DTI (Deep Trench Isolation ) isolation structure S. In this embodiment, the first doping type is, for example, P-type doping, and the second doping type is, for example, N-type doping.

A first buried layer 302 is located on the substrate 301, covering a part of the surface of the substrate 301, and an epitaxial layer 303 is located on the substrate 301 and the first buried layer 302, covering the surface of the substrate 301 and the surface of the first buried layer 302. The DTI isolation structure S extends from the surface of the epitaxial layer 303 toward the substrate 301, and penetrates the epitaxial layer 303 and extends into the substrate 301. The DTI isolation structure S isolates the epitaxial layer 303 into a plurality of regions to form a corresponding semiconductor device within each region.

The DTI isolation structure S includes an isolation trench S01, a dielectric layer S02 located within the trench S01, and an air gap (air-gap) S03 inside the dielectric layer S02. The isolation trench S01 extends from the surface of the epitaxial layer 303 to the inside thereof, penetrates the epitaxial layer 303, and extends into the substrate 301. Dielectric layer S02 is located within isolation trench S01, and an air gap S03 is formed within dielectric layer S02.

The DTI isolation structure S with the air gap is mainly used between a level shift circuit area and a high-side drive circuit area, the isolation groove structure is different from junction isolation, and the high-voltage overline has no influence on the isolation groove structure, so that the problems of field opening phenomenon and lower isolation voltage are avoided. The isolation voltage and the breakdown voltage of the DTI isolation structure S of the present application have small influence, and the influence of the width of the isolation region on the breakdown voltage of the high-voltage LDMOS device and the isolation voltage between the high-voltage LDMOS device and the high-side driving circuit region is not required to be considered. The sensitivity of breakdown voltage and isolation voltage existing in the conventional process to the process and the layout can be effectively relieved, and larger tolerance is provided. The high breakdown voltage is obtained, and meanwhile, a high isolation voltage is also arranged between the level shift circuit area and the high-side drive circuit area.

For medium-high voltage devices (> 30V) a larger rule (considering the cross-expansion of the well) is generally used to achieve a satisfactory isolation withstand voltage, thus occupying a larger chip area, resulting in an increase in the cost of the chip. The DTI isolation structure S can effectively solve the problem, and the corresponding isolation pressure-resistant requirement can be met only by the isolation groove S01 (the medium layer S02 is filled in the isolation groove S01 and the air gap S03 is formed in the medium layer S02) with the thickness of 1.0-2.0 mu m. The area of the DTI isolation structure S is smaller, the area of a chip is reduced, the isolation area of the chip can be effectively saved, and the cost is reduced.

FIG. 5a is a schematic diagram showing the simulation of the breakdown voltage and isolation voltage as a function of trench bottom implant dose for a conventional poly-filled DTI isolation structure; fig. 5b shows a schematic simulation of breakdown voltage and isolation voltage of the DTI isolation structure according to the first embodiment of the present application as a function of the trench bottom implant dose; in fig. 5a and 5b, the abscissa indicates the dose injected at the bottom of the trenchD _bi The left ordinate is breakdown voltage and the right ordinate is isolation voltage. The bottom of the groove is injected mainly to increase the concentration of P-type impurities at the bottom of the groove, and relieve the field opening phenomenon at two ends of the isolation groove, so that the isolation voltage is increased. In practical applications, breakdown voltages greater than 800V are required, while isolation voltages greater than 30V are required. As shown in fig. 5a, in the case of the conventional poly-filled DTI structure without bottom filling, the breakdown voltage is greater than 800V, but the isolation voltage is lower, only 8V, and the requirement of application cannot be met; with the increase of the injection dosage at the bottom of the tank, the injection dosage is 5e12cm ^-2 The isolation voltage can reach more than 30V under the dosage, but at the moment, the breakdown voltage is reduced due to the increase of the curvature effect of the groove bottom, so that the conventional polycrystal filling DTI isolation structure cannot meet the requirements of the breakdown voltage and the isolation voltage at the same time. As shown in fig. 5b, the DTI isolation structure of the first embodiment of the present application has no field opening phenomenon caused by the introduction of polycrystal, so that a higher isolation voltage can be obtained without bottom injection, and the DTI isolation structure has the characteristics of high breakdown voltage and high isolation voltage, and satisfies HVI C (High Voltage Integrated Circuit) is more suitable for high-voltage occasions. In addition, the DTI isolation structure S of the embodiment of the application can relieve inherent stress problems brought by a conventional full-medium DTI isolation structure, and improves reliability.

The DTI isolation structure of the embodiments of the present application may also be used for isolation of other devices, such as between a high-side driver circuit region and a low-side driver circuit region. Junction isolation structure J can have a significant latch-up problem. Compared with the junction isolation structure J, the DTI isolation structure S with the air gap can reduce the risk of starting parasitic triodes in a circuit, so that the latch-up effect is relieved, related electric leakage and reliability problems are improved, and the negative pressure problem and dV/dT problem of an inductive load in practical application are well relieved due to the isolation effect of the DTI isolation structure. The DTI isolation structure S integrates the characteristics of good isolation, small electric leakage, small area, high reliability and high breakdown voltage, and can play a good role in isolation.

With continued reference to fig. 4b, the high voltage LDMOS device comprises a high voltage well 304 of the second doping type located in the epitaxial layer 303, a low voltage well 306b of the first doping type located in the high voltage well 304 of the second doping type, and a plurality of ohmic contact regions respectively located in the high voltage well 304 of the second doping type and the low voltage well 306b of the first doping type, the plurality of ohmic contact regions comprising an ohmic contact region 308a of the second doping type and an ohmic contact region 308b of the first doping type, the ohmic contact region 308a being located in the high voltage well 304 and the low voltage well 306b, the ohmic contact region 308b being located in the low voltage well 306 b; ohmic contact regions 308a and 308b are provided as source and/or drain regions of the high voltage LDMOS device.

The high voltage LDMOS device further comprises a field oxide layer 305 on the high voltage well 304 and the low voltage well 306b, and a gate structure 307 on the surfaces of the low voltage well 306b, the high voltage well 304 and the field oxide layer 305, the gate structure 307 comprising a gate oxide layer and a gate poly.

The high voltage LDMOS device further comprises an insulating layer 311 and a metal electrode 309, the insulating layer 311 covering the gate structure 307, the field oxide layer 305 and the ohmic contact regions 308a, 308b, and the metal electrode 309 is formed on the insulating layer 311 penetrating the insulating layer 311 and being connected to the ohmic contact regions 308a, 308b and the gate structure 307.

Preferably, the high voltage LDMOS device further comprises a second buried layer 310 of the first doping type located within the high voltage well 304. As shown in fig. 4b and 4c, the second buried layer 310 includes a first portion 3101 located under the low-voltage well 306b, the first portion 3101 being located between the source and drain regions and being in contact with the low-voltage well 306b of the first doping type; a second portion 3102 located below the field oxide layer 305 and spaced apart from the field oxide layer 305; and a third portion 3103 connecting the first portion 3101 and the second portion 3102, the first portion 3101, the second portion 3102, and the third portion 3103 being integrally connected, and the first portion 3101 being in contact with the low-voltage well 306b such that the entire second buried layer 310 is electrically connected with the low-voltage well 306 b.

In this application, the second buried layer 310 is introduced into the high-voltage well 304, and the first buried layer 310 of the first doping type, the first buried layer 302 of the second doping type, the epitaxial layer 303 of the first doping type, the high-voltage well 304 of the second doping type, and the low-voltage well 306b of the first doping type form a Triple RESURF (Triple reduced surface field, triple surface electric field reduction) structure.

In order to obtain better dynamic performance, the floating second buried layer 310 is not adopted in the Triple RESURF structure, but the second buried layer 310 is connected with the low-voltage well 306b part of the first doping type to enable the second buried layer 310 to be electrically connected, so that the high-voltage LDMOS device provides a discharging passage for depletion charges in the second buried layer 310 at the moment of switching on/off state, and the switching speed is increased.

The introduction of the second buried layer 310 increases the concentration of the first doping type (e.g., P-type) impurity in the high-voltage LDMOS device, and the concentration of the second doping type (e.g., N-type) impurity in the high-voltage well 304 is also increased in order to maintain charge balance, and the increase in the first doping type impurity concentration of the high-voltage well 304 reduces the specific on-resistance of the high-voltage LDMOS device at the same drift region length and breakdown voltage. Under the same current application requirement, the area of the high-voltage LDMOS device is smaller, the capacitance is smaller, and the high-voltage LDMOS device is more suitable for being applied to high-frequency scenes.

Further, the second doping type impurity concentration of the drain electrode is increased by introducing the second buried layer 310, which is favorable for improving the on-state characteristic of the high-voltage LDMOS device, so that the safe operating area of the high-voltage LDMOS device is expanded, the effect of concentrating the electric field of the thin epitaxy process towards the source end is reduced, and the reliability problem caused by overlarge electric field of the beak part is reduced.

The high-voltage LDMOS device has a parasitic NPN triode formed by the ohmic contact region 308a of the second doping type, the low-voltage well 306b of the first doping type and the high-voltage well 304 of the second doping type, and the opening of the parasitic NPN triode causes a Snapback effect (negative resistance effect) to affect the output characteristics of the high-voltage LDMOS device. The concentration of the base region (low-voltage well 306 b) of the parasitic NPN triode can be increased by injecting the second buried layer 310 of the first doping type under the low-voltage well 306b of the high-voltage LDMOS device, so that the difficulty of opening the parasitic NPN triode is increased, and the stability of the high-voltage LDMOS device is improved.

Fig. 6 shows a variation trend of breakdown voltage and specific on-resistance of the high-voltage LDMOS device according to the first embodiment of the present application with the implantation dosage of the second buried layer 310. The specific on-resistance increases with an increase in the implant dose of the second buried layer 310, since the specific on-resistance is mainly determined by the concentration of the high-voltage well 304 and the conductive path. The increase in the implant dose of the second buried layer 310 consumes only a portion of the first doping type impurity concentration in the high voltage well 304 and a portion of the conductive path, and thus has only a slight increase in the on-resistance. The specific on-resistance of the invention reaches 100 m ohm cm ² Is much smaller than 300 m Ω -cm of Single RESURF ² And Double RESURF 170 m Ω·cm ² The same current capability can be provided in a smaller area.

Too much or too little of the implant dose of the second buried layer 310 may cause charge imbalance, and thus the breakdown voltage may be greatly reduced when the implant dose is too much or too little. At 2.9e12 cm ^-2 Is true at the implantation dose of (2)The charge balance of the N-type impurity and the P-type impurity is achieved, the maximum breakdown voltage (more than 800V) is obtained, and the application of the high-voltage gate driving circuit of 600V specifications is met.

Referring to fig. 4b and 4d, the buried layer 302 in the medium voltage NMOS device is located on the substrate 301, the epitaxial layer 303 is located on the buried layer 302, the medium voltage NMOS device includes a high voltage well 304 of a second doping type located in the epitaxial layer 303, a low voltage well 306a of the second doping type located in the high voltage well 304, a low voltage well 306b of a first doping type located in the epitaxial layer 303 and a low voltage well 306a of the second doping type located in the low voltage well 306a of the first doping type, and a plurality of ohmic contact regions in the low voltage well 306a of the second doping type and the low voltage well 306b of the first doping type, respectively, the plurality of ohmic contact regions including an ohmic contact region 308a of the second doping type and an ohmic contact region 308b of the first doping type, the ohmic contact region 308a being located in the low voltage well 306b of the first doping type and the low voltage well 306a of the second doping type, the ohmic contact region 308a and the ohmic contact region 308b being the source region and/or drain region of the medium voltage NMOS device 30 b.

The medium voltage NMOS device further includes a field oxide layer 305, a gate structure 307, an insulating layer 311, and a metal electrode 309. A field oxide layer 305 is located on the epitaxial layer 303, the high voltage well 304, the low voltage well 306a, and the low voltage well 306 b; gate structure 307 is located on the surfaces of low voltage well 306b, low voltage well 306a and field oxide layer 305; an insulating layer 311 covers the low voltage well 306a, the low voltage well 306b, the ohmic contact regions 308a, 308b, the gate structure 307 and the field oxide layer 305, and a metal electrode 309 is located on the insulating layer 311 and connected to the ohmic contact regions 308a, 308b and the gate structure 307 through the insulating layer 311.

The medium voltage NMOS device further comprises a second buried layer 310 of the first doping type located within the epitaxial layer 303. The second buried layer 310 is located under the low-voltage wells 306a and 306b in the epitaxial layer 303, and is in contact with the low-voltage wells 306a and 306b, respectively.

The high-voltage well 304 in the high-voltage LDMOS device and the high-voltage well 304 in the medium-voltage NMOS device are formed simultaneously; the low-voltage well 306b of the first doping type in the high-voltage LDMOS device and the low-voltage well 306b of the first doping type in the medium-voltage NMOS device are formed simultaneously; the second buried layer 310 in the high-voltage LDMOS device and the second buried layer 310 in the medium-voltage NMOS device are formed simultaneously; the field oxide layer 305 in the high voltage LDMOS device and the field oxide layer 305 in the medium voltage NMOS device are formed simultaneously; ohmic contact regions 308a of the first doping type in the high-voltage LDMOS device and ohmic contact regions 308a of the first doping type in the medium-voltage NMOS device are formed simultaneously; ohmic contact regions 308b of the second doping type in the high voltage LDMOS device and ohmic contact regions 308b of the second doping type in the medium voltage NMOS device are formed simultaneously; the gate structure 307 in the high voltage LDMOS device and the gate structure 307 in the medium voltage NMOS device are formed simultaneously; the insulating layer 311 in the high voltage LDMOS device and the insulating layer 311 in the medium voltage NMOS device are formed simultaneously; the metal electrode 309 in the high voltage LDMOS device and the metal electrode 309 in the medium voltage NMOS device are formed simultaneously.

In this embodiment, the second buried layer 310 is introduced into the medium-voltage NMOS device 30b, so as to improve the vertical isolation voltage of the medium-voltage NMOS device.

In the medium voltage NMOS device, the high voltage wells 304 are located on two sides of the medium voltage NMOS device and connected to the first buried layer 302, and the low voltage wells 306a of the second doping type in the epitaxial layer 303 are isolated from the first buried layer 302 by the second buried layer 310 and the epitaxial layer 303.

In the medium voltage NMOS device of the present embodiment, the isolation voltage between the drain and the isolation ISO ring whose periphery is composed of the high voltage well 304 depends on the first doping type impurity concentration therebetween, and the larger the concentration, the higher the isolation voltage. Since the medium voltage NMOS device is laterally isolated by the low voltage well 306b having a higher concentration, the isolation voltage between the drain of the medium voltage NMOS device and the isolation ISO ring whose periphery is composed of the high voltage well is mainly dependent on the first doping type impurity concentration between the low voltage well 306a and the first buried layer 302, i.e., the first doping type impurity concentration of the epitaxial layer 303. But epitaxial layer 303 limits the isolation voltage of the medium voltage NMOS device due to the lighter concentration. The introduction of the second buried layer 310 increases the concentration of the first doping type impurity, thereby increasing the isolation voltage between the low-voltage well 306a of the second doping type and the first buried layer 302 through the second buried layer 310, and saving additional lithography level while realizing a fully isolated medium-voltage NMOS device with higher breakdown voltage. Fig. 7a shows a vertical isolation withstand voltage simulation diagram of a medium voltage NMOS device according to a first embodiment of the present application; fig. 7b shows a breakdown voltage simulation diagram of a medium voltage NMOS device according to the first embodiment of the present application; as shown in fig. 7a, due to the introduction of the second buried layer 310, the isolation voltage between the low-voltage well 306a of the second doping type and the first buried layer 302 through the second buried layer 310 reaches 62V, so that the full-isolation medium-voltage NMOS device with higher breakdown voltage is realized, and meanwhile, additional lithography level is saved, and the application range of the medium-voltage NMOS device is enlarged. By introducing the second buried layer 310, the breakdown voltage of the medium voltage NMOS device of the present embodiment can be realized in the range of less than 62 a V a. As shown in fig. 7b, the present embodiment provides a breakdown voltage of 34.2V for a medium voltage NMOS of 20V class.

Referring to fig. 4b and 4e, a buried layer 302 in a medium voltage PMOS device is located on a substrate 301, an epitaxial layer 303 is located on the buried layer 302, the medium voltage PMOS device includes a high voltage well 304 of a second doping type located in the epitaxial layer 303 and the high voltage well 304 is located on the buried layer 302, a low voltage well 306a of the second doping type and a low voltage well 306b of the first doping type located in the high voltage well 304, and a plurality of ohmic contact regions respectively located in the low voltage well 306a of the second doping type and the low voltage well 306b of the first doping type, the plurality of ohmic contact regions including an ohmic contact region 308a of the second doping type and an ohmic contact region 308b of the first doping type, the ohmic contact region 308a being located in the low voltage well 306a of the second doping type and the low voltage well 306a of the first doping type, the ohmic contact region 308a and the ohmic contact region 308b being source and/or drain regions of the medium voltage PMOS device.

The medium voltage PMOS device further includes a field oxide layer 305, a gate structure 307, an insulating layer 311, and a metal electrode 309. A field oxide layer 305 is located over the high voltage wells 304, low voltage wells 306a, and low voltage wells 306 b; gate structure 307 is located on the surfaces of low voltage well 306b, low voltage well 306a and field oxide layer 305; an insulating layer 311 covers the low voltage well 306a, the low voltage well 306b, the ohmic contact regions 308a, 308b, the gate structure 307 and the field oxide layer 305, and a metal electrode 309 is located on the insulating layer 311 and connected to the ohmic contact regions 308a, 308b and the gate structure 307 through the insulating layer 311.

Fig. 8 shows a schematic structural diagram of a high-voltage gate driving circuit according to a second embodiment of the present application; as shown in fig. 8, the high voltage gate driving circuit includes a substrate 301 of a first doping type, a first buried layer 302 of a second doping type, an epitaxial layer 303 of the first doping type, a high voltage LDMOS device 30a, a medium voltage NMOS device 30b, a medium voltage PMOS device 30c, a low voltage CMOS device 30d, and a bipolar NPN device 30e within the epitaxial layer 303, and the high voltage LDMOS device 30a, the medium voltage NMOS device 30b, the medium voltage PMOS device 30c, the low voltage CMOS device 30d, and the bipolar NPN device 30e are separated by a DTI isolation structure S.

In other embodiments, the high voltage gate drive circuit may also include one or more of transistors, resistors, capacitors, and the like.

The various semiconductor devices listed in this embodiment are examples, and the positions and the number thereof may be adjusted accordingly, and are not limiting to the present application. It should be understood by those skilled in the art that the semiconductor device is not limited to the few types of semiconductor devices listed in the present embodiment, but may be other semiconductor devices not mentioned in the present embodiment, and the positional relationship among various semiconductor devices may be adjusted according to the specific structure. The semiconductor device described above may be located in the high-side drive circuit region and/or the low-side drive circuit region. It will be appreciated that although the semiconductor devices in fig. 8 are each separated by a DTI isolation structure S, in other embodiments, the semiconductor devices may be separated by a conventional junction isolation structure or may not be separated.

Fig. 9a to 9j are schematic structural diagrams illustrating various stages in the manufacturing process of the high voltage gate driving circuit according to the first embodiment of the present application, wherein the structure shown in fig. 4b is used for illustration, but not limited thereto.

As shown in fig. 9a, a first buried layer 302 of a second doping type is formed on a substrate 301 of a first doping type.

In this step, a first buried layer 302 is formed on a substrate 301 using photolithography and ion implantation processes, and then the first buried layer 302 is activated by a push junction. In this embodiment, the first buried layer 302 covers a part of the surface of the substrate 301. Wherein the substrate 301 has a first doping type and the first buried layer 302 has a second doping type, and the resistivity of the substrate 301 may be selected according to the breakdown voltage of the device to be formed, e.g. a high voltage LDMOS device.

The first buried layer 302 is used for isolation to reduce latch-up, reduce or block leakage between the individual semiconductor devices. Further, for the high-voltage LDMOS device, the first buried layer 302 is used to reduce the capacitance between the drain and the substrate 301, thereby increasing the switching speed of the high-voltage LDMOS device, but the introduction of the first buried layer 302 may cause the high-voltage LDMOS device to breakdown in advance here, so that a trade-off needs to be made between reducing the capacitance and maintaining the breakdown voltage.

As shown in fig. 9b, an epitaxial layer 303 of a first doping type is formed on a substrate 301 of a first doping type and a first buried layer 302 of a second doping type. The thickness of the epitaxial layer 303 is, for example, 7 μm to 10 μm.

As shown in fig. 9c, a high-voltage well 304 is formed in the epitaxial layer 303 with the first doping type, where the high-voltage well 304 is used for voltage withstanding and isolation of the high-voltage LDMOS device, the doping concentration of the high-voltage well 304 of the high-voltage LDMOS device in the embodiment of the present application is increased to a certain extent compared with that of the conventional Single and Double RESURF structures, so that the specific on-resistance of the high-voltage LDMOS device can be reduced under the same breakdown voltage. In addition, the high-voltage well 304 of the second doping type can be used in the middle-voltage and low-voltage MOS devices to increase the drift region concentration of the NMOS device or decrease the threshold voltage of the PMOS device; and the bipolar transistor can also be used as the base electrode of a lateral PNP device and the collector electrode of a longitudinal NPN device.

As shown in fig. 9d, DTI isolation structures S are formed.

In this step, the epitaxial layer 303 of the first doping type and a portion of the substrate 301 are etched to form an isolation trench S01, and then a dielectric layer S02 is deposited and backfilled to form a DTI isolation structure S. The DTI isolation structure S includes an isolation trench S01, a dielectric layer S02 located on an inner wall of the trench S01, and an air gap S03 inside the dielectric layer S02. The isolation trench S01 extends from the surface of the epitaxial layer 303 to the inside thereof, penetrates the epitaxial layer 303, and extends to the inside of the substrate 301. Dielectric layer S02 is located within isolation trench S01, and an air gap S03 is formed within dielectric layer S02.

The isolation trenches S01 of the DTI isolation structures S may be formed using dry etching, for example, using Reactive Ion Etching (RIE). The width-depth ratio of the isolation trench S01 is controlled at 1: 5-1: 20, and different etch angles may be used to achieve different trench sizes. The dielectric layer S02 is deposited inside the isolation trench S01, and a Low Pressure Chemical Vapor Deposition (LPCVD) or sub-atmospheric chemical vapor deposition (SACVD) process may be used, so as to mainly alleviate the reliability problem caused by the stress of the dielectric layer. After the deposition of the dielectric layer S02, the dielectric layer S02 on the surface of the isolation trench S01 needs to be sealed in advance, so that a certain gap exists in the middle of the dielectric layer S02, and an air gap S03 is formed. The isolation trench S01 is typically 1.0 μm to 3.0 μm in width and 15 μm to 30 μm in depth.

As shown in fig. 9e, the active region is formed by photolithography and etching, the field oxide layer 305 is formed by thermal oxidation, and the field oxide layer 305 is used for device isolation.

As shown in fig. 9f, a second buried layer 310 is formed.

In this step, the second buried layer 310 of the first doping type is formed by high-energy implantation. The second buried layer 310 in the high-voltage LDMOS device and the second buried layer 310 in the medium-voltage NMOS device are formed by the same photomask, i.e., the second buried layer 310 in the high-voltage LDMOS device and the second buried layer 310 in the medium-voltage NMOS device are the same layer. The introduction of the second buried layer 310 increases the concentration of the first doping type impurity in the high-voltage LDMOS device, and improves the isolation voltage between the low-voltage well 306a of the second doping type in the medium-voltage NMOS device and the first buried layer 302 through the second buried layer 310, so that the full-isolation medium-voltage NMOS device with higher breakdown voltage is realized, and meanwhile, additional photolithography level is saved.

As shown in fig. 9g, a low-voltage well 306a of the second doping type and a low-voltage well 306b of the first doping type are formed.

In this step, the low-voltage well 306a of the second doping type and the low-voltage well 306b of the first doping type are formed by high-energy implantation, and the low-voltage well 306a of the second doping type and the low-voltage well 306b of the first doping type are used as well regions of the medium-low voltage device.

As shown in fig. 9h, a gate structure 307 is formed.

In this step, a thin gate oxide layer is grown by thermal oxidation, the thickness of the gate oxide layer is selected according to practical application, and then polysilicon is deposited to form the gate structure 307, and alternatively, polysilicon may be used to form a polysilicon field plate or a capacitor field plate.

As shown in fig. 9i, the implantation activation forms an ohmic contact region 308b of a first doping type and an ohmic contact region 308a of a second doping type, and the ohmic contact region 308b of the first doping type and the ohmic contact region 308a of the second doping type are heavily doped regions, forming ohmic contacts to reduce contact resistance.

As shown in fig. 9j, similar to a common CMOS process, the deposition of an insulating layer, the lithography and etching of a contact hole, the deposition and lithography etching of a first metal layer, the formation of a via between two metal layers, the deposition and lithography etching of a second metal layer, and the formation of a passivation layer are completed, thereby forming a complete high voltage gate driving circuit.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims

1. A high voltage gate drive circuit comprising:

a substrate of a first doping type;

a first buried layer of a second doping type located on the substrate;

an epitaxial layer of a first doping type on the substrate and the first buried layer, the epitaxial layer including a high-side drive circuit region, a low-side drive circuit region, and a level shift circuit region, the level shift circuit region including at least a high-voltage LDMOS device; and

A high-voltage isolation island and an isolation structure, the high-side drive circuit region and the low-side drive circuit region being isolated via the high-voltage isolation island, the level shift circuit region and the high-side drive circuit region being isolated via the isolation structure;

wherein, the isolation structure includes:

an isolation trench extending from a surface of the epitaxial layer to an inside of the substrate;

the dielectric layer is positioned on the inner wall of the isolation groove; and

an air gap located inside the dielectric layer;

the high-voltage LDMOS device comprises:

a high-voltage well of a second doping type located in the epitaxial layer;

a low voltage well of a first doping type located in the high voltage well;

a second buried layer of the first doping type located in the high-voltage well;

a field oxide layer located on the high voltage well and the low voltage well of the first doping type;

an ohmic contact region of a second doping type located in the high voltage well and the low voltage well of the first doping type;

an ohmic contact region of a first doping type located in the low voltage well of the first doping type; and

the grid structure is positioned on the field oxide layer, the high-voltage well and the low-voltage well of the first doping type;

Wherein the second buried layer includes:

a first portion located under and in contact with the low voltage well of the first doping type;

a second portion below the field oxide layer and spaced apart from the field oxide layer; and

and a third portion connecting the first portion and the second portion such that the second buried layer is electrically connected with the low-voltage well of the first doping type.

2. The high voltage gate driving circuit of claim 1, wherein the isolation trench has a width of 1.0 μm to 3.0 μm and a depth of 15 μm to 30 μm, and the isolation trench has a width to depth ratio of 1: 5-1: 20.

3. the high voltage gate drive circuit of claim 1, wherein the high side drive circuit region comprises at least a medium voltage NMOS device and a medium voltage PMOS device, the medium voltage NMOS device comprising:

the substrate of the first doping type;

the first buried layer with the second doping type is positioned on the substrate;

the epitaxial layer with the first doping type is positioned on the first buried layer;

the high-voltage well of the second doping type is positioned in the epitaxial layer, and the high-voltage well in the high-voltage LDMOS device and the high-voltage well in the medium-voltage NMOS device are formed at the same time;

The low-voltage well of the first doping type is positioned in the epitaxial layer, and the low-voltage well of the first doping type in the high-voltage LDMOS device and the low-voltage well of the first doping type in the medium-voltage NMOS device are formed at the same time;

a low voltage well of a second doping type located in the epitaxial layer and the high voltage well;

the second buried layer of the first doping type is positioned below the low-voltage well of the first doping type and the low-voltage well of the second doping type in the epitaxial layer and is in contact with the low-voltage well of the first doping type and the low-voltage well of the second doping type, and the second buried layer in the high-voltage LDMOS device and the second buried layer in the medium-voltage NMOS device are formed at the same time;

a field oxide layer located on the high-voltage well, the low-voltage well of the first doping type, the low-voltage well of the second doping type and the epitaxial layer, wherein the field oxide layer in the high-voltage LDMOS device and the field oxide layer in the medium-voltage NMOS device are formed at the same time;

the ohmic contact region of the first doping type is positioned in the low-voltage well of the first doping type, and the ohmic contact region of the first doping type in the high-voltage LDMOS device and the ohmic contact region of the first doping type in the medium-voltage NMOS device are formed simultaneously;

The ohmic contact region of the second doping type is positioned in the low-voltage well of the first doping type and the low-voltage well of the second doping type, and the ohmic contact region of the second doping type in the high-voltage LDMOS device and the ohmic contact region of the second doping type in the medium-voltage NMOS device are formed at the same time; and

the gate structure is positioned on the field oxide layer, the low-voltage well of the first doping type and the low-voltage well of the second doping type, and the gate structure in the high-voltage LDMOS device and the gate structure in the medium-voltage NMOS device are formed at the same time;

in the medium voltage NMOS device, the high voltage well is positioned at two sides of the medium voltage NMOS device and connected with the first buried layer, and the low voltage well with the second doping type and the first buried layer are isolated through the second buried layer and the epitaxial layer.

4. The high voltage gate driving circuit according to any one of claims 1 to 3, further comprising: one or more of low-voltage NMOS, low-voltage PMOS, triode, resistor and capacitor.

5. A preparation method of a high-voltage gate driving circuit comprises the following steps:

forming a first buried layer of a second doping type on the substrate of the first doping type;

Forming an epitaxial layer of a first doping type on the substrate and the first buried layer, wherein the epitaxial layer comprises a high-side driving circuit region, a low-side driving circuit region and a level shift circuit region;

forming an isolation structure;

forming at least a high-voltage LDMOS device in an epitaxial layer of the level shift circuit area, wherein the level shift circuit area is isolated from the high-side driving circuit area through the isolation structure; and

forming a high-voltage isolation island in the epitaxial layer, the high-side drive circuit region being isolated from the low-side drive circuit region via the high-voltage isolation island;

the method for forming the isolation structure comprises the following steps:

etching the epitaxial layer and part of the substrate to form an isolation trench extending from the surface of the epitaxial layer to the inside of the substrate;

forming a dielectric layer on the inner wall of the isolation trench; and

forming an air gap inside the dielectric layer;

forming a high-voltage well of a second doping type in the epitaxial layer;

forming a low-voltage well of a first doping type in the high-voltage well;

forming a second buried layer of the first doping type in the high-voltage well;

forming a field oxide layer on the high voltage well and the low voltage well of the first doping type in the high voltage well;

Forming an ohmic contact region of a second doping type in the high-voltage well and a low-voltage well of the first doping type in the high-voltage well, and forming an ohmic contact region of the first doping type in the low-voltage well of the first doping type in the high-voltage well; and

forming a gate structure on the field oxide layer, the high voltage well and the low voltage well of the first doping type in the high voltage well;

wherein the second buried layer includes:

6. The method of claim 5, wherein the isolation trench has a width of 1.0-3.0 μm and a depth of 15-30 μm, the isolation trench having a width to depth ratio of 1: 5-1: 20.

7. the method of claim 5, further comprising forming at least a medium voltage NMOS device and a medium voltage PMOS device in an epitaxial layer of the high side drive circuit region, the method of forming the medium voltage NMOS device comprising:

Forming the first buried layer of a second doping type on the substrate of a first doping type;

forming the epitaxial layer of the first doping type on the first buried layer;

forming the high-voltage well with the second doping type in the epitaxial layer, wherein the high-voltage well in the high-voltage LDMOS device and the high-voltage well in the medium-voltage NMOS device are formed at the same time;

forming a low-voltage well of the first doping type in the epitaxial layer of the medium-voltage NMOS device, wherein the low-voltage well of the first doping type in the high-voltage LDMOS device and the low-voltage well of the first doping type in the medium-voltage NMOS device are formed simultaneously;

forming a low-voltage well of a second doping type in the epitaxial layer and the high-voltage well of the medium-voltage NMOS device;

forming the second buried layer of a first doping type in the epitaxial layer of the medium voltage NMOS device, wherein the second buried layer is positioned below the low-voltage well of the first doping type and the low-voltage well of the second doping type in the epitaxial layer and is in contact with the low-voltage well of the first doping type and the low-voltage well of the second doping type, and the second buried layer in the high voltage LDMOS device and the second buried layer in the medium voltage NMOS device are formed simultaneously;

Forming the field oxide layer on the high voltage well in the epitaxial layer, the low voltage well of the first doping type in the epitaxial layer, the low voltage well of the second doping type in the epitaxial layer and the epitaxial layer of the medium voltage NMOS device, wherein the field oxide layer in the high voltage LDMOS device and the field oxide layer in the medium voltage NMOS device are formed simultaneously;

forming an ohmic contact region of the first doping type in the low-voltage well of the first doping type in the epitaxial layer of the medium-voltage NMOS device, wherein the ohmic contact region of the first doping type in the high-voltage LDMOS device and the ohmic contact region of the first doping type in the medium-voltage NMOS device are formed simultaneously;

forming ohmic contact regions of the second doping type in the low-voltage well of the first doping type in the epitaxial layer of the medium-voltage NMOS device and the low-voltage well of the second doping type in the epitaxial layer, wherein the ohmic contact regions of the second doping type in the high-voltage LDMOS device and the ohmic contact regions of the second doping type in the medium-voltage NMOS device are formed simultaneously; and

forming the gate structure on the field oxide layer of the medium voltage NMOS device, the low voltage well of the first doping type in the epitaxial layer, and the low voltage well of the second doping type in the epitaxial layer, wherein the gate structure in the high voltage LDMOS device and the gate structure in the medium voltage NMOS device are formed simultaneously;

8. The method according to any one of claims 5-7, further comprising: one or more devices of low-voltage NMOS, low-voltage PMOS, triode, resistor and capacitor are formed.