JP2001168345A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

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Publication number
JP2001168345A
JP2001168345A JP35387499A JP35387499A JP2001168345A JP 2001168345 A JP2001168345 A JP 2001168345A JP 35387499 A JP35387499 A JP 35387499A JP 35387499 A JP35387499 A JP 35387499A JP 2001168345 A JP2001168345 A JP 2001168345A
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Japan
Prior art keywords
region
type
conductivity type
semiconductor
semiconductor region
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Application number
JP35387499A
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JP3446698B2 (en
Inventor
Masaki Shiraishi
正樹 白石
Mitsuzo Sakamoto
光造 坂本
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having high breakdown strength with a drift region where an n-type region and a p-type region are arranged alternately adjacent to each other. SOLUTION: An n--type region 10 is formed near an area comprising a place immediately below a boundary between a gate oxide film 11 and a second gate oxide film 14a between a drift region and a p-type channel region 3 for relaxing field concentration immediately below a boundary between the gate oxide film 11 and the second gate oxide film 14a and depletion immediately below the gate oxide film 11 is accelerated.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に関す
る。[0001] The present invention relates to a semiconductor device.

【０００２】[0002]

【従来の技術】一般に半導体装置においては、高比抵抗
で厚いドリフト領域を設けることで高耐圧化できるが、
その反面ドリフト領域での電圧降下が大きくなるためオ
ン抵抗が高くなり、耐圧とオン抵抗の間にはトレードオ
フの関係がある。特にパワーMOSFET等のユニポーラデバ
イスについてはシリコンリミットと呼ばれる物理的限界
値があり、ある耐圧におけるオン抵抗の最低値は決まっ
ていて、それ以上オン抵抗を低減することはできないと
されていた。2. Description of the Related Art In general, in a semiconductor device, a high withstand voltage can be achieved by providing a thick drift region having a high specific resistance.
On the other hand, the voltage drop in the drift region becomes large, so that the on-resistance increases, and there is a trade-off relationship between the withstand voltage and the on-resistance. In particular, a unipolar device such as a power MOSFET has a physical limit called a silicon limit, and the minimum value of the on-resistance at a certain withstand voltage is determined, and it is said that the on-resistance cannot be further reduced.

【０００３】これに対して特開平9−266311 号公報に記
載される横型ＳＯＩ（Silicon onInsulator)−MOSFETで
は、ドリフト領域を層状構造，繊維状構造ないし蜂の巣
構造などの並行分割構造とすると共に、第１導電型分割
ドリフト経路域の相隣る同士の側面間（境界）に介在し
てｐｎ接合分離する第２導電型仕切領域を設ける。半導
体装置がオン状態のときは、複数の分割ドリフト経路域
を介して電流が流れるが、他方、オフ状態のときは第１
導電型分割ドリフト経路域と第２導電型仕切領域とのｐ
ｎ接合からそれぞれ空乏層が第１導電型分割ドリフト経
路域内に広がる。一筋の第２導電型仕切領域の両側面か
ら空乏端が側方へ広がるので空乏化が非常に早まる。ま
た第２導電型仕切領域も同時に空乏化される。このた
め、半導体装置は高耐圧となり第１導電型分割ドリフト
経路域の不純物濃度を高めることが可能であるので、オ
ン抵抗の低減を実現できる。On the other hand, in a lateral SOI (Silicon on Insulator) -MOSFET described in Japanese Patent Application Laid-Open No. 9-266311, the drift region has a parallel divisional structure such as a layered structure, a fibrous structure or a honeycomb structure. A second conductivity type partition region is provided between the adjacent side surfaces (boundary) of the one conductivity type split drift path region to separate the pn junction. When the semiconductor device is in an on state, current flows through a plurality of divided drift path regions. On the other hand, when the semiconductor device is in an off state, the first current flows.
P between the conductive type divided drift path region and the second conductive type partition region
A depletion layer extends from the n-junction into the first conductivity type split drift path region. Since the depletion edge spreads laterally from both sides of the single second conductivity type partition region, depletion is greatly accelerated. Further, the second conductivity type partition region is also depleted at the same time. For this reason, the semiconductor device has a high withstand voltage and the impurity concentration in the first conductivity type divided drift path region can be increased, so that the on-resistance can be reduced.

【０００４】このような、ドリフト領域を設けること
で、シリコンリミットを越えてオン抵抗の低いデバイス
を作成することが可能である。By providing such a drift region, a device having a low on-resistance exceeding the silicon limit can be manufactured.

【０００５】[0005]

【発明が解決しようとする課題】上記の横型ＳＯＩ−MO
SFETでは、低オン抵抗化のためにドリフト領域の経路幅
を狭くし、ドリフト領域の不純物濃度を高濃度化する
と、耐圧が低下するという問題がある。The above-mentioned horizontal SOI-MO
The SFET has a problem that the breakdown voltage is reduced when the path width of the drift region is reduced to reduce the on-resistance and the impurity concentration of the drift region is increased.

【０００６】それゆえ、本発明の目的はｎ型領域とｐ型
領域が交互に隣接して配列するドリフト層を持つ高耐圧
・低オン抵抗の半導体装置を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a high breakdown voltage and low on-resistance semiconductor device having a drift layer in which n-type regions and p-type regions are alternately arranged adjacent to each other.

【０００７】[0007]

【課題を解決するための手段】本発明者の検討によれ
ば、ドリフト領域の不純物濃度を高くすると、ゲート絶
縁膜直下で電界が集中するために耐圧が低下する。特
に、ゲート絶縁膜を薄くすると、耐圧の低下が著しい。
このような検討に基づきなされた本発明による半導体装
置においては、半導体層中のゲート絶縁膜直下の一端側
を含むこのゲート絶縁膜の近傍に、ドリフト領域よりも
不純物濃度の低い領域を形成する。これにより、ゲート
酸化膜直下が空乏化しやすくなるので、高耐圧・低オン
抵抗の半導体装置が得られる。According to the study of the present inventors, when the impurity concentration in the drift region is increased, the withstand voltage is reduced because the electric field is concentrated immediately below the gate insulating film. In particular, when the gate insulating film is thin, the withstand voltage is significantly reduced.
In the semiconductor device according to the present invention made based on such a study, a region having a lower impurity concentration than the drift region is formed in the semiconductor layer near one end of the gate insulating film immediately below the gate insulating film. As a result, the portion immediately below the gate oxide film is easily depleted, so that a semiconductor device with a high breakdown voltage and a low on-resistance can be obtained.

【０００８】[0008]

【発明の実施の形態】次に、本発明の実施形態を図面を
参照し説明する。なお、各実施形態においては、ｎ型を
第１導電型とし、ｐ型を第２導電型とするが、本発明は
ｐ型を第１導電型とし、ｎ型を第２導電型とする場合に
も適用でき、同様の効果をもたらす。また図中、同一符
号は同一要素，相当要素を示す。Next, an embodiment of the present invention will be described with reference to the drawings. In each embodiment, the n-type is the first conductivity type and the p-type is the second conductivity type. However, in the present invention, the p-type is the first conductivity type and the n-type is the second conductivity type. The same effect can be obtained. In the drawings, the same reference numerals indicate the same elements and corresponding elements.

【０００９】（実施形態１）図１（ａ）は本発明の実施
形態１を示す横型構造のパワーMOSFETの縦断面図、図１
（ｂ）は図１（ａ）中の点線に沿って切断した場合の横
断面図である。なお以下の記述において、ｎ- ，ｎ，ｎ
+ は半導体領域の導電型がｎ型であり、かつこの順に不
純物濃度が高くなる。ｐ- ，ｐ，ｐ+ についても、この
順に不純物濃度が高く、ｐ型半導体領域であることを示
す。(Embodiment 1) FIG. 1A is a vertical sectional view of a power MOSFET having a horizontal structure according to Embodiment 1 of the present invention.
FIG. 2B is a cross-sectional view taken along a dotted line in FIG. In the following description, n -, n, n
+ Indicates that the conductivity type of the semiconductor region is n-type, and the impurity concentration increases in this order. p -, p, for p + also indicates that this order higher impurity concentration, a p-type semiconductor region.

【００１０】図１（ａ）の構造は、半導体基板９上の絶
縁膜８と、絶縁膜８上に垂直に板状のｎ型領域１（第１
半導体領域）とｐ型領域２（第２半導体領域）が図１
（ｂ）で示すように交互に隣接して配列するドリフト領
域と、ドリフト領域の一端側に形成されたｐ型チャネル
領域３（第３半導体領域）と、ｐ型チャネル領域３中に
形成されたｎ+ 型ソース領域４（第４半導体領域）と、
ｐ型チャネル領域３とｎ+ 型ソース領域４上にゲート酸
化膜１１を介して形成されたフィールドプレート付きゲ
ート電極７及びゲート端子１６と、ｐ型チャネル領域３
中に形成されたｐ+ 型コンタクト領域６と、ｐ+ 型コン
タクト領域６とｎ+ 型ソース領域４上に形成されたソー
ス電極１２及びソース端子１７と、ドリフト領域の他端
側に形成されたｎ+ ドレイン領域５（第６半導体領域）
と、ｎ+ ドレイン領域５上に形成されたドレイン電極１
３及びドレイン端子１８と、ドリフト領域上に形成され
たゲート酸化膜１１よりも厚い絶縁膜１４と、ｐ型チャ
ネル領域３とドリフト領域との間に形成されたｎ- 型領
域１０（第５半導体領域の第１導電型の領域）とを有す
る。ｎ- 型領域１０は、ドリフト領域におけるｎ型領域
１及びｐ型領域の不純物濃度よりも低不純物濃度であ
る。ここで、ゲート電極７直下の厚い絶縁膜１４の部分
を第２ゲート酸化膜１４ａと称することとする。The structure shown in FIG. 1A includes an insulating film 8 on a semiconductor substrate 9 and a plate-shaped n-type region 1 (first
FIG. 1 shows a semiconductor region) and a p-type region 2 (second semiconductor region).
As shown in (b), drift regions alternately arranged adjacently, a p-type channel region 3 (third semiconductor region) formed on one end side of the drift region, and a drift region formed in the p-type channel region 3. an n + type source region 4 (fourth semiconductor region);
a gate electrode 7 with a field plate and a gate terminal 16 formed on the p-type channel region 3 and the n + -type source region 4 via the gate oxide film 11;
The p + -type contact region 6 formed therein, the source electrode 12 and the source terminal 17 formed on the p + -type contact region 6 and the n + -type source region 4, and the other end side of the drift region n + drain region 5 (sixth semiconductor region)
And drain electrode 1 formed on n + drain region 5
3 and a drain terminal 18, an insulating film 14 thicker than the gate oxide film 11 formed on the drift region, and an n − -type region 10 (fifth semiconductor) formed between the p-type channel region 3 and the drift region. Region of the first conductivity type). The n − -type region 10 has a lower impurity concentration than the impurity concentrations of the n-type region 1 and the p-type region in the drift region. Here, the portion of the thick insulating film 14 immediately below the gate electrode 7 is referred to as a second gate oxide film 14a.

【００１１】本実施形態１のパワーMOSFETにおいて、オ
フ状態でドレイン端子１８に正の電圧を印加すると、絶
縁膜８上の板状のｎ型領域１とｐ型領域２のｐｎ接合面
から、ドリフト領域に電流経路と垂直の方向に空乏層が
広がるために、ｎ型領域１及びｐ型領域２は空乏化され
やすくなる。このため、ｎ型領域１の不純物濃度を従来
のパワーMOSFETに比べて高めても、ｎ型領域１とｐ型領
域２の間の電界がシリコンの臨界電界に到達する前にｎ
型領域１及びｐ型領域２が空乏化するように、ｎ型領域
１及びｐ型領域２の幅を十分狭くすることで高耐圧を保
つことができる。一方オン状態では、従来のパワーMOSF
ETに比べて不純物濃度が高いｎ型領域１を電流が流れる
ために、従来に比べオン抵抗を低減することができる。
例えば、ドレイン耐圧が６００Ｖ程度のパワーMOSFETを
考えると、オン抵抗を従来の１／５程度にまで低減する
ことができる。In the power MOSFET of the first embodiment, when a positive voltage is applied to the drain terminal 18 in the off state, the drift from the pn junction between the plate-like n-type region 1 and the p-type region 2 on the insulating film 8 Since the depletion layer spreads in the region in a direction perpendicular to the current path, the n-type region 1 and the p-type region 2 are easily depleted. For this reason, even if the impurity concentration of the n-type region 1 is increased as compared with the conventional power MOSFET, the electric field between the n-type region 1 and the p-type region 2 becomes n before the electric field reaches the critical electric field of silicon.
High breakdown voltage can be maintained by sufficiently narrowing the widths of the n-type region 1 and the p-type region 2 so that the type region 1 and the p-type region 2 are depleted. On the other hand, in the ON state, the conventional power MOSF
Since current flows through the n-type region 1 having a higher impurity concentration than ET, the on-resistance can be reduced as compared with the conventional case.
For example, when a power MOSFET having a drain withstand voltage of about 600 V is considered, the on-resistance can be reduced to about 1/5 of the conventional one.

【００１２】ここで、ｎ型領域１及びｐ型領域２の幅を
狭くし不純物濃度を高めると、ゲート酸化膜１１と第２
ゲート酸化膜１４ａの境界直下で電界が集中し、アバラ
ンシェ降伏しやすくなる。これは、ｎ型領域１とｐ型領
域２の不純物濃度が高くなり空乏層が広がりにくくなる
ためである。また、ゲート酸化膜１１が薄くなると電界
集中はさらに強くなり、高耐圧化が難しくなる。そこ
で、本実施形態１ではｐ型チャネル領域３とｎ型領域１
及びｐ型領域２の間で、ゲート酸化膜１１と第２ゲート
酸化膜１４ａの境界直下を含むこれら酸化膜の近傍にｎ
- 型領域１０を挿入した構造になっている。Here, when the width of the n-type region 1 and the p-type region 2 is reduced and the impurity concentration is increased, the gate oxide film 11 and the second
The electric field is concentrated just below the boundary of the gate oxide film 14a, and avalanche breakdown is likely to occur. This is because the impurity concentration of the n-type region 1 and the p-type region 2 becomes high, and the depletion layer becomes difficult to spread. Further, when the gate oxide film 11 becomes thinner, the electric field concentration becomes stronger, and it becomes difficult to increase the breakdown voltage. Therefore, in the first embodiment, the p-type channel region 3 and the n-type region 1
Between the gate oxide film 11 and the second gate oxide film 14a between the gate oxide film 11 and the second gate oxide film 14a.
- it has -type region 10 to the inserted structure.

【００１３】ｎ- 型領域１０はドレイン端子１８に正の
電圧が印加されるとｐ型チャネル領域３より空乏層が広
がり、ｎ型領域１及びｐ型領域２が空乏化される電圧よ
り低い電圧で完全空乏化し、ゲート酸化膜１１と第２ゲ
ート酸化膜１４ａの境界直下での電界集中を緩和しアバ
ランシェ降伏を避け、高耐圧で低オン抵抗のパワーMOSF
ETを実現できる。また、ゲート下の空乏層が早く広がる
ので、ゲート―ドレイン間の容量が小さくなる効果もあ
る。When a positive voltage is applied to the drain terminal 18, the depletion layer of the n − type region 10 expands more than the p-type channel region 3, and a voltage lower than the voltage at which the n-type region 1 and the p-type region 2 are depleted. To completely deplete the electric field, reduce the electric field concentration just below the boundary between the gate oxide film 11 and the second gate oxide film 14a, avoid avalanche breakdown, and provide a high breakdown voltage and low on-resistance power MOSF.
ET can be realized. Further, since the depletion layer below the gate spreads quickly, there is also an effect that the capacitance between the gate and the drain is reduced.

【００１４】次に、本実施形態１のパワーMOSFETの製造
方法の一例について図２(ａ)〜(ｆ)を参照して説明す
る。図２（ａ)〜(ｆ）はそれぞれ、パワーMOSFETの縦断
面図を示す。Next, an example of a method of manufacturing the power MOSFET according to the first embodiment will be described with reference to FIGS. FIGS. 2A to 2F respectively show longitudinal sectional views of the power MOSFET.

【００１５】図２（ａ）で示すように半導体基板９と絶
縁膜８で誘電体分離されたｎ- 層１０に、図２（ｂ）の
ように、イオン打ち込みと拡散でｎ+ ドレイン領域５を
形成する。次に、図２（ｃ）に示すように、フォトリソ
グラフィーとイオン打ち込み、拡散によってｎ型領域１
及びｐ型領域２を形成する。The semiconductor substrate 9 and the insulating film 8 n is dielectric isolation in as shown in Figure 2 (a) - the layer 10, as shown in FIG. 2 (b), n + drain region 5 by ion implantation and diffusion To form Next, as shown in FIG. 2C, the n-type region 1 is formed by photolithography, ion implantation, and diffusion.
And a p-type region 2 are formed.

【００１６】このような、互いに隣接した板状のｎ型領
域１及びｐ型領域２を作製するためには例えば、間隔が
１μｍのホトマスクを用いて約８×１０12／cm-2のリン
をイオン打ち込みした後１１００℃で３０分拡散する。
その後間隔が１μｍのホトマスクを用いて約８×１０12
／cm-2のボロンをイオン打ち込みした後１１００℃で６
０分拡散すると、ｎ型領域１，ｐ型領域２の幅がそれぞ
れ１μｍで厚さが1.5μｍの板状の層を形成することが
できる。In order to form such a plate-shaped n-type region 1 and p-type region 2 adjacent to each other, for example, phosphorous of about 8 × 10 12 / cm −2 is formed using a photomask having a spacing of 1 μm. After ion implantation, diffuse at 1100 ° C. for 30 minutes.
Thereafter, about 8 × 10 12 using a photomask with an interval of 1 μm.
/ Cm -2 boron at 1100 ° C after ion implantation
When the diffusion is performed for 0 minutes, a plate-like layer having the width of each of the n-type region 1 and the p-type region 2 of 1 μm and the thickness of 1.5 μm can be formed.

【００１７】次に図２（ｄ）のようにゲート酸化膜１１
及び厚い絶縁膜１４を形成し、その上にポリシリコンの
フィールドプレート付きゲート電極７を形成し、図２
（ｅ）のように、このポリシリコンのゲート電極７をマ
スクにしてｐ型チャネル領域３とｎ+ 型ソース領域４を
イオン打ち込みと拡散により自己整合で形成する。次に
図２（ｆ）のように、ｐ型コンタクト領域６を形成し、
ソース電極１２及びドレイン電極１３を形成する。この
とき、ｎ- 層領域１０をｐ型チャネル領域３とｎ型領域
１及びｐ型領域２の間に、ゲート酸化膜１１と第２ゲー
ト絶縁膜１４ａの境界直下を含む近傍に残すことで、ｎ
- 型領域１０をイオン打ち込み等の工程を踏まずに作成
することができ、プロセス工程数およびコストを削減で
きる。Next, as shown in FIG. 2D, the gate oxide film 11 is formed.
Then, a gate electrode 7 with a polysilicon field plate is formed thereon.
As shown in (e), the p-type channel region 3 and the n + -type source region 4 are formed in a self-aligned manner by ion implantation and diffusion using the polysilicon gate electrode 7 as a mask. Next, a p-type contact region 6 is formed as shown in FIG.
A source electrode 12 and a drain electrode 13 are formed. At this time, the n − layer region 10 is left between the p-type channel region 3 and the n-type region 1 and the p-type region 2 in the vicinity including immediately below the boundary between the gate oxide film 11 and the second gate insulating film 14a. n
- type region 10 can be created without going through steps such as ion implantation, can be reduced number of process steps and cost.

【００１８】（実施形態２）図３は本発明の実施形態２
を示す横型構造のパワーMOSFETの縦断面図である。本実
施形態２のパワーMOSFETの構造は、ドリフト領域以外の
構造については実施形態１と同じ構造である。すなわち
実施形態２のドリフト領域は、絶縁膜８の上に平行に板
状のｎ型領域１とｐ型領域２が、積み重なっている。(Embodiment 2) FIG. 3 shows Embodiment 2 of the present invention.
FIG. 2 is a vertical cross-sectional view of a power MOSFET having a horizontal structure shown in FIG. The structure of the power MOSFET of the second embodiment is the same as that of the first embodiment except for the structure other than the drift region. That is, in the drift region of the second embodiment, the plate-shaped n-type region 1 and the p-type region 2 are stacked in parallel on the insulating film 8.

【００１９】本実施形態２のパワーMOSFETにおいては、
オフ状態でドレイン端子１８に正の電圧を印加すると、
層状に積み重なったｎ型領域１とｐ型領域２の接合面か
ら縦方向に空乏層が広がるので、実施形態１の場合と同
様にｎ型領域１及びｐ型領域２は早く空乏化され、ｎ型
領域１，ｐ型領域２の不純物濃度を高めることができ、
高耐圧で低オン抵抗のパワーMOSFETを実現できる。In the power MOSFET according to the second embodiment,
When a positive voltage is applied to the drain terminal 18 in the off state,
Since the depletion layer extends in the vertical direction from the junction between the n-type region 1 and the p-type region 2 stacked in layers, the n-type region 1 and the p-type region 2 are depleted quickly as in the case of the first embodiment. The impurity concentration of the p-type region 1 and the p-type region 2 can be increased,
A power MOSFET with high withstand voltage and low on-resistance can be realized.

【００２０】本実施形態２においても、ゲート酸化膜１
１と第２ゲート酸化膜１４ａの境界直下で電界が集中し
アバランシェ降伏しやすいので、電界緩和のためにゲー
ト酸化膜１１と第２ゲート酸化膜１４ａの境界直下を含
む近傍にｎ- 型領域１０を挿入した構造をしている。Also in the second embodiment, the gate oxide film 1
Since the electric field is concentrated just below the boundary between the first and second gate oxide films 14a and avalanche breakdown is likely to occur, the n − -type region 10 is formed in the vicinity including immediately below the boundary between the gate oxide film 11 and the second gate oxide film 14a in order to alleviate the electric field. The structure is inserted.

【００２１】次に、本実施形態２のパワーMOSFETの製造
方法の一例について図５(ａ)〜(ｄ)を参照して説明す
る。図５（ａ)〜(ｄ）はそれぞれ、パワーMOSFETの縦断
面図を示す。Next, an example of a method for manufacturing the power MOSFET according to the second embodiment will be described with reference to FIGS. FIGS. 5A to 5D are vertical sectional views of the power MOSFET, respectively.

【００２２】図５（ａ）で示すように半導体基板９と絶
縁膜８で誘電体分離されたｎ- 層１０に、図５（ｂ）の
ように、イオン打ち込みと拡散でｎ+ ドレイン領域５を
形成し、図５（ｃ）に示すようにフォトリソグラフィー
とイオン打ち込み、拡散によりｐ型不純物領域２を形成
する。次に図５（ｄ）のようにフォトリソグラフィーと
イオン打ち込み、拡散によってｐ型領域２の上にｎ型領
域１を形成し、板状のｎ型領域１とｐ型領域２が積み重
なったドリフト領域を作製する。この後、実施形態１
（図２（ｄ)〜(ｆ））と同様に、ゲート酸化膜１１及び
厚い絶縁膜１４，フィールドプレート付きゲート電極７
を形成し、ｐ型チャネル領域３及びｎ型ソース領域４，
ｐ型コンタクト領域６を作製し、ソース電極１２及びド
レイン電極１３を形成する。FIG. 5 n is dielectric isolation in a semiconductor substrate 9 and the insulating film 8 as shown in (a) - the layer 10, FIG. 5 as shown in (b), n + drain region 5 by ion implantation and diffusion Is formed, and a p-type impurity region 2 is formed by photolithography and ion implantation and diffusion as shown in FIG. Next, as shown in FIG. 5D, an n-type region 1 is formed on the p-type region 2 by photolithography and ion implantation and diffusion, and a drift region in which the plate-like n-type region 1 and the p-type region 2 are stacked. Is prepared. Thereafter, the first embodiment
2 (d) to 2 (f), the gate oxide film 11, the thick insulating film 14, and the gate electrode 7 with the field plate.
Are formed, and the p-type channel region 3 and the n-type source region 4,
A p-type contact region 6 is formed, and a source electrode 12 and a drain electrode 13 are formed.

【００２３】図４は本実施形態２の変形例を示す別の構
造であり、ｎ型領域１とｐ型領域２が２対ある多層構造
の横型パワーMOSFETの縦断面図を示す。図４では、ｎ型
領域１とｐ型領域２が２対ある構造を示しているが対の
数が増えても良い。FIG. 4 is a vertical cross-sectional view of a multi-layered horizontal power MOSFET having two pairs of an n-type region 1 and a p-type region 2, which is another structure showing a modification of the second embodiment. FIG. 4 shows a structure having two pairs of the n-type region 1 and the p-type region 2, but the number of pairs may be increased.

【００２４】図４のようなｎ型領域１及びｐ型領域２の
層の幅が狭い多層構造は、MOCVD 法（有機金属化学堆積
法）やＭＢＥ法（分子線結晶成長法）といった薄膜を形
成するのに適した結晶成長方法を用いると、比較的容易
に作製することができる。また、このようなｎ型領域
１，ｐ型領域２では層の幅が薄い分だけ高濃度にするこ
とができるので、オン抵抗が低くなる。As shown in FIG. 4, a multilayer structure in which the layers of the n-type region 1 and the p-type region 2 are narrow forms a thin film such as MOCVD (metal organic chemical deposition) or MBE (molecular beam crystal growth). By using a crystal growth method suitable for such a method, it can be relatively easily manufactured. Further, in such an n-type region 1 and a p-type region 2, the high concentration can be achieved by the thinner layer width, so that the on-resistance is reduced.

【００２５】本実施形態２のパワーMOSFETは、実施形態
１と同様に高耐圧で低オン抵抗、低容量の効果がある。
また、ｎ型領域１及びｐ型領域２の層幅を狭くし多層構
造にすることで、よりオン抵抗が低くなる。The power MOSFET according to the second embodiment has the effects of a high withstand voltage, a low on-resistance, and a low capacitance as in the first embodiment.
Further, by reducing the layer width of the n-type region 1 and the p-type region 2 to form a multilayer structure, the on-resistance is further reduced.

【００２６】（実施形態３）図６は本発明の実施形態３
を示す横型パワーMOSFETの縦断面図である。(Embodiment 3) FIG. 6 shows Embodiment 3 of the present invention.
FIG. 2 is a vertical cross-sectional view of a horizontal power MOSFET showing the above.

【００２７】本実施形態３のパワーMOSFETは、実施形態
１のパワーMOSFETにおいて、ゲート酸化膜１１と第２ゲ
ート酸化膜１４ａの境界直下での電界集中を緩和するた
めに設けたｎ- 型領域１０の下部に、ｐ- 型領域１５
（第５半導体領域の第２導電型の領域）を形成してい
る。The power MOSFET according to the third embodiment is different from the power MOSFET according to the first embodiment in that the n − -type region 10 is provided for alleviating the electric field concentration just below the boundary between the gate oxide film 11 and the second gate oxide film 14a. Below the p - type region 15
(A region of the second conductivity type of the fifth semiconductor region).

【００２８】本実施形態３においてはｐ- 型領域１５が
挿入されているので、ｎ- 型領域１０はｐ型チャネル領
域３及びｐ- 型領域１５の両方から空乏層が広がり、低
いドレイン電圧で空乏化される。ｎ- 型領域１０が早く
空乏化されれば、ゲート酸化膜１１と第２ゲート酸化膜
１４ａの境界直下での電界集中が緩和されるので、ｎ型
領域１及びｐ型領域２の不純物濃度を高めることがで
き、さらにオン抵抗が低くなる。In the third embodiment, since the p − -type region 15 is inserted, the n − -type region 10 has a depletion layer extending from both the p-type channel region 3 and the p − -type region 15 and has a low drain voltage. Depleted. If the n − -type region 10 is depleted quickly, the electric field concentration immediately below the boundary between the gate oxide film 11 and the second gate oxide film 14a is reduced, so that the impurity concentrations of the n-type region 1 and the p-type region 2 are reduced. The ON resistance can be further reduced.

【００２９】次に、本実施形態３のパワーMOSFETの製造
方法の一例について図７(ａ)〜(ｄ)を参照して説明す
る。図７（ａ)〜(ｄ）はそれぞれ、パワーMOSFETの縦断
面図を示す。Next, an example of a method of manufacturing the power MOSFET according to the third embodiment will be described with reference to FIGS. FIGS. 7A to 7D are vertical sectional views of the power MOSFET, respectively.

【００３０】図７（ａ）で示すように半導体基板９と絶
縁膜８で誘電体分離されたｐ- 層１５に、図７（ｂ）の
ように、イオン打ち込みと拡散でｎ+ ドレイン領域５を
形成し、図７（ｃ）に示すようにフォトリソグラフィー
とイオン打ち込み、拡散によってｎ型領域１及びｐ型領
域２を形成する。このｎ型領域１とｐ型領域２は実施形
態１と同じプロセス条件を用いて形成する。次に図７
（ｄ）で示すように、ｎ型不純物をイオン打ち込みしｐ
- 型領域１５の表面層にｎ- 型領域１０を形成する。こ
の後、実施形態１と同様に、ゲート酸化膜１１及び厚い
絶縁膜１４，フィールドプレート付きゲート電極７を形
成し、ｐ型チャネル領域３及びｎ型ソース領域４，ｐ型
コンタクト領域６を作製し、ソース電極１２及びドレイ
ン電極１３を形成する。As shown in FIG. 7A, an n + drain region 5 is formed by ion implantation and diffusion in the p − layer 15 which is dielectrically separated by the semiconductor substrate 9 and the insulating film 8 as shown in FIG. 7B. Then, as shown in FIG. 7C, an n-type region 1 and a p-type region 2 are formed by photolithography and ion implantation and diffusion. The n-type region 1 and the p-type region 2 are formed using the same process conditions as in the first embodiment. Next, FIG.
As shown in (d), ion implantation of an n-type impurity
The n − -type region 10 is formed on the surface layer of the −-type region 15. Thereafter, as in the first embodiment, a gate oxide film 11, a thick insulating film 14, a gate electrode 7 with a field plate are formed, and a p-type channel region 3, an n-type source region 4, and a p-type contact region 6 are formed. , A source electrode 12 and a drain electrode 13 are formed.

【００３１】本実施形態３のパワーMOSFETは実施形態１
と同様に高耐圧で低容量を実現すると共に、オン抵抗を
低減できるという効果がある。The power MOSFET according to the third embodiment is similar to the power MOSFET according to the first embodiment.
Similarly to the above, there is an effect that a high withstand voltage and a low capacitance can be realized and the on-resistance can be reduced.

【００３２】（実施形態４）図８は本発明の実施形態４
を示す横型パワーMOSFETの縦断面図である。(Embodiment 4) FIG. 8 shows Embodiment 4 of the present invention.
FIG. 2 is a vertical cross-sectional view of a horizontal power MOSFET showing the above.

【００３３】本実施形態４のパワーMOSFETは、実施形態
２のパワーMOSFETにおいて、ｐ型領域２がｐ型チャネル
領域３まで伸びて接している。The power MOSFET according to the fourth embodiment is different from the power MOSFET according to the second embodiment in that the p-type region 2 extends to and contacts the p-type channel region 3.

【００３４】本実施形態４においてはｐ型領域２がｐ型
チャネル領域３まで伸びているので、ｎ- 型領域１０は
ｐ型領域２及びｐ型チャネル領域３の両方から空乏層が
広がり、実施形態３の場合と同様に低いドレイン電圧で
空乏化され、オン抵抗が低くなる。In the fourth embodiment, since the p-type region 2 extends to the p-type channel region 3, the depletion layer of the n − -type region 10 extends from both the p-type region 2 and the p-type channel region 3. As in the case of the third embodiment, depletion occurs at a low drain voltage, and the on-resistance decreases.

【００３５】次に、本実施形態４のパワーMOSFETの製造
方法の一例について図９(ａ)〜(ｄ)を参照して説明す
る。図９（ａ)〜(ｄ）はそれぞれ、パワーMOSFETの縦断
面図を示す。Next, an example of a method of manufacturing the power MOSFET according to the fourth embodiment will be described with reference to FIGS. FIGS. 9A to 9D are longitudinal sectional views of the power MOSFET, respectively.

【００３６】図９（ａ）で示すような半導体基板９と絶
縁膜８で誘電体分離されたｐ層上に、図９（ｂ）のよう
にｎ- 層１０をエピタキシャル成長し、図９（ｃ）に示
すようにｎ型不純物をイオン打ち込みすることにより、
ｎ- 層１０中にｎ型領域１を形成する。この後、実施形
態１〜３と同様に、ゲート酸化膜１１及び厚い絶縁膜１
４，フィールドプレート付きゲート電極７を形成し、ｐ
型チャネル領域３及びｎ型ソース領域４，ｐ型コンタク
ト領域６を作製し、ソース電極１２及びドレイン電極１
３を形成する。An n − layer 10 is epitaxially grown on a semiconductor substrate 9 and a p layer dielectrically separated by an insulating film 8 as shown in FIG. 9A, as shown in FIG. By implanting an n-type impurity as shown in FIG.
N-type region 1 is formed in n − layer 10. Thereafter, similarly to the first to third embodiments, the gate oxide film 11 and the thick insulating film 1 are formed.
4, forming a gate electrode 7 with a field plate;
A channel region 3 and an n-type source region 4 and a p-type contact region 6 are formed, and a source electrode 12 and a drain electrode 1 are formed.
Form 3

【００３７】本実施形態４のパワーMOSFETは実施形態１
と同様の効果がある。The power MOSFET according to the fourth embodiment is similar to the power MOSFET according to the first embodiment.
Has the same effect as.

【００３８】（実施形態５）図１０は本発明の実施形態
５を示す横型パワーMOSFETの縦断面図である。(Embodiment 5) FIG. 10 is a longitudinal sectional view of a horizontal power MOSFET showing Embodiment 5 of the present invention.

【００３９】本実施形態５のパワーMOSFETは、実施形態
１のパワーMOSFETにおいて、ゲート酸化膜１１と第２ゲ
ート酸化膜１４ａの境界直下での電界集中を緩和するた
めに設けたｎ- 型領域１０の内部に、部分的にｐ- 型領
域１５を形成している。すなわちゲート直下のｎ- 型領
域１０の一部の下にｐ- 型領域１５が位置し、さらにｐ
- 型領域１５の下にｎ- 型領域１０の他の一部が位置す
る。The power MOSFET according to the fifth embodiment is different from the power MOSFET according to the first embodiment in that the n − -type region 10 is provided to reduce the electric field concentration just below the boundary between the gate oxide film 11 and the second gate oxide film 14a. , The p − type region 15 is partially formed. That is, the p − type region 15 is located under a part of the n − type region 10 immediately below the gate,
Another part of the n − type region 10 is located below the − type region 15.

【００４０】本実施形態５においてはｐ- 型領域１５が
挿入されているので、ｎ- 型領域１０はｐ型チャネル領
域３及びｐ- 型領域１５の両方から空乏層が広がり、実
施形態３，４の場合と同様に低いドレイン電圧で空乏化
され、オン抵抗が低くなる。In the fifth embodiment, since the p − type region 15 is inserted, the depletion layer of the n − type region 10 extends from both the p type channel region 3 and the p − type region 15, As in the case of No. 4, depletion occurs at a low drain voltage, and the on-resistance decreases.

【００４１】本実施形態５の構造を作製するには、実施
形態１の図２（ｃ）の工程の後に、図７（ｄ）と同じホ
トマスクを用いて、ｐ型不純物を高エネルギーでイオン
打ち込みすることにより、ｎ- 型領域１０の下部に部分
的にｐ- 型領域１５を形成することができる。本実施形
態５の場合は、実施形態１の製造工程にイオン打ち込み
を加えるだけで作製できるので、簡略なプロセスで実施
形態３及び４と同等の効果を得ることができる。In order to fabricate the structure of the fifth embodiment, after the step of FIG. 2C of the first embodiment, a p-type impurity is ion-implanted with high energy using the same photomask as that of FIG. 7D. By doing so, p − type region 15 can be formed partially below n − type region 10. In the case of the fifth embodiment, since it can be manufactured only by adding ion implantation to the manufacturing process of the first embodiment, the same effects as those of the third and fourth embodiments can be obtained by a simple process.

【００４２】本実施形態５のパワーMOSFETは実施形態１
と同様に高耐圧で低容量を実現すると共に、オン抵抗を
さらに低減できるという効果がある。The power MOSFET according to the fifth embodiment is similar to the power MOSFET according to the first embodiment.
In the same manner as described above, there is an effect that a high withstand voltage and a low capacitance can be realized and the on-resistance can be further reduced.

【００４３】（実施形態６）図１１（ａ）は本発明の実
施形態６を示す横型パワーMOSFETの縦断面図、図１１
（ｂ）は図１１（ａ）において点線に沿って切断した場
合の横断面図である。(Embodiment 6) FIG. 11A is a longitudinal sectional view of a lateral power MOSFET showing Embodiment 6 of the present invention.
FIG. 12B is a cross-sectional view taken along a dotted line in FIG.

【００４４】本実施形態６のパワーMOSFETは、実施形態
１のパワーMOSFETにおいて、ゲート酸化膜１１と第２ゲ
ート酸化膜１４ａの境界直下の電界集中を緩和するため
に設けたｎ- 型領域１０のうち、図１１（ｂ）のように
ｐ型領域２に接する部分をｐ- 型領域１５に置き換え
る。The power MOSFET according to the sixth embodiment is different from the power MOSFET according to the first embodiment in that an n − -type region 10 provided for alleviating the electric field concentration immediately below the boundary between the gate oxide film 11 and the second gate oxide film 14a. Of these, the portion in contact with the p-type region 2 is replaced with the p − -type region 15 as shown in FIG.

【００４５】本実施形態６のパワーMOSFETにおいて、オ
フ状態でドレイン端子１８に正の電圧を印加すると、ｎ
型領域１とｐ型領域２の接合面から経路幅方向に空乏層
が広がると同時に、ｎ- 型領域１０とｐ- 型領域１５の
接合面からも経路幅方向に空乏層が広がる。ここで、ｎ
- 型領域１０及びｐ- 型領域１５はそれぞれｎ型領域１
及びｐ型領域２に比べて不純物濃度が少ないので、空乏
層は早く広がる。また、ｎ- 型領域１０はｐ- 型領域１
５に挟まれているので、空乏層は両側から広がり、低い
ドレイン電圧でｎ- 型領域１０を空乏化することができ
るため、さらに低オン抵抗が実現できるという効果があ
る。In the power MOSFET according to the sixth embodiment, when a positive voltage is applied to the drain terminal 18 in the off state, n
A depletion layer spreads in the path width direction from the junction between the p-type region 1 and the p-type region 2, and at the same time, a depletion layer spreads in the path width direction from the junction between the n - type region 10 and the p - type region 15. Where n
- -type region 10 and the p - type region 15, respectively n-type region 1
Since the impurity concentration is lower than that of the p-type region 2, the depletion layer spreads quickly. The n − type region 10 is a p − type region 1
5, the depletion layer spreads from both sides, and the n − -type region 10 can be depleted with a low drain voltage, so that there is an effect that a further lower on-resistance can be realized.

【００４６】本実施形態６の構造を作製するには、実施
形態１の図２（ｃ）の工程の後に、ホトマスクを用いて
ｐ型不純物をイオン打ち込みすることにより、ｎ- 型領
域１０中にｐ- 型領域１５を形成する。本実施形態６
は、実施形態５の場合と同様に、実施形態１の製造工程
にイオン打ち込みを加えるだけの簡易なプロセスで作製
できる。[0046] To produce the structure according to Embodiment 6, after the step of FIG. 2 embodiment 1 (c), by ion implantation of p-type impurity using a photomask, n - during -type region 10 A p - type region 15 is formed. Embodiment 6
As in the case of the fifth embodiment, can be manufactured by a simple process that only adds ion implantation to the manufacturing process of the first embodiment.

【００４７】（実施形態７）図１２（ａ）は本発明の実
施形態７を示す横型パワーMOSFETの縦断面図、図１２
（ｂ）は図１２（ａ）において点線に沿って切断した場
合の横断面図である。(Embodiment 7) FIG. 12A is a longitudinal sectional view of a lateral power MOSFET showing Embodiment 7 of the present invention.
FIG. 12B is a transverse sectional view when cut along a dotted line in FIG.

【００４８】本実施形態７のパワーMOSFETは、実施形態
１のパワーMOSFETにおいて、ゲート酸化膜１１と第２ゲ
ート酸化膜１４ａの境界直下での電界集中を緩和するた
めに、図１２（ｂ）のようにゲート酸化膜１１下のｎ型
領域１の幅をｐ型領域２の幅よりも狭める。The power MOSFET according to the seventh embodiment differs from the power MOSFET according to the first embodiment in that the electric field concentration just below the boundary between the gate oxide film 11 and the second gate oxide film 14a is reduced as shown in FIG. Thus, the width of n-type region 1 under gate oxide film 11 is made smaller than the width of p-type region 2.

【００４９】本実施形態７のパワーMOSFETにおいてオフ
状態でドレイン端子１８に正の電圧を印加すると、実施
形態１と同様にｎ型領域１とｐ型領域２の接合面からド
リフト領域に電流経路と垂直の方向に空乏層が広がる
が、本実施形態７の構造では、ゲート酸化膜１１および
第２ゲート酸化膜１４ａ直下でのｎ型領域１の経路幅は
実施形態１に比べて狭くなっているので、低いドレイン
電圧でゲート酸化膜１１及び第２ゲート酸化膜１４直下
のｎ型領域１を空乏化することができる。そのため、オ
ン抵抗を低減できる。When a positive voltage is applied to the drain terminal 18 in the power MOSFET of the seventh embodiment in the off state, a current path from the junction between the n-type region 1 and the p-type region 2 to the drift region is formed as in the first embodiment. Although the depletion layer expands in the vertical direction, in the structure of the seventh embodiment, the path width of the n-type region 1 immediately below the gate oxide film 11 and the second gate oxide film 14a is smaller than that of the first embodiment. Therefore, the n-type region 1 immediately below the gate oxide film 11 and the second gate oxide film 14 can be depleted at a low drain voltage. Therefore, the on-resistance can be reduced.

【００５０】次に、本実施形態７のパワーMOSFETの製造
方法の一例について図１３(ａ）〜(ｃ)を参照して説明
する。図１３（ａ)〜(ｃ）はそれぞれ、パワーMOSFETの
縦断面図を示す。Next, an example of a method of manufacturing the power MOSFET according to the seventh embodiment will be described with reference to FIGS. FIGS. 13A to 13C are vertical sectional views of the power MOSFET, respectively.

【００５１】図１３（ａ）で示すような半導体基板９と
絶縁膜８で誘電体分離されたｐ層に、図１３（ｂ）のよ
うに、イオン打ち込みと拡散でｎ+ ドレイン領域５を形
成し、図１３（ｃ）に示すようにｎ型不純物のイオン打
ち込みと拡散によってｎ型領域１及びｐ型領域２を形成
する。この後、実施形態１と同様に、ゲート酸化膜１１
及び厚い絶縁膜１４，フィールドプレート付きゲート電
極７を形成し、ｐ型チャネル領域３及びｎ型ソース領域
４，ｐ型コンタクト領域６を作製し、ソース電極１２及
びドレイン電極１３を形成する。本実施形態７では、ゲ
ート酸化膜１１と第２ゲート酸化膜１４ａの境界直下で
の電界の集中を緩和するために、ｎ- 型領域１０を形成
する必要がないので、プロセス工程数及びコストが低減
される。As shown in FIG. 13B, an n + drain region 5 is formed by ion implantation and diffusion in a p-layer dielectrically separated by a semiconductor substrate 9 and an insulating film 8 as shown in FIG. Then, as shown in FIG. 13C, an n-type region 1 and a p-type region 2 are formed by ion implantation and diffusion of an n-type impurity. Thereafter, similarly to the first embodiment, the gate oxide film 11 is formed.
Then, a thick insulating film 14, a gate electrode 7 with a field plate are formed, a p-type channel region 3, an n-type source region 4, and a p-type contact region 6 are formed, and a source electrode 12 and a drain electrode 13 are formed. In the seventh embodiment, it is not necessary to form the n − -type region 10 in order to reduce the concentration of the electric field immediately below the boundary between the gate oxide film 11 and the second gate oxide film 14a. Reduced.

【００５２】（実施形態８）図１４（ａ）は本発明の実
施形態８を示す横型パワーMOSFETのｎ型領域１に沿った
縦断面図、図１４（ｂ）はｐ型領域２に沿った縦断面図
である。(Eighth Embodiment) FIG. 14A is a longitudinal sectional view along an n-type region 1 of a lateral power MOSFET showing an eighth embodiment of the present invention, and FIG. It is a longitudinal cross-sectional view.

【００５３】本実施形態８は、実施形態１のパワーMOSF
ETにおいて絶縁膜８上にｐ型領域２があり、その上にｎ
型領域１とｐ型領域２が隣接して交互に配列されたドリ
フト領域があり、ゲート絶縁膜１１と第２ゲート酸化膜
１４の境界直下を含む近傍に、ｎ- 型領域１０がある。The eighth embodiment is based on the power MOSF of the first embodiment.
In the ET, there is a p-type region 2 on the insulating film 8 and n
There is a drift region in which the type regions 1 and the p-type regions 2 are alternately arranged adjacent to each other, and the n − -type region 10 is located near and immediately below the boundary between the gate insulating film 11 and the second gate oxide film 14.

【００５４】本実施形態８は、絶縁膜８上の半導体層が
厚い（例えば≧２μｍ）場合に有効である。これはイオ
ン打ち込みと拡散によって、ｎ型領域１とｐ型領域２が
隣接して交互に配列されたドリフト領域を形成しようと
すると、深さが１.５μｍ 程度までは層幅が１μｍ程度
の板状のｎ型領域１及びｐ型領域２を形成することがで
きるが、深さ２μｍ以上の層を形成するために拡散工程
の温度を上げたり、拡散時間を長くすると、ｎ型領域１
及びｐ型領域２の経路幅方向への拡散が大きくなり、層
幅１μｍ程度の層を形成することは困難であるからであ
る。これより実施形態１，３，５，６，７の構造におい
ては、絶縁膜８上の層の厚さは少なくとも２μｍ以下で
あることが望ましい。Embodiment 8 is effective when the semiconductor layer on the insulating film 8 is thick (for example, ≧ 2 μm). This is because when an n-type region 1 and a p-type region 2 are adjacently and alternately arranged by ion implantation and diffusion to form a drift region, a plate having a layer width of approximately 1 μm until a depth of approximately 1.5 μm is formed. The n-type region 1 and the p-type region 2 can be formed, but if the temperature of the diffusion step is increased or the diffusion time is increased to form a layer having a depth of 2 μm or more, the n-type region 1
This is because the diffusion of the p-type region 2 in the path width direction becomes large, and it is difficult to form a layer having a layer width of about 1 μm. Accordingly, in the structures of the first, third, fifth, sixth and seventh embodiments, it is desirable that the thickness of the layer on the insulating film 8 is at least 2 μm or less.

【００５５】本実施形態８の構造においても、ｎ- 型領
域１０を挿入することにより、ゲート絶縁膜１１と第２
ゲート酸化膜１４ａ直下での電界集中を緩和し高耐圧と
低容量を実現することができる。また、ｎ- 型領域１０
の下層にはｐ型領域２があるために、実施形態３〜５と
同様に空乏化を早めることができ、オン抵抗が低減す
る。[0055] Also in the structure of the present embodiment 8, n - by inserting -type region 10, the gate insulating film 11 and the second
The concentration of the electric field immediately below the gate oxide film 14a can be reduced, and a high breakdown voltage and a low capacitance can be realized. Also, the n − type region 10
Since there is a p-type region 2 in the lower layer, depletion can be accelerated similarly to the third to fifth embodiments, and the on-resistance is reduced.

【００５６】次に、本実施形態８のパワーMOSFETの製造
方法の一例について図１５（ａ）〜（ｃ）を参照して説
明する。図１５（ａ)〜(ｃ）はそれぞれ、パワーMOSFET
の縦断面図を示す。Next, an example of a method for manufacturing the power MOSFET according to the eighth embodiment will be described with reference to FIGS. FIGS. 15A to 15C respectively show power MOSFETs.
FIG.

【００５７】図１５（ａ）で示すような半導体基板９上
の絶縁膜８上に、ｐ型領域２と同じ濃度のｐ層をエピタ
キシャル成長し、図１５（ｂ）に示すようにｎ型不純物
をイオン打ち込みすることにより、ｐ型領域２の上にｎ
型領域１とｐ型領域２が隣接して交互に配列したドリフ
ト領域を作製する。この後、図１５（ｃ）に示すように
ｎ型不純物をイオン打ち込みすることにより、ｎ- 型領
域１０を形成する。その後、実施形態１と同様に、ゲー
ト酸化膜１１及び厚い絶縁膜１４，フィールドプレート
付きゲート電極７を形成し、ｐ型チャネル領域３及びｎ
型ソース領域４，ｐ型コンタクト領域６を作製し、ソー
ス電極１２及びドレイン電極１３を形成する。On the insulating film 8 on the semiconductor substrate 9 as shown in FIG. 15A, a p-layer having the same concentration as that of the p-type region 2 is epitaxially grown, and as shown in FIG. By ion implantation, n is formed on p-type region 2.
A drift region in which the mold regions 1 and the p-type regions 2 are adjacently and alternately arranged is manufactured. Thereafter, as shown in FIG. 15C, an n - type region 10 is formed by ion-implanting an n-type impurity. Thereafter, similarly to the first embodiment, a gate oxide film 11, a thick insulating film 14, and a gate electrode 7 with a field plate are formed, and the p-type channel region 3 and the n-type
A source electrode 4 and a p-type contact region 6 are formed, and a source electrode 12 and a drain electrode 13 are formed.

【００５８】本実施形態８は、絶縁膜上の半導体層が厚
い場合の構造に適応できるので、誘電体分離型のパワー
MOSFETだけでなくｐｎ接合分離型のパワーMOSFETにも応
用できる。Since the eighth embodiment can be applied to a structure in which the semiconductor layer on the insulating film is thick, a dielectric isolation type power
The present invention can be applied not only to MOSFETs but also to pn junction separation type power MOSFETs.

【００５９】（実施形態９）図１６は本発明の実施形態
９を示す横型のパワーMOSFETと縦型のｐｎｐトランジス
タ及びｎｐｎトランジスタの複合素子である。横型のパ
ワーMOSFETの構造は本実施形態１と同様に、ｎ型領域１
とｐ型領域２が交互に隣接して配列するドリフト層と、
ゲート酸化膜１１と第２ゲート酸化膜１４ａの境界直下
での電界の集中を緩和するためのｎ- 型不純物領域１０
が挿入されている。ｐｎｐ及びｎｐｎのトランジスタ
は、通常の縦型のトランジスタである。これらの素子は
それぞれ絶縁膜８で区切られているので、用途に応じて
素子を組み合わせることが可能である。(Embodiment 9) FIG. 16 shows a composite device of a horizontal power MOSFET and a vertical pnp transistor and npn transistor according to a ninth embodiment of the present invention. The structure of the lateral power MOSFET is the same as that of the first embodiment.
And a drift layer in which p-type regions 2 are alternately arranged adjacent to each other;
N − -type impurity region 10 for alleviating electric field concentration immediately below the boundary between gate oxide film 11 and second gate oxide film 14a
Is inserted. The pnp and npn transistors are normal vertical transistors. Since these elements are separated by the insulating film 8, the elements can be combined according to the application.

【００６０】本実施形態９の効果は、ＳＯＩ構造を用い
ることにより、様々なＩＣを作成することが可能になる
ことである。The effect of the ninth embodiment is that various ICs can be manufactured by using the SOI structure.

【００６１】（実施形態１０）図１７（ａ），図１８
（ａ），図１９（ａ），図２０（ａ），図２１（ａ）は
それぞれ本発明の実施形態１０を示すＳＯＩ構造の横型
パワーMOSFETの表面での横断面図である。図１７
（ｂ），図１８（ｂ），図１９（ｂ），図２０（ｂ），
図２１（ｂ）はそれぞれ図１７（ａ），図１８（ａ），
図１９（ａ），図２０（ａ），図２１（ａ）で点線に沿
って切断した状態の縦断面図を示す。図１７から図２０
までのパワーMOSFETは、中心にｎ+ 型ドレイン領域５
(第６半導体領域)があり、その周辺に複数のドリフト領
域及びｎ- 型領域１０，ｐ型チャネル領域３，ｎ型ソー
ス領域４がある。図２１のパワーMOSFETでは逆に、中心
にｎ型ソース領域４がありその周辺にｐ型チャネル領域
３，ｎ- 型領域１０，ドリフト領域及びｎ型ドレイン領
域５がある。このように、複数のドリフト領域の中心に
これらと隣接するドレイン領域またはソース領域がある
構造にするとノイズに対して強くなる。本実施形態１０
では、ドレイン領域が中心にあるためｎ型領域１とｐ型
領域２からなるドリフト領域の範囲が図１７（ａ）及び
図２１（ａ）で示されるように制限されるので、図１８
〜図２０（ａ）で示されるような電圧保持領域を設け
る。これらの電圧保持領域は、ｎ型領域１及びｐ型領域
２がそれぞれ空乏化されるのと同程度の電圧で空乏化さ
れる。図１８から図２０が示すのは、このような電圧保
持領域の構造の一例であり、電圧保持領域が空乏化され
やすい。図１７及び図２１は電圧保持領域を濃度の低い
ｎ- 領域にすることで空乏化を早めており、図１８，図
１９，図２０ではドリフト層と同様にｎ型領域とｐ型領
域を隣接して交互に配列することで、電圧保持領域の空
乏化を早めている。また図１９，図２０ではドレイン領
域５の角部をなくすことにより、電圧保持領域内の角部
での電界の集中を回避している。さらに図２０では電圧
保持領域のｎ層の一部をドリフト領域のｎ層と繋げるこ
とにより実効的にドリフト領域の面積を広げさらに低オ
ン抵抗化できる。(Embodiment 10) FIGS. 17A and 18
(A), FIG. 19 (a), FIG. 20 (a), and FIG. 21 (a) are cross-sectional views on the surface of a lateral power MOSFET having an SOI structure showing a tenth embodiment of the present invention. FIG.
(B), FIG. 18 (b), FIG. 19 (b), FIG. 20 (b),
FIG. 21 (b) shows FIGS. 17 (a), 18 (a),
FIGS. 19 (a), 20 (a) and 21 (a) are longitudinal sectional views cut along the dotted lines. 17 to 20
Power MOSFETs up to n + -type drain region 5
(Sixth semiconductor region), around which there are a plurality of drift regions and an n − -type region 10, a p-type channel region 3, and an n-type source region 4. Conversely, the power MOSFET of FIG. 21 has an n-type source region 4 at the center and a p-type channel region 3, an n − -type region 10, a drift region and an n-type drain region 5 around the n-type source region 4. As described above, a structure in which a drain region or a source region adjacent to a plurality of drift regions is provided at the center of the plurality of drift regions is resistant to noise. Embodiment 10
In FIG. 18, since the drain region is located at the center, the range of the drift region including the n-type region 1 and the p-type region 2 is limited as shown in FIGS. 17 (a) and 21 (a).
A voltage holding region as shown in FIG. These voltage holding regions are depleted at the same voltage as the n-type region 1 and the p-type region 2 are each depleted. FIGS. 18 to 20 show an example of the structure of such a voltage holding region, and the voltage holding region is easily depleted. 17 and 21, the depletion is accelerated by setting the voltage holding region to an n − region having a low concentration. In FIGS. 18, 19, and 20, the n-type region and the p-type region are adjacent to each other as in the drift layer. By alternately arranging them, the depletion of the voltage holding region is hastened. 19 and 20, the concentration of the electric field at the corner in the voltage holding region is avoided by eliminating the corner of the drain region 5. Further, in FIG. 20, by connecting a part of the n-layer of the voltage holding region to the n-layer of the drift region, the area of the drift region can be effectively increased and the on-resistance can be further reduced.

【００６２】本実施形態１０のパワーMOSFETの効果は、
中心にドレインまたはソースがある構造のパワーMOSFET
において、ドリフト領域及びその周辺領域を、ｎ型領域
１とｐ型領域２が交互に隣接して配列することで、高耐
圧で低損失、さらにノイズに対して強いパワーMOSFETを
実現できることである。The effect of the power MOSFET of the tenth embodiment is as follows.
Power MOSFET with a structure with a drain or source at the center
In this case, a power MOSFET having a high withstand voltage, a low loss and a high noise resistance can be realized by arranging the drift region and its peripheral region so that the n-type region 1 and the p-type region 2 are alternately arranged adjacent to each other.

【００６３】なお本実施形態１０において、図３または
図４におけるドリフト領域の構成、図６，図１０または
図１１のゲート直下の低不純物濃度領域の構成を用いて
もよい。また図１７〜図２１においてゲート直下の低不
純物濃度領域を設けず、従来と同様のｐ層としても、低
オン抵抗の半導体装置となる。またこの場合にもノイズ
に対して強くなる。In the tenth embodiment, the configuration of the drift region in FIG. 3 or FIG. 4 or the configuration of the low impurity concentration region immediately below the gate in FIG. 6, FIG. 10 or FIG. 17 to 21, a low impurity concentration region immediately below the gate is not provided, and a p-layer similar to the conventional one is a low on-resistance semiconductor device. Also in this case, it becomes strong against noise.

【００６４】（実施形態１１）図２２は本発明の実施形
態１１を示すｐｎ接合分離構造の横型のパワーMOSFETの
縦断面図である。(Embodiment 11) FIG. 22 is a longitudinal sectional view of a lateral power MOSFET having a pn junction isolation structure according to Embodiment 11 of the present invention.

【００６５】図２２の構造は、ｐ型半導体基板３７上に
エピタキシャル成長させたｎ- 型領域１０と、ｎ- 型領
域１０中に板状のｎ型領域１とｐ型領域２が交互に隣接
して配列するドリフト領域と、ドリフト領域の一端側に
形成されたｐ型チャネル領域３と、ｐ型チャネル領域３
中に形成されたｎ+ 型ソース領域４と、ｐ型チャネル領
域３とｎ+ 型ソース領域４上にゲート酸化膜１１を介し
て形成されたフィールドプレート付きゲート電極７及び
ゲート端子１６と、ｐ型チャネル領域３中に形成された
ｐ+ 型コンタクト領域６と、ｐ+ 型コンタクト領域６と
ｎ+ 型ソース領域４上に形成されたソース電極１２及び
ソース端子１７と、ドリフト領域の他端側に形成された
ｎ+ ドレイン領域５と、ｎ+ ドレイン領域５上に形成さ
れたドレイン電極１３及びドレイン端子１８と、ドリフ
ト領域上に形成された厚い絶縁膜１４とを有する。本実
施形態１１においては、ｐ型半導体基板３７とｎ- 型領
域１０とのｐｎ接合によるｐｎ接合分離構造になってい
る。The structure shown in FIG. 22 has an n − -type region 10 epitaxially grown on a p-type semiconductor substrate 37, and a plate-like n-type region 1 and a p-type region 2 in the n − -type region 10 are alternately adjacent to each other. Drift region, p-type channel region 3 formed on one end side of the drift region, and p-type channel region 3
An n + -type source region 4 formed therein, a p-type channel region 3, a gate electrode 7 with a field plate and a gate terminal 16 formed on the n + -type source region 4 via a gate oxide film 11; P + type contact region 6 formed in type channel region 3, source electrode 12 and source terminal 17 formed on p + type contact region 6 and n + type source region 4, and the other end of the drift region having an n + drain region 5 formed, the n + drain region 5 the drain electrode 13 is formed on and drain terminal 18, and a thick insulating film 14 formed on the drift region. In the eleventh embodiment, a pn junction isolation structure is provided by a pn junction between the p-type semiconductor substrate 37 and the n − -type region 10.

【００６６】本実施形態１１のパワーMOSFETにおいて
も、ゲート酸化膜１１と第２ゲート酸化膜１４ａの境界
直下での電界集中を緩和するために、ゲート酸化膜１１
と第２ゲート酸化膜１４ａの境界直下を含む近傍にｎ-
型領域１０が形成される。Also in the power MOSFET of the eleventh embodiment, the gate oxide film 11 is formed to reduce the electric field concentration just below the boundary between the gate oxide film 11 and the second gate oxide film 14a.
N − near the region immediately below the boundary between the gate electrode and the second gate oxide film 14a.
A mold region 10 is formed.

【００６７】本実施形態１１の構造を作製するには、ｐ
型半導体基板３７上にｎ- 型領域１０をエピタキシャル
成長し、その後は実施形態１と同様にフォトリソグラフ
ィーとイオン打ち込み、拡散によってドリフト領域等を
形成することができる。To fabricate the structure of the eleventh embodiment, p
An n − type region 10 is epitaxially grown on the type semiconductor substrate 37, and thereafter, a drift region or the like can be formed by photolithography and ion implantation and diffusion as in the first embodiment.

【００６８】本実施形態１１のパワーMOSFETは、ｐｎ接
合分離構造のパワーMOSFETにおいて、ゲート酸化膜直下
での電界集中を緩和することにより、高耐圧で低損失，
低容量のパワーMOSFETが実現できる。The power MOSFET according to the eleventh embodiment is a power MOSFET having a pn junction isolation structure, which has a high withstand voltage and low loss by relaxing electric field concentration immediately below a gate oxide film.
A low-capacity power MOSFET can be realized.

【００６９】以上、本発明の実施形態について主にＳＯ
Ｉ構造で横型のｎチャネル型パワーMOSFETの例を中心に
説明したが、本発明は前記実施形態に限定されたもので
はなく、縦型，ｐチャネル型のパワーMOSFETについても
適用可能である。また、本発明は、上述したMOSFETと同
様のドリフト領域を有するＩＧＢＴにも適用可能であ
る。As described above, the embodiments of the present invention are mainly
Although the description has been made centering on the example of the lateral n-channel type power MOSFET having the I structure, the present invention is not limited to the above-described embodiment, but is also applicable to vertical and p-channel type power MOSFETs. Further, the present invention is also applicable to an IGBT having a drift region similar to the MOSFET described above.

【００７０】[0070]

【発明の効果】本発明の効果はｎ型領域とｐ型領域が交
互に隣接して配列されるドリフト層を持つ半導体装置に
おいて、高耐圧・低オン抵抗の半導体装置を実現でき
る。According to the effects of the present invention, a semiconductor device having a high breakdown voltage and a low on-resistance can be realized in a semiconductor device having a drift layer in which n-type regions and p-type regions are alternately arranged adjacently.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施形態１のパワーMOSFETの構造を示
す。FIG. 1 shows a structure of a power MOSFET according to a first embodiment of the present invention.

【図２】本発明の実施形態１のパワーMOSFETの製造方法
を示す。FIG. 2 shows a method for manufacturing the power MOSFET according to the first embodiment of the present invention.

【図３】本発明の実施形態２のパワーMOSFETの構造を示
す。FIG. 3 shows a structure of a power MOSFET according to a second embodiment of the present invention.

【図４】本発明の実施形態２のパワーMOSFETの構造を示
す。FIG. 4 shows a structure of a power MOSFET according to a second embodiment of the present invention.

【図５】本発明の実施形態２のパワーMOSFETの製造方法
を示す。FIG. 5 shows a method for manufacturing a power MOSFET according to the second embodiment of the present invention.

【図６】本発明の実施形態３のパワーMOSFETの構造を示
す。FIG. 6 shows a structure of a power MOSFET according to a third embodiment of the present invention.

【図７】本発明の実施形態３のパワーMOSFETの製造方法
を示す。FIG. 7 shows a method for manufacturing a power MOSFET according to the third embodiment of the present invention.

【図８】本発明の実施形態４のパワーMOSFETの構造を示
す。FIG. 8 shows a structure of a power MOSFET according to a fourth embodiment of the present invention.

【図９】本発明の実施形態４のパワーMOSFETの製造方法
を示す。FIG. 9 shows a method for manufacturing a power MOSFET according to the fourth embodiment of the present invention.

【図１０】本発明の実施形態５のパワーMOSFETの構造を
示す。FIG. 10 shows a structure of a power MOSFET according to a fifth embodiment of the present invention.

【図１１】本発明の実施形態６のパワーMOSFETの構造を
示す。FIG. 11 shows a structure of a power MOSFET according to a sixth embodiment of the present invention.

【図１２】本発明の実施形態７のパワーMOSFETの構造を
示す。FIG. 12 shows a structure of a power MOSFET according to a seventh embodiment of the present invention.

【図１３】本発明の実施形態７のパワーMOSFETの製造方
法を示す。FIG. 13 shows a method for manufacturing a power MOSFET according to the seventh embodiment of the present invention.

【図１４】本発明の実施形態８のパワーMOSFETの構造を
示す。FIG. 14 shows a structure of a power MOSFET according to an eighth embodiment of the present invention.

【図１５】本発明の実施形態８のパワーMOSFETの製造方
法を示す。FIG. 15 shows a method for manufacturing a power MOSFET according to the eighth embodiment of the present invention.

【図１６】本発明の実施形態９のパワーMOSFETの構造を
示す。FIG. 16 shows a structure of a power MOSFET according to a ninth embodiment of the present invention.

【図１７】本発明の実施形態１０のパワーMOSFETの構造
を示す。FIG. 17 shows a structure of a power MOSFET according to a tenth embodiment of the present invention.

【図１８】本発明の実施形態１０のパワーMOSFETの構造
を示す。FIG. 18 shows a structure of a power MOSFET according to a tenth embodiment of the present invention.

【図１９】本発明の実施形態１０のパワーMOSFETの構造
を示す。FIG. 19 shows a structure of a power MOSFET according to a tenth embodiment of the present invention.

【図２０】本発明の実施形態１０のパワーMOSFETの構造
を示す。FIG. 20 shows a structure of a power MOSFET according to a tenth embodiment of the present invention.

【図２１】本発明の実施形態１０のパワーMOSFETの構造
を示す。FIG. 21 shows a structure of a power MOSFET according to a tenth embodiment of the present invention.

【図２２】本発明の実施形態１１のパワーMOSFETの構造
を示す。FIG. 22 shows a structure of a power MOSFET according to an eleventh embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１…ｎ型領域、１ａ…ｎ型電圧保持領域、２…ｐ型領
域、２ａ…ｐ型電圧保持領域、３…ｐ型チャネル領域、
４…ｎ+ 型ソース領域、５…ｎ+ 型ドレイン領域、６…
ｐ+ 型コンタクト領域、７…フィールドプレート付きゲ
ート電極、８…絶縁膜、９…半導体基板、１０…ｎ- 型
領域、１０ａ…ｎ- 型電圧保持領域、１１…ゲート酸化
膜、１２…ソース電極、１３…ドレイン電極、１４…厚
い絶縁膜、１５…ｐ- 型領域、１６…ゲート端子、１７
…ソース端子、１８…ドレイン端子、１９…酸化膜マス
ク、２０…ｎ+ バッファ層、２１…ｐ+ 型コレクタ領
域、２２…ｎ+ 型エミッタ領域、２３…コレクタ電極、
２４…エミッタ電極、２５…コレクタ端子、２６…エミ
ッタ端子、２７…ｎ型ベース領域、２８…ｎ+ 型ベース
領域、２９…ベース電極、３０…ベース端子、３１…ｐ
型コレクタ領域、３２…ｎ+ 型エミッタ領域、３３…ｎ
+ 型コレクタ領域、３４…ｐ型ベース領域、３５…ｐ+
型ベース領域、３６…ｎ型コレクタ領域、３７…ｐ型半
導体基板。1 ... n-type region, 1a ... n-type voltage holding region, 2 ... p-type region, 2a ... p-type voltage holding region, 3 ... p-type channel region,
4 ... n + type source region, 5 ... n + type drain region, 6 ...
p + type contact region, 7 gate electrode with field plate, 8 insulating film, 9 semiconductor substrate, 10 n - type region, 10a n - type voltage holding region, 11 gate oxide film, 12 source electrode , 13: drain electrode, 14: thick insulating film, 15: p - type region, 16: gate terminal, 17
... source terminal, 18 ... drain terminal, 19 ... oxide film mask, 20 ... n + buffer layer, 21 ... p + type collector region, 22 ... n + type emitter region, 23 ... collector electrode,
24 ... emitter electrode, 25 ... collector terminal, 26 ... emitter terminal, 27 ... n-type base region, 28 ... n + -type base region, 29 ... base electrode 30 ... base terminal, 31 ... p
Collector region, 32... N + emitter region, 33.
+ Type collector region, 34 ... p type base region, 35 ... p +
A base region, 36... An n-type collector region, 37.

───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5F110 AA07 BB12 CC02 DD05 EE09 FF02 FF12 GG02 GG37 GG52 HJ04 HJ06 HJ11 HJ13 HJ23 HM12  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F110 AA07 BB12 CC02 DD05 EE09 FF02 FF12 GG02 GG37 GG52 HJ04 HJ06 HJ11 HJ13 HJ23 HM12

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】第１導電型の第１半導体領域と第２導電型
の第２半導体領域が交互に隣接して配列するドリフト領
域と、前記ドリフト領域の一端側に形成された第２導電
型の第３半導体領域と、前記第３半導体領域内に形成さ
れた第１導電型の第４半導体領域と、前記第３及び第４
半導体領域とゲート絶縁膜を介在して対向するゲート電
極と、を有し、前記ドリフト領域と前記第３半導体領域
に挟まれるゲート絶縁膜直下の一端側を含む近傍に、前
記ドリフト領域の不純物濃度より低不純物濃度の第５半
導体領域を有する半導体装置。1. A drift region in which a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type are alternately arranged adjacently, and a second conductivity type formed on one end side of the drift region. A third semiconductor region, a fourth semiconductor region of a first conductivity type formed in the third semiconductor region, and the third and fourth semiconductor regions.
A gate electrode opposed to the semiconductor region with a gate insulating film interposed therebetween, and having an impurity concentration of the drift region in a vicinity including one end immediately below the gate insulating film sandwiched between the drift region and the third semiconductor region A semiconductor device having a fifth semiconductor region with a lower impurity concentration. 【請求項２】第１導電型の第１半導体領域と第２導電型
の第２半導体領域が交互に隣接して配列する複数のドリ
フト領域と、前記複数のドリフト領域を囲む第２導電型
の第３半導体領域と、前記第３半導体領域内に形成され
た第１導電型の第４半導体領域と、前記第３及び第４半
導体領域とゲート絶縁膜を介在して対向するゲート電極
と、前記複数のドリフト領域に隣接する第１導電型の第
６半導体領域と、を有し、前記複数のドリフト領域と第
３半導体領域に挟まれて、ゲート絶縁膜直下の一端側を
含む近傍に、前記複数のドリフト領域の不純物濃度より
低不純物濃度の第５半導体領域を有する半導体装置。2. A plurality of drift regions in which first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type are alternately arranged adjacently, and a second conductivity type surrounding the plurality of drift regions. A third semiconductor region, a fourth semiconductor region of a first conductivity type formed in the third semiconductor region, a gate electrode facing the third and fourth semiconductor regions with a gate insulating film interposed therebetween, A sixth semiconductor region of the first conductivity type adjacent to the plurality of drift regions, wherein the sixth semiconductor region is sandwiched between the plurality of drift regions and the third semiconductor region and includes a portion including one end side immediately below the gate insulating film; A semiconductor device having a fifth semiconductor region having a lower impurity concentration than a plurality of drift regions. 【請求項３】第１導電型の第１半導体領域と第２導電型
の第２半導体領域が交互に隣接して配列する複数のドリ
フト領域と、前記複数のドリフト領域に隣接する第２導
電型の第３半導体領域と、前記第３半導体領域内に形成
された第１導電型の第４半導体領域と、前記第３及び第
４半導体領域とゲート絶縁膜を介在して対向するゲート
電極と、前記複数のドリフト領域を囲む第１導電型の第
６半導体領域と、を有し、前記複数のドリフト領域と第
３半導体領域に挟まれて、ゲート絶縁膜直下の一端側を
含む近傍に、前記複数のドリフト領域の不純物濃度より
不純物低濃度の第５半導体領域を有する半導体装置。3. A plurality of drift regions in which first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type are alternately arranged adjacent to each other, and a second conductivity type adjacent to the plurality of drift regions. A third semiconductor region, a fourth semiconductor region of the first conductivity type formed in the third semiconductor region, a gate electrode facing the third and fourth semiconductor regions with a gate insulating film interposed therebetween, A sixth semiconductor region of a first conductivity type surrounding the plurality of drift regions, and a portion including the one end side immediately below the gate insulating film between the plurality of drift regions and the third semiconductor region; A semiconductor device having a fifth semiconductor region having a lower impurity concentration than a plurality of drift regions. 【請求項４】請求項１〜３のいずれか１項において、前
記第５半導体領域が第１導電型の領域である半導体装
置。4. The semiconductor device according to claim 1, wherein said fifth semiconductor region is a region of a first conductivity type. 【請求項５】請求項１〜３のいずれか１項において、前
記第５半導体領域が第１導電型の領域と第２導電型の領
域を有する半導体装置。5. The semiconductor device according to claim 1, wherein said fifth semiconductor region has a first conductivity type region and a second conductivity type region. 【請求項６】請求項５において、前記第１導電型の領域
が前記第１半導体領域に隣接し、前記第２導電型の領域
が前記第２半導体領域に隣接する半導体装置。6. The semiconductor device according to claim 5, wherein said first conductivity type region is adjacent to said first semiconductor region, and said second conductivity type region is adjacent to said second semiconductor region. 【請求項７】第１導電型の第１半導体領域と第２導電型
の第２半導体領域が交互に隣接して配列するドリフト領
域と、前記ドリフト領域の一端側に形成された第２導電
型の第３半導体領域と、前記第３半導体領域内に第１導
電型の第４半導体領域と、前記第３及び第４半導体領域
とゲート絶縁膜を介在して対向するゲート電極とを有
し、前記第１半導体領域のゲート絶縁膜直下の幅が前記
第２半導体領域のゲート絶縁膜直下の幅よりも狭い半導
体装置。7. A drift region in which a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type are alternately arranged adjacent to each other, and a second conductivity type formed on one end side of the drift region. A third semiconductor region, a fourth semiconductor region of a first conductivity type in the third semiconductor region, and a gate electrode facing the third and fourth semiconductor regions with a gate insulating film interposed therebetween, A semiconductor device in which the width of the first semiconductor region immediately below the gate insulating film is smaller than the width of the second semiconductor region immediately below the gate insulating film. 【請求項８】第１導電型の第１半導体領域と第２導電型
の第２半導体領域が交互に隣接して配列する複数のドリ
フト領域と、前記複数のドリフト領域を囲む第２導電型
の第３半導体領域と、前記第３半導体領域内に形成され
た第１導電型の第４半導体領域と、前記第３及び第４半
導体領域とゲート絶縁膜を介在して対向するゲート電極
と、前記複数のドリフト領域に隣接する第１導電型の第
６不純物領域と、を有する半導体装置。8. A plurality of drift regions in which first semiconductor regions of the first conductivity type and second semiconductor regions of the second conductivity type are alternately arranged adjacent to each other, and a second conductivity type surrounding the plurality of drift regions. A third semiconductor region, a fourth semiconductor region of a first conductivity type formed in the third semiconductor region, a gate electrode facing the third and fourth semiconductor regions with a gate insulating film interposed therebetween, And a sixth impurity region of the first conductivity type adjacent to the plurality of drift regions. 【請求項９】第１導電型の第１半導体領域と第２導電型
の第２半導体領域が交互に隣接して配列する複数のドリ
フト領域と、前記複数のドリフト領域に隣接する第２導
電型の第３半導体領域と、前記第３半導体領域内に形成
された第１導電型の第４半導体領域と、前記第３及び第
４半導体領域とゲート絶縁膜を介在して対向するゲート
電極と、前記複数のドリフト領域を囲む第１導電型の第
６不純物領域と、を有する半導体装置。9. A plurality of drift regions in which a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type are alternately arranged adjacent to each other, and a second conductivity type adjacent to the plurality of drift regions. A third semiconductor region, a fourth semiconductor region of the first conductivity type formed in the third semiconductor region, a gate electrode facing the third and fourth semiconductor regions with a gate insulating film interposed therebetween, And a sixth impurity region of the first conductivity type surrounding the plurality of drift regions.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1331193C (en) * 2002-07-16 2007-08-08 半导体元件工业有限责任公司 Method and its structure for forming semiconductor device
KR100760924B1 (en) 2006-09-13 2007-09-21 동부일렉트로닉스 주식회사 Method for forming semiconductor device
CN117219654A (en) * 2023-11-07 2023-12-12 杭州士兰微电子股份有限公司 High-voltage grid driving circuit and preparation method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1331193C (en) * 2002-07-16 2007-08-08 半导体元件工业有限责任公司 Method and its structure for forming semiconductor device
KR100760924B1 (en) 2006-09-13 2007-09-21 동부일렉트로닉스 주식회사 Method for forming semiconductor device
CN117219654A (en) * 2023-11-07 2023-12-12 杭州士兰微电子股份有限公司 High-voltage grid driving circuit and preparation method thereof
CN117219654B (en) * 2023-11-07 2024-02-23 杭州士兰微电子股份有限公司 High-voltage grid driving circuit and preparation method thereof

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