JPH09102506A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of a punch-through withstand voltage of MISFETQ and the deterioration of a junction withstand voltage at a pn junction part between a channel region and a drain region and to prevent a threshold voltage from fluctuating. SOLUTION: A process for forming a conductive film on the main surface of a semiconductor region 1B which is a drain region via a gate insulation film 2 and a process for forming a gate electrode 3A on a first region of the main surface of the semiconductor region 1B and for forming a gate opening 3B at the gate electrode 3A are provided. Further, a process for forming a semiconductor region 5A which is a channel formation region with an impurity 5 which is introduced in self-alignment manner for the gate electrode 3A into a second region on the main surface of the semiconductor region 1B and a process for forming a semiconductor region 6A which is a source region with an impurity 6 which is introduced in self-alignment manner for the gate electrode 3A on the main surface of the semiconductor region 5A are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices.
Regarding the technology, in particular, the vertical structure MISFET (Metal
InsulatorSemiconductorFieldEffectTransist
technology that is effective when applied to the manufacturing technology of semiconductor devices having
It is related to surgery.

[0002]

2. Description of the Related Art As a power transistor (semiconductor device) having a vertical MISFET, a power transistor having a MISFET in which a low resistance region is formed on a sidewall of a channel forming region is disclosed in, for example, Japanese Patent Laid-Open No. 1-29146.
No. 8 publication. The low resistance region is MISFE
A gate opening is formed in the gate electrode of T, and it is composed of a semiconductor region made of impurities introduced through the gate opening. Hereinafter, a method of manufacturing a power transistor having a MISFET in which a low resistance region is formed on a side wall of a channel forming region will be described with reference to FIGS.

First, a semiconductor substrate 1 in which an n-type epitaxial layer 1B is formed on the main surface of an n + type semiconductor substrate 1A is prepared. Next, a gate insulating film 2 is formed on the main surface of the n − type epitaxial layer 1B which is the main surface of the semiconductor substrate 1.
Then, as shown in FIG. 25, a conductive film 3 is formed on the main surface of the n − type epitaxial layer 1B with a gate insulating film 2 interposed.

Next, the conductive film 3 is patterned to form a gate electrode 3A on the first region of the main surface of the n--type epitaxial layer 1B. This patterning process is performed by an etching technique using a photoresist mask as an etching mask. The photoresist mask is formed by the photolithography technique.

Next, using the gate electrode 3A as a mask for introducing impurities, as shown in FIG. 26, p-type impurities 5 are ion-implanted into the second region of the main surface of the n-type epitaxial layer 1B. Introduce selectively.

Next, a photoresist mask 50 having an opening exposing a part of the main surface of the gate electrode 3A and covering the second region of the main surface of the n-type epitaxial layer 1B is formed. To do. Then, using the photoresist mask 50 as an etching mask, the gate electrode 3A
To the gate electrode 3A by etching the gate opening 3
Form B.

Next, as shown in FIG. 27, the gate opening 3 is formed in the first region of the main surface of the n--type epitaxial layer 1B.
The n-type impurity 4 is selectively introduced through B by the ion implantation method. Then, the photoresist mask 50 is removed.

Next, a thermal diffusion process is performed, and as shown in FIG. 28, an n-type semiconductor, which is a low resistance region with the n-type impurity 4, is formed in the first region of the main surface of the n-type epitaxial layer 1B. While forming the region 4A, the p-type impurity 5 is used to form a p-type semiconductor region 5A, which is a channel forming region, in the second region of the main surface of the n-type epitaxial layer 1B.

Next, a photoresist mask 51 is formed so as to cover the gate opening 3B and a part of the main surface of the p-type semiconductor region 5A. Thereafter, as shown in FIG. 29, the photoresist mask 51 is formed. Using the photoresist mass 51 and the gate electrode 3A as an impurity introduction mask, the n-type impurity 6 is selectively introduced into another region of the main surface of the p-type semiconductor region 5A by an ion implantation method.

Next, the photoresist mask 51 is removed, and then a thermal diffusion process is performed to, as shown in FIG. 30, the n-type impurity in a part of the main surface of the p-type semiconductor region 5A. 6, the n + type semiconductor region 6 which is the source region
Form A. In this step, a low resistance region n is formed on a side portion of the p-type semiconductor region 5A which is a channel formation region.
The MISFET Q in which the type semiconductor region 4A is formed is formed. The channel length of the MISFET Q is defined by the distance between the n-type semiconductor region 4A and the n + -type semiconductor region 6A.

Next, an interlayer insulating film 7 is formed on the entire main surface of the n--type epitaxial layer 1B including the gate electrode 3A and the gate opening 3B, and then the interlayer insulating film 7 is formed.
The connection hole 8 is formed in the.

Next, a p + type semiconductor region 9 which is a contact region is formed on the main surface of the p type semiconductor region 5A, and then, as shown in FIG. 31, a source wiring 10A is formed to have a MISFETQ. The power transistor is almost completed.

The power transistor having such a structure has a MISF corresponding to the area occupied by the gate opening 3B.
Since the gate input capacitance (feedback capacitance) added to the gate electrode 3A of the ETQ can be reduced, the operating speed can be increased and the power consumption can be reduced. Further, since the drain resistance can be reduced by the low resistance region (n-type semiconductor region 4A), low on-resistance can be achieved.

[0014]

However, as a result of examining the power transistor having the above-mentioned MISFETQ, the present inventor has found the following problems.

The gate opening 3B is formed after forming the gate electrode 3A. That is, the gate electrode 3A,
Since each of the gate openings 3B is formed by a forming process independent of each forming process, the position of the gate opening 3B with respect to the gate electrode 3A is displaced, and further, the n-type semiconductor region which is a low resistance region is formed. Positional deviation occurs at the position of 4A. The misalignment of the n-type semiconductor region 4A, which is a low resistance region, is as shown in FIG. To produce an overlapping region 14. In this overlapping region 14, the effective concentration of the p-type impurity 5 becomes low, so that the punch-through breakdown voltage of the MISFET Q deteriorates. Further, there is a possibility that the threshold voltage of the MISFETQ may change.

Further, when the n-type semiconductor region 4A, which is a low resistance region, is not formed, the gate opening 3B is misaligned, as shown in FIG. An empty area 15 is generated in which the semiconductor area 5A and the gate electrode 3A do not overlap each other. For this reason, the depletion region spreading from the p-type semiconductor region 5A to the n − -type epitaxial layer 1B becomes smaller and the electric field strength becomes stronger, so that the channel forming region (p-type semiconductor region 5A) and drain region (n − The junction breakdown voltage at the pn junction with the epitaxial layer 1B) deteriorates.

Further, even if a voltage is applied to the gate electrode 3A, since the channel layer (inversion layer) is not formed in the open area 12, the threshold voltage of the MISFET Q fluctuates.

An object of the present invention is to provide a technique capable of preventing deterioration of punch through breakdown voltage of a MISFET mounted on a power transistor (semiconductor device).

Another object of the present invention is to prevent deterioration of the junction breakdown voltage at the pn junction between the channel formation region and the drain region of a MISFET mounted on a power transistor (semiconductor device). To provide the technology.

Another object of the present invention is to provide a technique capable of preventing the fluctuation of the threshold voltage of the MISFET mounted on the power transistor (semiconductor device).

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0022]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In a method of manufacturing a power transistor (semiconductor device) having a MISFET, a step of forming a conductive film with a gate insulating film interposed on the main surface of a semiconductor region of the first conductivity type which is a drain region, Patterning the conductive film to form a gate electrode on the first region of the main surface of the semiconductor region of the first conductivity type and forming a gate opening in the gate electrode; and the first conductivity type. Forming a second conductivity type semiconductor region, which is a channel formation region, with a second conductivity type impurity introduced in a second region of the main surface of the semiconductor region in self-alignment with the gate electrode; Forming a first-conductivity-type semiconductor region, which is a source region, on the main surface of the second-conductivity-type semiconductor region with a first-conductivity-type impurity introduced in self-alignment with the gate electrode.

(2) In the method for manufacturing a power transistor according to the above-mentioned means (1), the first transistor introduced through the gate opening into the first region of the main surface of the first conductivity type semiconductor region which is the drain region. A step of forming a first conductive type semiconductor region, which is a low resistance region, with a conductive type impurity is provided.

According to the above-mentioned means (1), since the gate electrode and the gate opening are formed in the same step, it is possible to prevent the displacement of the gate opening with respect to the gate electrode. As a result, it is possible to suppress the formation of an empty area where the second conductivity type semiconductor region, which is the channel formation region, and the gate electrode do not overlap each other, so that the channel formation region (second conductivity type semiconductor region) of the MISFET is suppressed. Drain region
It is possible to prevent the junction breakdown voltage from deteriorating at the pn junction with the (first conductivity type semiconductor region).

Further, since the channel layer is surely formed, it is possible to prevent the threshold voltage of the MISFET from changing.

According to the above-mentioned means (2), the displacement of the gate opening with respect to the gate electrode can be prevented, so that the displacement of the first conductivity type semiconductor region, which is a low resistance region, can be prevented. . As a result, it is possible to suppress the formation of an overlapping region in which the first-conductivity-type semiconductor region that is a low-resistance region and the second-conductivity-type semiconductor region that is a channel formation region overlap with each other. Can be prevented.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIG. 1 is a chip layout diagram of a power transistor (semiconductor device) according to a first embodiment of the present invention, FIG. 2 is a plan view of essential parts of FIG. 1, and FIG. It is sectional drawing cut | disconnected in the position of the AA line shown in FIG.
Note that, in FIG. 2, a source wiring 10A, a final protective film 11 and the like, which will be described later, are omitted in order to make the diagram easy to see.

As shown in FIG. 1, the power transistor (semiconductor device) of the present embodiment is formed, for example, in a semiconductor chip forming region 16 having a rectangular plane. This power transistor basically has a single-layer wiring structure (single-layer aluminum wiring structure).

In the central region of the semiconductor chip forming region 16, the source wiring 10A is formed in most of the region,
Gate wiring 10B is formed in a part of the region. Source wiring 10A is an external terminal (bonding pad) 10A ₁
The gate wiring 10B is electrically connected to the external terminal (bonding pad) 10B ₁ . The source wiring 10A, the gate wiring 10B, and the external terminal 10
Each of A ₁ and the external terminal 10B ₁ is formed of, for example, an aluminum film or an aluminum alloy film.

A plurality of MISFETs Q are mounted in the central region of the semiconductor chip forming region 16 as shown in FIG. Each of the plurality of MISFETs Q is electrically connected in parallel and arranged in a triangular arrangement.

As shown in FIG. 3, the power transistor includes, for example, an n-type epitaxial layer (having a low impurity concentration) on the main surface of an n + type semiconductor substrate (semiconductor region having a high impurity concentration) 1A made of single crystal silicon. The semiconductor substrate 1 is mainly composed of the semiconductor substrate 1 in which the semiconductor region 1B is formed. The above-mentioned MISFETQ is formed on the main surface of the semiconductor substrate 1, and the drain electrode 12 is formed on the back surface thereof.

The MISFET Q is mainly composed of a channel forming region, a gate insulating film 2, a gate electrode 3A, a source region and a drain region. The channel formation region is
The p-type semiconductor region 5A is formed on the main surface of the n-type epitaxial layer 1B. Gate insulating film 2 is formed of a thermal oxidation insulating film formed on the main surface of n − type epitaxial layer 1B. Gate electrode 3A is formed of a polycrystalline silicon film formed on the main surface of gate insulating film 2. The source region is composed of an n + type semiconductor region 6A formed on the main surface of the p type semiconductor region 5A. The drain region includes the n + type semiconductor substrate 1A, the n− type epitaxial layer 1B, and the n type semiconductor region.
(Low resistance region) 4A. That is, the MISFET Q of the present embodiment is constituted by a vertical structure n-channel conductivity type in which the semiconductor substrate 1 serves as a drain region.

In the gate electrode 3A of the MISFET Q, as shown in FIGS. 2 and 3, a gate opening 3B exposing a part of the surface of the gate insulating film 2 is formed. The planar shape of the gate opening 3B is, for example, a triangular shape. Thus, the gate opening 3 is formed in the gate electrode 3A.
By forming B, the gate input capacitance (feedback capacitance) added to the gate electrode 3A can be reduced by an amount corresponding to the area occupied by the gate opening 3B, so that the operating speed of the power transistor can be increased or reduced. Power consumption can be reduced.

The p-type semiconductor region 5A which is the channel forming region of the MISFET Q is composed of p-type impurities introduced in self-alignment with the gate electrode 3A. The plane shape of the p-type semiconductor region 5A is, for example, circular. The n + type semiconductor region 6A, which is the source region of the MISFET Q, is composed of an n type impurity introduced in self alignment with the gate electrode 3A. This n + type semiconductor region 6A
Is formed in a ring shape, for example.

The n-type semiconductor region (low resistance region) 4A which is the drain region of the MISFET Q is formed in the first region of the main surface of the n-type epitaxial layer 1B below the gate electrode 3A and is a channel forming region p. The sidewall of the type semiconductor region 5A is contacted. The n-type semiconductor region 4A is composed of an n-type impurity introduced through the gate opening 3B, and has a higher impurity concentration than that of the n-type epitaxial layer 1B which is the drain region. That is, the resistance of the region on the channel formation region side of the drain region is reduced. Thus, M
Channel formation region of ISFETQ (p-type semiconductor region 5A)
Since the drain resistance of the MISFET Q can be reduced by forming the low resistance region (n-type semiconductor region 4A) on the side wall of the power transistor, the on-resistance of the power transistor can be reduced.

A p + type semiconductor region 9 which is a contact region is formed on the main surface of the p type semiconductor region 5A which is the channel forming region. The p + type semiconductor region 9 is set to have a higher impurity concentration than the p type semiconductor region 5A.

The p + type semiconductor region 9 and the n + type semiconductor region 6
A source wiring 10A is electrically connected to each of A through a connection hole 8 formed in the interlayer insulating film 7. Further, a gate wiring (10B) is electrically connected to the gate electrode 3A. The interlayer insulating film 7 is arranged between the gate electrode 3A and the source wiring 10A, and insulates and separates the gate electrode 3A and the source wiring 10A. Interlayer insulating film 7 is formed, for example, PSG (P hospho S ilicate G lass ) film.

Above the source wiring 10A and the gate wiring
A final protective film 11 is formed on the entire surface of the main surface of the n − type epitaxial layer 1B including (10B). The final protective film 11 is formed of, for example, a polyimide resin film.

Next, a method of manufacturing the power transistor having the MISFET Q will be described with reference to FIGS. 4 to 11 (main part sectional views for explaining the manufacturing method).

First, a semiconductor substrate 1 in which an n-type epitaxial layer (first conductivity type semiconductor region) 1B is formed on the main surface of an n + type semiconductor substrate 1A made of single crystal silicon is prepared.

Next, a thermal oxidation process is performed to form a gate insulating film 2 made of a thermal silicon oxide film on the main surface of the n--type epitaxial layer 1B.

Next, a conductive film 3 is formed on the main surface of the n − type epitaxial layer 1B with the gate insulating film 2 interposed.
The conductive film 3 is formed of, for example, a polycrystalline silicon film deposited by the CVD method. Impurities that reduce the resistance value are introduced into the polycrystalline silicon film during or after the deposition.

Next, as shown in FIG. 4, a mask 20 for forming a gate electrode and a gate opening is formed on the main surface of the conductive film 3. The mask 20 is formed of, for example, a photoresist film formed by a photolithography technique.

Next, the conductive film 3 is patterned by using the mask 20 as an etching mask,
As shown in FIG. 5, a gate electrode 3A is formed in the first region of the main surface of the n − -type epitaxial layer 1B, and a gate opening 3B exposing a part of the surface of the gate insulating film 2 is formed in the gate electrode 3A. Form. In this step, since the gate electrode 3A and the gate opening 3B are formed in the same step, the displacement of the gate opening 3B with respect to the gate electrode 3A can be prevented.

Next, the mask 20 is removed.

Next, the n-type impurity 4 is selectively introduced into the first region of the main surface of the n-type epitaxial layer 1B through the gate opening 3B. As shown in FIG. 6, the n-type impurity 4 is introduced by an ion implantation method using the mask 21 covering the second region of the main surface of the n − -type epitaxial layer 1B and the gate electrode 3A as an impurity introduction mask. To be done. The n-type impurity 4 has, for example, a final introduction amount of 10 ¹¹
It is introduced under the conditions set to about 10 ¹² [atoms / cm ² ]. The mask 21 is formed of, for example, a photoresist film formed by a photolithography technique.

Next, the p-type impurity 5 is selectively introduced into the second region of the main surface of the n-type epitaxial layer 1B in self-alignment with the gate electrode 3A. This p-type impurity 5
Is introduced by an ion implantation method using the mask 22 covering the gate opening 3B and the gate electrode 3A as an impurity introducing mask as shown in FIG. The p-type impurity 5 has a final introduction amount of 10 ¹³ to 10 ¹⁴ [at
oms / cm ² ]. The mask 22 is formed of, for example, a photoresist film formed by a photolithography technique.

Next, as shown in FIG. 8, a thermal diffusion process is applied to the first region of the main surface of the n--type epitaxial layer 1B with the n-type impurity 4 and the n-type semiconductor which is a low resistance region. While forming the region 4A, the p-type impurity 5 is used to form a p-type semiconductor region 5A, which is a channel forming region, in the second region of the main surface of the n-type epitaxial layer 1B. In this step, the gate opening 3B for the gate electrode 3A
Of the n-type semiconductor region made of the n-type impurity 4 introduced through the gate opening 3B, since the displacement of the
(Low resistance region) It is possible to prevent the displacement of 4A.

Next, the n-type impurity 6 is selectively introduced into a part of the main surface of the p-type semiconductor region 5A in self-alignment with the gate electrode 3A. As shown in FIG. 9, the n-type impurity 6 is introduced into the gate electrode 3A and the mask 23 that covers the gate opening 3B and covers the other region of the main surface of the p-type semiconductor region 5A. It is introduced by the ion implantation method used as a mask. The n-type impurity 6 has, for example, a final introduction amount of 10 ¹⁵ to 10 ¹⁶ [atom
s / cm ² ].
The mask 23 is formed of, for example, a photoresist film formed by a photolithography technique.

Next, a thermal diffusion process is performed, and as shown in FIG. 10, a part of the main surface of the p-type semiconductor region 5A is
The n-type impurity 6 forms the n + -type semiconductor region 6A which is the source region. Through this step, the n-type semiconductor region (low resistance region) 4A and the n + -type semiconductor region (channel formation region) 6
MISFET whose channel length is defined by the distance from A
Q is formed.

Next, an interlayer insulating film 7 made of a PSG film is formed on the entire main surface of the n-type epitaxial layer 1B including the gate electrode 3A, and thereafter, as shown in FIG.
A connection hole 8 is formed in the interlayer insulating film 7 to expose a part of the main surface of the p-type semiconductor region 5A and a part of the main surface of the n + type semiconductor region 6A.

Next, p-type impurities are selectively introduced into the main surface of the p-type semiconductor region 5A through the connection hole 8 by an ion implantation method, and a p + type semiconductor which is a contact region is formed on the main surface of the p-type semiconductor region 5A. Region 9 is formed.

Next, a source wiring 10A electrically connected to each of the n + type semiconductor region 6A and the p + type semiconductor region 9 is formed.
And a gate wiring (10B) electrically connected to the gate electrode 3A.

Next, a final protective film 11 made of a polyimide resin film is formed on the entire main surface of the n--type epitaxial layer 1B including the source wiring 10A and the gate wiring (10B). After that, the drain electrode 12 is formed on the back surface of the semiconductor substrate 1, whereby the power transistor having the MISFET Q is almost completed.

In the manufacturing process described above, the step of the n-type semiconductor region 4A may be omitted.

As described above, according to this embodiment, the following operational effects can be obtained.

(1) In a method of manufacturing a power transistor (semiconductor device) having a MISFET Q, a step of forming a conductive film 3 on the main surface of an n − type epitaxial layer 1 which is a drain region with a gate insulating film 2 interposed. And patterning the conductive film 3 to form a gate electrode 3A on the first region of the main surface of the n − type epitaxial layer 1B, and forming a gate opening 3B in the gate electrode, With the p-type impurity 5 introduced in the second region of the main surface of the n − -type epitaxial layer 1B in self-alignment with the gate electrode 3A, the p-type semiconductor region 5 serving as a channel forming region is formed.
A step of forming A, and a step of forming an n + type semiconductor region 6A, which is a source region, with the n type impurity 6 introduced in the main surface of the p type semiconductor region 5A in self-alignment with the gate electrode 3A. Prepare

As a result, since the gate electrode 3A and the gate opening 3B are formed in the same process, the gate electrode 3A
It is possible to prevent the displacement of the gate opening 3B with respect to. As a result, the n-type semiconductor region 4A which is a low resistance region
In the case where the gate electrode is not formed, the p-type semiconductor region 5A which is the channel formation region and the gate electrode do not overlap with each other.
Of the MISFETQ, it is possible to prevent the deterioration of the junction breakdown voltage at the pn junction between the channel formation region (p-type semiconductor region 5A) and the drain region (n-type epitaxial layer 1B) of the MISFETQ. You can

Further, since the channel layer is surely formed, it is possible to prevent the threshold voltage of the MISFET Q from changing.

Further, since the channel layer is surely formed, a plurality of MISFEs mounted on the power transistor are mounted.
The electrical characteristics of each TQ can be made uniform.

(2) In the method of manufacturing a power transistor (semiconductor device) described in (1) above, the power transistor (semiconductor device) is introduced into the first region of the main surface of the n − type epitaxial layer 1B, which is the drain region, through the gate opening 3B. N-type impurities 4
Then, a step of forming the n-type semiconductor region 4A which is a low resistance region is provided.

As a result, displacement of the gate opening 3B with respect to the gate electrode 3A can be prevented, and displacement of the n-type semiconductor region 4A, which is a low resistance region, can be prevented. As a result, the n-type semiconductor region 4A which is a low resistance region and the p-type semiconductor region 5A which is a channel forming region are formed.
Since it is possible to suppress the occurrence of the overlapping region (15) in which the and are overlapped with each other, it is possible to prevent the punch through breakdown voltage of the MISFET Q from being deteriorated.

The planar shape of the gate opening 3B is
As shown in FIG. 12 (plan view of the main part), it may be formed in a polygonal shape close to a circle.

Further, the gate opening 3B is formed in the structure shown in FIGS.
As shown in FIG. 5, the pattern opening 3C is arranged at the center. This is because the p-type semiconductor region 5A which is the channel forming region is composed of the p-type impurity 5 introduced through the pattern opening 3C, and the n-type semiconductor region 4A which is the low resistance region is introduced through the gate opening 3B. It is essential that the gate opening 3B and the pattern opening 3C are geometrically equidistant. If the plane area of the gate opening 3B is increased, the gate capacitance and ON resistance can be reduced, but the gate resistance will increase. On the contrary, if the gate opening 3B is made smaller, the gate capacitance and the on-resistance cannot be made smaller. As shown in FIG. 2 and FIG. 12, in the case of the MISFET Q having the triangular arrangement, if the planar shape of the gate opening 3B is a triangle or a polygon close to a circle, the above condition can be satisfied.

(Embodiment 2) FIGS. 13 to 17 show
FIG. 6 is a cross-sectional view for explaining the method for manufacturing the power transistor (semiconductor device) according to the second embodiment of the present invention.

First, a semiconductor substrate 1 in which an n-type epitaxial layer (first conductivity type semiconductor region) 1B is formed on the main surface of an n + type semiconductor substrate 1A made of single crystal silicon is prepared.

Next, a thermal oxidation process is performed to form a gate insulating film 2 made of a thermal silicon oxide film on the main surface of the n − type epitaxial layer 1B.

Next, as in the first embodiment, the n-
A conductive film (3) is formed on the main surface of the type epitaxial layer 1B with the gate insulating film 2 interposed.

Next, the conductive film (3) is patterned to form a gate electrode 3A on the first region of the main surface of the n--type epitaxial layer 1B, and the gate electrode 3A is covered with a gate insulating film. A gate opening 3B is formed to expose a part of the main surface of 3A. In this step, since the gate electrode 3A and the gate opening 3B are formed in the same step, the displacement of the gate opening 3B with respect to the gate electrode 3A can be prevented. Note that this patterning step is performed by an etching technique using a mask made of a photoresist film as an etching mask, as in the first embodiment described above.

Next, the n-type impurity 4 is selectively introduced into the first region of the main surface of the n-type epitaxial layer 1B through the gate opening 3B, and the first surface of the main surface of the n-type epitaxial layer 1B is removed. The n-type impurity 4 is selectively introduced into the two regions in self-alignment with the gate electrode 3A. This n-type impurity 4 is, as shown in FIG.
Is introduced by an ion implantation method using as a mask for introducing impurities. The n-type impurity 4 is introduced, for example, under the condition that the final introduction amount is set to about 10 ¹¹ to 10 ¹² [atoms / cm ² ].

Next, the introduction amount of the n-type impurity 4 was set higher than the introduction amount of the n-type impurity 4 in self-alignment with the gate electrode 3A in the second region of the main surface of the n-type epitaxial layer 1B. The p-type impurity 5 is selectively introduced. As shown in FIG. 14, the p-type impurity 5 is introduced by an ion implantation method using the mask 30 covering the gate opening 3B and the gate electrode 3A as an impurity introduction mask. p
The type impurity 5 has, for example, a final introduction amount of 10 ¹³ to 10 10.
It is introduced under the conditions set to about ¹⁴ [atoms / cm ² ]. The mask 30 is formed of, for example, a photoresist film formed by a photolithography technique.

Next, as shown in FIG. 15, a thermal diffusion process is applied to the first region of the main surface of the n − type epitaxial layer 1B, and the n type impurity 4 is added to the n type semiconductor which is a low resistance region. The n-type epitaxy layer 1 is formed while forming the region 4A.
A p-type semiconductor region 5A is formed of the p-type impurity 5 in the second region of the main surface of B. In this step, the n-type impurity 4 and the p-type impurity 5 are respectively introduced into the second region of the main surface of the n − -type epitaxial layer 1B, but the p-type impurity 5 is introduced in the second region on the main surface. Since it is about one digit higher than the introduced amount, p is formed in the second region of the main surface of the n-type epitaxial layer 1B.
The type semiconductor region 5A is formed. In addition, the gate electrode 3A
Since the gate opening 3B is prevented from being displaced relative to the gate opening 3B, it is possible to prevent the displacement of the n-type semiconductor region (low resistance region) 4A made of the n-type impurity 4 introduced through the gate opening 3B.

Next, an n-type impurity 6 is selectively introduced into a part of the main surface of the p-type semiconductor region 5A in self-alignment with the gate electrode 3A. As shown in FIG. 16, the n-type impurity 6 is introduced into the gate electrode 3A and the mask 31 that covers the gate opening 3B and covers the other region of the main surface of the p-type semiconductor region 5A. It is introduced by the ion implantation method used as a mask. The final introduction amount of the n-type impurity 6 is, for example, 10 ¹⁵ to 10 ¹⁶ [at
oms / cm ² ]. The mask 31 is formed of, for example, a photoresist film formed by a photolithography technique.

Next, a thermal diffusion process is performed, and as shown in FIG. 17, a part of the main surface of the p-type semiconductor region 5A is
The n-type impurity 6 forms the n + -type semiconductor region 6A which is the source region. Through this step, the n-type semiconductor region (low resistance region) 4A and the n + -type semiconductor region (channel formation region) 6
MISFET whose channel length is defined by the distance from A
Q is formed.

Next, as in the first embodiment, the interlayer insulating film (7), the connection hole (8), the p + type semiconductor region (9) which is a contact region, the source wiring (10A), and the gate wiring (10).
By forming each of B), the final protective film 11 and the drain electrode 12, the power transistor having the MISFET Q is almost completed.

In the manufacturing process described above, the step of the n-type semiconductor region 4A may be omitted.

As described above, according to this embodiment, the same effect as that of the first embodiment can be obtained, and the n-type impurity 4 is formed through the gate opening 3B in the first region of the main surface of the n-type epitaxial layer 1B. Since the mask used for selectively introducing can be eliminated, one photolithography process (coating, baking process, exposure process, development process, etc.) can be eliminated as compared with the first embodiment.

(Embodiment 3) FIGS. 18 to 22 show
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the power transistor (semiconductor device) according to the third embodiment of the present invention.

First, a semiconductor substrate 1 in which an n--type epitaxial layer (first conductivity type semiconductor region) 1B is formed on the main surface of an n + type semiconductor substrate 1A made of single crystal silicon is prepared.

Next, a thermal oxidation process is performed to form a gate insulating film 2 made of a thermal silicon oxide film on the main surface of the n--type epitaxial layer 1B.

Next, as in the first embodiment, the n-
A conductive film (3) is formed on the main surface of the type epitaxial layer 1B with the gate insulating film 2 interposed.

Next, the conductive film (3) is patterned to form a gate electrode 3A on the first region of the main surface of the n--type epitaxial layer 1B, and the gate electrode 3A is covered with a gate insulating film. An opening 3B is formed to expose a part of the main surface of 3A. In this step, since the gate electrode 3A and the gate opening 3B are formed in the same step, the displacement of the gate opening 3B with respect to the gate electrode 3A can be prevented. Note that this patterning step is performed by an etching technique using a mask made of a photoresist film as an etching mask, as in the first embodiment described above.

Next, the p-type impurity 5 is selectively introduced into the second region of the main surface of the n-type epitaxial layer 1B in self-alignment with the gate electrode 3A. This p-type impurity 5
18 is introduced by an ion implantation method using the mask 40 covering the gate opening 3B and the gate electrode 3A as an impurity introduction mask, as shown in FIG. The p-type impurity 5 has, for example, a final introduction amount of 10 ¹³ to 10 ¹⁴ [atom
s / cm ² ].
The mask 40 is formed of, for example, a photoresist film formed by a photolithography technique.

Then, a thermal diffusion process is performed, and as shown in FIG. 19, the p-type impurity 5 is added to the second region of the main surface of the n − -type epitaxial layer 1B to form a p-type semiconductor which is a channel forming region. Region 5A is formed.

Then, the n-type impurity 6 is selectively introduced into a part of the main surface of the p-type semiconductor region 5A in self-alignment with the gate electrode 3A. As shown in FIG. 20, the n-type impurity 6 is introduced into the mask 41 and the gate electrode 3A that cover the gate opening 3B and cover the other region of the main surface of the p-type semiconductor region 5A. It is introduced by the ion implantation method used as a mask. The final introduction amount of the n-type impurity 6 is, for example, 10 ¹⁵ to 10 ¹⁶ [at
oms / cm ² ]. The mask 41 is formed of, for example, a photoresist film formed by a photolithography technique.

Next, a thermal diffusion process is performed, and the n-type impurity 6 is added to a part of the main surface of the p-type semiconductor region 5A.
An n + type semiconductor region 6A which is a source region is formed.

Next, a thermal oxidation process is performed to form the accelerated oxide insulating film 13 on the main surface of the n + type semiconductor region 6A. In this step, the accelerated oxidation insulating film is formed on the other region of the main surface of the p-type semiconductor region 5A and also on the first region of the main surface of the n − type epitaxial layer 1B. Since the growth rate of the film varies depending on the impurity concentration, the film thickness of the accelerated oxidation insulating film 13 formed on the main surface of the n + type semiconductor region 6A having a high impurity concentration is the same as that of the p type semiconductor region 5A having a low impurity concentration. It becomes thicker than the film thickness of the accelerated oxidation insulating film formed on the other region of the surface and on the first region of the main surface of the n − type epitaxial layer 1B. The accelerated oxide insulating film 13 is also formed on the surface of the gate electrode 3A that is not covered with the mask 41 in the previous step.

Next, the n-type impurity 4 is selectively introduced into the first region of the main surface of the n-type epitaxial layer 1B through the gate opening 3B. This n-type impurity 4 is shown in FIG.
As shown in FIG. 3, the ion implantation method is used in which the accelerated oxide insulating film 13 and the gate electrode 3A are used as a mask for introducing impurities. The n-type impurity 4 is introduced, for example, under the condition that the final introduction amount is set to about 10 ¹¹ to 10 ¹² [atoms / cm ² ]. In this process, p
The n-type impurity 4 is formed in the other region of the main surface of the type semiconductor region 5A.
Is introduced.

Next, the interlayer insulating film 7 and the connection hole 8 are formed similarly to the first embodiment.

Next, a p-type impurity is selectively introduced into the main surface of the p-type semiconductor region 5A through the connection hole 8 by an ion implantation method. This p-type impurity is introduced, for example, under the condition that the final introduction amount is set to about 10 ¹⁵ to 10 ¹⁶ [atoms / cm ² ].

Next, as shown in FIG. 22, a thermal diffusion process is applied to the first region of the main surface of the n--type epitaxial layer 1B by the n-type impurity 4 and the n-type semiconductor which is a low resistance region. While forming the region 4A, a p + type semiconductor region 9 which is a contact region is formed of the p type impurity on the main surface of the p type semiconductor region 5A. In this step, the n-type impurity 4 and the p-type impurity are introduced into the main surface of the p-type semiconductor region 5A, respectively. Since it is slightly high, the p + type semiconductor region 9 is formed on the main surface of the p type semiconductor region 5A. Also,
In this step, since the displacement of the gate opening 3B with respect to the gate electrode 3A is prevented, the gate opening 3B is prevented.
It is possible to prevent the displacement of the n-type semiconductor region (low resistance region) 4 </ b> A made of the n-type impurity 4 introduced through. By this process, the n-type semiconductor region (low resistance region) 4A
A MISFET Q whose channel length is defined by the distance between the n + type semiconductor region (channel forming region) 6A and the n + type semiconductor region (channel forming region) 6A is formed.

Then, similarly to the first embodiment, the source wiring (10A), the gate wiring (10B) and the final protective film (1
1) By forming the drain electrode 12 respectively, the power transistor having the MISFET Q is almost completed.

In the manufacturing process described above, the step of n-type semiconductor region 4A may be omitted.

As described above, according to this embodiment, the same effect as that of the first embodiment can be obtained, and the n-type impurity 4 is formed in the first region of the main surface of the n--type epitaxial layer 1B through the gate opening 3B. Since it is possible to eliminate the photoresist mask when selectively introducing the photolithography process, the photolithography process (coating, baking process,
Exposure process, development process, etc.) can be eliminated by one step.

The inventions made by the present inventors are as follows.
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above embodiment, and various changes can be made without departing from the scope of the invention.

For example, according to the present invention, as shown in FIGS. 23 and 24 (planar views of the main part of the gate electrode), a MIS in which a gate opening 3B is formed in a stripe-shaped gate electrode 3A.
It can be applied to a power transistor having a FET.

[0099] Further, the present invention, equivalent circuit, pnp-type bipolar transistor, IGBT (I nsulated G constituted by respective MISFET ate B ipolar T ransisto
It can be applied to a power transistor (semiconductor device) having r).

[0100]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

It is possible to prevent the punch through breakdown voltage of the MISFET mounted on the power transistor (semiconductor device) from being deteriorated.

It is possible to prevent deterioration of the junction breakdown voltage at the pn junction between the channel formation region and the drain region of the MISFET mounted on the power transistor (semiconductor device).

MISF mounted on power transistor
It is possible to prevent fluctuations in the threshold voltage of ET.

[Brief description of the drawings]

FIG. 1 is a chip layout diagram of a power transistor according to a first embodiment of the present invention.

FIG. 2 is a plan view of an essential part of the power transistor.

3 is a cross-sectional view taken along the line AA shown in FIG.

FIG. 4 is a cross-sectional view of a main part for explaining a method for manufacturing the power transistor.

FIG. 5 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 6 is a cross-sectional view of a main part for explaining a method for manufacturing the power transistor.

FIG. 7 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 8 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 9 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 10 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 11 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 12 is a MIS mounted on the power transistor.
It is a principal part top view which shows the modification of the gate electrode of FET.

FIG. 13 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor according to the second embodiment of the present invention.

FIG. 14 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 15 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 16 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 17 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 18 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor according to the third embodiment of the present invention.

FIG. 19 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 20 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 21 is a main-portion cross-sectional view for illustrating the method for manufacturing the power transistor.

FIG. 22 is a fragmentary cross-sectional view for explaining the method for manufacturing the power transistor.

FIG. 23: MISFE mounted on a power transistor
It is a principal part top view which shows the modification of the gate electrode of T.

FIG. 24: MISFE mounted on a power transistor
It is a principal part top view which shows the modification of the gate electrode of T.

FIG. 25 is a main-portion cross-sectional view for illustrating the conventional method for manufacturing the power transistor.

FIG. 26 is a main-portion cross-sectional view for illustrating the conventional method for manufacturing a power transistor.

FIG. 27 is a main-portion cross-sectional view for illustrating the conventional method for manufacturing a power transistor.

FIG. 28 is a main-portion cross-sectional view for illustrating the conventional method for manufacturing the power transistor.

FIG. 29 is a cross-sectional view of a main part for explaining a conventional method for manufacturing a power transistor.

FIG. 30 is a main-portion cross-sectional view for illustrating the conventional method for manufacturing a power transistor.

FIG. 31 is a main-portion cross-sectional view for illustrating the conventional method for manufacturing a power transistor.

FIG. 32 is a main-portion cross-sectional view for explaining the problem of the conventional power transistor.

FIG. 33 is a main-portion cross-sectional view for explaining the problem of the conventional power transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1A ... n + type semiconductor substrate, 1B ... n- type epitaxial layer, 2 ... Gate insulating film, 3 ... Conductive film, 3A
... gate electrode, 3B ... gate opening, 3C ... pattern opening, 4 ... n type impurity, 4A ... n type semiconductor region (low resistance region), 5 ... p type impurity, 5A ... p type semiconductor region (channel forming region), 6 ... n-type impurities, 6A ... n + type semiconductor region (source region), 7 ... interlayer insulating film, 8 ... connection hole, 9 ... p + type semiconductor region, 10A ... source wiring, 10B ... gate wiring,
11 ... Final protective film, 12 ... Drain electrode, 13 ... Accelerated oxide insulating film, 14 ... Overlap region, 15 ... Blind region, 16 ... Semiconductor chip forming region.

Claims (9)

[Claims] 1. A method of manufacturing a semiconductor device having a MISFET, comprising the following steps (a) to (d) manufacturing methods. (A) A step of forming a conductive film with a gate insulating film interposed on the main surface of the first-conductivity-type semiconductor region, which is the drain region,
(B) a step of patterning the conductive film to form a gate electrode on the first region of the main surface of the first-conductivity-type semiconductor region, and forming a gate opening in the gate electrode; The second main surface of the semiconductor region of the first conductivity type
Forming a second-conductivity-type semiconductor region, which is a channel forming region, with a second-conductivity-type impurity introduced into the region in a self-aligned manner with respect to the gate electrode; Forming a first-conductivity-type semiconductor region, which is a source region, on the main surface of the first-conductivity-type impurity introduced in self-alignment with the gate electrode. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first conductivity type semiconductor layer is introduced into the first region of the main surface of the first conductivity type semiconductor region, which is the drain region, through the gate opening. A method of manufacturing a semiconductor device, comprising a step of forming a first conductivity type semiconductor region, which is a low resistance region, with impurities. 3. A method of manufacturing a semiconductor device having a MISFET, comprising the following steps (a) to (f): (A) a step of forming a conductive film on the main surface of a first semiconductor region of the first conductivity type, which is a drain region, with a gate insulating film interposed; (b) patterning the conductive film to form the first conductive film; Forming a gate electrode on the first region of the main surface of the first semiconductor region of the first type, and forming a gate opening in the gate electrode, (C) the main surface of the first semiconductor region of the first conductivity type Selectively introducing a first impurity of a first conductivity type into a first region through the gate opening; (d) the first
A step of selectively introducing a second impurity of the second conductivity type into the second region of the main surface of the first semiconductor region of the conductivity type in a self-aligned manner with respect to the gate electrode; First
The first impurity of the conductivity type forms the second semiconductor region of the first conductivity type which is a low resistance region, and the second impurity of the second conductivity type forms the third semiconductor of the second conductivity type which is the channel formation region.
Forming a semiconductor region, (f) selectively introducing a third impurity of the first conductivity type into the main surface of the third semiconductor region of the second conductivity type by self-alignment with the gate electrode. 1
A step of forming a fourth semiconductor region of a first conductivity type, which is a source region, with a third impurity of a conductivity type. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the first impurity of the first conductivity type covers the second region of the main surface of the first semiconductor region of the first conductivity type. 1 mask and the second electrode of the second conductivity type, which is introduced by an ion implantation method using the gate electrode as an impurity introduction mask, the second mask that covers the gate opening and the gate electrode is an impurity introduction mask. And the third impurity of the first conductivity type is introduced by an ion implantation method using the third mask covering the gate opening and the gate electrode as an impurity introduction mask. A method for manufacturing a semiconductor device, comprising: 5. A method of manufacturing a semiconductor device having a MISFET, comprising the following steps (a) to (f): (A) a step of forming a conductive film on the main surface of a first semiconductor region of the first conductivity type, which is a drain region, with a gate insulating film interposed; (b) patterning the conductive film to form the first conductive film; Forming a gate electrode on the first region of the main surface of the first semiconductor region of the first type, and forming a gate opening in the gate electrode, (C) the main surface of the first semiconductor region of the first conductivity type A first impurity of the first conductivity type is selectively introduced into the first region through the gate opening, and self-aligned with the gate electrode in the second region of the main surface of the first semiconductor region of the first conductivity type. Selectively introducing the first impurity of the first conductivity type with (d) the second region of the main surface of the first semiconductor region of the first conductivity type is self-aligned with the gate electrode in the second region. The introduction amount is set higher than the introduction amount of the first conductivity type impurity. A step of selectively introducing a second impurity of the second conductivity type, and (e) a thermal diffusion treatment, and a second semiconductor region of the first conductivity type that is the first impurity of the first conductivity type and is a low resistance region. And forming a second conductive type second
Forming a second conductive type third semiconductor region, which is a channel forming region, with impurities; (f) the second conductive type third
A third impurity of the first conductivity type is selectively introduced into the main surface of the semiconductor region in self-alignment with the gate electrode, and the third impurity of the first conductivity type is used to remove the impurities of the first conductivity type of the source region. A step of forming a fourth semiconductor region. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the first impurity of the first conductivity type is introduced by an ion implantation method using the gate electrode as an impurity introduction mask, and the second impurity is added. The second impurity of the conductive type is introduced by an ion implantation method using the first mask covering the gate opening and the gate electrode as a mask for introducing impurities, and the third impurity of the first conductive type is added to the gate opening. A method of manufacturing a semiconductor device, characterized by being introduced by an ion implantation method using the second mask covering the above and the gate electrode as a mask for introducing impurities. 7. A method of manufacturing a semiconductor device having a MISFET, comprising the following steps (a) to (h): (A) a step of forming a conductive film on the main surface of a first semiconductor region of the first conductivity type, which is a drain region, with a gate insulating film interposed; (b) patterning the conductive film to form the first conductive film; Forming a gate electrode on the first region of the main surface of the first semiconductor region of the first type, and forming a gate opening in the gate electrode, (C) the main surface of the first semiconductor region of the first conductivity type A step of selectively introducing a first impurity of a second conductivity type into the second region in self-alignment with the gate electrode;
(D) A step of performing a thermal diffusion process to form a second conductive type second semiconductor region which is a channel forming region with the second conductive type first impurity, and (e) a second conductive type second semiconductor region. A second impurity of the first conductivity type is selectively introduced into the main surface of the semiconductor region in a self-aligned manner with respect to the gate electrode, and the second impurity of the first conductivity type is used to remove the impurities of the first conductivity type of the source region. Forming a third semiconductor region; (f) performing a thermal oxidation process to form an accelerated oxide insulating film on the first conductive type second semiconductor region; (g) the first conductive type first A third region of the first conductivity type through the gate opening in the first region of the main surface of the first semiconductor region;
A step of selectively introducing impurities, and (h) a step of performing a thermal diffusion treatment to form a third semiconductor of the first conductivity type and a fourth semiconductor area of the first conductivity type which is a low resistance area. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the first impurity of the second conductivity type uses the first mask covering the gate opening and the gate electrode as an impurity introduction mask. Introduced by the ion implantation method,
The second impurity of the first conductivity type is introduced by an ion implantation method using the second mask covering the gate opening and the gate electrode as a mask for introducing impurities, and the third impurity of the first conductivity type is A method of manufacturing a semiconductor device, wherein the accelerated oxide insulating film and the gate electrode are introduced by an ion implantation method using the mask as an impurity introduction mask. 9. Any one of claims 1 to 8.
The method of manufacturing a semiconductor device according to the item 1, wherein:
The method of manufacturing a semiconductor device is characterized in that the FETs are arranged in a triangular arrangement, and the planar shape of the openings is formed in a triangular shape or a polygonal shape close to a circle.