JP3344381B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a plurality of unit cells having a rectangular trench structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art MOSFETs (Metal Oxide Semiconductors) are one type of power devices that handle relatively large currents and voltages.
ductor Field Effect Transistor).
Since this MOSFET is a voltage-controlled device, it has an advantage that an input current for control is unnecessary. Also, in principle, it operates using only one of electrons or holes as majority carriers, so it has no carrier accumulation effect, so it has excellent switching characteristics and punch-through resistance, and inductive loads such as switching regulators It is often applied to.

In such a MOSFET, an initial lateral MOSF is designed so that an operating current (drain current) flows in a lateral direction (horizontal direction) of a semiconductor substrate.
Vertical MOSFET designed to allow drain current to flow in the vertical direction (vertical direction) of the semiconductor substrate with respect to ET
Has been widely used. According to this vertical MOSFET, since it is possible to design a MOSFET by connecting a number of unit cells in parallel, there is an advantage that the current capacity can be increased.

In the above vertical MOSFET,
What formed each unit cell so as to have a trench structure, that is, a vertical MOSFET having a so-called trench structure has been widely used. This vertical MOSFET with trench structure
According to T, by forming the channel in the vertical direction along the side surface of the trench, it is possible to miniaturize the cell while utilizing the advantages such as excellent applicability to inductive load as described above, The resistance can be reduced.

FIG. 12 and FIG. 13 show a conventional configuration.
FIG. 12 shows a vertical MOSFET having a trench structure.
FIG. 13 is a plan view, and FIG. 13 is a sectional view taken along the line FF in FIG. same
As shown in FIG. 12 and FIG.
For example, n⁺Type semiconductor substrate (high impurity concentration semiconductor substrate) 5
1 has an impurity concentration lower than that of the semiconductor substrate 51.
N consisting of an axial layer^-Semiconductor layer (low impurity concentration semiconductor)
(Body layer) 52 is formed to form an n-type drain region 53.
N which becomes a part of the n-type drain region 53^-Mold semiconductive
A p-type impurity is ion-implanted into the body layer 52 to form a p-type impurity.
Source region 54 is formed, and the periphery of p-type base region 54 is formed.
Surrounded by n^-Trench 55 reaching the depth of the semiconductor layer 52
Is formed, and a gate oxide film 56 is
As a result, a gate electrode 57 made of a polysilicon film is formed.
The n-type impurity is ionized on the surface of the p-type base region 54.
It is implanted and has an endless n along the trench 55. ⁺Mold
Rectangular trenches formed with source regions 58
It is constituted by a unit cell 59 having a structure.

The surface of the unit cell 59 is covered with an interlayer insulating film 62, and a source and base contact opening 63 is formed in the interlayer insulating film 62. Through this opening 63, the p-type base region 54 and the n ⁺ -type A source electrode 64 made of, for example, an aluminum alloy and connected to the source region 58 is formed.

As described above, the vertical MOSF having the trench structure is formed.
ET is expected to reduce the channel resistance and to improve the element breakdown resistance when applied to an inductive load. Here, the element breakdown tolerance is a measure of how much current flows when the element breaks down when a reverse breakdown voltage is applied between the drain and source due to the connection of the inductive load, and is high. It is desirable that a value be obtained.

Incidentally, in the conventional semiconductor device shown in FIGS. 12 and 13, the connection of the drain
When a reverse breakdown voltage is applied between the sources and the device breaks down, the breakdown occurs first at the cell corners 65 at the four corners of the unit cell 59 where the trenches 55 intersect and the electric field is concentrated. Since the parasitic bipolar transistor formed by the n-type drain region 53, the p-type base region 54, and the n ⁺ -type source region 58 is turned on by the breakdown current, the above-described disadvantage that the element breakdown resistance decreases. Occurs.

A vertical MOSFET having a trench structure in which the above-described element breakdown resistance is prevented from being reduced.
Is disclosed, for example, in Japanese Patent No. 2894820. 9 to 11 show the same vertical MOSFET.
10 is a plan view, FIG. 10 is a sectional view taken along the line DD of FIG. 9, and FIG. 11 is a sectional view taken along the line EE of FIG. Vertical MOSFET
As shown in FIGS. 9 to 11, as shown in FIGS. 9 to 11, an n ⁺ -type source region 58 is formed in a cell corner 65 by forming a p-type region 66 in a cell corner 65 at four corners of a unit cell 59 where an electric field is concentrated It does not have a structure. According to this structure, even if a breakdown current flows through the current paths d and e extending from the drain region 53 to the side surface (channel layer) of the base region 54 and the surface of the base region 54, the source region 58 is formed in the cell corner 65. Does not exist,
Since the above-mentioned parasitic bipolar transistor is hard to be turned on, it is possible to improve the element breakdown resistance. In FIGS. 9 to 11, the same parts as those in FIGS. 12 and 13 are denoted by the same reference numerals and description thereof is omitted.

[0010]

However, in the semiconductor device described in Japanese Patent No. 2894820, the channel layer is not formed at the cell corner because the source region is not formed at the cell corner of the unit cell. Therefore, there is a problem that the channel resistance increases. That is, in the semiconductor device described in the above publication, since the source region 58 does not exist in the cell corner 65, it is possible to contribute to the improvement of the element breakdown resistance by that much. Since the width of the channel layer is reduced due to the interruption of the path, the channel resistance is sacrificed and an increase in the channel resistance cannot be avoided.

Further, the semiconductor device described in the above publication is suitable for cell miniaturization because the source region 58 does not exist in the cell corner portion 65, and the degree of reduction in channel width increases with cell miniaturization. No structure.

The present invention has been made in view of the above circumstances, and has a structure suitable for miniaturization of cells, and improves the element breakdown resistance at the time of reverse breakdown breakdown without sacrificing channel resistance. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which are capable of performing the following.

[0013]

According to a first aspect of the present invention, a second conductive type base region is formed adjacent to a first conductive type drain region. A trench is formed, a gate electrode is formed in the trench via a gate insulating film, and an endless first conductivity type source region is formed on the surface of the base region along the trench. In a semiconductor device including a unit cell having a rectangular trench structure, a source non-forming region is formed in a cell central portion on a rectangular surface of the unit cell and a cell diagonal portion radially extending from a periphery of the cell central portion. It is characterized by having been provided.

According to a second aspect of the present invention, a second conductivity type base region is formed adjacent to the first conductivity type drain region, a trench is formed around the base region, and a gate insulating film is formed in the trench. A gate electrode is formed through the first region, and an endless first electrode is formed on the surface of the base region along the trench.
The present invention relates to a semiconductor device including a plurality of unit cells having a rectangular trench structure in which a conductive type source region is formed, wherein the source region is provided on a diagonal of a cell on a rectangular surface of the unit cell and at a position near the diagonal of the cell. Is characterized in that a source region constriction portion for partially limiting the planar width dimension of the source region is formed.

According to a third aspect of the present invention, there is provided the semiconductor device according to the second aspect, wherein a surface of the unit cell is covered with an interlayer insulating film, and source and base contact openings are formed in the interlayer insulating film. A source electrode is formed through the source and base contact openings.

According to a fourth aspect of the present invention, there is provided the semiconductor device according to the third aspect, wherein the source region confinement portion extends from the source and base contact openings of the interlayer insulating film to the cell corner on the diagonal line of the cell. The source region is formed so as to narrow the source region by an arbitrary dimension.

According to a fifth aspect of the present invention, there is provided the semiconductor device according to the second aspect, wherein the source region constricted portion has a higher impurity concentration than the base region at a part of a position where the source region is to be formed. The semiconductor device is characterized in that the source region is formed after a two-conductivity type semiconductor region is formed in advance.

According to a sixth aspect of the present invention, a second conductivity type base region is formed adjacent to the first conductivity type drain region, a trench is formed around the base region, and a gate insulating film is formed in the trench. A gate electrode is formed through the first region, and an endless first electrode is formed on the surface of the base region along the trench.
The present invention relates to a method of manufacturing a semiconductor device comprising a plurality of unit cells having a rectangular trench structure in which a source region of a conductivity type is formed, wherein the first conductivity type semiconductor substrate has a first conductivity type having a lower impurity concentration than the semiconductor substrate. A drain region forming step of forming a semiconductor layer to form a drain region; and a trench forming step of forming a trench in the first conductivity type semiconductor layer at a position around the base region and dividing the trench into a plurality of unit cells. Forming a second conductivity type base region over the entire surface of the first conductivity type semiconductor layer surrounded by the trench; and selectively forming an endless first end on the surface of the second conductivity type base region. While forming a conductive type source region,
A source region forming step of selectively forming a source region constricted portion that partially limits a planar width dimension of the source region on a cell diagonal line which is a rectangular surface of the unit cell and at a position near the cell diagonal line. It is characterized by including.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the step of forming the source region extends radially from a central portion of the cell of the base region and a periphery of the central portion of the cell. The method is characterized in that a photoresist film patterned into a planar shape composed of cell diagonal portions is formed on the base region, and then the first conductivity type impurity is introduced using the photoresist film as a mask.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the step of forming the source region comprises a cell diagonal portion radially extending from a periphery of a cell central portion of the base region. After a first photoresist film patterned in a planar shape is formed on the base region, impurities of a second conductivity type are introduced using the first photoresist film as a mask so as to have a higher impurity concentration than the base region. A second photoresist film patterned into a planar shape comprising a cell central portion of the base region and a cell diagonal portion extending radially from the periphery of the cell central portion. After being formed thereon, the second photoresist film is used in combination with a second impurity introduction step in which a first conductivity type impurity is introduced using the second photoresist film as a mask. It is characterized by a door.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the sixth, seventh or eighth aspect, wherein a gate is provided on at least a side surface of the trench between the trench forming step and the base region forming step. After the formation of the insulating film, a gate electrode forming step of forming a gate electrode in the trench via the gate insulating film is included.

The invention according to claim 10 is the invention according to claims 6 to 9
In the method of manufacturing a semiconductor device according to any one of the above, the introduction of the first conductivity type or the second conductivity type impurity in the base region forming step and the source region forming step is performed by an ion implantation method. .

[0023]

Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using an embodiment. First Embodiment FIG. 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA of FIG. 1, and FIG. 3 is a line BB of FIG. 4 to 6 are sectional views showing a method of manufacturing the same semiconductor device in the order of steps. The semiconductor device 10 of this example has, for example, n
^{On a +} type semiconductor substrate (high impurity concentration semiconductor substrate) 1, an n ⁻ type semiconductor layer (low impurity concentration semiconductor layer) 2 composed of an epitaxial layer having a lower impurity concentration than the semiconductor substrate 1 is formed to form an n type drain region. A p-type impurity is ion-implanted into the n ⁻ -type semiconductor layer 2 which is a part of the n-type drain region 3 to form a p-type base region 4. Is the n ^- type semiconductor layer 2
Is formed, a gate electrode 7 made of a polysilicon film is formed in the trench 5 via a gate oxide film 6, and an n-type impurity is ion-implanted into the surface of the p-type base region 4. An endless n ⁺ -type source region 8 is formed along the trench 5 and includes a plurality of unit cells 9 having a rectangular trench structure.

As shown in FIGS. 1 and 3, the n ⁺ -type source region 8 is formed on a diagonal line L on the rectangular surface of the unit cell 9 and at a position near the diagonal line L, that is, at a cell corner portion 15. A source region narrowing portion 11 that partially limits the width W1 is formed. The source region narrowing portion 11 has, for example, a planar width dimension W on the diagonal line L.
2 (W2 <W1). That is, the unit cell 9
A source non-formation region is provided at a cell central portion and a cell diagonal portion radially extending from the four corners of the cell central portion on the rectangular surface of FIG. As described above, the planar width W1 of the endless n ⁺ -type source region 8 is partially limited to the width W2, particularly at the cell corner portion 15 on the rectangular surface of the unit cell 9, so that the channel of the element is reduced. It is possible to improve the element breakdown resistance during reverse breakdown breakdown without sacrificing resistance.

The surface of the unit cell 9 is covered with an interlayer insulating film 12 made of a silicon oxide film, and a source and base contact opening 13 is formed in the interlayer insulating film 12, and a p-type base region is formed through the opening 13. A source electrode 14 made of, for example, an aluminum alloy is formed to connect the source electrode 4 to the n ⁺ type source region 8.

In order to operate the semiconductor device 10 of this embodiment, a positive voltage equal to or higher than the threshold value is applied to the gate electrode 7 while a positive voltage is applied to the n ⁺ source region 8 and the n type drain region 3. When a voltage is applied, a channel layer is induced on the side surface of the trench 5, so that the n ⁺ -type source region 8 and the n-type drain region 3 conduct, and the element is turned on. On the other hand, when the voltage applied to the gate electrode 7 is equal to or lower than the threshold value, the channel layer disappears and the device is turned off.

In the semiconductor device 10 of this embodiment, when a reverse breakdown voltage is applied between the drain and the source due to the connection of the inductive load and the device breaks down, as shown in FIG. At the position, a current path a from the drain region 3 to the side surface (channel layer) of the base region 4 and the surface of the base region 4 is formed, causing a breakdown current to flow, and as shown in FIG.
In the cell corner portion 15 of the unit cell 9, a similar current path b is formed, and a breakdown current flows. Here, the breakdown occurs first at the cell corner portion 15 where the trench 5 of the unit cell 9 intersects and the electric field is concentrated, so that the breakdown in the current path b determines the element breakdown withstand capability. Become.

As is clear from FIGS. 1 and 3, the planar width of the source region 8 can be reduced substantially by (W 1 -W) at the cell corner 15 by forming the source region constricted portion 11.
2), the current path b
2, the distance from the drain region 3 to the source electrode 14 is shorter than that of the current path a in FIG. 2, and the current path b is formed on the surface of the base region 4 where the resistance is low. Therefore, a voltage drop when a current flows in the base region 4 is reduced, so that it is difficult to turn on the parasitic bipolar transistor. Therefore, the element breakdown resistance can be improved.

In this example, when the element is turned on, the source region 8 formed along the trench 5
Since there is no interruption due to the continuous formation through the source region narrowing portion 11, the channel width of the source region 8 can be increased by maintaining the endless shape, and the channel resistance is reduced. be able to. In addition, since the source region 8 exists in the cell corner 15, a structure suitable for miniaturization of the cell can be obtained. Therefore, according to this example, it has a structure suitable for cell miniaturization and without sacrificing the channel resistance.
It is possible to improve the element breakdown resistance at the time of reverse breakdown voltage breakdown.

Next, a method of manufacturing the same semiconductor device will be described in the order of steps with reference to FIGS. FIG.
6A to 6A are cross-sectional views corresponding to the cross-sectional view taken along the line AA of FIG. 1, and FIG. 6B are cross-sectional views corresponding to the cross-sectional view taken along the line BB of FIG. 1. . (A) and (b)
Although the two-dimensional dimensions actually differ from each other, they are shown with substantially the same dimensions to simplify the description. First, FIG.
As shown in (a) and (b), for example, an n ⁺ -type semiconductor substrate 1 is used, and an n ⁻ -type semiconductor layer 2 having a lower impurity concentration is epitaxially grown on the semiconductor substrate 1 to form a drain region 3. Form. Next, a trench 5 is formed in the n ⁻ -type semiconductor layer 2 at a position around a p-type base region 3 to be described later and divided into a plurality of unit cells 9 by etching.

Next, as shown in FIGS. 5A and 5B,
A gate oxide film 6 is formed on the entire surface including the trench 5 by a thermal oxidation method. Next, CVD (Chemical Vapor Deposit)
After a polysilicon film is formed on the entire surface by the ion) method,
An unnecessary portion of the polysilicon film is removed and the gate electrode 7 is formed so as to be buried only in the trench 5.

Next, as shown in FIGS. 6A and 6B,
After ion implantation using boron (B) as a p-type impurity, annealing is performed at 1100 to 1200 ° C. for 10 to 20 minutes, so that the entire surface of the n ⁻ -type semiconductor layer 2 surrounded by the trench 5 has a thickness of 1 to 2 μm. A p-type base region 4 having a depth is formed. Next, by photolithography, a planar shape composed of a cell central portion of the p-type base region 4 and cell diagonal portions radially extending from four corners of the cell central portion (a plane corresponding to the p-type base region 4 in FIG. 1). A photoresist film patterned in (shape) is formed on the p-type base region 4. Next, using this photoresist film as a mask, n
After ion implantation using arsenic (As) as a type impurity, annealing is performed at 980 to 1050 ° C. for 25 to 35 minutes to selectively apply 0.4 to 0.4 μm to the surface of the p-type base region 4.
A 0.8 μm n ⁺ type source region 8 and a source region constriction 11 are formed.

That is, after a p-type base region 4 is previously formed on the entire surface, an n-type impurity is ion-implanted on the base region 4 using the photoresist film patterned into the planar shape as described above as a mask. In the cell corner portion 15 on the rectangular surface of the unit cell 9, the source region narrowing portion 1 in which the planar width W 1 of the n ⁺ type source region 8 is partially limited to the width W 2.
1 is formed. Then, the source region 8 is formed continuously without the source region constricted portion 11 being formed endlessly without interruption.

Next, an interlayer insulating film 12 is formed on the entire surface by CVD, and the gate oxide film 5 and the interlayer insulating film 12 are patterned by photolithography to form source and base contact openings 13. A source electrode 14 is formed through the source and base contact openings 13 to complete the semiconductor device 10 of this example.

According to the method of manufacturing a semiconductor device as described above, a trench 5 is first formed in the n ⁻ type semiconductor layer 4 in the drain region 4, and a gate oxide film 6 and a gate electrode 7 are formed in the trench 5. After that, the base region 4 and the source region 8 are formed with a high-temperature treatment, so that the trench structure is stable characteristically without particularly thermally affecting the trench 5 and the semiconductor crystal in the vicinity of the trench 5. Can be formed. On the contrary, when the trench 5 is formed after the formation of the base region 4 and the source region 8 accompanied by the high-temperature treatment, the trench 5 is formed in the semiconductor crystal thermally affected by the high-temperature treatment. Forming
Subsequently, since the gate oxide film 6 and the gate electrode 7 are formed, it is difficult to form a trench structure which is characteristically stable.

As described above, in the configuration of the semiconductor device of this example,
According to this, on the diagonal line L on the rectangular surface of the unit cell 9 and
In the cell corner 15 near the diagonal line L
Is n ⁺The planar width dimension W1 of the mold source region 8 is partially
The source region constriction 11 is formed.
Through the cell corner 15 at the time of reverse breakdown voltage breakdown.
Current path from drain region 3 to source electrode 4
Is shorter than the current path not passing through the cell corner 15.
Can be done. Also, manufacture of the semiconductor device of this example
According to the method, the trench 5 is formed before the drain region 4.
After the formation of the base region 4 and the
Since the source region 8 is formed, the trench 5 and the
Thermally affects the semiconductor crystal in the vicinity of trench 5
Forming a trench structure that is characteristically stable
Can be. Therefore, a structure suitable for cell miniaturization
Reverse breakdown voltage without sacrificing channel resistance.
The element breakdown resistance during shutdown can be improved.
You.

Second Embodiment FIG. 7 is a plan view showing a configuration of a semiconductor device according to a second embodiment of the present invention, and FIG. 8 is a sectional view taken along the line CC of FIG.
The configuration of the semiconductor device of the second embodiment is significantly different from that of the first embodiment in that the structure of the source region narrowing portion is changed. In the semiconductor device 20 of this example, as shown in FIGS. 7 and 8, the source region narrowing portion 11 has a higher impurity than the p-type base region 4 at a part of the position where the n ⁺ -type source region 8 is to be formed. After the concentration of the p ⁺ -type semiconductor region 16 is formed in advance, the n ⁺ -type source region 8 is formed.
Is formed.

To manufacture the semiconductor device 20 of this example,
As shown in FIGS. 6A and 6B of the first embodiment, the steps up to the formation of the p-type base region 4 are performed in substantially the same steps. Next, patterning was performed by photolithography into a planar shape (a planar shape corresponding to the p ⁺ -type semiconductor region 16 in FIG. 7) consisting of cell diagonal portions radially extending from the periphery of the cell center of the p-type base region 4. After forming a first photoresist film on the p-type base region 4,
After ion implantation using boron difluoride (BF ₂ ) as an n-type impurity using the photoresist film as a mask, annealing is performed at 980 to 1050 ° C. for 25 to 35 minutes, so that the surface of the p-type base region 4 is 0.5 ~
A 1.0 μm p ⁺ type semiconductor region 16 is formed.

Next, by photolithography, a planar shape (a p ⁺ type semiconductor region 16 and a p ⁺ type semiconductor region 16 in FIG. 7) consisting of a cell central portion of the p-type base region 4 and a cell diagonal portion radially extending from the periphery of the cell central portion. p-type base region 4
After a second photoresist film patterned into a (planar shape corresponding to) is formed on the p-type base region 4, ion implantation is performed using the second photoresist film as a mask and arsenic as an n-type impurity. 980-1050
Annealing is performed at 25 ° C. for 25 to 35 minutes to selectively form an n ⁺ -type source region 8 and a source region constriction 11 of 0.4 to 0.8 μm on the surface of the p-type base region 4.

That is, after the p-type base region 4 is formed on the entire surface in advance, p-type impurities are ion-implanted on the base region 4 using the first photoresist film patterned into the planar shape as described above as a mask. To selectively form the p ⁺ -type semiconductor region 16 and then ion-implant an n-type impurity using the second photoresist film patterned into the planar shape as described above as a mask. In the same manner as described above, in particular, in the cell corner portion 15 on the rectangular surface of the unit cell 9, the planar width W1 of the n ⁺ type source region 8 is partially changed to the width W2.
The source region constriction 11 is formed so as to limit the width of the source region. Then, the source region 8 is formed continuously without the source region constricted portion 11 so as to be formed in an endless shape without interruption.

Subsequent steps may be performed in substantially the same manner as in the first embodiment. Since other points are substantially the same as those of the above-described first embodiment, the same reference numerals are given to the same parts in FIGS. 7 and 8 and the description is omitted.

According to this example, as shown by the current path c in FIG. 8, the current at the time of reverse breakdown breakdown flows through the surface of the low resistance p ⁺ type semiconductor region 16 with the shortest distance, so that the base region Since the voltage drop when the current flows through the inside 4 is reduced, it acts to make it difficult to turn on the parasitic bipolar transistor. Therefore, the element breakdown resistance can be further improved.

As described above, according to the structure of this embodiment, substantially the same effects as those described in the first embodiment can be obtained.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there are changes in the design without departing from the gist of the present invention. Is also included in the present invention. For example, the conductivity type of each semiconductor region included in the semiconductor device may be reversed between p-type and n-type. Further, the n ⁻ -type semiconductor layer serving as the drain region may be formed by doping an impurity from the outside by an ion implantation method or the like, instead of the epitaxial method, to adjust the impurity concentration.

In addition to the MOSFET, an oxide (O
The present invention can be applied to a MISFET constituted by using an insulator in general instead of the XIDE. The conditions for forming each semiconductor region, trench, interlayer insulating film, etc., the type of ion source at the time of implanting impurity ions, and the like are merely examples, and can be changed as necessary.

[0046]

As described above, according to the semiconductor device of the present invention, the planar width dimension of the source region is formed on the diagonal line on the rectangular surface of the unit cell and on the cell corner portion near the diagonal line. Is formed, the current path from the drain region to the source electrode via the cell corner at the time of reverse breakdown voltage breakdown is changed from the current path not via the cell corner during the reverse breakdown voltage breakdown. Can also be shortened. Further, according to the method of manufacturing a semiconductor device of the present invention, the base region and the source region are formed with high-temperature treatment after forming the trench in the drain region first. A characteristically stable trench structure can be formed without thermally affecting the semiconductor crystal. Therefore, the device has a structure suitable for miniaturization of cells, and can improve the withstand voltage against element breakdown at the time of reverse breakdown breakdown without sacrificing channel resistance.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA of FIG.

FIG. 3 is a sectional view taken along the line BB of FIG. 1;

FIG. 4 is a process chart showing a method of manufacturing the semiconductor device in the order of steps.

FIG. 5 is a process chart showing a method for manufacturing the same semiconductor device in the order of steps.

FIG. 6 is a process chart showing a method for manufacturing the semiconductor device in the order of steps.

FIG. 7 is a plan view showing a configuration of a semiconductor device according to a second embodiment of the present invention.

8 is a sectional view taken along the line CC of FIG. 7;

FIG. 9 is a plan view showing a configuration of a conventional semiconductor device.

FIG. 10 is a sectional view taken along the line DD in FIG. 9;

11 is a sectional view taken along the line EE in FIG. 9;

FIG. 12 is a plan view showing a configuration of a conventional semiconductor device.

FIG. 13 is a sectional view taken along the line FF in FIG. 12;

[Explanation of symbols]

Reference Signs ^List 1 n ⁺ type semiconductor substrate (high impurity concentration semiconductor substrate) 2 n ⁻ type semiconductor layer (low impurity concentration semiconductor layer) 3 n type drain region 4 p type base region 5 trench 6 gate oxide film 7 gate electrode 8 n ⁺ type source Region 9 Unit cell 10, 20 Semiconductor device (vertical MO having trench structure)
SFET) 11 Source region constriction 12 Interlayer insulating film 13 Source and base contact opening 14 Source electrode 15 Cell corner 16 p ⁺ type semiconductor region

Claims (10)

(57) [Claims] A first conductive type drain region adjacent to the first conductive type drain region;
A conductivity type base region is formed, a trench is formed around the base region, a gate electrode is formed in the trench via a gate insulating film, and an endless shape is formed on the surface of the base region along the trench. What is claimed is: 1. A semiconductor device comprising a plurality of unit cells each having a rectangular trench structure in which a source region of a first conductivity type is formed, comprising: a central portion of a rectangular surface of the unit cell; A semiconductor device, wherein a source non-formation region is provided in a diagonal portion of a cell extending in the direction of the arrow. A second conductive type drain region adjacent to the first conductive type drain region;
A conductivity type base region is formed, a trench is formed around the base region, a gate electrode is formed in the trench via a gate insulating film, and an endless shape is formed on the surface of the base region along the trench. A semiconductor device including a plurality of unit cells having a rectangular trench structure in which a source region of a first conductivity type is formed, wherein a cell is located on a diagonal of a cell on a rectangular surface of the unit cell and at a position near the diagonal of the cell. A semiconductor device, wherein a source region narrowing portion for partially limiting a planar width dimension of the source region is formed. 3. The unit cell has a surface covered with an interlayer insulating film, a source and base contact opening is formed in the interlayer insulating film, and a source electrode is formed through the source and base contact opening. 3. The semiconductor device according to claim 2, wherein: 4. The source region narrowing portion is formed so as to narrow the source region by an arbitrary size from a source and base contact opening of the interlayer insulating film to a cell corner on the cell diagonal line. 4. The semiconductor device according to claim 3, wherein: 5. A method according to claim 1, wherein the source region confinement portion is formed after a second conductivity type semiconductor region having a higher impurity concentration than the base region is formed in advance at a part of a position where the source region is to be formed. 3. The semiconductor device according to claim 2, wherein the semiconductor device is formed by being formed. 6. A second conductive type second drain region adjacent to the first conductive type drain region.
A conductivity type base region is formed, a trench is formed around the base region, a gate electrode is formed in the trench via a gate insulating film, and an endless shape is formed on the surface of the base region along the trench. A method for manufacturing a semiconductor device comprising a plurality of unit cells having a rectangular trench structure in which a source region of a first conductivity type is formed, wherein a first conductivity type semiconductor substrate has a lower impurity concentration than the semiconductor substrate. Forming a drain region by forming a first conductivity type semiconductor layer; forming a trench in the first conductivity type semiconductor layer at a position around the base region to divide the plurality of unit cells; Forming a base region for forming a second conductivity type base region on the entire surface of the first conductivity type semiconductor layer surrounded by the trench; An endless first conductivity type source region is selectively formed on the surface of the source region, and the source region is selectively planarized on a cell diagonal line and a position near the cell diagonal line which is a rectangular surface of the unit cell. A source region forming step of forming a source region constricted portion that partially limits a critical width dimension. 7. The method according to claim 7, wherein the step of forming the source region includes forming a photoresist film patterned on the base region into a planar shape including a cell central portion of the base region and a cell diagonal portion radially extending from the periphery of the cell central portion. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the first conductivity type impurity is introduced using the photoresist film as a mask after the formation. 8. The source region forming step includes forming, on the base region, a first photoresist film patterned in a planar shape including a cell diagonal portion radially extending from a periphery of a cell central portion of the base region. Thereafter, a first impurity introducing step of introducing a second conductivity type impurity so as to have a higher impurity concentration than the base region using the first photoresist film as a mask, and a cell central portion of the base region and After forming a second photoresist film patterned into a planar shape composed of cell diagonal portions radially extending from the periphery of the cell center portion on the base region, the first conductive film is masked using the second photoresist film as a mask. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the method is performed in combination with a second impurity introduction step performed by introducing a type impurity. 9. A gate for forming a gate electrode on at least a side surface of the trench between the trench forming step and the base region forming step, and then forming a gate electrode in the trench via the gate insulating film. 9. The method of manufacturing a semiconductor device according to claim 6, further comprising an electrode forming step. 10. The method according to claim 6, wherein the impurity of the first conductivity type or the second conductivity type in the base region forming step and the source region forming step is introduced by an ion implantation method. The manufacturing method of the semiconductor device described in the above.