KR102369057B1 - Power semiconductor device and method of fabricating the same - Google Patents

Abstract

A power semiconductor device according to an aspect of the present invention includes a semiconductor layer of silicon carbide (SiC), a gate insulating layer on at least a portion of the semiconductor layer, a gate electrode layer on the gate insulating layer, and a lower portion of the gate electrode layer on the semiconductor layer A first well formed to include at least one protruding portion disposed in a region and a second well region formed in the semiconductor layer outside the gate electrode layer and connected to the first well region, a well region having a second conductivity type; a first source region formed in the first well region; A second source region formed in the second well region and connected to the first source region, a source region having a first conductivity type, and disposed under the gate electrode layer, the at least one protrusion of the drift region and a channel region formed in the semiconductor layer between the portion and the first source region, the inversion channel being formed, and having a first conductivity type.

Description

Power semiconductor device and method of manufacturing the same

The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device for switching power transmission and a method of manufacturing the same.

A power semiconductor device is a semiconductor device that operates in a high voltage and high current environment. Such power semiconductor devices are used in fields requiring high power switching, for example, power conversion, power converters, inverters, and the like. For example, the power semiconductor device may include an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), or the like. Such a power semiconductor device is basically required to withstand high voltage, and recently, a high-speed switching operation is additionally required.

Accordingly, a power semiconductor device using silicon carbide (SiC) instead of conventional silicon (Si) is being studied. Silicon carbide (SiC) is a wide-gap semiconductor material having a higher bandgap than silicon, and can maintain stability even at high temperatures compared to silicon. Furthermore, silicon carbide has a very high insulating wave field compared to silicon, so it can operate stably even at a high voltage. Therefore, silicon carbide has a higher breakdown voltage than silicon, and exhibits excellent heat dissipation, so that it can be operated at a high temperature.

In the case of a power semiconductor device using such silicon carbide, the band gap on the surface of the silicon carbide rises upward due to the influence of negative charges due to the formation of carbon clusters in the gate insulating layer, so there is a problem in that the threshold voltage is increased and the channel resistance is increased. In addition, since the source contact structure is disposed between the gate electrodes, it is difficult to narrow the gap between the gate electrodes, so there is a limit in reducing the channel density.

Republic of Korea Publication No. 2011-0049249 (published on May 11, 2011)

An object of the present invention is to solve the above problems, and to provide a silicon carbide power semiconductor device capable of increasing channel density and a method for manufacturing the same. However, these problems are exemplary, and the scope of the present invention is not limited thereto.

A power semiconductor device according to an aspect of the present invention for solving the above problems is a semiconductor layer of silicon carbide (SiC), a gate insulating layer on at least a portion of the semiconductor layer, a gate electrode layer on the gate insulating layer, and the semiconductor a drift region formed in a layer including at least one protruding portion disposed under the gate electrode layer and having a first conductivity type; and the at least one protrusion of the drift region formed in the semiconductor layer under the gate electrode layer a well region having a second conductivity type, comprising a first well region in contact with a portion and a second well region formed in the semiconductor layer outside the gate electrode layer and connected to the first well region; A first source region and a second source region formed in the second well region and connected to the first source region, a source region having a first conductivity type, and disposed under the gate electrode layer, the drift region formed in the semiconductor layer between the at least one protruding portion of

The power semiconductor device may further include a source electrode layer connected to the second source region outside the gate electrode layer.

According to the power semiconductor device, the second source region includes a well contact region extending from the second well region through the second source region and connected to the source electrode layer, the well contact region having a second conductivity type; The contact region may be doped at a higher concentration than the well region.

According to the power semiconductor device, the at least one protruding portion of the drift region, the first well region, and the first source region may extend in one direction.

According to the power semiconductor device, the first well region, the first source region, and the channel region may be respectively formed in the semiconductor layer on both sides of the at least one protruding portion of the drift region.

According to the power semiconductor device, the channel region may be a part of the well region.

According to the power semiconductor device, the at least one protruding portion includes a plurality of protruding portions whose sidewalls are surrounded by the first well region, and the channel region is between the plurality of protruding portions and the first source region. can be formed in

According to the power semiconductor device, the plurality of protruding portions may extend in parallel in one direction.

According to the power semiconductor device, the first well region is symmetrically formed with respect to the second well region, the first source region is symmetrically formed with respect to the second source region, and the channel region may be formed symmetrically with respect to the second well region or the second source region.

According to the power semiconductor device, the at least one protruding portion includes a plurality of protruding portions symmetrically disposed with respect to the second well region or the second source region, and the plurality of protruding portions are oriented in one direction. can be elongated.

According to the power semiconductor device, the gate electrode layer may be formed to expose the second source region and cover the at least one protruding portion of the first source region, the channel region, and the drift region.

According to the power semiconductor device, a drain region having a first conductivity type may be further included in the semiconductor layer under the drift region, and the drain region may be doped with a higher concentration than the drift region.

A method of manufacturing a power semiconductor device according to another aspect of the present invention for solving the above problems includes forming a drift region having a first conductivity type in a semiconductor layer of silicon carbide (SiC), wherein the drift region is at least one A well region comprising a first well region defining the at least one protrusion and a second well region connected to the first well region, the well region having a second conductivity type, in the semiconductor layer to include a protruding portion of forming a source region comprising a first source region formed in the first well region and a second source region formed in the second well region and connected to the first source region, the source region having a first conductivity type forming a gate insulating layer on the at least one protruding portion of the drift region and the semiconductor layer between the at least one protruding portion and the first source region; and forming one gate electrode layer, wherein the second well region is formed in the semiconductor layer outside the gate electrode layer.

According to the method of manufacturing the power semiconductor device, a well contact region extending from the second well region through the second source region and having a second conductivity type is formed in the second source region outside the gate electrode layer. The method may further include: the well contact region may be doped with a higher concentration than the well region.

The method of manufacturing the power semiconductor device may further include forming a source electrode layer on the semiconductor layer to be connected to the second source region and the well contact region.

According to the method of manufacturing the power semiconductor device, the forming of the well region is performed by implanting an impurity of a second conductivity type into the semiconductor layer, and the forming of the source region is a first conductivity type in the well region. This can be done by injecting impurities of

According to the method of manufacturing the power semiconductor device, the at least one protrusion part may include a plurality of protrusion parts whose sidewalls are surrounded by the first well region.

According to the method of manufacturing the power semiconductor device, the first well region may be symmetrically formed with respect to the second well region, and the first source region may be symmetrically formed with respect to the second source region. there is.

According to the method of manufacturing the power semiconductor device, the drift region may be formed on a drain region having a first conductivity type, and the drift region may be formed as an epitaxial layer on the drain region.

According to the power semiconductor device and the method for manufacturing the same according to an embodiment of the present invention made as described above, it is possible to increase the degree of integration by increasing the channel density.

Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

1 is a schematic schematic perspective view showing a power semiconductor device according to an embodiment of the present invention.
FIG. 2 is a plan view showing the power semiconductor device taken along line II-II of FIG. 1 .
3 is a cross-sectional view illustrating a power semiconductor device taken along line III-III of FIG. 2 .
4 is a cross-sectional view illustrating the power semiconductor device taken along line IV-IV of FIG. 2 .
FIG. 5 is a cross-sectional view showing the power semiconductor device taken along line VV of FIG. 2 .
6 is a cross-sectional view illustrating a power semiconductor device taken along line VI-VI of FIG. 2 .
7 to 10 are schematic perspective views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. It is provided to fully inform In addition, in the drawings for convenience of description, the size of at least some of the components may be exaggerated or reduced. In the drawings, like numbers refer to like elements.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for the purpose of explanation, and thus are provided to explain the general structures of the present invention.

Like reference signs indicate like elements. When referring to one component as being on another component, such as a layer, region, or substrate, it will be understood that other intervening components may also be present, either directly on top of the other component or in between. On the other hand, when referring to one configuration as being “directly on” of another, it is understood that intervening configurations do not exist.

1 is a schematic schematic perspective view showing a power semiconductor device 100 according to an embodiment of the present invention, FIG. 2 is a plan view showing the power semiconductor device 100 taken along line II-II of FIG. 1, 3 is a cross-sectional view showing the power semiconductor device 100 taken along line III-III of FIG. 2, FIG. 4 is a cross-sectional view showing the power semiconductor device 100 taken along line IV-IV of FIG. 2, and FIG. is a cross-sectional view showing the power semiconductor device 100 taken along the line VV of FIG. 2 , and FIG. 6 is a cross-sectional view showing the power semiconductor device 100 taken along the line VI-VI of FIG. 2 .

1 to 6 , the power semiconductor device 100 may include at least a semiconductor layer 105 , a gate insulating layer 118 , and a gate electrode layer 120 . For example, the power semiconductor device 100 may have a power MOSFET structure.

The semiconductor layer 105 may refer to one or more semiconductor material layers, for example, one or multiple epitaxial layers. Furthermore, the semiconductor layer 105 may refer to one or multiple epitaxial layers on a semiconductor substrate.

For example, the semiconductor layer 105 may be made of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

Silicon carbide (SiC) has a wider bandgap than silicon, so it can maintain stability even at high temperatures compared to silicon. Furthermore, silicon carbide has a very high insulating wave field compared to silicon, so it can operate stably even at a high voltage. Accordingly, the power semiconductor device 100 using silicon carbide as the semiconductor layer 105 has a high breakdown voltage and excellent heat dissipation characteristics compared to the case where silicon is used, and may exhibit stable operating characteristics even at high temperatures.

More specifically, the semiconductor layer 105 may include a drift region 107 . The drift region 107 may have the first conductivity type, and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105 . For example, the drift region 107 may be formed by doping an impurity of the first conductivity type into an epitaxial layer of silicon carbide.

Furthermore, the drift region 107 may include at least one protruding portion 107a disposed under the gate electrode layer 120 . During operation of the power semiconductor device 100 , the protruding portion 107a may provide a vertical movement path of electric charges.

The well region 110 may be formed to contact at least a portion of the drift region 107 in the semiconductor layer 105 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in the drift region 107 .

For example, the well region 110 includes a first well region 110a formed in the semiconductor layer 105 under the gate electrode layer 120 and in contact with the protruding portion 107a of the drift region 107, and the gate electrode layer ( 120) may include a second well region 110b formed in the outer semiconductor layer 105 . The first well region 110a and the second well region 110b may be connected to each other. Substantially, the protruding portion 107a of the drift region 107 may be defined by the first well region 110a, and more specifically, may be in contact with a sidewall of the first well region 110a.

A source region 112 may be formed in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the well region 110 with an impurity of the first conductivity type. The source region 112 may be formed by doping a higher concentration of impurities of the first conductivity type than the drift region 107 .

For example, the source region 112 may include a first source region 112a formed in the first well region 110a and a second source region 112b formed in the second well region 110b. The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed under the gate electrode layer 120 , and the second source region 112b may be disposed outside the gate electrode layer 120 .

The second source region 112b may include a source contact region 113 connected to the source electrode layer 140 outside the gate electrode layers 120 . For example, the source contact region 113 is a part of the second source region 112b and may refer to a portion to which the source electrode layer 140 is connected.

The well contact region 114 may be formed in the second source region 112b, more specifically, in the source contact region 113 . For example, the well contact region 114 may extend from the second well region 110b through the second source region 112b and may have the second conductivity type. One or a plurality of well contact regions 114 may be formed in the source contact region 113 .

The well contact region 114 may be connected to the source electrode layer 140 , and may be doped with an impurity of the second conductivity type at a higher concentration than the well region 110 to reduce contact resistance when connected to the source electrode layer 140 . .

The channel region 110c may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112 . For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The channel region 110c may have a second conductivity type to form an inversion channel.

Since the channel region 110c has a doping type opposite to that of the source region 112 and the drift region 107 , the channel region 110c may form a diode junction junction with the source region 112 and the drift region 107 . can Accordingly, although the channel region 110c does not allow the movement of charges under normal circumstances, when an operating voltage is applied to the gate electrode layer 120 , an inversion channel is formed therein to allow the movement of charges. .

For example, the channel region 110c may be a part of the well region 110 . In this case, the channel region 110c may be formed to be continuously connected to the well region 110a. The doping concentration of the impurity of the second conductivity type in the channel region 110c may be the same as that of other portions of the well region 110 or may be different for controlling the threshold voltage.

In some embodiments, the protruding portion 107a of the drift region 107 , the first well region 110a , the channel region 110c , and/or the first source region 112a may extend in one direction. For example, the direction of line V-V or line VI-VI of FIG. 2 may be one direction.

In some embodiments, the first well region 110a , the channel region 110c , and the first source region 112a may be formed symmetrically with respect to the protruding portion 107a of the drift region 107 . For example, the first well region 110a , the channel region 110c , and the first source region 112a may be respectively formed in the semiconductor layer 105 on both sides of the protruding portion 107a of the drift region 107 . there is.

In some embodiments, the drift region 107 may include a plurality of protruding portions 107a whose sidewalls are surrounded by the first well region 110a. For example, the first well region 110a may be formed in a stripe pattern extending in one direction, and the protruding portions 107a may also be formed in a stripe pattern. In this case, the protruding portions 107a may extend in parallel in one direction.

Also, the first source region 112a may be formed in a stripe pattern in the first well region 110a. The channel region 110c may be formed between the protruding portions 107a and the first source region 112a.

In some embodiments, the first well region 110a is symmetrically formed with respect to the second well region 110b, and the first source region 112a is symmetrically formed with respect to the second source region 112b. can be formed. In this case, the protruding portions 107a and the channel region 110c of the drift region 107 may be formed symmetrically with respect to the second well region 110b or the second source region 112b.

Furthermore, the first well region 110a and the second well region 110b may be repeatedly formed alternately in one direction. In this case, the first source region 112a and the second source region 112b may also be repeatedly formed.

Additionally, the drain region 102 may be formed in the semiconductor layer 105 under the drift region 107 and may have a first conductivity type. For example, the drain region 102 may be doped at a higher concentration than the drift region 107 .

In some embodiments, the drain region 102 may be provided as a substrate of silicon carbide having a first conductivity type. In this case, the drain region 102 may be understood as a part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105 .

The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105 . For example, the gate insulating layer 118 may be formed on at least the channel region 110c. More specifically, the gate insulating layer 118 may be formed on the first source region 112a , the channel region 110c , and the protruding portion 107a of the drift region 107 .

For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stacked structure thereof.

At least one gate electrode layer 120 may be formed on the gate insulating layer 118 . For example, the gate electrode layer 120 may be formed on at least the channel region 110c. More specifically, the gate electrode layer 120 may be formed on the first source region 112a , the channel region 110c , and the protruding portion 107a of the drift region 107 . Furthermore, the second well region 110b , the second source region 112b , and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120 .

For example, the gate electrode layer 120 may include a suitable conductive material, such as polysilicon, metal, metal nitride, metal silicide, or the like, or may include a stacked structure thereof.

The interlayer insulating layer 130 may be formed on the gate electrode layer 120 . For example, the interlayer insulating layer 130 may include a suitable insulating material, such as an oxide layer, a nitride layer, or a laminate structure thereof.

The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112 , more specifically, the second source region 112b. Furthermore, the source electrode layer 140 may be commonly connected to the second source region 112b and the well contact region 114 . For example, the source electrode layer 140 may be formed of an appropriate conductive material, metal, or the like.

In the above-described power semiconductor device 100 , the first conductivity type and the second conductivity type may have opposite conductivity types, but may be either n-type or p-type, respectively. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

More specifically, when the power semiconductor device 100 is an N-type MOSFET, the drift region 107 is an N- region, the source region 112 and the drain region 102 are N+ regions, and the well region 110 and The channel region 110c may be a P− region, and the well contact region 114 may be a P+ region.

In operation of the power semiconductor device 100 , current flows from the drain region 102 in a generally vertical direction along the protruding portions 107a of the drift region 107 , and then through the channel region 110c to the source region 112 . ) can flow.

In the above-described power semiconductor device 100 , the source contact region 113 and the well contact region 114 may be separately disposed outside the gate electrode layer 120 . Accordingly, the first well region 110a and the first source region 112a may be formed such that the protruding portions 107a of the drift region 107 are densely disposed, and thus the channel region 110c is formed as a gate electrode layer. (120) may be densely formed in the lower portion. Accordingly, the power semiconductor device 100 may have a high degree of integration.

7 to 10 are schematic perspective views illustrating a method of manufacturing the power semiconductor device 100 according to an embodiment of the present invention.

Referring to FIG. 7 , a drift region 107 having a first conductivity type may be formed in the semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 may be formed on the drain region 102 having the first conductivity type. In some embodiments, drain region 102 is provided as a substrate of a first conductivity type, and drift region 107 may be formed on one or more epitaxial layers on such a substrate.

Next, the well region 110 having the second conductivity type may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107 . For example, the forming of the well region 110 may be performed by implanting impurities of the second conductivity type into the semiconductor layer 105 .

For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes at least one protruding portion 107a at least partially surrounded by the well region 11 . More specifically, the well region 110 may be formed by doping the drift region 107 with an impurity opposite to that of the drift region 107 .

The well region 110 may be divided into a first well region 110a in which the channel region 110c is to be formed and a second well region 110b in which the well contact region 114 is to be formed. For example, the first well region 110a may define the protruding portion 107a of the drift region 107 . The first well region 110a and the second well region 110b may be connected to each other.

Referring to FIG. 8 , a source region 112 having a first conductivity type may be formed in the well region 110 . For example, the forming of the source region 112 may be performed by implanting impurities of the first conductivity type into the well region 110 .

For example, forming the source region 112 may include forming the first source region 112a in the first well region 110a and forming the second source region 112b in the second well region 110b. may include doing A portion of the second source region 112b may be allocated as the source contact region 113 to be connected to the source electrode layer 140 . The first source region 112a and the second source region 112b may be connected to each other.

In addition to forming the source region 112 , an inversion channel may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107 to form a channel region 110c having a second conductivity type. there is. For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a.

Optionally, a well contact region 114 extending from the second well region 110b through the second source region 112b may be formed in the second source region 112b. For example, the well contact region 114 may be formed by implanting impurities of the second conductivity type into a portion of the well region 110 at a higher concentration than that of the well region 110 .

In the above-described manufacturing method, impurity implantation or impurity doping may be performed such that ions are implanted into the semiconductor layer 105 or impurities are mixed during formation of the epitaxial layer. However, for implantation of impurities in the selective region, an ion implantation method using a mask pattern may be used.

Optionally, the ion implantation may be followed by a thermal treatment step to activate or diffuse the impurities.

Referring to FIG. 9 , a gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105 . For example, the gate insulating layer 118 may be formed on at least the channel region 110c and the protruding portion 107a of the drift region 107 .

For example, the gate insulating layer 118 may be formed of an oxide by oxidizing the semiconductor layer 105 , or may be formed by depositing an insulating material such as oxide or nitride on the semiconductor layer 105 .

Subsequently, gate electrode layers 120 may be formed on the gate insulating layer 118 . For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning it. The gate electrode layer 120 may be formed by doping polysilicon with impurities or may be formed to include a conductive metal or metal silicide.

The patterning process may be performed using photo lithography and etching processes. The photolithography process includes a process of forming a photoresist pattern with a mask layer using a photolithography process and a developing process, and the etching process includes a process of selectively etching an underlying structure using the photoresist pattern can do.

Referring to FIG. 10 , the interlayer insulating layer 130 may be formed on the gate electrode layer 120 . Optionally, when the interlayer insulating layer 130 is entirely formed on the lower structure, a process of forming a contact hole pattern for exposing the source contact region 113 and the well contact region 114 may be followed.

Subsequently, the source electrode layer 140 may be formed on the semiconductor layer 105 to be connected to the second source region 112b and the well contact region 114 . For example, the source electrode layer 140 may be formed by forming a conductive layer, for example, a metal layer, on the interlayer insulating layer 130 and then patterning or planarizing it.

According to the above-described manufacturing method, it is possible to economically manufacture the high-integration power semiconductor device 100 by using the semiconductor layer 105 of silicon carbide by using a process used for a conventional silicon substrate.

Although the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: power semiconductor device
102: drain region
105: semiconductor layer
107: drift zone
110: well area
112: source area
118: gate insulating layer
120: gate electrode layer
130: interlayer insulating layer
140: source electrode layer

Claims (19)

a semiconductor layer of silicon carbide (SiC);
a gate insulating layer on at least a portion of the semiconductor layer;
a gate electrode layer on the gate insulating layer;
a drift region formed in the semiconductor layer to include at least one protruding portion disposed under the gate electrode layer and having a first conductivity type;
A first well region formed in the semiconductor layer under the gate electrode layer and in contact with the at least one protruding portion of the drift region, and a second well region formed in the semiconductor layer outside the gate electrode layer and connected to the first well region a well region comprising: a well region having a second conductivity type;
a source region comprising a first source region formed in the first well region and a second source region formed in the second well region and connected to the first source region, the source region having a first conductivity type;
a channel region disposed under the gate electrode layer and formed in the semiconductor layer between the at least one protruding portion of the drift region and the first source region, the channel region having an inversion channel and having a second conductivity type; doing,
power semiconductor devices. The method of claim 1,
Further comprising a source electrode layer connected to the second source region outside the gate electrode layer,
power semiconductor devices. 3. The method of claim 2,
a well contact region extending from the second well region through the second source region and connected to the source electrode layer in the second source region and having a second conductivity type;
the well contact region is more heavily doped than the well region;
power semiconductor devices. The method of claim 1,
the at least one protruding portion of the drift region, the first well region, and the first source region extend in one direction;
power semiconductor devices. 5. The method of claim 4,
the first well region, the first source region and the channel region are respectively formed in the semiconductor layer on both sides of the at least one protruding portion of the drift region;
power semiconductor devices. The method of claim 1,
wherein the channel region is part of the well region;
power semiconductor devices. The method of claim 1,
the at least one protruding portion comprises a plurality of protruding portions whose sidewalls are surrounded by the first well region;
the channel region is formed between the plurality of protruding portions and the first source region;
power semiconductor devices. 8. The method of claim 7,
The plurality of protruding parts extend side by side in one direction,
power semiconductor devices. The method of claim 1,
the first well region is formed symmetrically with respect to the second well region;
The first source region is formed symmetrically with respect to the second source region,
the channel region is formed symmetrically with respect to the second well region or the second source region;
power semiconductor devices. 10. The method of claim 9,
the at least one protrusion part includes a plurality of protrusion parts symmetrically disposed with respect to the second well region or the second source region;
The plurality of protruding parts are extended in one direction,
power semiconductor devices. The method of claim 1,
the gate electrode layer is formed to expose the second source region and to cover the at least one protruding portion of the first source region, the channel region, and the drift region;
power semiconductor devices. The method of claim 1,
a drain region having a first conductivity type in the semiconductor layer under the drift region;
The drain region is doped with a higher concentration than the drift region,
power semiconductor devices. forming a drift region having a first conductivity type in a semiconductor layer of silicon carbide (SiC);
a first well region defining the at least one protruding portion and a second well region connected to the first well region in the semiconductor layer such that the drift region includes at least one protruding portion; forming a well region having a shape;
forming a source region having a first conductivity type including a first source region formed in the first well region and a second source region formed in the second well region and connected to the first source region;
forming a gate insulating layer on the at least one protruding portion of the drift region and on the semiconductor layer between the at least one protruding portion and the first source region; and
forming at least one gate electrode layer on the gate insulating layer;
the second well region is formed in the semiconductor layer outside the gate electrode layer;
A method of manufacturing a power semiconductor device. 14. The method of claim 13,
The method further comprising: forming a well contact region extending from the second well region through the second source region and having a second conductivity type in the second source region outside the gate electrode layer;
the well contact region is more heavily doped than the well region;
A method of manufacturing a power semiconductor device. 15. The method of claim 14,
The method further comprising: forming a source electrode layer on the semiconductor layer to be connected to the second source region and the well contact region;
A method of manufacturing a power semiconductor device. 14. The method of claim 13,
The forming of the well region is performed by implanting impurities of a second conductivity type into the semiconductor layer,
The forming of the source region is performed by implanting impurities of the first conductivity type into the well region.
A method of manufacturing a power semiconductor device. 14. The method of claim 13,
The at least one protrusion part includes a plurality of protrusion parts whose sidewalls are surrounded by the first well region. 14. The method of claim 13,
the first well region is formed symmetrically with respect to the second well region;
The first source region is formed symmetrically with respect to the second source region,
A method of manufacturing a power semiconductor device. 14. The method of claim 13,
the drift region is formed on a drain region having a first conductivity type;
wherein the drift region is formed as an epitaxial layer on the drain region;
A method of manufacturing a power semiconductor device.

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