KR102309431B1 - Power semiconductor device and method of fabricating the same - Google Patents

Abstract

A power semiconductor device according to an aspect of the present disclosure includes: a semiconductor layer of silicon carbide (SiC); at least one trench extending in one direction and recessed into the semiconductor layer from a surface of the semiconductor layer by a predetermined depth; a gate insulating layer disposed on at least an inner wall of the at least one trench; at least one gate electrode layer disposed on the gate insulating layer to fill the at least one trench; a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer and having a first conductivity type; a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, so as to be in contact with at least a part of the drift region and to surround a bottom surface of the at least one gate electrode layer at least at one end of the at least one gate electrode layer, and having a second conductivity type; a deep well region formed under the well region in contact with the well region and the drift region and having a second conductivity type; a source region disposed in the well region and having the first conductivity type; and at least one channel region extending in the one direction, disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region, and having the second conductivity type. An aspect of the present disclosure provides a silicon carbide-based power semiconductor device capable of alleviating electric field concentration and increasing a channel density and a method of fabricating the same.

Description

Power semiconductor device and method of fabricating the same

The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device for switching power transmission and a method of manufacturing the same.

A power semiconductor device is a semiconductor device that operates in a high voltage and high current environment. Such power semiconductor devices are used in fields requiring high power switching, for example, power conversion, power converters, inverters, and the like. For example, the power semiconductor device may include an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), and the like. Such a power semiconductor device is fundamentally required to withstand high voltage, and recently, a high-speed switching operation is additionally required.

Accordingly, a power semiconductor device using silicon carbide (SiC) instead of conventional silicon (Si) is being studied. Silicon carbide (SiC) is a wide-gap semiconductor material having a higher bandgap than silicon, and can maintain stability even at high temperatures compared to silicon. Furthermore, silicon carbide has a very high insulating wave field compared to silicon, so it can operate stably even at a high voltage. Therefore, silicon carbide has a high breakdown voltage compared to silicon, and exhibits excellent heat dissipation, so that it can be operated at a high temperature.

In order to increase the channel density of a power semiconductor device using such silicon carbide, a trench-type gate structure having a vertical channel structure is being studied. In such a trench-type gate structure, there is a problem in that an electric field is concentrated at the trench edge, so there is a limit in reducing the channel density by applying a structure for protecting the lower portion of the trench. Furthermore, since the source contact structure is disposed between the gate electrodes, it is also difficult to narrow the gap between the gate electrodes, so there is a limit in reducing the channel density.

Republic of Korea Publication No. 2011-0049249 (published on May 11, 2011)

An object of the present invention is to provide a silicon carbide power semiconductor device capable of increasing channel density while reducing electric field concentration and a method for manufacturing the same. However, these problems are exemplary, and the scope of the present invention is not limited thereto.

A power semiconductor device according to an aspect of the present invention for solving the above problems is formed by recessing a semiconductor layer of silicon carbide (SiC) by a predetermined depth from the surface of the semiconductor layer into the semiconductor layer and extending in one direction at least one trench, a gate insulating layer formed on at least an inner wall of the at least one trench, and at least one gate electrode layer formed on the gate insulating layer to fill the at least one trench; a drift region formed in the semiconductor layer on one side of the electrode layer and having a first conductivity type; a well region formed in the semiconductor layer deeper than the gate electrode layer of A channel formed in the well region, a source region having a first conductivity type, and the semiconductor layer formed on one side of the at least one gate electrode layer between the drift region and the source region, and extending along the one direction. includes area.

According to the power semiconductor device, a source contact region in the source region outside one end of the at least one gate electrode layer, and extending from the well region in the source contact region through the source region and having a second conductivity type; It may further include a well contact region doped to a higher concentration than the well region, the source contact region and a source electrode layer connected to the well region.

According to the power semiconductor device, the deep well region is formed to have a width narrower than a width of the well region in the one direction, and both ends of the deep well region are formed from both ends of the well region in the one direction. Each may be moved to the inside and disposed.

According to the power semiconductor device, the drift region includes vertical portions extending perpendicular to the semiconductor layer on both sides of the at least one gate electrode layer, and the channel region includes the vertical portions of the drift region and the source region. It may be formed in the semiconductor layer in between.

According to the power semiconductor device, the channel region may have a second conductivity type such that an inversion channel is formed along the one direction, and the channel region may be a part of the well region.

According to the power semiconductor device, the channel region may have a first conductivity type such that an accumulation channel is formed along the one direction, and the channel region may be a part of the drift region.

According to the power semiconductor device, the at least one trench includes a plurality of trenches formed in parallel with the semiconductor layer along the one direction, and the at least one gate electrode layer includes a plurality of trenches formed by filling the plurality of trenches. gate electrode layers, and the well region and the source region may be connected to each other across the plurality of gate electrode layers.

According to the power semiconductor device, the at least one trench includes a plurality of trenches spaced apart in a line in the one direction, and the at least one gate electrode layer includes a plurality of gate electrode layers formed by filling the plurality of trenches. and the well region and the source region may be respectively formed in at least the semiconductor layer between the plurality of trenches.

According to the power semiconductor device, at least one groove penetrating through the source region and recessed into the well region by a predetermined depth, a well contact region formed on a bottom surface of the at least one groove in contact with the well region; A source electrode layer formed to fill at least one groove and connected to the source region and the well contact region may be further included.

According to the power semiconductor device, further comprising a drain region having a first conductivity type in the semiconductor layer under the drift region, the drain region is doped with a higher concentration than the drift region, the drift region is on the drain region It may be formed as an epitaxial layer.

A method of manufacturing a power semiconductor device according to another aspect of the present invention for solving the above problems includes forming a drift region having a first conductivity type in a semiconductor layer of silicon carbide (SiC), and the drift in the semiconductor layer forming a well region in contact with the region and having a second conductivity type; forming a deep well region in contact with the well region and the drift region under the well region and having a second conductivity type; forming a source region having a first conductivity type therein; forming a channel region extending in one direction in a semiconductor layer between the drift region and the source region; forming at least one trench recessed by a predetermined depth into the layer, extending across the drift region in the one direction, and shallower than the well region, on at least an inner wall of the at least one trench; forming a gate insulating layer on the gate insulating layer; and forming at least one gate electrode layer on the gate insulating layer to fill the at least one trench, wherein the well region is formed at one end of the at least one gate electrode layer. is formed in the semiconductor layer deeper than the at least one gate electrode layer to surround a bottom surface of the at least one gate electrode layer, and the channel region is formed on one side of the at least one gate electrode layer between the drift region and the source region. formed on the semiconductor layer.

According to the method of manufacturing the power semiconductor device, forming a source contact region outside one end of the at least one gate electrode layer, extending through the source region from the well region in the source contact region, and having a second conductivity The method may further include forming a well contact region having a shape and doping higher than that of the well region, and forming the source contact region and a source electrode layer connected to the well contact region.

According to the method of manufacturing the power semiconductor device, forming at least one groove in the source region to penetrate the source region and to be recessed into the well region; The method may further include: forming a well contact region having a second conductivity type to be in contact with the electrode; and forming a source electrode layer to fill the at least one groove and to be connected to the source region and the well contact region.

According to the power semiconductor device and the method for manufacturing the same according to an embodiment of the present invention made as described above, it is possible to increase the degree of integration by increasing the channel density while alleviating the concentration of the electric field.

Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

1 is a schematic schematic perspective view showing a power semiconductor device according to an embodiment of the present invention.
FIG. 2 is a plan view showing the power semiconductor device taken along line II-II of FIG. 1 .
3 is a cross-sectional view illustrating a power semiconductor device taken along line III-III of FIG. 2 .
4 is a cross-sectional view showing a power semiconductor device according to another embodiment of the present invention.
5 is a schematic perspective view showing a power semiconductor device according to another embodiment of the present invention.
6 is a plan view illustrating a power semiconductor device taken along line VI-VI of FIG. 5 .
7 is a cross-sectional view illustrating a power semiconductor device taken along line VII-VII of FIG. 6 .
8 is a cross-sectional view illustrating a power semiconductor device taken along line VIII-VIII of FIG. 6 .
9 and 10 are cross-sectional views illustrating power semiconductor devices according to still other embodiments of the present invention.
11 to 13 are schematic perspective views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. It is provided to fully inform In addition, in the drawings for convenience of description, the size of at least some of the components may be exaggerated or reduced. In the drawings, like reference numerals refer to like elements.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for the sake of illustration, and are therefore provided to illustrate the general structures of the present invention.

Like reference signs indicate like elements. When referring to one component, such as a layer, region, or substrate, being on another component, it will be understood that other intervening components may also be present, either directly on top of the other component or in between. On the other hand, when referring to one configuration as being “directly on” of another, it is understood that intervening configurations do not exist.

1 is a schematic schematic perspective view showing a power semiconductor device 100 according to an embodiment of the present invention, and FIG. 2 is a plan view showing the power semiconductor device 100 taken along line II-II of FIG. 1, FIG. 3 is a cross-sectional view illustrating the power semiconductor device 100 taken along line III-III of FIG. 2 .

1 to 3 , the power semiconductor device 100 may include at least a semiconductor layer 105 , a gate insulating layer 118 , and a gate electrode layer 120 . For example, the power semiconductor device 100 may have a power MOSFET structure.

The semiconductor layer 105 may refer to one or more semiconductor material layers, for example, one or multiple epitaxial layers. Furthermore, the semiconductor layer 105 may refer to one or multiple epitaxial layers on a semiconductor substrate.

For example, the semiconductor layer 105 may be made of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

Silicon carbide (SiC) has a wider bandgap than silicon, so it can maintain stability even at high temperatures compared to silicon. Furthermore, silicon carbide has a very high insulating wave field compared to silicon, so it can operate stably even at a high voltage. Therefore, the power semiconductor device 100 using silicon carbide as the semiconductor layer 105 has a high breakdown voltage and excellent heat dissipation characteristics compared to the case where silicon is used, and may exhibit stable operating characteristics even at high temperatures.

More specifically, the semiconductor layer 105 may include a drift region 107 . The drift region 107 may have the first conductivity type and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105 . For example, the drift region 107 may be formed by doping an impurity of the first conductivity type into an epitaxial layer of silicon carbide.

The well region 110 may be formed in contact with the drift region 107 in the semiconductor layer 105 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type in the drift region 107 .

For example, the well region 110 may be formed to surround at least a portion of the drift region 107 . Accordingly, the drift region 107 may include a vertical portion 107a at least partially surrounded by the well region 110 . During operation of the power semiconductor device 100 , the vertical portion 107a may provide a vertical movement path of electric charges.

In FIG. 1 , the well region 110 is formed to be spaced apart into two regions and the vertical portion 107a is defined therebetween, but other various modifications may be made. For example, the vertical portion 107a may have a shape in which a side surface thereof is surrounded by the well region 110 once.

A deep well region 111 may be formed under the well region 110 to contact the well region 110 and the drift region 107 . The deep well region 111 may have the same second conductivity type as the well region 110 . The doping concentration of the impurity of the second conductivity type in the deep well region 111 may be equal to or less than the doping concentration of the impurity of the second conductivity type in the well region 110 .

For example, the deep well region 111 may be formed to have a width narrower than the width of the well region 110 in one direction. One direction may refer to a line III-III direction in FIG. 2 . Furthermore, both ends of the deep well region 111 may be respectively moved inward from both ends of the well region 110 in one direction.

Accordingly, the deep well region 111 may be disposed to be in contact with the well region 110 by retreating inward from both ends of the well region 110 under the well region 110 . Sides and lower surfaces of the deep well region 111 may contact the drift region 107 .

For example, when the deep well region 111 is formed to be spaced apart into two regions along the well region 110 , the spacing between the two deep well regions 111 is greater than the spacing between the two well regions 110 . can be large

A source region 112 is formed in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the well region 110 with an impurity of the first conductivity type. The source region 112 may be formed by doping a higher concentration of impurities of the first conductivity type than the drift region 107 .

The channel region 110a may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112 . For example, the channel region 110a may have a second conductivity type, and an inversion channel may be formed along one direction during operation of the power semiconductor device 100 .

Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107 , the channel region 110a may form a diode junction junction with the source region 112 and the drift region 107 . can Accordingly, although the channel region 110a does not allow the movement of charges under normal circumstances, when an operating voltage is applied to the gate electrode layer 120 , an inversion channel is formed therein to allow the movement of charges. .

In some embodiments, the channel region 110a may be a part of the well region 110 . In this case, the channel region 110a may be integrally formed to be continuously connected to the well region 110a. The doping concentration of the impurity of the second conductivity type in the channel region 110a may be the same as that of other portions of the well region 110 or may be different for controlling the threshold voltage.

In some embodiments, the well region 110 , the deep well region 111 , the channel region 110a , and the source region 112 may be formed symmetrically about the vertical portion 107a of the drift region 107 . have. For example, the well region 110 , the deep well region 111 , the channel region 110a , and the source region 112 may be formed at both ends of the vertical portion 107a of the drift region 107 , and the vertical portion ( 107a) may include a first portion and a second portion symmetrically formed about the center, respectively. The first and second portions of the well region 110 , the deep well region 111 , the channel region 110a , and the source region 112 may be separated from or connected to each other.

Additionally, the drain region 102 may be formed in the semiconductor layer 105 under the drift region 107 and may have a first conductivity type. For example, the drain region 102 may be doped at a higher concentration than the drift region 107 .

In some embodiments, the drain region 102 may be provided as a substrate of silicon carbide having a first conductivity type. In this case, the drain region 102 may be understood as a part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105 .

The at least one trench 116 may be formed by recessing a predetermined depth into the semiconductor layer 105 from the surface of the semiconductor layer 105 . The trench 116 may extend in one direction within the semiconductor layer 105 . One direction refers to a length direction rather than a depth direction of the trench 116 , and may refer to a line III-III direction in FIG. 2 .

The gate insulating layer 118 may be formed on at least an inner wall of the trench 116 . For example, the gate insulating layer 118 may be formed on the inner surface of the trench 116 and the semiconductor layer 105 outside the trench 116 . The thickness of the gate insulating layer 118 may be uniform or the portion formed on the bottom surface of the trench 116 may be thicker than the portion formed on the sidewall in order to lower the electric field of the bottom portion of the trench 116 .

For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stacked structure thereof.

At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to fill the trench 116 . For example, the gate electrode layer 120 may include a suitable conductive material, such as polysilicon, metal, metal nitride, metal silicide, or the like, or may include a stacked structure thereof.

The drift region 107 may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 . For example, the vertical portion 107a of the drift region 107 may extend vertically to the semiconductor layer 105 on one side of the gate electrode layer 120 . The channel region 110a may be formed in the semiconductor layer 105 on one side of the gate electrode layer 120 between the source region 112 and the vertical portion 107a of the drift region 107 . Accordingly, the semiconductor layer 105 on one side of the gate electrode layer 120 may include a structure in which the source region 112, the channel region 110a, and the vertical portion 107a of the drift region 107 are connected along one direction. can

In some embodiments, the drift region 107 may be formed in the semiconductor layer 105 on both sides of the gate electrode layer 120 . For example, the drift region 107 may include vertical portions 107a extending perpendicular to the semiconductor layer 105 on both sides of the gate electrode layer 120 . The channel region 110a may be formed in the semiconductor layer 105 on both sides of the gate electrode layer 120 between the source region 112 and the vertical portions 107a of the drift region 107 .

Since the channel region 110a is formed along the sidewall of the gate electrode layer 120, it may be referred to as a lateral channel.

The well region 110 may be formed to be deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120 . Furthermore, the well region 110 may be formed to be deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at both ends of the gate electrode layer 120 . Accordingly, both ends of the gate electrode layer 120 around the source region 112 may be surrounded by the well region 110 .

This structure of the well 110 may further alleviate the problem of the electric field being concentrated at the bottom of the trench 116 , that is, at the bottom of the gate electrode layer 120 . Furthermore, by disposing the deep well region 111 under the well region 110 , the electric field applied to the gate insulating layer 118 may be lowered as well as the electric field at the bottom of the trench 116 . Accordingly, the electric field margin applied to the gate insulating layer 118 in the power semiconductor device 100 may be increased, thereby increasing the operational reliability of the power semiconductor device 100 . Furthermore, by lowering the electric field at the bottom of the trench 116 and lowering the electric field applied to the gate insulating layer 118 , there is a room for lowering the junction resistance of the vertical portion 107a of the drift region 107 .

In some embodiments, the gate insulating layer 118 and the gate electrode layer 120 may be formed to extend outside the trench 116 as well as inside the trench 116 .

In some embodiments, one or more trenches 116 may be provided in the semiconductor layer 105 . The number of trenches 116 may be appropriately selected, thus not limiting the scope of this embodiment.

For example, the plurality of trenches 116 may be formed in parallel in the semiconductor layer 105 along one direction. The trenches 116 may extend in one direction and may be spaced apart from each other in a direction perpendicular to the one direction and disposed in parallel.

In this case, the plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the inside of the trenches 116 . Accordingly, the gate electrode layers 120 may be formed in the semiconductor layer 105 in a trench type, and may be disposed to extend in parallel in one direction like the trenches 116 .

Furthermore, the well region 110 and the source region 112 may each extend across the gate electrode layers 120 . The vertical portions 107a of the drift region 107 may be disposed in the semiconductor layer 105 between the gate electrode layers 120 . The channel region 110a may be formed in the semiconductor layer 105 between the vertical portions 107a of the source region 112 and the drift region 107 on one or both sides of the gate electrode layers 120 .

In some embodiments, the well region 110 abuts the vertical portions 107a of the drift region 107 , and includes gate electrode layers at both ends of the gate electrode layers 120 to surround the bottom surface of the gate electrode layers 120 . It may be formed in the semiconductor layer 105 deeper than (120).

The interlayer insulating layer 130 may be formed on the gate electrode layer 120 . For example, the interlayer insulating layer 130 may include a suitable insulating material, such as an oxide layer, a nitride layer, or a laminate structure thereof.

The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112 . For example, the source electrode layer 140 may be formed of an appropriate conductive material, metal, or the like.

In the above-described power semiconductor device 100 , the first conductivity type and the second conductivity type may have opposite conductivity types, but may be either n-type or p-type, respectively. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

More specifically, when the power semiconductor device 100 is an N-type MOSFET, the drift region 107 is an N- region, the source region 112 and the drain region 102 are an N+ region, and the well region 110, The deep well region 111 and the channel region 110a may be P-regions.

In operation of the power semiconductor device 100 , current flows from the drain region 102 in a generally vertical direction along the vertical portions 107a of the drift region 107 , and then through the channel region 110a to the gate electrode layers ( It may flow along the side of 120 to the source region 112 .

In the power semiconductor device 100 described above, the gate electrode layers 120 in the trench 116 may be densely disposed in parallel in a stripe type or a line type, and the channel regions 110a are formed by the gate electrode layers ( 120), so that the channel density can be increased.

4 is a cross-sectional view showing a power semiconductor device 100a according to another embodiment of the present invention.

The power semiconductor device 100a according to this embodiment uses or partially modified the power semiconductor device 100 of FIGS. 1 to 3 , and thus the redundant description is omitted.

Referring to FIG. 4 , in the power semiconductor device 100a , the channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112 . For example, the channel region 107b may have a first conductivity type, and an accumulation channel may be formed therein during operation of the power semiconductor device 100 .

For example, the channel region 107b may be formed in the semiconductor layer 105 between the source region 112 and the vertical portions 107a of the drift region 107 . The channel region 107b may have the same doping type as the source region 112 and the drift region 107 .

In this case, the source region 112 , the channel region 107b , and the drift region 107 have a structure that can be normally electrically connected. However, in the structure of the semiconductor layer 105 of silicon carbide, the band of the channel region 107b bends upward due to the influence of a negative charge generated while carbon clusters are formed in the gate insulating layer 118 , resulting in a potential barrier. this is formed Accordingly, when an operating voltage is applied to the gate electrode layer 120 , an accumulation channel allowing the flow of electric charge or current may be formed in the channel region 107b.

Accordingly, the threshold voltage to be applied to the gate electrode layer 120 to form an accumulation channel in the channel region 107b is applied to the gate electrode layer 120 to form an inversion channel in the channel region 110a of FIGS. 1 to 3 . It may be significantly lower than the threshold voltage to be applied.

In some embodiments, the channel region 107b may be part of the drift region 107 . More specifically, the channel region 107b may be part of the vertical portions 107a of the drift region 107 . For example, the channel region 107b may be integrally formed with the drift region 107 . In this case, the drift region 107 may be connected to the source region 112 through the channel region 107b. That is, in the channel region 107b portion, the drift region 107 and the source region 112 may contact each other.

The doping concentration of the impurity of the first conductivity type in the channel region 107b may be the same as that of other portions of the drift region 107 or may be different for controlling the threshold voltage.

In a modified example of this embodiment, the well region 110 is formed to protrude in the vertical portion 107a direction of the drift region 107 rather than a portion of the source region 112 , and the channel region 107b is formed to protrude from the well region 110 . ) may be formed on the semiconductor layer 105 on the protruding portion.

Furthermore, the well region 110 may further include a tab portion extending toward the gate electrode layer 120 at an end of the protruding portion. The channel region 107b may be formed in a refractive shape on the protruding portion and the tab portion of the well region 110 .

Additionally, the vertical portion 107a of the drift region 107 may further extend between the bottom of the source region 112 and the well region 110 . In this case, the channel region 107b may be further extended between the lower portion of the source region 112 and the well region 110 .

These structures may allow the channel region 107b to be further defined between the gate electrode layer 120 and the well region 110 .

According to the power semiconductor device 100a, in addition to the advantages of the power semiconductor device 100 of FIGS. 1 to 3 , the effect of lowering the threshold voltage can be further expected.

5 is a schematic perspective view showing a power semiconductor device 100b according to another embodiment of the present invention, FIG. 6 is a plan view showing the power semiconductor device 100b taken along line VI-VI of FIG. 5, and FIG. 7 is a cross-sectional view showing the power semiconductor device 100b taken along line VII-VII of FIG. 6 , and FIG. 8 is a cross-sectional view showing the power semiconductor device 100b taken along line VIII-VIII of FIG. 6 .

The power semiconductor device 100b according to this embodiment uses or partially modified the power semiconductor device 100 of FIGS. 1 to 3 , and thus the redundant description is omitted.

5 to 8 , in the power semiconductor device 100b , the source region 112 may include a source contact region 112a outside at least one end of the gate electrode layers 120 . For example, the source contact region 112a is a part of the source region 112 and may refer to a portion to which the source electrode layer 140 is connected.

The well contact region 114 may be formed in the source contact region 112a. For example, the well contact region 114 may extend from the well region 110 through the source region 112 and may have the second conductivity type. One or a plurality of well contact regions 114 may be formed in the source contact region 112a.

For example, the well contact region 114 may be doped with an impurity of the second conductivity type at a higher concentration than the well region 110 in order to lower a contact resistance when connected to the source electrode layer 140 .

The source electrode layer 140 may be commonly connected to the source contact region 112a and the well contact region 114 .

5 to 8 show that the source contact region 112a and the well contact region 114 are formed in the source region 112 on one side with respect to the vertical portions 107a of the drift region 107, but the source contact When the source region 112 and the well region 110 are separated into a plurality, the region 112a and the well contact region 114 may be respectively formed therein.

In some embodiments, the plurality of trenches 116 may be spaced apart from each other in a line along one direction. Accordingly, the gate electrode layers 120 may also be disposed to be spaced apart in a line along the trenches 116 and in one direction. In this case, the well region 110 , the source region 112 , the source contact region 112a , and the well contact region 114 are formed in a semiconductor layer 105 between the trenches 116 spaced apart from each other in one direction. may be formed in each.

For example, in the power semiconductor device 100b, a plurality of structures of the power semiconductor device 100 of FIGS. 1 to 3 are disposed along one direction, and a well region 110, a source region 112, and a source are disposed therebetween. A contact region 112a and a well contact region 114 may be disposed and formed.

For example, when the power semiconductor device 100 is an N-type MOSFET, the source contact region 112a may be an N+ region, and the well contact region 114 may be a P+ region.

According to the power semiconductor device 100b, by disposing the source contact region 112a and the well contact region 114 outside the gate electrode layers 120 rather than between them, the gate electrode layers 120 are very densely arranged. can be placed Accordingly, the channel density of the power semiconductor device 100a may be greatly increased.

9 and 10 are cross-sectional views 100c and 100d illustrating power semiconductor devices according to still other embodiments of the present invention.

Referring to FIG. 9 , the power semiconductor device 100c has at least one groove 138 formed to penetrate the source region 112 in the source contact region 112a of the source region 112 and to be recessed into the well region 110 . ) may be included. A well contact region 114a may be formed on at least a bottom surface of the groove 138 to be in contact with the well region 110 .

The source electrode layer 140a may be formed to fill the groove 138 , and may be connected to the well contact region 114a , the well region 110 , and/or the source region 112 . Such a structure may increase the contact area between the source electrode layer 140a and the well region 110 and the source electrode layer 140a and the source region 112 to help reduce contact resistance therebetween.

In some embodiments, the well contact region 114a may be entirely formed on the surface of the well region 110 exposed by the groove 138 . Accordingly, the well contact region 114a may be formed on the well region 110 exposed from the bottom and sidewalls of the groove 138 . The structure of the well contact region 114a may serve to further reduce the contact resistance between the source electrode layer 140a and the well region 110 .

Referring to FIG. 10 , the power semiconductor device 100d may include a channel region 107b forming an accumulation channel instead of the channel region 110a of the power semiconductor 100b of FIGS. 5 to 8 . The structure of the power semiconductor device 100d including the channel region 107b may refer to the description of FIG. 4 .

Accordingly, in the power semiconductor device 100d, a plurality of power semiconductor devices 100a of FIG. 4 are connected, and a well region 110, a source region 112, a source contact region 112a, and a well contact region 114 are connected therebetween. ) may correspond to the structure in which it is arranged.

11 to 13 are schematic perspective views illustrating a method of manufacturing the power semiconductor device 100 according to an embodiment of the present invention.

Referring to FIG. 11 , a drift region 107 having a first conductivity type may be formed in the semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 may be formed on the drain region 102 having the first conductivity type. In some embodiments, the drain region 102 is provided as a substrate of a first conductivity type, and the drift region 107 may be formed as one or more epitaxial layers on this substrate.

Next, the well region 110 having the second conductivity type may be formed in the semiconductor layer 105 to be in contact with the drift region 107 . For example, the forming of the well region 110 may be performed by implanting impurities of the second conductivity type into the semiconductor layer 105 .

For example, the well region 110 may be formed in the semiconductor layer 105 such that the drift region 107 includes a vertical portion 107a at least partially surrounded by the well region 11 . More specifically, the well region 110 may be formed by doping the drift region 107 with an impurity opposite to that of the drift region 107 .

Subsequently, a deep well region 111 having a second conductivity type may be formed under the well region 110 to be in contact with the well region 110 and the drift region 107 . The deep well region 111 may be formed by implanting impurities of the same second conductivity type as the well region 110 . The well region 110 and the deep well region 111 may be formed in any order.

Subsequently, a source region 112 having a first conductivity type may be formed in the well region 110 . For example, the forming of the source region 112 may be performed by implanting impurities of the first conductivity type into the well region 110 .

In addition to forming the source region 112 , a channel region 110a in which an inversion channel is formed in one direction may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107 . The channel region 110a may be formed between the source region 112 and the vertical portion 107a of the drift region 107 . For example, the channel region 110a may be a part of the well region 110 , and may be formed by implanting impurities of the second conductivity type into the semiconductor layer 105 .

In the above-described manufacturing method, impurity implantation or impurity doping may be performed such that ions are implanted into the semiconductor layer 105 or impurities are mixed during formation of the epitaxial layer. However, for implantation of impurities in the selective region, an ion implantation method using a mask pattern may be used.

Optionally, the ion implantation may be followed by a thermal treatment step to activate or diffuse the impurities.

Referring to FIG. 12 , at least one trench 116 may be formed to be recessed by a predetermined depth from the surface of the semiconductor layer 105 into the semiconductor layer 105 .

For example, the trench 116 may extend across the drift region 107 in one direction and be formed to be shallower than the well region 110 .

Furthermore, the at least one trench 116 may include a plurality of trenches 116 , and for example, the trenches 116 may be simultaneously formed in the semiconductor layer 105 in parallel in one direction. The channel region 110a may be further defined by the trenches 116 .

For example, the trenches 116 may be formed by forming a photomask using photolithography, and then etching the semiconductor layer 105 using the photomask as an etch protective layer.

Referring to FIG. 13 , a gate insulating layer 118 may be formed on the bottom and inner walls of the trenches 116 . For example, the gate insulating layer 118 may be formed of an oxide by oxidizing the semiconductor layer 105 , or may be formed by depositing an insulating material such as oxide or nitride on the semiconductor layer 105 .

Subsequently, gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the trenches 116 . For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning it. The gate electrode layer 120 may be formed by doping polysilicon with impurities or may be formed to include a conductive metal or metal silicide.

The patterning process may be performed using photo lithography and etching processes. The photolithography process includes a process of forming a photoresist pattern with a mask layer using a photolithography process and a developing process, and the etching process includes a process of selectively etching an underlying structure using the photoresist pattern can do.

Accordingly, the well region 110 is disposed deeper than the gate electrode layer 120 so as to surround the bottom surface of the gate electrode layer 120 at one end of the gate electrode layer 120 , and the channel region 110a includes the drift region 107 and The semiconductor layer 105 may be formed on one side or both sides of the gate electrode layer 120 between the source regions 112 .

Subsequently, the interlayer insulating layer 130 may be formed on the gate electrode layer 120 .

Subsequently, the source electrode layer 140 may be formed on the interlayer insulating layer 130 . For example, the source electrode layer 140 may be formed by forming a conductive layer, for example, a metal layer, on the interlayer insulating layer 130 and then patterning it.

Meanwhile, the power semiconductor device 100a of FIG. 4 may be manufactured by adding or modifying some processes to the above-described manufacturing process of the power semiconductor device 100 . For example, the channel region 107b may be formed as part of the drift region 107 to form an accumulation channel.

The power semiconductor device 100b of FIGS. 5 to 8 may be manufactured by adding or modifying some processes to the above-described manufacturing process of the power semiconductor device 100 .

For example, when the power semiconductor device 100b is manufactured, the forming of the source region 112 includes at least a source contact region 112a connected to the source electrode layer 140 outside one end of the gate electrode layer 120 . It may include the step of forming. In some embodiments, the source contact region 112a may be a part of the source region 112 .

Furthermore, before forming the trenches 116 , a well contact region 114 may be formed in the source contact region 112a. For example, the well contact region 114 may be formed by implanting impurities of the second conductivity type into a portion of the well region 110 at a higher concentration than that of the well region 110 .

When the power semiconductor device 100b is manufactured, the trenches 116 may be disposed to be spaced apart in a line in one direction. Further, the well region 110 , the channel region 110a , and the source region 112 may be respectively formed in the semiconductor layer 105 between the trenches 116 .

The fabrication of the power semiconductor device 100c of FIG. 9 forms at least one groove 138 in the source region 112 to penetrate the source region 112 and to be recessed into the well region 110, the groove ( A well contact region 114 is formed on the bottom surface of 138 to be in contact with the well region 110 , and the source electrode layer 140 is connected to the source region 112 and the well contact region 114 by filling the groove 138 . A step of forming may be added.

According to the above-described manufacturing method, the power semiconductor device 100 can be economically manufactured by using the semiconductor layer 105 of silicon carbide and using a process used for an existing silicon substrate.

Although the present invention has been described with reference to the embodiment shown in the drawings, which is merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: power semiconductor device
102: drain region
105: semiconductor layer
107: drift zone
110: well area
111: deep well region
112: source area
118: gate insulating layer
120: gate electrode layer
130: interlayer insulating layer
140: source electrode layer

Claims (13)

a semiconductor layer of silicon carbide (SiC);
at least one trench formed by recessing a predetermined depth into the semiconductor layer from the surface of the semiconductor layer and extending in one direction;
a gate insulating layer formed on at least an inner wall of the at least one trench;
at least one gate electrode layer formed on the gate insulating layer to fill the at least one trench;
a drift region formed in the semiconductor layer on one side of the at least one gate electrode layer and having a first conductivity type;
a well region formed in the semiconductor layer deeper than the at least one gate electrode layer so as to contact the drift region and surround a bottom surface of the at least one gate electrode layer at one end of the at least one gate electrode layer, the well region having a second conductivity type;
a deep well region formed under the well region in contact with the well region and the drift region and having a second conductivity type;
a source region formed in the well region and having a first conductivity type; and
a channel region formed in the semiconductor layer on one side of the at least one gate electrode layer between the drift region and the source region and extending along the one direction;
The deep well region is formed to have a narrower width than a width of the well region in the one direction,
both ends of the deep well region are respectively moved inward from both ends of the well region with respect to the one direction;
power semiconductor devices. The method of claim 1,
a source contact region in the source region outside one end of the at least one gate electrode layer;
a well contact region extending from the well region through the source region in the source contact region, having a second conductivity type, and doped with a higher concentration than the well region; and
a source electrode layer connected to the source contact region and the well region;
power semiconductor devices. delete The method of claim 1,
the drift region includes vertical portions extending perpendicular to the semiconductor layer on both sides of the at least one gate electrode layer;
the channel region is formed in the semiconductor layer between the source region and the vertical portions of the drift region;
power semiconductor devices. The method of claim 1,
The channel region has a second conductivity type so that an inversion channel is formed along the one direction;
wherein the channel region is part of the well region;
power semiconductor devices. The method of claim 1,
the channel region has a first conductivity type such that an accumulation channel is formed along the one direction;
wherein the channel region is part of the drift region;
power semiconductor devices. The method of claim 1,
The at least one trench includes a plurality of trenches formed in parallel in the semiconductor layer along the one direction,
the at least one gate electrode layer includes a plurality of gate electrode layers formed by filling the plurality of trenches;
the well region and the source region are respectively connected across the plurality of gate electrode layers;
power semiconductor devices. The method of claim 1,
The at least one trench includes a plurality of trenches spaced apart in a line in the one direction,
the at least one gate electrode layer includes a plurality of gate electrode layers formed by filling the plurality of trenches;
the well region and the source region are respectively formed in the semiconductor layer between at least the plurality of trenches;
power semiconductor devices. The method of claim 1,
at least one groove passing through the source region and recessed into the well region by a predetermined depth;
a well contact region formed in contact with the well region on a bottom surface of the at least one groove; and
a source electrode layer formed to fill the at least one groove and connected to the source region and the well contact region;
power semiconductor devices. The method of claim 1,
a drain region having a first conductivity type in the semiconductor layer under the drift region;
the drain region is doped at a higher concentration than the drift region;
wherein the drift region is formed as an epitaxial layer on the drain region;
power semiconductor devices. forming a drift region having a first conductivity type in a semiconductor layer of silicon carbide (SiC);
forming a well region in contact with the drift region and having a second conductivity type in the semiconductor layer;
forming a deep well region in contact with the well region and the drift region under the well region and having a second conductivity type;
forming a source region having a first conductivity type in the well region;
forming a channel region extending in one direction in a semiconductor layer between the drift region and the source region;
forming at least one trench recessed by a predetermined depth from the surface of the semiconductor layer into the semiconductor layer, extending across the drift region in the one direction, and shallower than the well region;
forming a gate insulating layer on at least an inner wall of the at least one trench; and
forming at least one gate electrode layer on the gate insulating layer to fill the at least one trench;
The well region is formed in the semiconductor layer deeper than the at least one gate electrode layer so as to surround a bottom surface of the at least one gate electrode layer at one end of the at least one gate electrode layer;
the channel region is formed in the semiconductor layer on one side of the at least one gate electrode layer between the drift region and the source region;
The deep well region is formed to have a width narrower than a width of the well region in the one direction,
both ends of the deep well region are respectively moved inward from both ends of the well region based on the one direction;
A method of manufacturing a power semiconductor device. 12. The method of claim 11,
forming a source contact region outside one end of the at least one gate electrode layer;
forming a well contact region extending from the well region through the source region in the source contact region, having a second conductivity type, and doped at a higher concentration than the well region; and
Forming a source electrode layer connected to the source contact region and the well contact region; further comprising
A method of manufacturing a power semiconductor device. 12. The method of claim 11,
forming at least one groove in the source region to penetrate the source region and to be recessed into the well region;
forming a well contact region having a second conductivity type in contact with the well region on a bottom surface of the at least one groove; and
Forming a source electrode layer to fill the at least one groove and to be connected to the source region and the well contact region;
A method of manufacturing a power semiconductor device.

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