KR102379155B1 - Power semiconductor device and method of fabricating the same - Google Patents

Abstract

A power semiconductor device according to an aspect of the present invention includes a semiconductor layer of silicon carbide (SiC), at least one trench formed by recessing a predetermined depth into the semiconductor layer from a surface of the semiconductor layer, and the at least one trench a gate insulating layer formed on at least an inner surface of a, at least one gate electrode layer formed on the gate insulating layer to fill the at least one trench; a drift region having a first conductivity type and including a protrusion in contact with a portion of the bottom surface of the one trench; and a well region having a second conductivity type, and a source region formed in the well region and having a first conductivity type.

Description

Power semiconductor device and method of manufacturing the same

The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device for switching power transmission and a method of manufacturing the same.

A power semiconductor device is a semiconductor device that operates in a high voltage and high current environment. Such power semiconductor devices are used in fields requiring high power switching, for example, power conversion, power converters, inverters, and the like. For example, the power semiconductor device may include an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), or the like. Such a power semiconductor device is basically required to withstand high voltage, and recently, a high-speed switching operation is additionally required.

Accordingly, a power semiconductor device using silicon carbide (SiC) instead of conventional silicon (Si) is being studied. Silicon carbide (SiC) is a wide-gap semiconductor material having a higher bandgap than silicon, and can maintain stability even at high temperatures compared to silicon. Furthermore, silicon carbide has a very high insulating wave field compared to silicon, so it can operate stably even at a high voltage. Therefore, silicon carbide has a higher breakdown voltage than silicon, and exhibits excellent heat dissipation, so that it can be operated at a high temperature.

In order to increase the channel density of a power semiconductor device using such silicon carbide, a trench-type gate structure having a vertical channel structure is being studied. In such a trench-type gate structure, there is a problem in that an electric field is concentrated at the edge of the trench, and various structures are applied to protect the lower portion of the trench, but there is a limit in alleviating the electric field in the vertical channel structure.

Republic of Korea Publication No. 2011-0049249 (published on May 11, 2011)

An object of the present invention is to provide a silicon carbide power semiconductor device capable of improving reliability by alleviating electric field concentration at a trench edge, and a method for manufacturing the same. However, these problems are exemplary, and the scope of the present invention is not limited thereto.

A power semiconductor device according to an aspect of the present invention for solving the above problems includes a semiconductor layer of silicon carbide (SiC), and at least one trench formed by recessing a predetermined depth into the semiconductor layer from the surface of the semiconductor layer; , a gate insulating layer formed on at least an inner surface of the at least one trench; at least one gate electrode layer formed on the gate insulating layer to fill the at least one trench; and the semiconductor layer under the at least one gate electrode layer. a drift region having a first conductivity type and including a protrusion in contact with a portion of a bottom surface of the at least one trench; and a well region formed on the semiconductor layer and having a second conductivity type, and a source region formed in the well region and having a first conductivity type.

According to the power semiconductor device, the well region is formed in the semiconductor layer deeper than the at least one trench while exposing a central portion of the bottom surface of the at least one trench and surrounding the bottom edges, A protrusion may be formed to contact the gate insulating layer and the well region at a central portion of the bottom surface of the at least one trench exposed by the well region.

The power semiconductor device may further include a channel region formed in the well region adjacent to the at least one gate electrode layer so as to extend from the protrusion of the drift region to the source region.

According to the power semiconductor device, the channel region is a horizontal portion formed horizontally in the well region under the bottom surface of the at least one gate electrode layer and a vertical portion formed perpendicular to the well region on one side of the at least one gate electrode layer. may include wealth.

According to the power semiconductor device, the at least one trench extends in one direction in a line type, and the at least one trench includes both side surfaces and both side bottom corners connected to the both side surfaces with respect to the one direction, and the A well region may extend below the bottom surface of the at least one trench to cover both sides of the at least one trench and to cover both bottom edges of the at least one trench.

According to the power semiconductor device, the at least one trench includes a plurality of trenches extending in one direction in a line type and arranged in parallel with each other, and the gate insulating layer is formed on at least inner surfaces of the plurality of trenches, The at least one gate electrode layer may include a plurality of gate electrode layers formed on the gate insulating layer to respectively fill the plurality of trenches.

According to the power semiconductor device, the well region is formed in the semiconductor layer between the plurality of trenches to cover both side surfaces of the plurality of trenches, and the well region is formed in the plurality of trenches to cover both bottom corners of the plurality of trenches. It can be stretched below the floor surface.

The power semiconductor device may further include a drain region having a first conductivity type in the semiconductor layer under the drift region, wherein the drain region is doped to a higher concentration than the drift region.

According to the power semiconductor device, the drain region may be provided as a silicon carbide substrate having a first conductivity type, and the drift region may be formed as an epitaxial layer on the drain region.

A method of manufacturing a power semiconductor device according to another aspect of the present invention for solving the above problems includes the steps of: forming a drift region including a protrusion and having a first conductivity type in a semiconductor layer of silicon carbide (SiC); forming a well region having a second conductivity type in the semiconductor layer on a drift region; forming a source region having a first conductivity type in the semiconductor layer on the well region; forming at least one trench recessed into the semiconductor layer so as to penetrate a portion of the source region and contact the protrusion of the drift region; and forming a gate insulating layer on at least an inner surface of the at least one trench. and forming at least one gate electrode layer on the gate insulating layer to fill the at least one trench, wherein the protrusion of the drift region is in contact with a portion of a bottom surface of the at least one trench; The well region is formed in the semiconductor layer to surround side surfaces and bottom corners of the at least one trench and to be in contact with the drift region.

According to the method of manufacturing the power semiconductor device, the method may further include forming a channel region in the well region adjacent to the at least one gate electrode layer so as to extend from the protrusion of the drift region to the source region.

According to the power semiconductor device and the method for manufacturing the same according to an embodiment of the present invention made as described above, it is possible to improve the reliability of the device by reducing the concentration of the electric field at the edge of the trench.

Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

1 is a schematic cross-sectional view showing a power semiconductor device according to an embodiment of the present invention.
2 to 5 are cross-sectional views illustrating a method of manufacturing the power semiconductor device of FIG. 1 .
6 is a schematic perspective view showing a power semiconductor device according to another embodiment of the present invention.
7 is a schematic cross-sectional view showing a power semiconductor device according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. It is provided to fully inform the In addition, in the drawings for convenience of description, the size of at least some of the components may be exaggerated or reduced. In the drawings, like numbers refer to like elements.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for the purpose of explanation, and thus are provided to explain the general structures of the present invention.

Like reference signs indicate like elements. When referring to one component as being on another component, such as a layer, region, or substrate, it will be understood that other intervening components may also be present, either directly on top of the other component or in between. On the other hand, when referring to one configuration as being “directly on” of another, it is understood that intervening configurations do not exist.

1 is a schematic cross-sectional view showing a power semiconductor device 100 according to an embodiment of the present invention.

Referring to FIG. 1 , the power semiconductor device 100 may include at least a semiconductor layer 105 , a gate insulating layer 118 , and a gate electrode layer 120 . For example, the power semiconductor device 100 may have a power MOSFET structure.

The semiconductor layer 105 may refer to one or more semiconductor material layers, for example, one or multiple epitaxial layers. Furthermore, the semiconductor layer 105 may refer to one or multiple epitaxial layers on a semiconductor substrate.

For example, the semiconductor layer 105 may be made of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

Silicon carbide (SiC) has a wider bandgap than silicon, so it can maintain stability even at high temperatures compared to silicon. Furthermore, silicon carbide has a very high insulating wave field compared to silicon, so it can operate stably even at a high voltage. Accordingly, the power semiconductor device 100 using silicon carbide as the semiconductor layer 105 has a high breakdown voltage and excellent heat dissipation characteristics compared to the case where silicon is used, and may exhibit stable operating characteristics even at high temperatures.

More specifically, the semiconductor layer 105 may include a drift region 107 . The drift region 107 may have the first conductivity type, and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105 . For example, the drift region 107 may be formed by doping an impurity of the first conductivity type into an epitaxial layer of silicon carbide. Further, the drift region 107 may include a protrusion 107a, a portion of which extends upward.

A well region 110 may be formed in contact with the drift region 107 in the semiconductor layer 105 and may have a second conductivity type. For example, the well region 110 may be formed by doping the semiconductor layer 105 with impurities of a second conductivity type opposite to the first conductivity type.

For example, the well region 110 may be formed to surround at least a portion of the drift region 107 and be in contact with the drift region 107 . More specifically, the well region 110 may surround a side surface of the protrusion 107a of the drift region 107 and be formed on another portion of the drift region 107 . During operation of the power semiconductor device 100 , the protrusion 107a may provide a vertical movement path of electric charges.

In FIG. 1 , the well region 110 is formed to be spaced apart into two regions and the vertical portion 107a is defined therebetween, but other various modifications may be made. For example, the vertical portion 107a may have a shape in which a side surface thereof is surrounded by the well region 110 once.

A source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the well region 110 with an impurity of the first conductivity type. The source region 112 may be formed by doping a higher concentration of impurities of the first conductivity type than the drift region 107 .

Additionally, the drain region 102 may be formed in the semiconductor layer 105 under the drift region 107 and may have a first conductivity type. For example, the drain region 102 may be doped at a higher concentration than the drift region 107 .

In some embodiments, the drain region 102 may be provided as a substrate of silicon carbide having a first conductivity type. In this case, the drain region 102 may be understood as a part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105 .

The at least one trench 116 may be formed by recessing a predetermined depth into the semiconductor layer 105 from the surface of the semiconductor layer 105 . For example, the trench 116 may be formed to etch a portion of the well region 110 from the surface of the semiconductor layer 105 and contact the protrusion 107a of the drift region 107 . Accordingly, the protrusion 107a of the drift region 107 may come into contact with a portion of the bottom surface ( 116a of FIG. 3 ) of the trench 116 .

Furthermore, in the portion in contact with the trench 116 , the well region 110 has a bent shape due to its edge being dug, and the trench 116 has a structure seated on the bent portion of the well region 110 . can Accordingly, the well region 110 may be formed to surround the side surfaces ( 116b of FIG. 3 ) and bottom corners ( 116c of FIG. 3 ) of the trench 116 and be in contact with the drift region 107 .

In some embodiments, the number of trenches 116 may be appropriately selected from one or a plurality according to the performance of the power semiconductor device 100 , and may be variously arranged, such as a line type or a matrix structure.

The gate insulating layer 118 may be formed on at least an inner surface of the trench 116 . For example, the gate insulating layer 118 may be formed on the inner surface of the trench 116 and the semiconductor layer 105 outside the trench 116 . The thickness of the gate insulating layer 118 may be uniform, or the portion formed on the bottom surface of the trench 116 may be thicker than the portion formed on the sidewall in order to lower the electric field at the bottom portion of the trench 116 .

For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stacked structure thereof.

At least one gate electrode layer 120 may be formed on the gate insulating layer 118 to fill at least the trench 116 . For example, the gate electrode layer 120 may include a suitable conductive material, such as polysilicon, metal, metal nitride, metal silicide, or the like, or may include a stacked structure thereof.

In some embodiments, the gate electrode layer 120 may be formed to fill the inside of the trench 116 and to further protrude onto the semiconductor layer 105 . Furthermore, the protruding portion of the gate electrode layer 120 may further extend onto the well region 110 or the source region 112 . Accordingly, the cross-sectional area of the protruding portion of the gate electrode layer 120 may be larger than the cross-sectional area of the buried portion in the trench 116 .

In some embodiments, the well region 110 may be formed in the semiconductor layer 105 deeper than the trench 116 while surrounding the bottom edges 116c while exposing at least a central portion above the bottom surface 116a of the trench 116 . can The protrusion 107a of the drift region 107 is to be formed in contact with the gate insulating layer 118 and the well region 110 at the center of the bottom surface 116a of the trench 116 exposed by the well region 110 . can

The channel region 110a may be formed in the well region 110 adjacent to the gate electrode layer 120 so as to extend from the protrusion 107a of the drift region 107 to the source region 112 . For example, the channel region 110a may have a second conductivity type, and an inversion channel may be formed in the channel region 110a during operation of the power semiconductor device 100 .

Since the channel region 110a has a doping type opposite to that of the source region 112 and the drift region 107 , the channel region 110a may form a diode junction junction with the source region 112 and the drift region 107 . can Accordingly, although the channel region 110a does not allow the movement of charges under normal circumstances, when an operating voltage is applied to the gate electrode layer 120 , an inversion channel is formed therein to allow the movement of charges. .

In some embodiments, the channel region 110a may be a part of the well region 110 . In this case, the channel region 110a may be integrally formed to be continuously connected to the well region 110 . The doping concentration of the impurity of the second conductivity type in the channel region 110a may be the same as that of other portions of the well region 110 or may be different for controlling the threshold voltage.

More specifically, the channel region 110a includes a horizontal portion 110a1 formed horizontally in the well region 110 under the bottom surface of the gate electrode layer 120 or the bottom surface 116a of the trench 116 and the gate electrode layer ( A vertical portion 110a2 formed perpendicular to the well region 110 on one side surface of 120 or one side 116b of the trench 116 may be included. One end of the horizontal portion 110a1 of the channel region 110 may be in contact with the protrusion 107a of the drift region 107 , and one end of the vertical portion 110a2 of the channel region 110 may be in contact with the source region 112 . . Accordingly, the channel region 110a may have a structure in which a horizontal structure and a vertical structure are combined, rather than simply having a vertical structure.

The well contact region 114 may be formed in the source region 112 or on the well region 110 . For example, the well contact region 114 may extend from the well region 110 through the source region 112 and may have the second conductivity type. One or a plurality of well contact regions 114 may be formed in the source region 112 . The well contact region 114 may be doped with an impurity of the second conductivity type at a higher concentration than the well region 110 in order to lower the contact resistance.

The interlayer insulating layer 130 may be formed on the gate electrode layer 120 . For example, the interlayer insulating layer 130 may include a suitable insulating material, such as an oxide layer, a nitride layer, or a laminate structure thereof.

The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be connected to the source region 112 and the well contact region 114 . For example, the source electrode layer 140 may be formed of an appropriate conductive material, metal, or the like.

In the above-described power semiconductor device 100 , the first conductivity type and the second conductivity type may have opposite conductivity types, but may be either n-type or p-type, respectively. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

More specifically, when the power semiconductor device 100 is an N-type MOSFET, the drift region 107 is an N- region, the source region 112 and the drain region 102 are an N+ region, and the well region 110 and The channel region 110a may be a P− region, and the well contact region 114 may be a P+ region.

In operation of the power semiconductor device 100 , a current flows from the drain region 102 in a generally vertical direction along the protrusion 107a of the drift region 107 , and then through the channel region 110a of the gate electrode layer 120 . It may flow in a horizontal direction along a bottom surface and then in a vertical direction along a side surface of the gate electrode layer 120 to the source region 112 .

In the power semiconductor device 100 , the well region 110 may surround all bottom edges of the gate electrode layer 120 or bottom edges 116c of the trench 116 . Accordingly, it is possible to further alleviate the problem that the electric field is concentrated on the bottom edges of the gate electrode layer 120 or the bottom edges 116c of the trench 116 . Accordingly, the electric field margin applied to the gate insulating layer 118 in the power semiconductor device 100 may be increased, thereby increasing the operational reliability of the power semiconductor device 100 . Furthermore, by lowering the electric field at the bottom of the trench 116 and lowering the electric field applied to the gate insulating layer 118 , there is a room for lowering the junction resistance of the vertical portion 107a of the drift region 107 .

2 to 5 are cross-sectional views illustrating a method of manufacturing the power semiconductor device 100 of FIG. 1 .

Referring to FIG. 2 , the drift region 107 including the protrusion 107a and having the first conductivity type may be formed in the semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 may be formed on the drain region 102 having the first conductivity type. In some embodiments, drain region 102 is provided as a substrate of silicon carbide having a first conductivity type, and drift region 107 may be formed as one or more epitaxial layers on this substrate.

Next, the well region 110 having the second conductivity type may be formed in the semiconductor layer 105 to be in contact with the drift region 107 . For example, the forming of the well region 110 may be performed by implanting impurities of the second conductivity type into the semiconductor layer 105 .

For example, the well region 110 may be formed in the semiconductor layer 105 to surround the protrusion 107a of the drift region 107 . In some embodiments, the drift region 107 is formed in at least one layer on the drain region 102 , and the well region 110 is formed by doping the drift region 107 with an impurity opposite to that of the drift region 107 . can be formed In this case, the well region 110 may be formed such that the protrusion 107a is defined in the drift region 107 .

In some embodiments, unlike FIG. 2 , the well region 110 may be continuously formed on the protrusion 107a of the drift region 107 .

Subsequently, the source region 112 having the first conductivity type may be formed in or on the well region 110 . For example, the forming of the source region 112 may be performed by implanting impurities of the first conductivity type into the semiconductor layer 105 on the well region 110 or into the well region 110 .

Furthermore, a well contact region 114 may be formed on the well region 110 . For example, the well contact region 114 may contain impurities of the second conductivity type in a portion of the semiconductor layer 105 on the well region 110 or in a portion of the well region 110 at a higher concentration than that of the well region 110 . It can be formed by injection.

Furthermore, the channel region 110a may be formed in the semiconductor layer 105 between the source region 112 and the protrusion 107a of the drift region 107 . For example, the channel region 110a may be a part of the well region 110 , and may be formed by implanting impurities of the second conductivity type into the semiconductor layer 105 .

In the above-described steps, impurity implantation or impurity doping may be performed such that ions are implanted into the semiconductor layer 105 or impurities are mixed during formation of the epitaxial layer. However, for implantation of impurities in the selective region, an ion implantation method using a mask pattern may be used.

Optionally, the ion implantation may be followed by a thermal treatment step to activate or diffuse the impurities.

Referring to FIG. 3 , at least one trench 116 may be formed to be recessed by a predetermined depth from the surface of the semiconductor layer 105 into the semiconductor layer 105 .

For example, the trench 116 may be formed by partially etching the protrusion 107a of the drift region 107 and a portion of the well region 110 . Accordingly, the source region 112 may be disposed to be in contact with the trench 116 . Furthermore, the bottom surface 116a of the trench 116 may be formed to contact the protrusion 107a of the drift region 107 . Accordingly, the trench 116 may be formed to be shallower than the average depth 110 of the well region 110 .

More specifically, in the portion in contact with the trench 116 , the well region 110 has a bent shape due to its edge being dug, and the trench 116 is seated on the bent portion of the well region 110 . can have Accordingly, the well region 110 surrounds the side surfaces 116b and the bottom corners 116c of the trench 116 and comes into contact with the drift region 107 , and the protrusion 107a of the drift region 107 forms the trench. It may come into contact with a portion of the bottom surface 116a of 116 . Further, the source region 112 may be in contact with upper ends of the side surfaces 116b of the trench 116 .

In some embodiments, when the well region 110 is continuously disposed on the protrusion 107a of the drift region 107 , the trench 116 passes through a portion of the source region 112 and extends through a portion of the well region 110 . It may be formed by partially etching a part.

Due to the structure of the trench 116 , the channel region 110a includes a horizontal portion 110a1 formed horizontally in the well region 110 under the bottom surface 116a of the trench 116 and one side of the trench 116 . A vertical portion 110a2 formed perpendicular to the well region 110 on the 116b may be included.

For example, the trench 116 may be formed by forming a photomask using photolithography, and then etching the semiconductor layer 105 using the photomask as an etch protective layer.

Referring to FIG. 4 , a gate insulating layer 118 may be formed on at least inner surfaces of the trenches 116 . For example, the gate insulating layer 118 may be formed of an oxide by oxidizing the semiconductor layer 105 , or may be formed by depositing an insulating material such as oxide or nitride on the semiconductor layer 105 .

Next, gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the trenches 116 . For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning it. The gate electrode layer 120 may be formed by doping polysilicon with impurities or may be formed to include a conductive metal or metal silicide.

The patterning process may be performed using photo lithography and etching processes. The photolithography process includes a process of forming a photoresist pattern as a mask layer using a photolithography process and a developing process, and the etching process includes a process of selectively etching an underlying structure using the photoresist pattern can do.

Referring to FIG. 5 , an interlayer insulating layer 130 may be formed on the gate electrode layer 120 . For example, the interlayer insulating layer 130 may be formed by forming at least one insulating layer, for example, an oxide layer, on the structure on which the gate electrode layer 120 is formed and then patterning it.

Subsequently, the source electrode layer 140 may be formed on the interlayer insulating layer 130 to be connected to the source region 112 and the well contact region 114 . For example, the source electrode layer 140 may be formed by forming a conductive layer, for example, a metal layer, on the interlayer insulating layer 130 and then patterning it.

According to the above-described manufacturing method, the power semiconductor device 100 can be economically manufactured by using the semiconductor layer 105 of silicon carbide and using a process used for an existing silicon substrate.

6 is a schematic perspective view showing a power semiconductor device 100a according to another embodiment of the present invention. The power semiconductor device 100a according to this embodiment uses or partially modified the power semiconductor device 100 of FIG. 1 , and thus can be referenced to each other, and repeated descriptions are omitted.

Referring to FIG. 6 , in the power semiconductor device 100a, the trench 116 may be formed to extend in one direction in a line type. Accordingly, the trench 116 may include both side surfaces ( 116b of FIG. 3 ) and bottom corners ( 116c of FIG. 3 ) connected to both side surfaces 116b in one direction.

The well region 110 may extend below the bottom surface ( 116b of FIG. 3 ) of the trench 116 to cover both sides 116b of the trench 116 and to cover both bottom corners 116c of the trench 116 .

As the trench 116 is formed in a line type, the gate electrode layer 120 may also be formed in a line type to extend in one direction. Accordingly, both bottom corners of the gate electrode layer 120 may be surrounded by the well region 110 .

The manufacturing method of the power semiconductor device 100a may refer to the manufacturing method of the power semiconductor device 100 of FIGS. 2 to 5 .

According to the power semiconductor device 100a, like the power semiconductor device 100, it is possible to further alleviate the problem that the electric field is concentrated at the bottom corners of the gate electrode layer 120 or the bottom corners 116c of the trench 116. . Accordingly, the electric field margin applied to the gate insulating layer 118 in the power semiconductor device 100a may be increased, thereby increasing the operational reliability of the power semiconductor device 100a.

7 is a schematic perspective view showing a power semiconductor device 100b according to another embodiment of the present invention. The power semiconductor device 100b according to this embodiment uses or partially modifies the power semiconductor device 100 of FIG. 1 and the power semiconductor device 100a of FIG. do.

Referring to FIG. 7 , in the power semiconductor device 100b, a plurality of trenches 116 may be formed to be arranged in parallel with each other in a line type extending in one direction.

The gate insulating layer 118 may be formed on inner surfaces of the trenches 116 . The plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the trenches 116 , respectively. Accordingly, the gate electrode layers 120 may be formed in the semiconductor layer 105 in a trench type, and may be disposed to extend in parallel in one direction like the trenches 116 .

The well region 110 may be formed in the semiconductor layer 105 between the trenches 116 to cover both side surfaces 116b of the trenches 116 . Further, the well region 110 may extend below the bottom surfaces 116a of the trenches 116 to cover both bottom edges 116c of the trenches 116 . The well region 110 may expose at least a central portion of the bottom surface 116a of the trenches 116 , in which the protrusions 107a of the drift region 107 are adjacent to the well region 110a in the exposed portion. can be formed

In some embodiments, the drift region 107 is to be disposed on the drain region 102 across the trenches 116 or the gate electrode layers 120 under the well region 110 except for the protrusions 107a. can

In the power semiconductor device 100b, the gate electrode layers 120 in the trenches 116 may be densely disposed in parallel in a stripe type or a line type.

The manufacturing method of the power semiconductor device 100b may refer to the manufacturing method of the power semiconductor device 100 of FIGS. 2 to 5 .

According to the power semiconductor device 100b, similar to the power semiconductor device 100, the problem of electric field concentration on the bottom edges of the gate electrode layers 120 or the bottom edges 116c of the trenches 116 can be further alleviated. can Accordingly, the electric field margin applied to the gate insulating layer 118 in the power semiconductor device 100b may be increased, thereby improving the operational reliability of the power semiconductor device 100b.

Although the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: power semiconductor device
102: drain region
105: semiconductor layer
107: drift zone
110: well area
112: source area
114: well contact area
118: gate insulating layer
120: gate electrode layer
130: interlayer insulating layer
140: source electrode layer

Claims (11)

a semiconductor layer of silicon carbide (SiC);
at least one trench formed by recessing a predetermined depth into the semiconductor layer from the surface of the semiconductor layer;
a gate insulating layer formed on at least an inner surface of the at least one trench;
at least one gate electrode layer formed on the gate insulating layer to fill the at least one trench;
a drift region formed in the semiconductor layer under the at least one gate electrode layer, the drift region having a first conductivity type, the drift region including a protrusion in contact with a portion of a bottom surface of the at least one trench;
a well region having a second conductivity type, formed in the semiconductor layer to surround side surfaces and bottom corners of the at least one trench and to be in contact with the drift region;
a source region formed in the well region and having a first conductivity type; and
a channel region formed in the well region adjacent to the at least one gate electrode layer so as to extend from the protrusion of the drift region to the source region;
The channel area is
a horizontal portion formed horizontally in the well region under a bottom surface of the at least one gate electrode layer and a vertical portion formed perpendicular to the well region on both sides of the at least one gate electrode layer;
The channel area is
It is symmetrically formed to cover both bottom edges of the at least one trench,
the horizontal part
spaced apart from both sides of the bottom surface of the at least one trench,
power semiconductor devices. The method of claim 1,
The well region is formed in the semiconductor layer deeper than the at least one trench while surrounding the bottom corners while exposing a central portion of the bottom surface of the at least one trench;
The protrusion of the drift region is formed to contact the gate insulating layer and the well region at a central portion of the bottom surface of the at least one trench exposed by the well region;
power semiconductor devices. delete delete The method of claim 1,
The at least one trench extends in one direction in a line type,
The at least one trench includes both side surfaces and both side bottom edges connected to the both side surfaces with respect to the one direction,
the well region extends below the bottom surface of the at least one trench to cover both sides of the at least one trench and to cover the both bottom edges of the at least one trench;
power semiconductor devices. The method of claim 1,
The at least one trench includes a plurality of trenches extending in one direction in a line type and arranged in parallel with each other,
the gate insulating layer is formed on at least inner surfaces of the plurality of trenches;
wherein the at least one gate electrode layer includes a plurality of gate electrode layers formed on the gate insulating layer to respectively fill the plurality of trenches,
power semiconductor devices. 7. The method of claim 6,
The well region is formed in the semiconductor layer between the plurality of trenches to cover both side surfaces of the plurality of trenches, and extends below the bottom surfaces of the plurality of trenches to cover both bottom edges of the two plurality of trenches. ,
power semiconductor devices. The method of claim 1,
a drain region having a first conductivity type in the semiconductor layer under the drift region;
The drain region is formed by doping at a higher concentration than the drift region,
power semiconductor devices. 9. The method of claim 8,
The drain region is provided as a substrate of silicon carbide having a first conductivity type;
wherein the drift region is formed as an epitaxial layer on the drain region;
power semiconductor devices. forming a drift region including protrusions and having a first conductivity type in a semiconductor layer of silicon carbide (SiC);
forming a well region having a second conductivity type in the semiconductor layer on the drift region;
forming a source region having a first conductivity type in the semiconductor layer on the well region;
forming at least one trench recessed into the semiconductor layer from the surface of the semiconductor layer through a portion of the source region and in contact with the protrusion of the drift region;
forming a gate insulating layer on at least an inner surface of the at least one trench;
forming at least one gate electrode layer on the gate insulating layer to fill the at least one trench; and
forming a channel region in the well region adjacent to the at least one gate electrode layer so as to extend from the protrusion of the drift region to the source region;
the protrusion of the drift region abuts a portion of the bottom surface of the at least one trench,
the well region is formed in the semiconductor layer to surround side surfaces and bottom corners of the at least one trench and to be in contact with the drift region;
The channel area is
a horizontal portion formed horizontally in the well region under a bottom surface of the at least one gate electrode layer and a vertical portion formed perpendicular to the well region on both sides of the at least one gate electrode layer;
The channel area is
It is symmetrically formed to cover both bottom edges of the at least one trench,
the horizontal part
spaced apart from both sides of the bottom surface of the at least one trench,
A method of manufacturing a power semiconductor device. delete

Images