KR102369054B1 - Power semiconductor device and method of fabricating the same - Google Patents

Abstract

A power semiconductor device according to an aspect of the present invention provides a semiconductor layer of silicon carbide (SiC), a gate insulating layer on a part of the semiconductor layer, a gate electrode layer on the gate insulating layer, and a vertical movement path for electric charges. a drift region formed in a semiconductor layer and including at least one protruding portion disposed under the gate electrode layer, the drift region having a first conductivity type; and the at least one protrusion of the drift region in the semiconductor layer under the gate electrode layer a well region having a second conductivity type, comprising a first well region formed in contact with a portion and a second well region formed in the semiconductor layer outside the gate electrode layer and connected to the first well region; a pillar region of a second conductivity type formed in the semiconductor layer in contact with the well region and having a second conductivity to form a super junction with the drift region; a second source region formed in the semiconductor layer on a second well region and connected to the first source region, a source region having a first conductivity type; the at least one protruding portion of the drift region; and the first source region and including a channel region formed in the semiconductor layer between the regions.

Description

Power semiconductor device and method of manufacturing the same

The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device for switching power transmission and a method of manufacturing the same.

A power semiconductor device is a semiconductor device that operates in a high voltage and high current environment. Such power semiconductor devices are used in fields requiring high power switching, for example, power conversion, power converters, inverters, and the like. For example, the power semiconductor device may include an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), or the like. Such a power semiconductor device is basically required to withstand high voltage, and recently, a high-speed switching operation is additionally required.

Accordingly, a power semiconductor device using silicon carbide (SiC) instead of conventional silicon (Si) is being studied. Silicon carbide (SiC) is a wide-gap semiconductor material having a higher bandgap than silicon, and can maintain stability even at high temperatures compared to silicon. Furthermore, silicon carbide has a very high insulating wave field compared to silicon, so it can operate stably even at a high voltage. Therefore, silicon carbide has a higher breakdown voltage than silicon, and exhibits excellent heat dissipation, so that it can be operated at a high temperature.

In the case of a power semiconductor device using such silicon carbide, the band gap on the surface of the silicon carbide rises upward due to the influence of negative charges due to the formation of carbon clusters in the gate insulating layer, so there is a problem in that the threshold voltage is increased and the channel resistance is increased. In addition, since the source contact structure is disposed between the gate electrodes, it is difficult to narrow the gap between the gate electrodes, so there is a limit in reducing the channel density.

Republic of Korea Publication No. 2011-0049249 (published on May 11, 2011)

An object of the present invention is to provide a silicon carbide power semiconductor device capable of reducing operation loss and increasing channel density, and a method for manufacturing the same, in order to solve the above problems. However, these problems are exemplary, and the scope of the present invention is not limited thereto.

A power semiconductor device according to an aspect of the present invention for solving the above problems is a semiconductor layer of silicon carbide (SiC), a gate insulating layer on a part of the semiconductor layer, a gate electrode layer on the gate insulating layer, and a vertical charge a drift region formed in the semiconductor layer to provide a movement path and including at least one protruding portion disposed under the gate electrode layer, the drift region having a first conductivity type; and the drift region in the semiconductor layer under the gate electrode layer A well region having a second conductivity type, comprising: a first well region formed in contact with the at least one protrusion of a pillar region formed in the semiconductor layer under the well region in contact with the well region and having a second conductivity type to form a super junction with the drift region; a source region including a first source region and a second source region formed in the semiconductor layer on the second well region and connected to the first source region, the source region having a first conductivity type; and the at least one protrusion of the drift region and a channel region formed in the semiconductor layer between the portion and the first source region.

According to the power semiconductor device, the amount of charge in the pillar region may be greater than the amount of charge in the drift region so that the maximum electric field is located in the drift region on the same line as the bottom surface of the pillar region during operation.

According to the power semiconductor device, a doping concentration of the impurity of the second conductivity type in the pillar region may be greater than a doping concentration of the impurity of the first conductivity type in the drift region.

According to the power semiconductor device, the at least one protruding portion of the drift region, the first well region and the first source region extend in one direction, and the first well region, the first source region, and the channel Regions may be respectively formed in the semiconductor layer on both sides of the at least one protruding portion of the drift region.

According to the power semiconductor device, the channel region may have a second conductivity type such that an inversion channel is formed, and the channel region may be a part of the well region.

According to the power semiconductor device, the channel region may have a first conductivity type to form an accumulation channel, and the channel region may be a part of the drift region.

According to the power semiconductor device, the first well region protrudes more in a direction of the at least one protruding portion of the drift region than the first source region, and the channel region is formed on the protruding portion of the first well region. It may be formed on the semiconductor layer.

According to the power semiconductor device, the at least one protruding portion may include a plurality of protruding portions formed in parallel in one direction, and the channel region may be formed between the plurality of protruding portions and the first source region. .

According to the power semiconductor device, the first well region is formed symmetrically with respect to the second well region,

The first source region is symmetrically formed with respect to the second source region, and the at least one protruding portion of the drift region is symmetrically disposed with respect to the second well region or the second source region. It may include a plurality of protruding portions.

According to the power semiconductor device, in the second source region, a well contact region extending from the second well region through the second source region and having a second conductivity type, the second source region, and the well contact region It may include a connected source electrode layer.

According to the power semiconductor device, at least one groove passing through the second source region and exposing the second well region is formed in a bottom surface of the at least one groove to be in contact with the second well region, and a second conductivity It may further include a well contact region having a shape, and a source electrode layer formed to fill the at least one groove and connected to the second source region and the well contact region.

The power semiconductor device may further include a drain region having a first conductivity type in the semiconductor layer under the drift region, wherein the drain region may be doped with an impurity of the first conductivity type at a higher concentration than the drift region. there is.

In a method for manufacturing a power semiconductor device according to another aspect of the present invention for solving the above problems, a vertical movement path of electric charges is provided in a semiconductor layer of silicon carbide (SiC) and a drift region having a first conductivity type is formed. a well having a second conductivity type; forming a region; forming a pillar region in contact with the well region in the semiconductor layer under the well region and having a second conductivity type to form a super junction with the drift region; a first source region formed in the semiconductor layer on a well region, and a second source region formed in the semiconductor layer on the second well region and connected to the first source region, to form a source region having a first conductivity type forming a channel region in the semiconductor layer between the at least one protruding portion of the drift region and the first source region; on the channel region and the at least one protruding portion of the drift region forming a gate insulating layer and forming a gate electrode layer on the gate insulating layer, wherein the second well region and the second source region are formed in the semiconductor layer outside the gate electrode layer.

According to the method of manufacturing the power semiconductor device, forming a well contact region extending from the second well region through the second source region and having a second conductivity type in the second source region; and forming a source region and a source electrode layer connected to the well contact region, wherein the well contact region may be doped with a higher concentration than the well region.

According to the method of manufacturing the power semiconductor device, forming at least one groove exposing the second well region through the second source region, and the second well region on a bottom surface of the at least one groove The method may further include forming a well contact region in contact with and having a second conductivity type, and forming a source electrode layer filling the at least one groove to be connected to the second source region and the well contact region.

According to the power semiconductor device and the method for manufacturing the same according to an embodiment of the present invention made as described above, it is possible to increase the degree of integration by reducing the operation loss and increasing the channel density.

Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

1 is a schematic schematic perspective view showing a power semiconductor device according to an embodiment of the present invention.
FIG. 2 is a plan view showing the power semiconductor device taken along line II-II of FIG. 1 .
3 is a cross-sectional view illustrating a power semiconductor device taken along line III-III of FIG. 2 .
4 is a cross-sectional view illustrating the power semiconductor device taken along line IV-IV of FIG. 2 .
5 to 8 are cross-sectional views illustrating power semiconductor devices according to other embodiments of the present invention.
9 to 11 are schematic perspective views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention.
12 is a graph showing a change in an electric field according to a depth of a power semiconductor device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. It is provided to fully inform the In addition, in the drawings for convenience of description, the size of at least some of the components may be exaggerated or reduced. In the drawings, like numbers refer to like elements.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for the purpose of explanation, and thus are provided to explain the general structures of the present invention.

Like reference signs indicate like elements. When referring to one component as being on another component, such as a layer, region, or substrate, it will be understood that other intervening components may also be present, either directly on top of the other component or in between. On the other hand, when referring to one configuration as being “directly on” of another, it is understood that intervening configurations do not exist.

1 is a schematic schematic perspective view showing a power semiconductor device 100 according to an embodiment of the present invention, FIG. 2 is a plan view showing the power semiconductor device 100 taken along line II-II of FIG. 1, FIG. 3 is a cross-sectional view showing the power semiconductor device 100 taken along line III-III of FIG. 2 , and FIG. 4 is a cross-sectional view showing the power semiconductor device 100 taken along line IV-IV of FIG. 2 .

1 to 4 , the power semiconductor device 100 may include at least a semiconductor layer 105 , a gate insulating layer 118 , and a gate electrode layer 120 . For example, the power semiconductor device 100 may have a power MOSFET structure.

The semiconductor layer 105 may refer to one or more semiconductor material layers, for example, one or multiple epitaxial layers. Furthermore, the semiconductor layer 105 may refer to one or multiple epitaxial layers on a semiconductor substrate.

For example, the semiconductor layer 105 may be made of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

Silicon carbide (SiC) has a wider bandgap than silicon, so it can maintain stability even at high temperatures compared to silicon. Furthermore, silicon carbide has a very high insulating wave field compared to silicon, so it can operate stably even at a high voltage. Accordingly, the power semiconductor device 100 using silicon carbide as the semiconductor layer 105 has a high breakdown voltage and excellent heat dissipation characteristics compared to the case where silicon is used, and may exhibit stable operating characteristics even at high temperatures.

More specifically, the semiconductor layer 105 may include a drift region 107 . The drift region 107 may have the first conductivity type, and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105 . For example, the drift region 107 may be formed by doping an impurity of the first conductivity type into an epitaxial layer of silicon carbide.

The drift region 107 may provide a vertical movement path for electric charges. Furthermore, the drift region 107 may include at least one protruding portion 107a disposed under the gate electrode layer 120 . The protruding portion 107a may extend substantially onto the surface of the semiconductor layer 105 .

The well region 110 may be formed to contact at least a portion of the drift region 107 in the semiconductor layer 105 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type into the semiconductor layer 105 or the drift region 107 .

For example, the well region 110 includes a first well region 110a formed in the semiconductor layer 105 under the gate electrode layer 120 and formed in contact with the protruding portion 107a of the drift region 107 ; A second well region 110b formed in the semiconductor layer 105 outside the electrode layer 120 may be included. The first well region 110a and the second well region 110b may be connected to each other. Substantially, a lower portion of the protruding portion 107a of the drift region 107 may be defined by the first well region 110a, and more specifically, may be in contact with a sidewall of the first well region 110a.

The pillar region 111 may be formed in the semiconductor layer 105 to have a conductivity type different from that of the drift region 107 to form a super junction with the drift region 107 . For example, the pillar region 111 may have the second conductivity type and may be formed in the semiconductor layer 105 under the well region 110 to be in contact with the well region 110 .

For example, the pillar region 111 may be formed to contact or surround the sidewall of the drift region 107 . As another example, the pillar regions 111 may be divided into a plurality and formed to alternately contact the drift regions 107 .

In some embodiments, the pillar region 111 is narrower than the well region 10 to expose at least a portion of the bottom surface of the well region 110 , and is retreated inward from the end of the well region 110 to form the well region ( 110) may be formed in the lower part. Accordingly, the well region 110 may be formed to protrude more in the direction of the protruding portion 107a of the drift region 107 than the pillar region 111 .

A source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the semiconductor layer 105 or the well region 110 with impurities of the first conductivity type. The source region 112 may be formed by doping a higher concentration of impurities of the first conductivity type than the drift region 107 .

For example, the source region 112 may include a first source region 112a formed on the first well region 110a and a second source region 112b formed on the second well region 110b. . The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed under the gate electrode layer 120 , and the second source region 112b may be disposed outside the gate electrode layer 120 .

The second source region 112b may include a source contact region 112b1 connected to the source electrode layer 140 outside the gate electrode layers 120 . For example, the source contact region 112b1 is a part of the second source region 112b and may refer to a portion to which the source electrode layer 140 is connected.

The well contact region 114 may be formed in the second source region 112b, more specifically, in the source contact region 112b1. For example, the well contact region 114 may extend from the second well region 110b through the second source region 112b and may have the second conductivity type. One or a plurality of well contact regions 114 may be formed in the source contact region 112b1.

The well contact region 114 may be connected to the source electrode layer 140 , and may be doped with an impurity of the second conductivity type at a higher concentration than the well region 110 to reduce contact resistance when connected to the source electrode layer 140 . .

The channel region 110c may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112 . For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a.

For example, the channel region 110c may have the second conductivity type to form an inversion channel. Since the channel region 110c has a doping type opposite to that of the source region 112 and the drift region 107 , the channel region 110c may form a diode junction junction with the source region 112 and the drift region 107 . can Accordingly, although the channel region 110c does not allow the movement of charges under normal circumstances, when an operating voltage is applied to the gate electrode layer 120 , an inversion channel is formed therein to allow the movement of charges. .

For example, the channel region 110c may be a part of the well region 110 . More specifically, the channel region 110c may be a part of the well region 110 adjacent to the lower portion of the gate electrode layer 120 . In this case, the channel region 110c may be formed to be integrally or continuously connected to the well region 110a. The doping concentration of the impurity of the second conductivity type in the channel region 110c may be the same as that of other portions of the well region 110 or may be different for controlling the threshold voltage.

In some embodiments, the protruding portion 107a of the drift region 107 , the first well region 110a , the channel region 110c , and/or the first source region 112a may extend in one direction. For example, the IV-IV direction of FIG. 2 may be one direction. Here, the extension direction of the channel region 110c does not mean a movement direction of charges.

In some embodiments, the first well region 110a , the channel region 110c , and the first source region 112a may be formed symmetrically with respect to the protruding portion 107a of the drift region 107 . For example, the first well region 110a , the channel region 110c , and the first source region 112a may be respectively formed in the semiconductor layer 105 on both sides of the protruding portion 107a of the drift region 107 . there is. Furthermore, the pillar region 111 may also be formed under the first well region 110a on both sides of the protruding portion 107a of the drift region 107 .

In some embodiments, the drift region 107 may include a plurality of protruding portions 107a formed side by side in one direction. For example, the first well region 110a may be formed in a stripe pattern extending in one direction, and the protruding portions 107a may also be formed in a stripe pattern. Also, the first source region 112a may be formed in a stripe pattern on the first well region 110a. The channel region 110c may be formed between the protruding portions 107a of the drift region 107 and the first source region 112a.

In some embodiments, the first well region 110a is symmetrically formed with respect to the second well region 110b, and the first source region 112a is symmetrically formed with respect to the second source region 112b. can be formed. In this case, the protruding portions 107a of the drift region 107 may include a plurality of protruding portions 107a symmetrically formed with respect to the second well region 110b or the second source region 112b. there is.

Furthermore, the first well region 110a and the second well region 110b may be repeatedly formed alternately in one direction. In this case, the first source region 112a and the second source region 112b may also be repeatedly formed.

Additionally, the drain region 102 may be formed in the semiconductor layer 105 under the drift region 107 and may have a first conductivity type. For example, the drain region 102 may be doped at a higher concentration than the drift region 107 .

In some embodiments, the drain region 102 may be provided as a substrate of silicon carbide having a first conductivity type. In this case, the drain region 102 may be understood as a part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105 .

The gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105 . For example, the gate insulating layer 118 may be formed on at least the channel region 110c. More specifically, the gate insulating layer 118 may be formed on the first source region 112a , the channel region 110c , and the protruding portions 107a of the drift region 107 .

For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stacked structure thereof.

At least one gate electrode layer 120 may be formed on the gate insulating layer 118 . For example, the gate electrode layer 120 may be formed on at least the channel region 110c. More specifically, the gate electrode layer 120 may be formed on the first source region 112a , the channel region 110c , and the protruding portions 107a of the drift region 107 . The second well region 110b , the second source region 112b , and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120 .

For example, the gate electrode layer 120 may include a suitable conductive material, such as polysilicon, metal, metal nitride, metal silicide, or the like, or may include a stacked structure thereof.

The interlayer insulating layer 130 may be formed on the gate electrode layer 120 . For example, the interlayer insulating layer 130 may include a suitable insulating material, such as an oxide layer, a nitride layer, or a laminate structure thereof.

The source electrode layer 140 may be formed on the interlayer insulating layer 130 , and may be connected to the source region 112 , more specifically, the second source region 112b or the source contact region 112b1 . Furthermore, the source electrode layer 140 may be commonly connected to the second source region 112b and the well contact region 114 . For example, the source electrode layer 140 may be formed of an appropriate conductive material, metal, or the like.

In the above-described power semiconductor device 100 , the first conductivity type and the second conductivity type may have opposite conductivity types, but may be either n-type or p-type, respectively. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

More specifically, when the power semiconductor device 100 is an N-type MOSFET, the drift region 107 is an N- region, the source region 112 and the drain region 102 are N+ regions, and the well region 110, The channel region 110c and the pillar region 111 may be a P− region, and the well contact region 114 may be a P+ region.

In operation of the power semiconductor device 100 , current flows from the drain region 102 in a generally vertical direction along the protruding portions 107a of the drift region 107 , and then through the channel region 110c to the source region 112 . ) can flow.

In the above-described power semiconductor device 100 , the source contact region 112b1 and the well contact region 114 may be separately disposed outside the gate electrode layer 120 . Accordingly, the first well region 110a and the first source region 112a may be formed such that the protruding portions 107a of the drift region 107 are densely disposed, and thus the channel region 110c is formed as a gate electrode layer. (120) may be densely formed in the lower portion. Accordingly, the power semiconductor device 100 may have a high degree of integration.

On the other hand, in the case of the power semiconductor device 100, since it is used for high power switching, high withstand voltage characteristics are required. When a high voltage is applied to the drain region 102 , a depletion region may extend from the semiconductor layer 105 adjacent to the drain region 102 , so that a voltage barrier of a channel may be lowered. This phenomenon is called DIBL (drain induced barrier lowering).

Such DIBL may cause abnormal turn-on of the channel region 110c, and further may cause a punch-through phenomenon in which the depletion layer between the drain region 102 and the source region 112 expands and comes into contact. there is.

However, the above-described power semiconductor device 100 uses the drift region 107 and the pillar region 111 forming a super junction to reduce the resistance of the drift region 107 and the channel region 110c and to DIBL. By suppressing abnormal current flow and punch-through phenomenon, it is possible to secure appropriate withstand voltage characteristics. Accordingly, a high breakdown voltage can be maintained even when the thickness of the drift region 107 constituting the body is reduced.

Such withstand voltage characteristics may be further improved by adjusting the charge amount of the pillar region 111 and the charge amount of the drift region 107 .

12 is a graph showing a change in an electric field according to a depth of the power semiconductor device 100 according to an embodiment of the present invention. In FIG. 12 , the position of A indicates the surface of the first well region 110a , the position of B indicates the bottom surface of the pillar region 111 , and the position of C indicates the bottom surface of the drift region 107 . instruct

Referring to FIG. 12 , when the charge amount Qp of the pillar region 111 is greater than the charge amount Qn of the drift region 107 , the maximum electric field of the pillar region 111 during operation of the power semiconductor device 100 is The breakdown voltage can be increased by making it occur in the drift region 107 on the same line as the bottom. In FIG. 12 , the slope of the intensity of the electric field between the positions A and B may be controlled by adjusting the charge amount Qp of the pillar region 108 .

For example, the doping concentration of the impurity of the second conductivity type in the pillar region 111 may be higher than that of the impurity of the first conductivity type in the drift region 107 to adjust the charge amount balance. Accordingly, the field applied to the gate insulating layer 118 may be lowered and the DIBL margin may be increased by controlling the balance of the charge amount, thereby improving the withstand voltage characteristics of the power semiconductor device 100 .

Accordingly, according to the above-described power semiconductor device 100 , it is possible to maintain a withstand voltage while increasing the degree of integration by increasing the channel density, thereby reducing the operation loss.

5 to 8 are cross-sectional views illustrating power semiconductor devices 100a, 100b, 100c, and 100d according to other embodiments of the present invention. The power semiconductor devices 100a, 100b, 100c, and 100d are modified or further added to some configurations in the power semiconductor device 100 of FIGS. do.

Referring to FIG. 5 , the power semiconductor device 100a may include at least one groove 138 penetrating through the second source region 112b and exposing the second well region 110b. The groove 138 may be formed to expose the surface of the second well region 110b or to be recessed to a predetermined depth of the second well region 110b. A well contact region 114a may be formed on at least a bottom surface of the groove 138 to be in contact with the second well region 110b.

The source electrode layer 140 may be formed to fill the groove 138 and may be connected to the well contact region 114a, the second well region 110b, and/or the second source region 112b. Such a structure may help to reduce a contact resistance between the source electrode layer 140 and the second well region 110b and the second source region 112b by increasing the contact area therebetween.

In some embodiments, the well contact region 114a may be entirely formed on the surface of the second well region 110b exposed by the groove 138 . Accordingly, the well contact region 114a may be formed on the second well region 110b exposed from the bottom and sidewalls of the groove 138 . The structure of the well contact region 114a may serve to further reduce the contact resistance between the source electrode layer 140 and the second well region 110b.

Referring to FIG. 6 , in the power semiconductor device 100b , the channel region 107b may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112 . For example, the channel region 107b may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The channel region 107b may have a first conductivity type to form an accumulation channel.

For example, the channel region 107b may have the same doping type as the source region 112 and the drift region 107 . In this case, the source region 112 , the channel region 107b , and the drift region 107 have a structure that can be normally electrically connected. However, in the structure of the semiconductor layer 105 of silicon carbide, the band of the channel region 107b bends upward due to the influence of a negative charge generated while carbon clusters are formed in the gate insulating layer 118 , resulting in a potential barrier. this is formed Accordingly, when an operating voltage is applied to the gate electrode layer 120 , an accumulation channel allowing the flow of charges or currents may be formed in the channel region 107b.

Accordingly, the threshold voltage that must be applied to the gate electrode layer 120 to form the accumulation channel in the channel region 107b may be significantly lower than the threshold voltage that must be applied to the gate electrode layer 120 to form a typical inversion channel. .

In some embodiments, the channel region 107b may be part of the drift region 107 . More specifically, the channel region 107b may be a part of the protruding portion 107a of the drift region 107 . For example, the channel region 107b may be integrally formed with the drift region 107 .

The drift region 107 may be connected to the source region 112 through the channel region 107b. More specifically, in the channel region 107b, the protruding portion 107a of the drift region 107 and the first source region 112a may contact each other.

For example, the doping concentration of the impurity of the first conductivity type in the channel region 107b may be the same as that of other portions of the drift region 107 or may be different for adjusting the threshold voltage.

In some embodiments, the first well region 110a may be formed below the first source region 112a to protrude in the direction of the protruding portion 107a of the drift region 107 than the first source region 112a. The channel region 107b may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the protruding portion 107a of the drift region 107 may further extend into a groove portion between the first well region 110a and the gate electrode layer 120 , and the channel region 107b is formed in this portion. can be This structure allows the channel region 107b to be defined between the gate electrode layer 120 and the well region 110 .

In some embodiments, the width of the first well region 110a and the first source region 112a may be the same. In this case, the first source region 112a may be in contact with the protruding portion 107a of the drift region 107 , and the channel region 107b may be defined in the contacting portion of the protruding portion 107a .

Referring to FIG. 7 , in the power semiconductor device 100c , the first well region 110a protrudes in the direction of the protruding portion 107a of the drift region 107 rather than the first source region 112a, and the gate electrode layer is disposed at the end thereof. It may include a tab portion extending in the (120) direction.

The channel region 107b1 may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the channel region 107b1 may be formed in a refractive shape on the protruding portion and the tab portion of the first well region 110a. This structure may allow the channel region 107b1 to be more confined between the gate electrode layer 120 and the first well region 110a.

Referring to FIG. 8 , in the power semiconductor device 100d, the first well region 110a protrudes in the direction of the protruding portion 107a of the drift region 107 rather than the first source region 112a, and a tab is provided at the end thereof. It may contain parts. Furthermore, the protruding portion 107a of the drift region 107 may further extend between the lower portion of the first source region 112a and the first well region 110a.

The channel region 107b2 may be formed by further extending into the semiconductor layer 105 between the lower portion of the first source region 112a and the first well region 110a. For example, the channel region 107b2 may be formed in a refractive shape from the tab portion of the first well region 110a to the lower portion of the first source region 112a. This structure may contribute to increasing the contact area between the channel region 107b2 and the first source region 112a.

9 to 11 are schematic perspective views illustrating a method of manufacturing the power semiconductor device 100 according to an embodiment of the present invention.

Referring to FIG. 9 , a drift region 107 having a first conductivity type may be formed to provide a vertical movement path for electric charges in the semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 may be formed on the drain region 102 having the first conductivity type. In some embodiments, drain region 102 is provided as a substrate of a first conductivity type, and drift region 107 may be formed on one or more epitaxial layers on such a substrate.

Next, the well region 110 having the second conductivity type may be formed in the semiconductor layer 105 to contact at least a portion of the drift region 107 . For example, the forming of the well region 110 may be performed by implanting impurities of the second conductivity type into the semiconductor layer 105 .

More specifically, the well region 110 may be formed in the semiconductor layer 105 in contact with the protruding portion 107a to define at least one protruding portion 107a of the drift region 107 . More specifically, the well region 110 may be formed by doping the drift region 107 or the semiconductor layer 105 with an impurity opposite to that of the drift region 107 .

The well region 110 may be divided into a first well region 110a under the gate electrode layer 120 and a second well region 110b outside the gate electrode layer 120 . For example, the first well region 110a may define the protruding portion 107a of the drift region 107 , and a well contact region 114 may be formed later in the second well region 110b . The first well region 110a and the second well region 110b may be connected to each other.

The pillar region 111 may be formed in the semiconductor layer 105 under the well region 110 to be in contact with the well region 110 . The pillar region 111 may have a second conductivity type to form a super junction with the drift region 107 . For example, the pillar region 111 may be formed by implanting impurities of the second conductivity type into the semiconductor layer 105 or the drift region 107 .

Furthermore, the source region 112 having the first conductivity type may be formed on or in the well region 110 . For example, the forming of the source region 112 may be performed by implanting impurities of the first conductivity type into the well region 110 or into the semiconductor layer 105 .

For example, forming the source region 112 may include forming the first source region 112a on or in the first well region 110a, and forming the second well region 110b. It may include forming the second source region 112b on or in the second well region 110b. A portion of the second source region 112b may be allocated as the source contact region 112b1 to be connected to the source electrode layer 140 . The first source region 112a and the second source region 112b may be connected to each other. The source region 112 may be formed substantially from the surface of the semiconductor layer 105 to a predetermined depth in the well region 110 or above the well region 110 .

In addition to forming the source region 112 , a channel region 110c having a second conductivity type may be formed in the semiconductor layer 105 between the source region 112 and the drift region 107 to form an inversion channel. . For example, the channel region 110c may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. For example, the channel region 110c is a part of the first well region 110a and may be formed together with the first well region 110a without being separately formed.

Optionally, a well contact region 114 extending from the second well region 110b through the second source region 112b may be formed in the second source region 112b. For example, the well contact region 114 may be formed by implanting impurities of the second conductivity type into a portion of the well region 110 at a higher concentration than that of the well region 110 .

In a modified example of this embodiment, the order of impurity doping of the well region 110 , the pillar region 111 , the source region 112 , the channel region 110c , and the well contact region 114 may be appropriately changed.

In the above-described manufacturing method, impurity implantation or impurity doping may be performed such that ions are implanted into the semiconductor layer 105 or impurities are mixed during formation of the epitaxial layer. However, for implantation of impurities in the selective region, an ion implantation method using a mask pattern may be used.

Optionally, the ion implantation may be followed by a thermal treatment step to activate or diffuse the impurities.

Referring to FIG. 10 , a gate insulating layer 118 may be formed on at least a portion of the semiconductor layer 105 . For example, the gate insulating layer 118 may be formed on at least the channel region 110c and the protruding portion 107a of the drift region 107 .

For example, the gate insulating layer 118 may be formed of an oxide by oxidizing the semiconductor layer 105 , or may be formed by depositing an insulating material such as oxide or nitride on the semiconductor layer 105 .

Subsequently, gate electrode layers 120 may be formed on the gate insulating layer 118 . For example, the gate electrode layer 120 may be formed by forming a conductive layer on the gate insulating layer 118 and then patterning it. The gate electrode layer 120 may be formed by doping polysilicon with impurities or may be formed to include a conductive metal or metal silicide.

The patterning process may be performed using photo lithography and etching processes. The photolithography process includes a process of forming a photoresist pattern as a mask layer using a photolithography process and a developing process, and the etching process includes a process of selectively etching an underlying structure using the photoresist pattern can do.

Referring to FIG. 11 , an interlayer insulating layer 130 may be formed on the gate electrode layer 120 . Optionally, when the interlayer insulating layer 130 is entirely formed on the lower structure, a process of forming a contact hole pattern for exposing the source contact region 112b1 and the well contact region 114 may be followed.

Subsequently, the source electrode layer 140 may be formed on the semiconductor layer 105 to be connected to the second source region 112b and the well contact region 114 . For example, the source electrode layer 140 may be formed by forming a conductive layer, for example, a metal layer, on the interlayer insulating layer 130 and then patterning or planarizing it.

Meanwhile, the power semiconductor device 100a of FIG. 5 may be manufactured by adding or modifying some processes to the above-described manufacturing process of the power semiconductor device 100 .

Fabrication of the power semiconductor device 100a of FIG. 5 forms at least one groove 138 penetrating the second source region 112b and exposing the second well region 110b in the second source region 112b. A well contact region 114 is formed on the bottom surface of the groove 138 to be in contact with the well region 110 , and the groove 138 is filled to be connected to the source region 112 and the well contact region 114 . A step of forming the source electrode layer 140 may be added.

Meanwhile, when the power semiconductor devices 100b, 100c, and 100d of FIGS. 6 to 8 are manufactured, the channel regions 107b, 107b1, and 107b2 may be formed to have a first conductivity type to form an accumulation channel. For example, the channel regions 107b , 107b1 , and 107b2 may be formed as a part of the drift region 107 .

According to the above-described manufacturing method, it is possible to economically manufacture the high-integration power semiconductor device 100 by using the semiconductor layer 105 of silicon carbide by using a process used for a conventional silicon substrate.

Although the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: power semiconductor device
102: drain region
105: semiconductor layer
107: drift zone
110: well area
111: pillar area
112: source area
118: gate insulating layer
120: gate electrode layer
130: interlayer insulating layer
140: source electrode layer

Claims (15)

a semiconductor layer of silicon carbide (SiC);
a gate insulating layer on a portion of the semiconductor layer;
a gate electrode layer on the gate insulating layer;
a drift region formed in the semiconductor layer to provide a vertical movement path of electric charge, the drift region including at least one protruding portion disposed under the gate electrode layer, the drift region having a first conductivity type;
A first well region formed in the semiconductor layer under the gate electrode layer in contact with the at least one protruding portion of the drift region, and a second well region formed in the semiconductor layer outside the gate electrode layer and connected to the first well region a well region comprising a second conductivity type;
a pillar region formed in the semiconductor layer under the well region in contact with the well region and having a second conductivity type to form a super junction with the drift region;
a source having a first conductivity type, comprising a first source region formed in the semiconductor layer on the first well region and a second source region formed in the semiconductor layer on the second well region and connected to the first source region area;
a channel region formed in the semiconductor layer between the at least one protruding portion of the drift region and the first source region; and
a well contact region extending from the second well region through the second source region and having a second conductivity type in the second source region;
the pillar region overlaps the well contact region and is formed to contact the second well region under the second well region;
power semiconductor devices. The method of claim 1,
In operation, the amount of charge in the pillar region is greater than the amount of charge in the drift region so that a maximum electric field is located in the drift region on the same line as the bottom surface of the pillar region;
power semiconductor devices. 3. The method of claim 2,
a doping concentration of the impurity of the second conductivity type in the pillar region is greater than a doping concentration of the impurity of the first conductivity type in the drift region;
power semiconductor devices. The method of claim 1,
the at least one protruding portion of the drift region, the first well region, and the first source region extend in one direction;
the first well region, the first source region and the channel region are respectively formed in the semiconductor layer on both sides of the at least one protruding portion of the drift region;
power semiconductor devices. The method of claim 1,
the channel region has a second conductivity type such that an inversion channel is formed;
wherein the channel region is part of the well region;
power semiconductor devices. The method of claim 1,
the channel region has a first conductivity type such that an accumulation channel is formed;
wherein the channel region is part of the drift region;
power semiconductor devices. 7. The method of claim 6,
the first well region protrudes more in a direction of the at least one protruding portion of the drift region than the first source region;
wherein the channel region is formed in the semiconductor layer on a protruding portion of the first well region;
power semiconductor devices. The method of claim 1,
The at least one protruding portion includes a plurality of protruding portions formed side by side in one direction,
the channel region is formed between the plurality of protruding portions and the first source region;
power semiconductor devices. The method of claim 1,
the first well region is formed symmetrically with respect to the second well region;
The first source region is formed symmetrically with respect to the second source region,
The at least one protrusion portion of the drift region includes a plurality of protrusion portions symmetrically disposed with respect to the second well region or the second source region.
power semiconductor devices. The method of claim 1,
and a source electrode layer connected to the second source region and the well contact region.
power semiconductor devices. The method of claim 1,
at least one groove passing through the second source region to expose the second well region;
a well contact region formed in contact with the second well region on a bottom surface of the at least one groove and having a second conductivity type; and
and a source electrode layer formed to fill the at least one groove and connected to the second source region and the well contact region.
power semiconductor devices. The method of claim 1,
a drain region having a first conductivity type in the semiconductor layer under the drift region;
The drain region is doped with an impurity of the first conductivity type more heavily than the drift region,
power semiconductor devices. providing a vertical movement path for electric charges in a semiconductor layer of silicon carbide (SiC) and forming a drift region having a first conductivity type;
a first well region in contact with the at least one protrusion to define at least one protrusion of the drift region and a second well region connected to the first well region, the well region having a second conductivity type to do;
forming a pillar region formed in contact with the well region in the semiconductor layer under the well region and having a second conductivity type to form a super junction with the drift region;
a source having a first conductivity type, comprising a first source region formed in the semiconductor layer on the first well region and a second source region formed in the semiconductor layer on the second well region and connected to the first source region forming a region;
forming a channel region in the semiconductor layer between the at least one protruding portion of the drift region and the first source region;
forming a gate insulating layer on the at least one protruding portion of the channel region and the drift region;
forming a gate electrode layer on the gate insulating layer; and
forming a well contact region extending from the second well region through the second source region and having a second conductivity type in the second source region;
the second well region and the second source region are formed in the semiconductor layer outside the gate electrode layer;
the pillar region overlaps the well contact region and is formed to contact the second well region under the second well region;
A method of manufacturing a power semiconductor device. 14. The method of claim 13,
forming a source electrode layer connected to the second source region and the well contact region;
the well contact region is more heavily doped than the well region;
A method of manufacturing a power semiconductor device. 14. The method of claim 13,
forming at least one groove through the second source region to expose the second well region;
forming a well contact region in contact with the second well region and having a second conductivity type on a bottom surface of the at least one groove; and
The method further comprising: forming a source electrode layer filling the at least one groove to be connected to the second source region and the well contact region;
A method of manufacturing a power semiconductor device.

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