JP2006059916A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006059916A
JP2006059916A JP2004238476A JP2004238476A JP2006059916A JP 2006059916 A JP2006059916 A JP 2006059916A JP 2004238476 A JP2004238476 A JP 2004238476A JP 2004238476 A JP2004238476 A JP 2004238476A JP 2006059916 A JP2006059916 A JP 2006059916A
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epitaxial layer
concentration
well region
insulating film
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JP4922554B2 (en
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Kaichiro Taguchi
嘉一郎 田口
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that is improved in the fracture resistance of an F-ASO and R-ASO without expanding the size of an element nor increasing the man-hour of a process and, at the same time, can suppress the rise of the Ron. <P>SOLUTION: The semiconductor device comprises a first-conductivity semiconductor substrate 1, a first-conductivity epitaxial layer 2, and a first-conductivity high-concentration epitaxial layer 3. The device is also provided with a second-conductivity well region 5, a first-conductivity source region 7, and a source electrode 11 formed on the surfaces of the well and source regions 5 and 7. The device also comprises a second-conductivity channel region 6 which is lower in concentration than the well region 5, a gate electrode 9 provided on the surface of the channel region 6 through a gate insulating film 8, and an interlayer insulating film 10 which insulates the gate and source electrodes 9 and 11. Moreover, the device comprises a drain electrode 12 on the bottom surface of the semiconductor substrate 1, and a high-concentration diffusion region 4 which is arranged in the high-concentration epitaxial layer 3 near the surface of the layer 3 and is higher in concentration than the layer 3 adjacently to the channel region 6. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、高耐圧と低動作抵抗で高出力に使用し得るＭＯＳ−ＦＥＴ素子を含んだ半導体装置に関する。   The present invention relates to a semiconductor device including a MOS-FET element that can be used for high output with high breakdown voltage and low operating resistance.

縦型ＭＯＳ−ＦＥＴは、一般的に拡散自己整合、いわゆるＤＳＡ（Ｄｉｆｆｕｓｅｄ Ｓｅｌｆ Ａｌｉｇｎｅｄ）構造をしている。   A vertical MOS-FET generally has a diffusion self-alignment, a so-called DSA (Diffused Self Aligned) structure.

図４に、従来の半導体装置の一つのセルとして形成された縦型ＭＯＳ−ＦＥＴの一例を示す。ドレイン領域となるＮ型の半導体基板１上に、Ｎ型のエピタキシャル層２が形成されている。エピタキシャル層２の表面に、チャンネル領域を含むＰ型の第一ウェル領域１３が形成され、さらに第一ウェル領域１３内に第一ウェル領域１３よりも高濃度のＰ型の第二ウェル領域１４が形成されている。   FIG. 4 shows an example of a vertical MOS-FET formed as one cell of a conventional semiconductor device. An N type epitaxial layer 2 is formed on an N type semiconductor substrate 1 serving as a drain region. A P-type first well region 13 including a channel region is formed on the surface of the epitaxial layer 2, and a P-type second well region 14 having a higher concentration than the first well region 13 is formed in the first well region 13. Is formed.

さらに、第二ウェル領域１４内の表面近傍に第一ウェル領域１３に接して、Ｎ型のソース領域７が形成されている。また、エピタキシャル層２の表面に、ゲート絶縁膜８が形成され、ゲート絶縁膜８上に多結晶シリコンから成るゲート電極９が形成されている。さらに、ゲート電極９を覆った層間絶縁膜１０と、ソース領域７に接続され、層間絶縁膜１０および第二ウェル領域１４を覆ったソース電極１１が形成されている。また、半導体基板１の裏面には、ドレイン電極１２が形成されている。   Further, an N-type source region 7 is formed in contact with the first well region 13 in the vicinity of the surface in the second well region 14. A gate insulating film 8 is formed on the surface of the epitaxial layer 2, and a gate electrode 9 made of polycrystalline silicon is formed on the gate insulating film 8. Further, an interlayer insulating film 10 covering the gate electrode 9 and a source electrode 11 connected to the source region 7 and covering the interlayer insulating film 10 and the second well region 14 are formed. A drain electrode 12 is formed on the back surface of the semiconductor substrate 1.

しかしながら、図４の構造においては、ドレイン電流の導通時に、第一ウェル領域１３と隣接したエピタキシャル層２との境界にできた空乏層が拡がるため、ドレイン電流の導通時におけるチャンネルの抵抗Ｒｏｎの低下を妨げる一因となることが問題である。   However, in the structure of FIG. 4, a depletion layer formed at the boundary between the first well region 13 and the adjacent epitaxial layer 2 spreads when the drain current is conducted, so that the channel resistance Ron is lowered when the drain current is conducted. The problem is that it contributes to the problem.

特許文献１には、図４の構成の改良例が示されており、その構成を図５に示す。図４と同じ構成要素は、同じ符号を付す。図５において、Ｎ型の半導体基板１上に形成されたＮ型のエピタキシャル層２の上層部に、エピタキシャル層２より高濃度であるＮ型の高濃度エピタキシャル層３が形成され、高濃度エピタキシャル層３とＰ型の第一ウェル領域１３とが隣接している。その他は、図４と同じ構造である。この構造により、第一ウェル領域１３から、隣接した高濃度エピタキシャル層３へ空乏層が拡がることが抑制され、ドレイン電流導通時のＲｏｎが、図４の構造のＲｏｎに比べて低下する。   Patent Document 1 shows an improved example of the configuration of FIG. 4, and the configuration is shown in FIG. The same components as those in FIG. 4 are denoted by the same reference numerals. In FIG. 5, an N-type high-concentration epitaxial layer 3 having a higher concentration than the epitaxial layer 2 is formed on an upper layer portion of the N-type epitaxial layer 2 formed on the N-type semiconductor substrate 1. 3 and the P-type first well region 13 are adjacent to each other. The other structure is the same as that of FIG. With this structure, the depletion layer is prevented from spreading from the first well region 13 to the adjacent high-concentration epitaxial layer 3, and Ron at the time of drain current conduction is lower than Ron of the structure of FIG. 4.

次に、従来構造の縦型ＭＯＳ−ＦＥＴである図４の構成のもう一つの問題点を示す。その問題点とは、高濃度のＮ型ソース領域７の下部に抵抗成分を下げるために設けられた第二ウェル領域１４の拡散のばらつきによって、順方向安全動作領域（以下Ｆ−ＡＳＯと称する）、逆方向安全動作領域（以下Ｒ−ＡＳＯと称する）の破壊耐量が低下する点である。   Next, another problem of the configuration of FIG. 4 which is a conventional vertical MOS-FET will be described. The problem is that a forward safe operation region (hereinafter referred to as F-ASO) is caused by variations in diffusion of the second well region 14 provided to lower the resistance component under the high-concentration N-type source region 7. In this case, the breakdown tolerance in the reverse direction safe operation region (hereinafter referred to as R-ASO) is reduced.

この理由は、第二ウェル領域１４の横方向への拡散が不足した場合、ソース領域７の下部の抵抗成分が増加するからである。インダクタンスが負荷された回路では、ゲート入力がオンからオフになるとき、素子のドレイン−ソース間耐圧（ＶＤＳＳ）を超える電圧が掛り、素子がブレークダウンを起こす。このときブレークダウン電流が素子内部を通り、ソース領域７に流れる。   This is because the resistance component under the source region 7 increases when the lateral diffusion of the second well region 14 is insufficient. In a circuit loaded with inductance, when the gate input is switched from on to off, a voltage exceeding the drain-source breakdown voltage (VDSS) of the element is applied, causing the element to break down. At this time, a breakdown current flows through the inside of the element and flows into the source region 7.

第一ウェル領域１３は高濃度でないため、その抵抗成分は第二ウェル領域１４よりも大きくなり、ソース領域７の下部である第一ウェル領域１３にブレークダウン電流が流れることにより生じる電圧降下が大きくなる。この電圧降下によりソース領域７と、第一ウェル領域１３および第二ウェル領域１４と、エピタキシャル層２および半導体基板１とにより形成される寄生トランジスタがオン状態となる。この状態は、ベースがオン状態となり、さらにベース電流が増加する正帰還の状態であるバイポーラ型のトランジスタと見なすことができるため、電流と温度が上昇し続けて破壊に至る。従って、ソース領域７の下部におけるウェル領域の抵抗成分が大きい程Ｒ−ＡＳＯ破壊耐量が小さくなる。   Since the first well region 13 is not high in concentration, its resistance component is larger than that of the second well region 14 and a voltage drop caused by a breakdown current flowing through the first well region 13 below the source region 7 is large. Become. Due to this voltage drop, the parasitic transistor formed by the source region 7, the first well region 13, the second well region 14, the epitaxial layer 2 and the semiconductor substrate 1 is turned on. This state can be regarded as a bipolar transistor that is in a positive feedback state in which the base is turned on and the base current further increases, so that the current and temperature continue to rise, leading to destruction. Therefore, the larger the resistance component of the well region below the source region 7, the smaller the R-ASO breakdown resistance.

また、第二ウェル領域１４が横方向へ過剰に拡散した場合、チャンネル領域へ拡散が進行してチャンネル領域の濃度が高くなるため、閾値電圧が高くなり、ゲート入力がオンになると、チャンネル領域を流れる電流により温度が上昇し、Ｆ−ＡＳＯ破壊レベルが下がる。   Further, when the second well region 14 is excessively diffused in the lateral direction, the diffusion proceeds to the channel region and the concentration of the channel region is increased. Therefore, when the threshold voltage is increased and the gate input is turned on, the channel region is The temperature increases due to the flowing current, and the F-ASO breakdown level decreases.

図４の半導体装置の構成における第２の改良例を図６に示す。図４と同じ構成要素は、同じ符号を付す。図６において、ドレイン領域となるＮ型の半導体基板１の上層部にＮ型のエピタキシャル層２が形成されている。エピタキシャル層２の表面から延在して、高濃度のウェル領域５が形成され、ウェル領域５の表面の中央部から外側にＮ型のソース領域７と、ウェル領域５より低濃度のチャンネル領域６が形成されている。   FIG. 6 shows a second improvement example in the configuration of the semiconductor device of FIG. The same components as those in FIG. 4 are denoted by the same reference numerals. In FIG. 6, an N-type epitaxial layer 2 is formed in the upper layer portion of an N-type semiconductor substrate 1 serving as a drain region. A well region 5 having a high concentration is formed extending from the surface of the epitaxial layer 2. An N-type source region 7 and a channel region 6 having a concentration lower than that of the well region 5 are formed outside the center of the surface of the well region 5. Is formed.

さらに、チャンネル領域６より外側にエピタキシャル層２より高濃度のＮ型であり、ゲートの閾値電圧が２．０〜３．０Ｖとなる濃度の高濃度拡散層４が形成されている。チャンネル領域６と高濃度拡散層４との上にゲート絶縁膜８が形成され、ゲート絶縁膜８の表面に多結晶シリコンから成るゲート電極９が形成されている。さらに、ゲート電極９を覆う層間絶縁膜１０と、層間絶縁膜１０とソース領域７とウェル領域５とを覆ってソース電極１１が形成されている（例えば特許文献２参照）。   Further, a high concentration diffusion layer 4 having an N type concentration higher than that of the epitaxial layer 2 and having a gate threshold voltage of 2.0 to 3.0 V is formed outside the channel region 6. A gate insulating film 8 is formed on the channel region 6 and the high concentration diffusion layer 4, and a gate electrode 9 made of polycrystalline silicon is formed on the surface of the gate insulating film 8. Further, an interlayer insulating film 10 covering the gate electrode 9, and a source electrode 11 are formed covering the interlayer insulating film 10, the source region 7, and the well region 5 (see, for example, Patent Document 2).

この図６に示した縦型ＭＯＳ−ＦＥＴは、図４におけるソース領域７の下部の抵抗成分を下げるために設けた第二ウェル領域１４の拡散のばらつきによるＦ−ＡＳＯとＲ−ＡＳＯの破壊耐量低下を防止することができる。   The vertical MOS-FET shown in FIG. 6 has F-ASO and R-ASO breakdown tolerance due to variations in diffusion of the second well region 14 provided to lower the resistance component under the source region 7 in FIG. A decrease can be prevented.

図６の構造によれば、ウェル領域５を任意の高濃度で形成できるため、ウェル領域５の抵抗成分を小さくすることができる。この場合においても、ソース−ドレイン電極間にインダクタンスが負荷されていると、ゲート入力をオンからオフにした際に、ソース領域７−チャンネル領域６形成領域間のジャンクションが動作しにくくなり、チャンネル領域６を通らずに電流が流れる。すなわち、ドレイン電極１２から半導体基板１、エピタキシャル層２、ウェル領域５、ソース領域７を通ってソース電極１１へと流れる。しかし、図６の構造では、ウェル領域５の抵抗が小さいため、ウェル領域５における電圧降下が小さく、ＭＯＳ−ＦＥＴのＲ−ＡＳＯは高い。   According to the structure of FIG. 6, since the well region 5 can be formed at an arbitrary high concentration, the resistance component of the well region 5 can be reduced. Also in this case, if an inductance is loaded between the source and drain electrodes, the junction between the source region 7 and the channel region 6 formation region becomes difficult to operate when the gate input is turned from on to off. Current flows without passing through 6. That is, it flows from the drain electrode 12 to the source electrode 11 through the semiconductor substrate 1, the epitaxial layer 2, the well region 5, and the source region 7. However, in the structure of FIG. 6, since the resistance of the well region 5 is small, the voltage drop in the well region 5 is small, and the R-ASO of the MOS-FET is high.

また、チャンネル領域６へのＰ型の不純物拡散が発生しないため、ゲートの閾値電圧ＶTHの上昇を防ぐと共にＦ−ＡＳＯ破壊耐量を向上させることができる。
特開平０７−１６９９５０号公報 特開平０４−２５１８０号公報 Further, since the P-type impurity diffusion into the channel region 6 is not generated, it is possible to improve the F-ASO destruction resistance while preventing an increase in the threshold voltage V TH of the gate.
Japanese Patent Application Laid-Open No. 07-169950 Japanese Patent Laid-Open No. 04-25180

Ｆ−ＡＳＯとＲ−ＡＳＯの破壊耐量を向上させるために図６の構造を用いた場合、図５の構造に比べて、高濃度エピタキシャル層がないため、空乏層が広がり、Ｒｏｎが上昇するという問題がある。   When the structure of FIG. 6 is used to improve the breakdown tolerance of F-ASO and R-ASO, the depletion layer expands and Ron increases because there is no high concentration epitaxial layer compared to the structure of FIG. There's a problem.

本発明は、従来の問題を解決するもので、素子サイズの拡大とプロセス工数を増やす事なく、Ｆ−ＡＳＯとＲ−ＡＳＯの破壊耐量を向上させると共にＲｏｎの上昇も抑制させた半導体装置を提供することを目的とする。   SUMMARY OF THE INVENTION The present invention solves the conventional problems and provides a semiconductor device that improves the breakdown tolerance of F-ASO and R-ASO and suppresses the rise of Ron without increasing the element size and increasing the number of process steps. The purpose is to do.

第一導電型の半導体基板と、前記半導体基板上に形成された第一導電型のエピタキシャル層と、前記エピタキシャル層の上層部に形成された前記エピタキシャル層より高濃度で第一導電型の高濃度エピタキシャル層と、前記高濃度エピタキシャル層内に前記高濃度エピタキシャル層の表面から内部に延在させて形成された第二導電型のウェル領域と、前記ウェル領域内に配置され、前記ウェル領域表面から内部に延在させて形成された第一導電型のソース領域と、前記ウェル領域表面および前記ソース領域表面に形成されたソース電極と、前記ソース領域と前記高濃度エピタキシャル層とに隣接して、前記ウェル領域の表面から内部に延在して形成され、前記ウェル領域よりも低濃度である第二導電型のチャンネル領域と、前記チャンネル領域の表面にゲート絶縁膜を介して設けられたゲート電極と、前記ゲート電極と前記ソース電極を絶縁する層間絶縁膜と、前記半導体基板の下面にドレイン電極とを備える。上記の問題を解決するために、前記高濃度エピタキシャル層内の表面近傍に配置され、前記高濃度エピタキシャル層よりもさらに高濃度であり、前記チャンネル領域に隣接した高濃度拡散領域を備えたことを特徴とする。   A first conductivity type semiconductor substrate, a first conductivity type epitaxial layer formed on the semiconductor substrate, and a higher concentration of the first conductivity type than the epitaxial layer formed on the upper layer of the epitaxial layer An epitaxial layer; a well region of a second conductivity type formed in the high-concentration epitaxial layer so as to extend from the surface of the high-concentration epitaxial layer; and disposed in the well region, from the surface of the well region Adjacent to the source region of the first conductivity type formed extending inside, the source electrode formed on the well region surface and the source region surface, the source region and the high-concentration epitaxial layer, A channel region of a second conductivity type formed extending from the surface of the well region and having a lower concentration than the well region; and the channel region. Comprising a gate electrode provided via a gate insulating film on the surface of the interlayer insulating film for insulating the source electrode and the gate electrode, and a drain electrode on the lower surface of the semiconductor substrate. In order to solve the above-described problem, a high concentration diffusion region is provided near the surface in the high concentration epitaxial layer, which is higher in concentration than the high concentration epitaxial layer, and adjacent to the channel region. Features.

本発明の半導体装置は、素子サイズの拡大とプロセス工数を増やす事なく、Ｆ−ＡＳＯとＲ−ＡＳＯの破壊耐量が向上すると共にＲｏｎも低下することができる。   The semiconductor device of the present invention can improve the breakdown tolerance of F-ASO and R-ASO and reduce Ron without increasing the element size and increasing the number of process steps.

（実施の形態）
本発明の実施の形態について、図面を用いて説明する。 (Embodiment)
Embodiments of the present invention will be described with reference to the drawings.

図１は、本発明の実施の形態における半導体装置の一つのセルとして形成された縦型ＭＯＳ−ＦＥＴ素子の断面図である。Ｎ型の半導体基板１の上部にＮ型のエピタキシャル層２が形成されている。エピタキシャル層２の上層部に、Ｎ型でエピタキシャル層２より高濃度の高濃度エピタキシャル層３が形成され、高濃度エピタキシャル層３内にＰ型の高濃度のウェル領域５が形成されている。ウェル領域５内には、Ｐ型のチャンネル領域６と、Ｎ型のソース領域７が形成され、高濃度エピタキシャル層３内には、チャネル領域６に接して、高濃度エピタキシャル層３より高濃度のＮ型の高濃度拡散層４が形成されている。   FIG. 1 is a cross-sectional view of a vertical MOS-FET element formed as one cell of a semiconductor device according to an embodiment of the present invention. An N type epitaxial layer 2 is formed on the N type semiconductor substrate 1. An N-type high-concentration epitaxial layer 3 having a higher concentration than the epitaxial layer 2 is formed in the upper layer portion of the epitaxial layer 2, and a P-type high-concentration well region 5 is formed in the high-concentration epitaxial layer 3. A P-type channel region 6 and an N-type source region 7 are formed in the well region 5, and in the high-concentration epitaxial layer 3 is in contact with the channel region 6 and has a higher concentration than the high-concentration epitaxial layer 3. An N-type high concentration diffusion layer 4 is formed.

さらに、チャネル領域６と高濃度拡散層４の表面を覆うゲート絶縁膜８が形成され、ゲート絶縁膜８上に覆ったゲート電極９と、ゲート電極９を覆う層間絶縁膜１０が形成されている。さらに、ソース領域７と接続され、ウェル領域５と層間絶縁膜１０を覆ったソース電極１１が形成され、半導体基板１の裏面にドレイン電極１２が形成されている。   Further, a gate insulating film 8 covering the surface of the channel region 6 and the high concentration diffusion layer 4 is formed, and a gate electrode 9 covering the gate insulating film 8 and an interlayer insulating film 10 covering the gate electrode 9 are formed. . Further, a source electrode 11 connected to the source region 7 and covering the well region 5 and the interlayer insulating film 10 is formed, and a drain electrode 12 is formed on the back surface of the semiconductor substrate 1.

図２は、本実施の形態における半導体装置と従来品の性能を比較したグラフである。（ａ）はＲｏｎレベル、（ｂ）はＲ−ＡＳＯレベル、（ｃ）はＦ−ＡＳＯレベルを示す。それぞれのグラフの×印が従来品、○印が本実施の形態における半導体装置の値を示している。（ａ）では、値が小さいほど抵抗が小さく、（ｂ）、（ｃ）では、値が大きいほど破壊耐圧が高いことを示している。従来品として、図２（ａ）の比較実験では、図４、図６に示した構造の従来品を用い、図２（ｂ）、（ｃ）の比較実験では、図４、図５に示した構造の従来品を用いた。   FIG. 2 is a graph comparing the performance of the semiconductor device according to the present embodiment and the conventional product. (A) shows Ron level, (b) shows R-ASO level, and (c) shows F-ASO level. In each graph, a cross indicates a conventional product, and a circle indicates the value of the semiconductor device in this embodiment. In (a), the smaller the value, the smaller the resistance. In (b) and (c), the larger the value, the higher the breakdown voltage. As the conventional product, the conventional product having the structure shown in FIGS. 4 and 6 is used in the comparative experiment of FIG. 2A, and the comparative test shown in FIGS. 2B and 2C is shown in FIGS. The conventional product with the same structure was used.

本実施の形態における構成によれば、高濃度の高濃度エピタキシャル層３を形成することにより、ウェル領域５から高濃度エピタキシャル層３への空乏領域の拡がりが抑えられ、図２（ａ）に示すように、従来例に比べてＲｏｎを低く抑制することができる。   According to the configuration of the present embodiment, by forming the high concentration high concentration epitaxial layer 3, the expansion of the depletion region from the well region 5 to the high concentration epitaxial layer 3 can be suppressed, as shown in FIG. Thus, Ron can be suppressed lower than in the conventional example.

また、高濃度拡散層４とウェル領域５との濃度調整により、閾値電圧ＶTHが２．０〜３．０ＶとなるＰ型チャンネル領域６を形成する事ができる。そして、ソース領域７の下部を高濃度のウェル領域５として抵抗成分を下げる事が出来るため、図２（ｂ）に示すように、従来例に比べてＲ−ＡＳＯであるアバランシェ破壊耐量を向上させることができる。さらに、チャンネル領域６へのＰ型の不純物拡散が発生しないためにＶTHの上昇を抑制でき、図２（ｃ）に示すように、従来例に比べてＦ−ＡＳＯ破壊レベルが向上する。以上により図４に示した従来例に比べて、Ｒ−ＡＳＯ、Ｆ−ＡＳＯおよびＲｏｎの各々の性能が向上した。 Further, by adjusting the concentration between the high concentration diffusion layer 4 and the well region 5, it is possible to form the P-type channel region 6 in which the threshold voltage V TH is 2.0 to 3.0V. Since the resistance component can be lowered by making the lower portion of the source region 7 a high-concentration well region 5, as shown in FIG. 2B, the avalanche breakdown resistance as R-ASO is improved as compared with the conventional example. be able to. Furthermore, since no P-type impurity diffusion into the channel region 6 occurs, an increase in V TH can be suppressed, and the F-ASO breakdown level is improved as compared with the conventional example, as shown in FIG. As a result, the performance of each of R-ASO, F-ASO, and Ron was improved as compared with the conventional example shown in FIG.

図３は、図１に示した半導体装置の各製造工程を示す断面図である。各構成部分の符号は、各部分の最終形態に図１の符号を用い、製造途中の形態においては、１ａのように最終形態の符号と、その形態ごとにａからアルファベットを対応させた符号を用いる。   FIG. 3 is a cross-sectional view showing each manufacturing process of the semiconductor device shown in FIG. 1 is used for the final form of each part, and in the form in the middle of manufacture, the code of the final form as in 1a and the code corresponding to the alphabet from a for each form are used. Use.

まず、図３（ａ）に示すように、半導体基板１上にＮ型のエピタキシャル層２ａを形成した後、図３（ｂ）に示すように、Ｎ型のエピタキシャル層２ａの上層を、拡散法を用いて、エピタキシャル層２ａより高濃度の高濃度エピタキシャル層３ａを形成する。   First, as shown in FIG. 3A, after an N-type epitaxial layer 2a is formed on a semiconductor substrate 1, an upper layer of the N-type epitaxial layer 2a is formed by a diffusion method as shown in FIG. Is used to form a high-concentration epitaxial layer 3a having a higher concentration than the epitaxial layer 2a.

次に、図３（ｃ）に示すように、高濃度拡散層４ａを形成する。その工程は図示しないが、高濃度エピタキシャル層３ａの表面の高濃度拡散層４ａを作成しない領域をレジスト膜でマスクし、ドナーをドープし、拡散させる。拡散されたことにより高濃度エピタキシャル層３ａの表面に高濃度拡散層４ａが作成され、その後レジスト膜を除去する。この工程により、高濃度エピタキシャル層３ａの表面近傍において、レジスト膜で覆われていた領域は変化せず、縦型ＭＯＳ−ＦＥＴ素子のセルの中心部となり、他の領域は、高濃度拡散層４ａとなる。   Next, as shown in FIG. 3C, a high concentration diffusion layer 4a is formed. Although not shown in the figure, the region where the high-concentration diffusion layer 4a on the surface of the high-concentration epitaxial layer 3a is not formed is masked with a resist film, and the donor is doped and diffused. As a result of the diffusion, a high concentration diffusion layer 4a is formed on the surface of the high concentration epitaxial layer 3a, and then the resist film is removed. By this process, in the vicinity of the surface of the high concentration epitaxial layer 3a, the region covered with the resist film is not changed and becomes the center of the cell of the vertical MOS-FET element, and the other regions are the high concentration diffusion layer 4a. It becomes.

次に、図３（ｄ）に示すように、半導体基板１の表面全面にシリコン酸化膜からなるゲート絶縁膜８ａをパイロジェニック法により形成する。さらに、ゲート絶縁膜８ａの表面全体に多結晶シリコンからなるゲート電極９ａを化学気相成長法（以下ＣＶＤと称する）を用いて形成する。形成されたゲート電極９ａは、フォトリソグラフィーによりパターニングが行われ、セルの中心部から円状にエッチング除去される。すなわち、ゲート絶縁膜８ａに接した高濃度エピタキシャル層３ｂの領域および、高濃度拡散層４ａの高濃度エピタキシャル層３ｂとの境界付近の領域に対応したゲート電極９ａが除去される。   Next, as shown in FIG. 3D, a gate insulating film 8a made of a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 by a pyrogenic method. Further, a gate electrode 9a made of polycrystalline silicon is formed on the entire surface of the gate insulating film 8a by chemical vapor deposition (hereinafter referred to as CVD). The formed gate electrode 9a is patterned by photolithography and etched away from the center of the cell in a circular shape. That is, the gate electrode 9a corresponding to the region of the high concentration epitaxial layer 3b in contact with the gate insulating film 8a and the region in the vicinity of the boundary between the high concentration diffusion layer 4a and the high concentration epitaxial layer 3b is removed.

次に、図３（ｅ）に示すように、ウェル領域５ａを形成する。すなわち、ゲート電極９をマスクとし、ゲート絶縁膜８ａを介したセルフアライメント拡散により、高濃度エピタキシャル層３ｂと高濃度拡散層４ａの表面から高濃度エピタキシャル層３ｂの内部にかけて、Ｎ型の高濃度拡散層４ａより不純物濃度の高いＰ型のウェル領域５を形成する。その後、ＣＶＤを用いて、ゲート電極９の表面およびエッチングされた端面と、ゲート絶縁膜８ａの表面にかけての全面とを覆って、酸化シリコンからなる層間絶縁膜１０ａを形成する。   Next, as shown in FIG. 3E, a well region 5a is formed. That is, N-type high concentration diffusion is performed from the surface of the high concentration epitaxial layer 3b and the high concentration diffusion layer 4a to the inside of the high concentration epitaxial layer 3b by self-alignment diffusion through the gate insulating film 8a using the gate electrode 9 as a mask. A P-type well region 5 having an impurity concentration higher than that of the layer 4a is formed. Thereafter, an interlayer insulating film 10a made of silicon oxide is formed by using CVD so as to cover the surface of the gate electrode 9 and the etched end face and the entire surface of the gate insulating film 8a.

この工程により、ウェル領域５は、横方向にも拡散してゲート電極９の下層にも入り込み、ウェル領域５が形成された高濃度拡散層４ａの領域は、ウェル領域５の他の部分よりも低濃度のＰ型に反転し、チャンネル領域６ａとなる。   By this step, the well region 5 diffuses also in the lateral direction and enters the lower layer of the gate electrode 9, and the region of the high concentration diffusion layer 4 a where the well region 5 is formed is more than the other part of the well region 5. The channel region 6a is obtained by inverting to the low concentration P type.

次に、層間絶縁膜１０ａを選択的にエッチングして、図３（ｆ）に示すように、ゲート電極９の上部以外の層間絶縁膜１０ａとゲート電極９の下部以外のゲート絶縁膜８ａとを共に除去し、ウェル領域５とチャンネル領域６ａの表面を露出させる。この工程により、ゲート電極９の上面に形成された層間絶縁膜１０ｂの端面は、ゲート電極９およびゲート絶縁膜８の端面と同一面となる。次に、露出された表面のウェル領域５の領域上面をレジスト膜で覆う。   Next, the interlayer insulating film 10a is selectively etched to form an interlayer insulating film 10a other than the upper part of the gate electrode 9 and a gate insulating film 8a other than the lower part of the gate electrode 9, as shown in FIG. Both are removed to expose the surface of the well region 5 and the channel region 6a. By this step, the end surface of the interlayer insulating film 10 b formed on the upper surface of the gate electrode 9 is flush with the end surfaces of the gate electrode 9 and the gate insulating film 8. Next, the upper surface of the well region 5 on the exposed surface is covered with a resist film.

その後、レジスト膜と層間絶縁膜１０ｂをマスクとして、ドープした領域がＮ型となる量のドナーをドープし、拡散させることにより、ウェル領域５内部にＰ型のチャンネル領域６ａと同様の深さに、チャンネル領域６ａの一部にＮ型のソース領域７を形成し、その後にレジスト膜を除去する。形成されたソース領域７は横方向にも拡散して、ゲート絶縁膜８の下層にも入り込む。   Thereafter, using the resist film and the interlayer insulating film 10b as a mask, the doped region is doped with an amount of N-type donor and diffused, so that the well region 5 has the same depth as the P-type channel region 6a. The N-type source region 7 is formed in a part of the channel region 6a, and then the resist film is removed. The formed source region 7 is also diffused in the lateral direction and enters the lower layer of the gate insulating film 8.

次に、図３（ｇ）に示すように、ＣＶＤによって、層間絶縁膜１０ｂの表面と、同一端面上にある層間絶縁膜１０ｂ、ゲート電極９およびゲート絶縁膜８の各々の端面と、露出したウェル領域５およびソース領域７の表面との全面を覆った層間絶縁膜１０ｃを追加形成し、ウェル領域５の全表面と、ウェル領域５近傍のソース領域７表面の一部を覆う層間絶縁膜１０ｃをエッチング除去して、コンタクト窓を形成する。   Next, as shown in FIG. 3G, the surface of the interlayer insulating film 10b and the end surfaces of the interlayer insulating film 10b, the gate electrode 9 and the gate insulating film 8 on the same end surface are exposed by CVD. An interlayer insulating film 10c that covers the entire surface of the well region 5 and the source region 7 is additionally formed, and an interlayer insulating film 10c that covers the entire surface of the well region 5 and part of the surface of the source region 7 near the well region 5 is formed. Is removed by etching to form a contact window.

この状態で、残された層間絶縁膜１０は、ゲート電極９とゲート絶縁膜８との端面を覆っており、ソース領域７表面の一部領域にもかかっている。次に、露出したウェル領域５と、ソース領域７と、層間絶縁膜１０の表面を覆ったソース電極１１を形成する。さらに、半導体基板１の裏面をメタライズすることにより、ドレイン電極１２を形成し、図１に示す構造が完成する。   In this state, the remaining interlayer insulating film 10 covers the end surfaces of the gate electrode 9 and the gate insulating film 8 and also covers a part of the surface of the source region 7. Next, the exposed well region 5, the source region 7, and the source electrode 11 covering the surface of the interlayer insulating film 10 are formed. Furthermore, the drain electrode 12 is formed by metallizing the back surface of the semiconductor substrate 1, and the structure shown in FIG. 1 is completed.

本発明の半導体装置は、高耐圧と低動作抵抗で高出力に使用し得る半導体装置として有用であり、特に高出力タイプに適している。   The semiconductor device of the present invention is useful as a semiconductor device that can be used for high output with high breakdown voltage and low operating resistance, and is particularly suitable for a high output type.

本発明の実施の形態における半導体装置の断面図Sectional drawing of the semiconductor device in embodiment of this invention 本発明の半導体装置と従来の半導体装置の特性比較グラフであり、（ａ）は、Ｒｏｎレベル、（ｂ）は、Ｒ−ＡＳＯレベル、（ｃ）は、Ｆ−ＡＳＯレベルを示すグラフ4 is a characteristic comparison graph between the semiconductor device of the present invention and a conventional semiconductor device, where (a) is a Ron level, (b) is an R-ASO level, and (c) is a graph showing an F-ASO level. 本発明の半導体装置の各製造工程における断面図Sectional drawing in each manufacturing process of the semiconductor device of this invention 従来の半導体装置の断面図Sectional view of a conventional semiconductor device 従来の半導体装置の断面図Sectional view of a conventional semiconductor device 従来の半導体装置の断面図Sectional view of a conventional semiconductor device

符号の説明Explanation of symbols

１ 半導体基板
２、２ａ エピタキシャル層
３、３ａ、３ｂ 高濃度エピタキシャル層
４、４ａ 高濃度拡散層
５ ウェル領域
６、６ａ チャンネル領域
７ ソース領域
８、８ａ ゲート絶縁膜
９、９ａ ゲート電極
１０、１０ａ、１０ｂ、１０ｃ 層間絶縁膜
１１ ソース電極
１２ ドレイン電極
１３ 第一ウェル領域
１４ 第二ウェル領域 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2, 2a Epitaxial layer 3, 3a, 3b High concentration epitaxial layer 4, 4a High concentration diffusion layer 5 Well region 6, 6a Channel region 7 Source region 8, 8a Gate insulating film 9, 9a Gate electrode 10, 10a, 10b, 10c Interlayer insulating film 11 Source electrode 12 Drain electrode 13 First well region 14 Second well region

Claims (1)

第一導電型の半導体基板と、
前記半導体基板上に形成された第一導電型のエピタキシャル層と、
前記エピタキシャル層の上層部に形成された前記エピタキシャル層より高濃度で第一導電型の高濃度エピタキシャル層と、
前記高濃度エピタキシャル層内に前記高濃度エピタキシャル層の表面から内部に延在させて形成された第二導電型のウェル領域と、
前記ウェル領域内に配置され、前記ウェル領域表面から内部に延在させて形成された第一導電型のソース領域と、
前記ウェル領域表面および前記ソース領域表面に形成されたソース電極と、
前記ソース領域と前記高濃度エピタキシャル層とに隣接して、前記ウェル領域の表面から内部に延在して形成され、前記ウェル領域よりも低濃度である第二導電型のチャンネル領域と、
前記チャンネル領域の表面にゲート絶縁膜を介して設けられたゲート電極と、
前記ゲート電極と前記ソース電極を絶縁する層間絶縁膜と、
前記半導体基板の下面にドレイン電極とを備えた半導体装置において、
前記高濃度エピタキシャル層内の表面近傍に配置され、前記高濃度エピタキシャル層よりもさらに高濃度であり、前記チャンネル領域に隣接した高濃度拡散領域を備えたことを特徴とする半導体装置。 A first conductivity type semiconductor substrate;
An epitaxial layer of a first conductivity type formed on the semiconductor substrate;
A high-concentration epitaxial layer of the first conductivity type at a higher concentration than the epitaxial layer formed in the upper layer portion of the epitaxial layer;
A well region of a second conductivity type formed in the high concentration epitaxial layer so as to extend from the surface of the high concentration epitaxial layer to the inside;
A source region of a first conductivity type disposed in the well region and extending from the surface of the well region to the inside;
A source electrode formed on the surface of the well region and the surface of the source region;
Adjacent to the source region and the high-concentration epitaxial layer, a channel region of a second conductivity type formed extending from the surface of the well region to the inside and having a lower concentration than the well region;
A gate electrode provided on the surface of the channel region via a gate insulating film;
An interlayer insulating film for insulating the gate electrode and the source electrode;
In a semiconductor device comprising a drain electrode on the lower surface of the semiconductor substrate,
A semiconductor device comprising a high concentration diffusion region disposed near a surface in the high concentration epitaxial layer, having a higher concentration than the high concentration epitaxial layer, and adjacent to the channel region.
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