JPH01292862A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase an effective area of an element and to acquire a high breakdown strength even when a junction is shallow, by providing an extension section of a gate electrode layer and a gate wiring electrode layer which functions as a field plate in a circumference section inside an element formation region. CONSTITUTION:A gate electrode layer 26 of MOS structure 35a which positions at the outermost side inside an element formation region 36 extends to the outside of the MOS structure 35a through a gate insulation layer 25 by a specified size (a1). A gate wiring electrode layer 27 is formed extending further to the outside of the outermost end of the gate electrode layer 26 by a specified size (a2). Since the gate electrode 26 and the wiring electrode layer 27 are used as a part of a field plate, a larger effective area can be provided for element formation. The extension section of the gate electrode layer 26 from the outermost MOS structure 35a functions as a field plate, and is opposite to a substrate through a thin gate oxide from 25a at an area near a bending section 33 of the junction of the MOS structure 35a. Therefore, field concentration at the bending section 33 can be considerably relaxed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a semiconductor device having a vertical insulated gate type element, and particularly relates to a voltage withstanding structure at the outer periphery of a vertical MO3FET element. .

(Prior Art) Conventionally, a field plate structure is often used in a vertical MOS F E 'I'' in order to improve the breakdown voltage between the drain and the source on the main surface side of the substrate.

A conventional example thereof will be explained below with reference to the drawings.

FIG. 4 is a sectional view of the peripheral portion of the conventional FET.

A plurality of P-type base regions 3 or 3A are selectively formed on one main surface of the N4-type silicon substrate 1 on which N-type epitaxial N2 is laminated, and selectively a plurality of P-type base regions 3 or 3A are formed in each P-type base region. A P4 type base fA region 9 or 9A is formed. A highly doped N'' type source region 4 is provided in the P type base region 3 except for the P type base region 3A outside fk.
Through the gate oxide film 5 and the N-type channel forming region 3h of the P-type base region 3 which is sandwiched between the N-type epitaxial layer 2 (hereinafter also referred to as the N-type drain region) and the N4-type source region 4 and which is exposed on the substrate surface. Opposing gate electrodes 6 are formed. An oxide film 7 is provided that includes the junction @10 between the outermost P-type base region 3A and the N-type drain region 2, spans the regions 2 and 3A, and extends outward. sauce"
An interlayer insulator [8 is provided to cover the gate electrode 6 and the oxide film 7 except for the r4 electrode opening, and a source wiring type @ including the source electrode is provided on the upper surface of the source electrode opening and the glabella insulating film 8.
11 is formed. Further, a drain electrode 12 is provided on the other main surface of the N+ type silicon substrate 1.

When a drain voltage with a polarity such that the drain electrode 12 is positive and the source electrode 11 is negative, and a positive gate voltage exceeding a certain value is applied to the gate electrode, a channel is formed in the N-type channel forming region 3h, and a drain current flows. Drain current is controlled by gate voltage. When the gate voltage is lower than a certain value, the drain current is cut off, and the drain voltage is mainly borne by the depletion layer at the junction between the N- type drain region 2 and the P-type base region 3 or 3A.

In an element having a planar structure as shown in FIG. 4, there is a problem in that the electric field due to the drain voltage is concentrated on the curved portion 13 of the outer junction between the P-type base region 3A and the N-type drain region, resulting in a decrease in breakdown voltage. There is. This conventional example has a field plate structure in which the source wiring electrode 11 protrudes outward by a length a from the outside of the base region 3A.

In the field plate structure, by appropriately selecting the film thickness of the insulating layer under the field plate and the protrusion width a of the field plate, it is possible to avoid electric field concentration at the bent portion 13 of the junction, and to increase the drain-source breakdown voltage. It is possible to improve.

The reason why the field plate structure improves the withstand voltage of the planar structure is as follows. Prerna'! f4
In 3ia, the reason why the withstand voltage is lower than that of a planar junction is that the junction has a curved part and the electric field is concentrated at that part. As shown in Figure 4, the field plate (protruding part a of the source wiring electrode) is attached to the vertical MO3FET.
When forming a forward direction between the drain and source (in the case of N-channel MO8PET, the drain is positive, and the P-channel M
In the case of an O3FET, when a voltage is applied to the drain (which is at a negative potential), carriers on the surface of the N- type drain region 2 under the field plate are driven away, so that a depletion layer is formed here. This depletion layer is continuous with the depletion layer of the junction, and can relax the radius of curvature of the depletion layer at the curved portion of the junction. In other words, electric field concentration at the bent portion 13 is prevented, and the withstand voltage can be improved.

The effect of improving breakdown voltage by the field plate largely depends on the thickness and material of the insulating layer under the field plate (IEEE TRANSACTIONS, ED
-26, NO3, JULY, 1977, P, 1098~
11009), in Fig. 4, the drain voltage fi
The forward blocking voltage applied to the source electrode 12 and the source electrode 11 is the voltage applied to the insulating layers 7 and 8 and the N under the field plate.
The voltage applied to the depletion layer in the - type drain region is divided into voltages applied to the depletion layer in the -type drain region, and this ratio is inversely proportional to each capacitance calculation.
Larger voltage is applied to the smaller capacitance. When the voltage applied to the depletion layer is large, the elongation of the depletion layer becomes large, and the curvature of the depletion layer at the curved portion of the junction is greatly relaxed, making it possible to prevent electric field concentration at the curved portion of the junction. Therefore, the thickness of the insulating layer should be made as thin as possible, a material with a relative permittivity as large as possible should be used, and the capacitance using the insulating layers 7 and 8 as dielectric layers should be made larger than the capacitance of the depletion layer. Become.

However, in this case, a large voltage will be applied at the edge of the field plate as well, and electric field concentration will occur just below the edge of the field plate, so the thickness of the insulating layer in this area should be at least a certain value to prevent a drop in breakdown voltage. There is a need.

In the conventional field plate structure shown in Fig. 4, insulation [[
It is necessary to determine the film thicknesses of 7 and 8. The shallower the depth of the junction, the greater the curvature of the curved portion of the junction. Therefore, in order to prevent electric field concentration in this portion, it is necessary to reduce the thickness of the insulating layer directly under the field plate at the curved portion.

Therefore, in the conventional structure as shown in FIG. 4, the effect of improving breakdown voltage is small in the case of a shallow junction.

In this case, as shown in Figure 5, field play 1-2 is
It is conceivable to reduce the thickness of the insulating layer near the junction and increase the thickness of the insulating layer at the end of the field plate. However, in the conventional structure in which the source electrode 11 protrudes, the manufacturing process becomes quite complicated.

Another method for improving the withstand voltage is a guard ring structure, but in this structure, a considerable area around the device periphery can be used as a guard ring formation region, reducing the effective area of the device.

(Problems to be Solved by the Invention) As mentioned above, a field plate structure is used in vertical MOS FETs and the like to improve the withstand voltage at the outer periphery, but for example, the conventional structure shown in FIG. So,
Since the source wiring electrode is used on the field plate,
Quite an extra surface 8 as a field plate forming area!
Moreover, as the junction depth becomes shallower, the withstand voltage improvement effect becomes smaller.

Although the conventional structure shown in FIG. 5 can improve the breakdown voltage to some extent, the problem of reducing the effective area of the element because a considerable area around the element is taken up as a field plate formation area remains unsolved. Furthermore, a structure in which a source wiring electrode is used as a field plate has the disadvantage that the process for forming an insulating layer having a two-step thickness structure is complicated, which reduces productivity.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a vertical insulated gate type element, which can increase the effective area of the element compared to the conventional one and can obtain a high withstand voltage even when the junction depth is shallow, with the manufacturing process being almost the same as the conventional one. It is.

[Structure of the Invention] (Means for Solving the Problems and Their Effects) The semiconductor device of the present invention according to the first claim includes an Mx type MO3FET, an insulated gate bipolar transistor (In5ulated G
ate Bipolar Transister
, IG8T), etc., with a structure in which an extended portion of a gate electrode layer and a gate wiring electrode layer having a function of a field plate is provided in the peripheral part of the element formation region. This is a solution to a problem.

In other words, one of the characteristics of the II structure in the peripheral area is that the first conductive layer (including the gate electrode that functions as a gate) of the MO3M structure located at the outermost side is connected to the first insulating layer (including the gate oxide film) The point is that it extends outward by a predetermined amount from the outermost MO3 structure. As a result, the extending portion of the first conductive layer has the function of a field plate, and in the vicinity of the junction of the outer surface of the MO8#l3jj, the extending first conductive layer covers the thin first insulating layer. Since it faces the substrate through the junction, even if the junction depth is shallow, a high breakdown voltage can be obtained for the above-mentioned reason. Further, the first conductive layer and the first insulating layer can be formed using the same number of steps as in the conventional method.

Another feature of the structure of the peripheral part is that the first conductive layer is
A second conductive layer is formed to protrude from the conductive layer by a predetermined amount to the outer side of the conductive layer, and is connected to have the same potential as the first conductive layer.
This is because a conductive layer is provided. This second conductive layer also has a function as a field plate, and since the thickness of the insulating trs layer between the layer end and the substrate can be made sufficiently large, electric field concentration near the end can be reduced. . Further, the second insulating layer and the second conductive layer can be formed using the same number of steps as in the conventional method.

In the above peripheral structure, a part of the field plate can be used as the second conductive layer (equivalent to the gate wiring electrode layer), so there is no need to provide a separate gate wiring electrode layer, and the effective area for element formation is reduced. Can be made larger.

The semiconductor device of the present invention according to the second claim is a vertical MO8FET.
The present invention is a single or composite semiconductor device having an element, and is different in that it embodies the desired shape of the first insulating layer in the semiconductor device according to the first aspect. That is, the outermost MO5
The point is that the layer thickness of the first insulating layer extending outward from the 4111 structure increases toward the outside. As a result, the thickness of the insulating layer is reduced near the junction of the outer surface of the outermost MO3 structure, while the thickness of the insulating layer between the respective ends of the first conductive layer and the second conductive layer and the substrate is increased. becomes possible,
The effect of preventing electric field concentration at each end can be increased. Note that the other configurations and functions of the peripheral portion of the element of the present invention are equivalent to those of the element described in the first claim,
The manufacturing process is relatively simple and the effective area of the device can be large.

(Example) As an example of the present invention, a semiconductor device in which an N-channel vertical MO3FET element is individually formed in one pellet will be described below with reference to the drawings. Note that the semiconductor device of the embodiment is included in the semiconductor device described in the first claim, and is a semiconductor device according to the second claim that embodies the desired shape of the first insulating layer.

FIG. 1 shows the vertical MO3F E which is an embodiment of the present invention.
A schematic partial cross-sectional view of the peripheral part of the element 'I' is shown.

Note that in the drawing, the left side is the outer circumferential direction. FIG. 2 also shows the source and gate wiring voltage fl! of the device. FIG. 3 is a plan view schematically showing the shape of layers.

In FIG. 1, the surface of the N4″ type silicon substrate 21 is
- type epitaxial layer 22 is formed. In this embodiment, the semiconductor substrate 11 described in the first claim is a combination of the substrate 21 and an N-type epitaxial layer 22,
The one conductivity type impurity region corresponds to the N- type epitaxial layer 22. An opposite conductivity type impurity region (also called a P-type base region) 23 is selectively formed in this N-type epitaxial layer (also called an N-type drain layer) 22 .

A high concentration impurity region of one conductivity type (also referred to as an N'' type source region) 24 is selectively provided in this P type base region 23. It is sandwiched between this N type source region 24 and N− type drain region 22. An N-type channel forming region 23h in a portion of the P-type base region 23 exposed to the main surface of the substrate, and the region 23h.
and a first insulating layer (also called a gate insulating layer, including the insulating layer of the extended part described later in the peripheral part), and a first conductive layer (also called a gate electrode layer, which in the peripheral part includes the insulating layer of the extended part described later), facing each other via λj-. (including the extension part) 26 and MO3 structure 35 and 3
5a is formed.

The MO3O3 structure 35a located at the outermost side in the element formation region 36 (see FIG. 2) protrudes outward from the MO3 structure 35a by a predetermined distance a through the gate insulating layer, λj. It has been extended. The extended portion of the gate insulating layer 1 is composed of a oxide film 25a and an oxide film 25b which is thicker than the oxide film 25a and is connected in a stepwise manner.

Further, a second insulating layer (also referred to as an interlayer insulating film) 28 is formed covering the gate electrode layer 26, and a second conductive layer (also referred to as a gate wiring electrode layer) 27 is deposited thereon. The gate wiring "@ pole layer 27 is formed so as to protrude further outward by a predetermined size a2 from the outer end of the gate electrode layer 26. Furthermore, the gate wiring electrode layer 27 and the gate electrode layer 26 are formed through the opening 30 of the interlayer insulating film 28. electrically connected to each other.

Next, an overview of the steps for manufacturing the semiconductor device shown in FIGS. 1 and 2 will be explained with reference to FIG. 3.

In the same figure (a), the concentration is 3x 10'8ato
After growing an epitaxial layer 22 containing phosphorus (P) at a concentration of 2x10'' atoms/an3 on an N4 type silicon substrate 21 containing antimony at a concentration of 2x10'' atoms/an3,
Grow the oxide film at 5000X, pattern it,
A relatively thick oxide film 25b is formed around the element formation region. Next, in the same figure (b), the gate oxide film 25a
Grow 1000 polycrystalline silicon and further grow 5000 polycrystalline silicon.
X is deposited and patterned to form the gate electrode layer 26. Thereafter, using the gate electrode layer 26 as a mask, boron (B) was applied at an acceleration voltage of 40 key and a dose of 4. OX
Ions are implanted at 10" at O113/C112 and diffused in N2 gas at 1100° C. for about 6 hours to form a P-type base region 23. Next, as shown in FIG. ) Boron is accelerated at a voltage of 40 keys and a dose of 3X 10'atols.
After ion implantation at /c112, the P1 type base region 29 was formed by annealing at 1100° C. for 15 minutes in 02 gas, and then resist was applied again and patterned to mask the resist 34 and gate electrode 26. Arsenic (As) is accelerated at a voltage of 40keV and a dose of 15x1.
Ion implantation was performed at 0"atols/cIl',
Annealing is performed for 20 minutes at 00° C. in 02 gas to form an N-type source region 24. Next, in Figure 1, CV D
(Che IIical νapor Depositi
An oxide film is deposited by a method such as on) and patterned to form an interlayer insulating film 28. In the glabella insulating film 28,
An opening 30 for connecting the gate electrode layer 26 and a gate wiring electrode layer 27 to be described later, and an N4 type source region 24
A contact opening is formed between the gate wiring electrode layer 27 and the P" type base region 29. Next, aluminum is deposited and patterned to form the gate wiring electrode layer 27 and the source wiring electrode layer 31.
form. In the semiconductor device with the above configuration and manufacturing method, the extending portion 25a of the gate insulating layer 25- to the step boundary portion 34 is formed simultaneously with the gate oxide film of the MO3 structure 35 in the gate oxide film forming step, and Since the oxide film 25b connected to the oxide film 25a remains the oxide film shown in FIG. 3<a>, the manufacturing process of the semiconductor device of the present invention shown in FIG. Vertical MO, 5FE
It is almost the same as the manufacturing process of T, and moreover, the manufacturing process of
A structure similar to the stage field plate can be realized.

Further, as shown in FIG. 2, in the structure of the present invention, since the gate electrode layer 26 and the gate wiring electrode layer 27 are used as part of the field plate, a large effective area required for element formation can be obtained.

Further, the portion where the gate electrode layer 26 extends from the outermost MO3 structure 35a has a function as a field plate, and in the vicinity of the junction bend 33 of the MO3 structure 35a, the gate electrode layer 26 is connected to the substrate through the thin gate oxide film 25a. , the electric field concentration at the bend 33 of the outermost junction is significantly alleviated. The outer portion of the gate electrode M26 is deposited on the thick oxide film 25b and connected to the gate wiring electrode layer 27 via the interlayer insulation [28]. Therefore, since the outer end of the gate wiring electrode layer 27, which is the substantial end of the field plate, faces the substrate via the laminated film of the oxidized WA 25b and the interlayer insulating film 28, the electric field concentration in this part is sufficiently alleviated. Pressure resistance is improved.

For example, a vertical MO3F with a drain-source breakdown voltage of 170V
When forming ET, the conventional structure has a specific resistance of 3.5Ω.
・A wafer of about C1 is required, but in the structure of the present invention, the electric field in the periphery of the element formation region is relaxed as described above, so it is possible to use a wafer with a specific resistance of about 2.7Ω・CI. So, the chip area lX1111I
In the case of ', the on-resistance is 2.67Ω in the conventional structure, whereas it is 1.91Ω in the structure of the present invention, and power loss in the on-state can be significantly reduced.

In this embodiment, an N-channel vertical MO3FET has been described, but the present invention is applicable not only to a P-channel vertical MO8FET but also to an additional stacking of a region of the opposite conductivity type in contact with the other main surface side of the drain region of the vertical MO3FET. IGB
It is also applicable to T elements.

Also, the semiconductor element of the present invention and other active or passive elements can be combined into one semiconductor chip! The present invention is also applicable to so-called composite semiconductor devices.

[Effects of the Invention] In the semiconductor device of the present invention,! The V manufacturing process is almost the same as that of conventional semiconductor devices, the number of steps is the same, and a stepped field plate structure can be realized.

In addition, in the structure of the semiconductor device of the present invention, a part of the field plate can be used as a gate wiring electrode layer, so there is no need to provide a separate gate wiring t[i layer, and the structure of the MO3FET element is reduced compared to the conventional structure. The effective area can be increased.

Generally, in the case of vertical MOSFETs, in order to reduce the resistance between the source and drain in the on state (on resistance), it is necessary to reduce the wafer resistance as much as possible, but its value is limited due to the relationship with the withstand voltage. . The main factor that limits the breakdown voltage is the breakdown voltage at the junction between the base region and drain region of the device. In the structure of the present invention, there are two levels of field plates, and the field plate on the curved part of the junction faces the substrate through a thin gate oxide film, so a high withstand voltage can be obtained even when the junction depth is shallow. Since the outer end of the plate faces the substrate through a thick laminated insulating film, the withstand voltage at the end of the chain is improved. As shown in the examples, according to the structure of the present invention, the same level of breakdown voltage can be obtained with a wafer having a lower specific resistance than that of the conventional structure.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the peripheral part of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view showing a wiring electrode layer of the semiconductor device of FIG. 1, and FIG. 3 is a fabrication of the semiconductor device of FIG. 1. 4 and 5 are cross-sectional views showing the peripheral portion of a conventional semiconductor device. λU... Semiconductor substrate, 21... (N" type silicon substrate), 22... One conductivity type impurity region (N~ type epitaxial layer), 23... Opposite conductivity type impurity region (
P-type base region), 23h...channel forming region,
24... High concentration impurity region of one conductivity type (N'' type source region), l2... First insulating layer (gate insulating layer),
25a... (gate oxide film), 25b... (oxide film), 26... first conductive layer (gate electrode layer), 2
7...Second conductive layer (gate wiring electrode Jt, 28.
... second insulating layer (interlayer insulating film), 30... opening,
31... (source wiring in pole layer), 34... stairs, 35... MO3 structure, 35a... outermost MO
8 structure, 36... element formation region, a,, a2.
...Protruding portion of a predetermined size. (Note) The names in parentheses are the names used in "3. Detailed Description of the Invention." Patent applicant: Toshiba Corporation 27: Second conductive layer Figure 1 Figure 2 (a) 23 25a Figure 4

Claims (1)

[Claims] 1. A semiconductor substrate having one conductivity type impurity region on one principal surface, an opposite conductivity type impurity region selectively formed in the one conductivity type impurity region, and an opposite conductivity type impurity region formed in the opposite conductivity type impurity region. A selectively formed high concentration impurity region of one conductivity type, and the opposite conductivity type impurity region sandwiched between the high concentration impurity region of one conductivity type and the one conductivity type impurity region are exposed on the main surface of the substrate. In a semiconductor device having a MOS structure including a channel forming region in a portion where the channel forming region is formed and a first conductive layer facing the channel forming region with a first insulating layer interposed therebetween, A first conductive layer of a MOS structure extends outward from the MOS structure by a predetermined amount via a first insulating layer, and extends through a second insulating layer covering the first conductive layer to the first conductive layer. The second conductive layer is formed to protrude outward from the layer by a predetermined amount, and the second conductive layer is electrically connected to the first conductive layer through the opening in the second insulating layer. A semiconductor device comprising a semiconductor element characterized by: 2. In the semiconductor device according to claim 1,
The semiconductor substrate is a one conductivity type substrate, the substrate is a drain region, the opposite conductivity type impurity region is a base region, the one conductivity type high concentration impurity region is a source region, the first conductive layer is a gate electrode layer, and The second conductive layer is a gate wiring electrode layer, and the layer thickness of the first insulating layer extending outward from the outermost MOS structure increases in a stepwise manner toward the outside. A semiconductor device comprising a vertical MOS field effect transistor element.