JPS62224074A - Insulated-gate semiconductor device - Google Patents

Insulated-gate semiconductor device

Info

Publication number
JPS62224074A
JPS62224074A JP61065746A JP6574686A JPS62224074A JP S62224074 A JPS62224074 A JP S62224074A JP 61065746 A JP61065746 A JP 61065746A JP 6574686 A JP6574686 A JP 6574686A JP S62224074 A JPS62224074 A JP S62224074A
Authority
JP
Japan
Prior art keywords
layer
gate
conductive wiring
bonding pad
mosfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61065746A
Other languages
Japanese (ja)
Inventor
Tetsuo Iijima
哲郎 飯島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61065746A priority Critical patent/JPS62224074A/en
Publication of JPS62224074A publication Critical patent/JPS62224074A/en
Pending legal-status Critical Current

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To reduce the chip area of a semiconductor chip by forming a bonding pad for a gate electrode for an MOSFET onto a cell forming region in the MOSFET. CONSTITUTION:A bonding pad 9 for a gate electrode is shaped onto a plurality of power MOSFETs shaped onto a substrate 1. The bonding pad 9 for the gate electrode is formed by a second layer conductive wiring (Al) 10, and one end of the second layer conductive wiring 10 is connected electrically to the gate electrodes 2 consisting of polycrystalline silicon for a plurality of the power MOSFETs. Layer insulating films 11 and a first layer conductive wiring (Al) 5 are shaped among the second layer conductive wiring 10 and the gate electrodes 2, and the first layer conductive wiring 5 functions as a source electrode for the MOSFET. Accordingly, the power MOSFET is fined while the efficiency of a chip can be improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は絶縁ゲート半導体装置、特に二重拡散による縦
形のパワーＭＯ８ＦＥＴ（金属酸化物半導体電界効果ト
ランジスタ）の電極構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrode structure of an insulated gate semiconductor device, particularly a double-diffused vertical power MO8FET (metal oxide semiconductor field effect transistor).

〔従来の技術〕[Conventional technology]

縦形構造のパワーＭＯ８ＦＥＴはオン抵抗Ｒ８Ｎが小さ
く、増幅率ｇｍが大きくとれることにより、スイッチン
グ用や超音波応用機器の出力用として実用されている。The power MO8FET with a vertical structure has a small on-resistance R8N and a large amplification factor gm, so it is used for switching purposes and for outputting ultrasonic application equipment.

第４図は縦形ｎチャネルＭＯ８ＦＥＴの一例を示し、ｎ
’−ＩＸＶ、ｓｉ基体１をドレインとしてその一主表面
上にポリＳｉからなる絶縁ゲート２が形成され、このポ
リＳｉを共通のマスクとする２重拡散によって形成した
ｐ型領域３の一部をチャネル部とするとともに、ｎ＋型
領領域４ソース領域とするセルを複数個配列し、各ソー
ス領域にＡ２膜５を並列に接続してその一部をソース電
極端子（ポンディングパッド）とし、ポリＳｉゲートに
接続したＡ！膜の一部６をゲート電極端子（ポンディン
グパッド）とするものである。そのことが（株）工業調
査会電子材料１９８１年９月ｐ２２−２７に記載されて
いる。FIG. 4 shows an example of a vertical n-channel MO8FET, with n
'-IXV, an insulated gate 2 made of poly-Si is formed on one main surface of the Si substrate 1 as a drain, and a part of the p-type region 3 is formed by double diffusion using this poly-Si as a common mask. A plurality of cells are arranged to serve as a channel part and an n+ type region 4 as a source region, and an A2 film 5 is connected in parallel to each source region, a part of which is used as a source electrode terminal (ponding pad). A connected to Si gate! A portion 6 of the film is used as a gate electrode terminal (ponding pad). This is described in Kogyo Kenkyukai Electronic Materials, September 1981, p. 22-27.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、半導体デバイスの微細化傾向によりパワーＭ
Ｏ８ＦＥＴも５ｍｍ角のものからさらに２〜３ｍｍ角寸
法が指向され、低オン抵抗化が進む中で、ソースポンデ
ィングパッドの他、ゲートポンディングパッド下のデッ
ドスペースが相対的に太き（なりチップ効率向上を阻ん
でいる。By the way, due to the trend toward miniaturization of semiconductor devices, the power M
O8FETs are also trending from 5 mm square to 2 to 3 mm square, and as the on-resistance is becoming lower, the dead space under the gate bonding pad as well as the source bonding pad is becoming relatively thick (as chip size increases). This is hindering efficiency improvement.

すなわち、第４図に示すように、従来は、ポンディング
パッドを含む１１電極５，６は人７単層の構造であるこ
とにより、ゲートパッド（６）下ではＭＯＳセルとのコ
ンタクトができないためこの部分にはＭＯＳセルを配置
することができず、したがってここがデッドスペース１
５となっており、チップ寸法の微細化でこの傾向が顕著
となっている。That is, as shown in FIG. 4, conventionally, the 11 electrodes 5 and 6 including the bonding pad have a single-layer structure, so that contact with the MOS cell cannot be made under the gate pad (6). MOS cells cannot be placed in this part, so this is dead space 1.
5, and this tendency has become more noticeable as chip dimensions become finer.

本発明は上記した問題を克服するためになされたもので
あり、その目的とするところは、パワーＭＯ３ＦＥＴの
微細化とともにチップ効率を向上することにある。The present invention has been made to overcome the above-mentioned problems, and its purpose is to miniaturize power MO3FETs and improve chip efficiency.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔問題を解決するための手段〕[Means to solve the problem]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

すなわち、ゲート電極用ポンディングパッドを基板上に
形成した複数のパワーＭＯ８ＦＥＴの上に設ける。この
ゲート電極用ポンディングパッドは＠２層目の導電性配
線（Ａ−ｅ”）で形成され、該第２層目の導電性配線の
一端は複数のパワーＭＯ８ＦＥＴの多結晶シリコンから
なるゲート電極に電気的に接続されている。前記＠２層
目の導電性配線とゲート電極の間には眉間絶ｌｔ１膜と
第１層目の導電性配線（ＡＡ　）が設けられ、前記第１
層目の導電性配線はＭＯＳＦＥＴのソース電極として働
（。That is, a gate electrode bonding pad is provided on a plurality of power MO8FETs formed on a substrate. This gate electrode bonding pad is formed of the second layer conductive wiring (A-e''), and one end of the second layer conductive wiring is connected to the gate electrode made of polycrystalline silicon of a plurality of power MO8FETs. Between the conductive wiring in the second layer and the gate electrode, a lt1 film and a conductive wiring in the first layer (AA) are provided.
The conductive wiring in the second layer acts as the source electrode of the MOSFET.

〔作用〕[Effect]

ゲート用ポンディングパッド下に眉間絶縁膜と第１層目
の導電性配線層とが設けられているため、このパッドか
らＭＯ５ＦＥＴ形成領域までの距離が大きいという作用
でワイヤボンディング時のダメージが半導体基板上のＭ
ＯＳＦＥＴに影！＃すれない。それゆえ、ゲート用ポン
ディングパッド下においてもＭＯ８ＦＥＴセルを配置す
ることができ、チップの微小寸法化、及びチップ効率を
高め、オン抵抗を向上し、前記発明の目的を達成できる
。Since the glabella insulating film and the first conductive wiring layer are provided under the gate bonding pad, the distance from this pad to the MO5FET formation area is large, so damage during wire bonding is less likely to occur on the semiconductor substrate. upper M
Shadow on OSFET! #I can't stand it. Therefore, the MO8FET cell can be placed even under the gate bonding pad, thereby achieving miniaturization of the chip, increasing the chip efficiency, improving the on-resistance, and achieving the object of the invention.

〔実施例〕〔Example〕

第１図は本発明の実施例を示すものであって、縦形ＭＯ
８ＦＥＴの要部縦断面図である。FIG. 1 shows an embodiment of the present invention, in which a vertical MO
It is a longitudinal cross-sectional view of the main part of 8FET.

１はｎ−型Ｓｉ基体で、下側主面にドレイン電極との低
抵抗接続のための高濃度ｎ＋層７を形成しである。Reference numeral 1 denotes an n-type Si substrate, on the lower main surface of which a high concentration n+ layer 7 is formed for low resistance connection with the drain electrode.

２は絶縁ゲートで基板上にうすい酸化膜を介してポＩＪ
　Ｓ　ｉをデポジットしパターニングしたものである。2 is an insulated gate that connects the poIJ through a thin oxide film on the substrate.
S i was deposited and patterned.

ポリＳｉゲート２０表面には酸化膜８で覆われている。The surface of the poly-Si gate 20 is covered with an oxide film 8.

３は上記ポリＳｉゲートをマスクにアクセプタを基板に
注入拡散することにより自己整合的に形成したｐ型層で
ポリＳｉゲート直下の部分はチャネル部となる。3 is a p-type layer formed in a self-aligned manner by implanting and diffusing an acceptor into the substrate using the poly-Si gate as a mask, and the portion immediately below the poly-Si gate becomes a channel portion.

４は同じくポリＳｉゲートをマスクにドナを注入拡散し
て自己整合的に形成したｎ＋型層でソース領域となる。Reference numeral 4 denotes an n+ type layer formed in a self-aligned manner by implanting and diffusing donors using the poly-Si gate as a mask, and serves as a source region.

５は第１層Ａ１膜よりなるソース電極でソースのｎ＋型
層４と、チャネル部とならないｐ型層とに対し低抵抗接
続し、ゲート電極の上をａうように形成される。Reference numeral 5 denotes a source electrode made of the first layer A1 film, which is connected with low resistance to the n+ type layer 4 of the source and the p type layer which does not become a channel portion, and is formed so as to extend over the gate electrode.

９は第２層Ａ４膜よりなるゲート電極端子（ボンディン
グ・パッド）、１０は第２層Ａ４膜よりなるソース電極
端子であって、一部層間膜（プラズマＳｉｎ、、ＰＳＧ
、５ＯＧ）１１を介して第２層Ａ７膜の上に形成され、
スルーホールを通じてポリＳｉゲート、ソース電極に接
続される。Reference numeral 9 denotes a gate electrode terminal (bonding pad) made of a second layer A4 film, and 10 a source electrode terminal made of a second layer A4 film.
, 5OG) formed on the second layer A7 film via 11,
It is connected to the poly-Si gate and source electrode through a through hole.

１２．１３はワイヤボンディングされたＡｕポールであ
る。１４はパックベイジョン（保護絶縁膜）であって、
パッド部分を除（第２層Ａ！膜の上をａＺている。12 and 13 are wire-bonded Au poles. 14 is a pack vasion (protective insulating film),
Excluding the pad part (second layer A! The top of the film is aZ.

第２図は縦形ＭＯ８ＦＥＴの電極端子の配置を示す平面
図である。FIG. 2 is a plan view showing the arrangement of electrode terminals of a vertical MO8FET.

５はソース側ポンディングパッドとなる第２層Ａ！膜、
６はゲート側ポンディングパッドとなる第２層Ａ４膜で
ある。5 is the second layer A which becomes the source side bonding pad! film,
6 is a second layer A4 film which becomes a gate side bonding pad.

１５は層間膜にあげたゲートとの接続部分（スルーホー
ル）の位置を示す。Reference numeral 15 indicates the position of the connection portion (through hole) with the gate provided in the interlayer film.

１６はソース電極取出しのためのコンタクトホールの位
置を示す。16 indicates the position of a contact hole for taking out the source electrode.

以上実施例で述べた本発明によれば下記の効果が期待さ
れる。According to the present invention described in the examples above, the following effects are expected.

（１＞　　Ａ７配線膜を２層構造にしてソース電極とポ
ンディングパッド部分とを別にしたことによりゲート用
パッド直下にもＭＯＳＦＥＴのセルを形成することが可
能となり、したがってデッドスペースをなくし、チップ
効率（単位チップ面積当りアクティブ領域面積）を高め
ることができる。たとえば、５．０ＩＩＩＩｍ角相当の
チップでチップ効率を７７％から８８％へ向上できる。(1> By making the A7 wiring film a two-layer structure and separating the source electrode and the bonding pad part, it is possible to form a MOSFET cell directly under the gate pad, thereby eliminating dead space and improving chip efficiency. (Active region area per unit chip area) can be increased.For example, chip efficiency can be improved from 77% to 88% with a chip equivalent to 5.0m square.

（２）上記（１）にともない、ＭＯＳＦＥＴのオン抵抗
を１２％程度向上することができる。(2) According to (1) above, the on-resistance of the MOSFET can be improved by about 12%.

（３１Ａ４２層構造ではＩＣ配線仕様に準じＡ）膜厚は
１層分で１／２に低減でき微細加工が可能となる。(For 31A42 layer structure, according to IC wiring specifications A) The film thickness can be reduced to 1/2 by one layer, allowing fine processing.

上記のような発明の効果が得られる理由をさらに詳述す
ると下記のとおりである。The reason why the above-mentioned effects of the invention can be obtained is as follows.

５３ＩＩｌｌ角相当のチップでは電流容量が３ＯＡと大
きいため、ボンディングのためのＡ２ワイヤを５００μ
ｍφと太くする必要がある。このため、パッド面積もゲ
ート、ソース両方で２．７〜３．３１１１１２と大きく
なり、２ｒ１１Ｔ＆２角チツプ相当の面積が必要となる
。本発明のようにソース・ゲートパッド下の全面にセル
を配置できる構造とすることで、デッドスペースとなっ
た部分のセルがオン抵抗に寄与することになり、１２〜
１５％オン抵抗を低減できる。Since the current capacity of a chip equivalent to 53IIll square is as large as 3OA, the A2 wire for bonding is 500μ
It is necessary to make it as thick as mφ. Therefore, the pad area for both the gate and the source increases to 2.7 to 3.311112, and an area equivalent to a 2r11T&2 square chip is required. By adopting a structure in which cells can be placed over the entire surface under the source and gate pads as in the present invention, the cells in the dead space contribute to the on-resistance.
On-resistance can be reduced by 15%.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で極々変更可
能である。Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited to the above-mentioned examples, and can be modified to a large extent without departing from the gist thereof.

たとえば、ソース用パッドとなる第２層Ａ２膜とソース
電極第１層Ａ４膜とは全面的に接続することができるが
、＠３図に示すようにゲート２上で眉間絶縁膜１１を残
存させることにより、ワイヤボンディングの際の衝撃を
この層間絶縁膜により緩和しゲート絶縁膜の破壊を防止
することができる。For example, the second layer A2 film serving as the source pad and the source electrode first layer A4 film can be connected across the entire surface, but as shown in Figure @3, the eyebrow insulating film 11 remains on the gate 2. As a result, the impact during wire bonding can be alleviated by the interlayer insulating film, and breakdown of the gate insulating film can be prevented.

本発明は縦形パワーＭＯ３ＦＥＴの全てに適用すること
ができる。The present invention can be applied to all vertical power MO3FETs.

本発明は特にチップ寸法が３．Ｑ！１ｍ角以下１オン抵
抗が５０ｍΩ以下の超低オン抵抗パワーＭＯ３ＦＥ、Ｔ
に応用した場合に最も効果を奏するものである。In particular, the present invention has a chip size of 3. Q! Ultra-low on-resistance power MO3FE, T with an on-resistance of 50mΩ or less under 1m square
It is most effective when applied to.

〔発明の効果〕〔Effect of the invention〕

本願によって開示された発明のうち代表的なものにより
て得られる効果を簡単に説明すれば下記のとおりである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

ＭＯＳＦＥＴのセル形成領域上に該ＭＯ８ＦＥＴのゲー
ト電極用ポンディングパッドを設けることにより、ゲー
ト電極用ポンディングパッド形成のために必要な占有面
積を縮少できるという作用で、°半導体チップのチップ
面積を縮少できる。　、By providing a bonding pad for the gate electrode of the MO8FET on the cell formation area of the MOSFET, the area required for forming the bonding pad for the gate electrode can be reduced, thereby reducing the chip area of the semiconductor chip. Can be reduced. ,

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す縦形ＭＯ８ＦＥＴの要
部断面図である。 第２図は本発明の一実施例を示す縦形ＭＯ８ＦＥＴの全
体平面図である。 第３図は本発明の他の実施例を示すＭＯＳＦＥＴの一部
断面図である。 第４図はこれまでの縦形ＭＯ８ＦＥＴの一例を示す要部
断面図である。 １・・・Ｓｉ基体（ドレイン）、２・・・ポリＳｉゲー
ト、３・・・ｐ型拡散層、４・・・ｎ＋型型数散層ソー
ス）、５．６・・・第１層人！電極、７・・・ｎ＋層、
８・・・酸化膜、９・・・Ｗ、２層Ａ！膜（ゲート用ポ
ンプイングツくラド）、１０・・・第２層Ａ２膜（ソー
ス用ポンディングパッド）、１１・・・層間絶縁膜、１
２．１３・・・ボンディングワイヤ、１４・・・パッシ
ベイション、１５・・・デッドスペース。FIG. 1 is a sectional view of a main part of a vertical MO8FET showing an embodiment of the present invention. FIG. 2 is an overall plan view of a vertical MO8FET showing an embodiment of the present invention. FIG. 3 is a partial sectional view of a MOSFET showing another embodiment of the present invention. FIG. 4 is a sectional view of a main part of an example of a conventional vertical MO8FET. DESCRIPTION OF SYMBOLS 1...Si base (drain), 2...Poly-Si gate, 3...p-type diffusion layer, 4...n+ type scattering layer source), 5.6...1st layer layer ! electrode, 7...n+ layer,
8...Oxide film, 9...W, 2 layers A! Film (pumping pad for gate), 10... Second layer A2 film (pumping pad for source), 11... Interlayer insulating film, 1
2.13... Bonding wire, 14... Passivation, 15... Dead space.

Claims (1)

【特許請求の範囲】[Claims] １、半導体基体の一主表面に設けられた複数の絶縁ゲー
ト電界効果トランジスタを有し、前記複数の絶縁ゲート
電界効果トランジスタのゲート電極用ワイヤボンディン
グパッドが前記複数の絶縁ゲート電界効果トランジスタ
上に設けられていることを特徴とする絶縁ゲート半導体
装置。1. A plurality of insulated gate field effect transistors are provided on one main surface of a semiconductor substrate, and wire bonding pads for gate electrodes of the plurality of insulated gate field effect transistors are provided on the plurality of insulated gate field effect transistors. An insulated gate semiconductor device characterized in that:
JP61065746A 1986-03-26 1986-03-26 Insulated-gate semiconductor device Pending JPS62224074A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61065746A JPS62224074A (en) 1986-03-26 1986-03-26 Insulated-gate semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61065746A JPS62224074A (en) 1986-03-26 1986-03-26 Insulated-gate semiconductor device

Publications (1)

Publication Number Publication Date
JPS62224074A true JPS62224074A (en) 1987-10-02

Family

ID=13295890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61065746A Pending JPS62224074A (en) 1986-03-26 1986-03-26 Insulated-gate semiconductor device

Country Status (1)

Country Link
JP (1) JPS62224074A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01290265A (en) * 1988-05-18 1989-11-22 Fuji Electric Co Ltd Mos type semiconductor device
JPH01292862A (en) * 1988-05-20 1989-11-27 Toshiba Corp Semiconductor device
JPH0394472A (en) * 1989-09-06 1991-04-19 Matsushita Electron Corp Vertical type mos field-effect transistor
JP2005150348A (en) * 2003-11-14 2005-06-09 Fuji Electric Device Technology Co Ltd Semiconductor device
JP2005294872A (en) * 2005-07-05 2005-10-20 Mitsubishi Electric Corp Semiconductor device and its manufacturing method
JP2009105177A (en) * 2007-10-23 2009-05-14 Shindengen Electric Mfg Co Ltd Semiconductor device
JP2012064899A (en) * 2010-09-17 2012-03-29 Toshiba Corp Semiconductor device and method of manufacturing the same
EP3644363A1 (en) * 2013-11-28 2020-04-29 Rohm Co., Ltd. Semiconductor device
JP2022527399A (en) * 2019-04-11 2022-06-01 ウルフスピード インコーポレイテッド Transistor semiconductor die with increased working area

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01290265A (en) * 1988-05-18 1989-11-22 Fuji Electric Co Ltd Mos type semiconductor device
JPH01292862A (en) * 1988-05-20 1989-11-27 Toshiba Corp Semiconductor device
JPH0394472A (en) * 1989-09-06 1991-04-19 Matsushita Electron Corp Vertical type mos field-effect transistor
JP2005150348A (en) * 2003-11-14 2005-06-09 Fuji Electric Device Technology Co Ltd Semiconductor device
JP2005294872A (en) * 2005-07-05 2005-10-20 Mitsubishi Electric Corp Semiconductor device and its manufacturing method
JP2009105177A (en) * 2007-10-23 2009-05-14 Shindengen Electric Mfg Co Ltd Semiconductor device
JP2012064899A (en) * 2010-09-17 2012-03-29 Toshiba Corp Semiconductor device and method of manufacturing the same
EP3644363A1 (en) * 2013-11-28 2020-04-29 Rohm Co., Ltd. Semiconductor device
US10886300B2 (en) 2013-11-28 2021-01-05 Rohm Co., Ltd. Semiconductor device
US11367738B2 (en) 2013-11-28 2022-06-21 Rohm Co., Ltd. Semiconductor device
US11908868B2 (en) 2013-11-28 2024-02-20 Rohm Co., Ltd. Semiconductor device
JP2022527399A (en) * 2019-04-11 2022-06-01 ウルフスピード インコーポレイテッド Transistor semiconductor die with increased working area

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