JP2004281524A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2004281524A
JP2004281524A JP2003068102A JP2003068102A JP2004281524A JP 2004281524 A JP2004281524 A JP 2004281524A JP 2003068102 A JP2003068102 A JP 2003068102A JP 2003068102 A JP2003068102 A JP 2003068102A JP 2004281524 A JP2004281524 A JP 2004281524A
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trench
substrate
adjacent
region
wide
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Hirotoshi Kubo
博稔 久保
Hiroyasu Ishida
裕康 石田
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Priority to JP2003068102A priority Critical patent/JP2004281524A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a trench-type power MOSFET can have advantages of both a stripe-shaped trench and a latticed trench when the trench-type power MOSFET is arranged on a bent pattern, but the corner of the pattern is terminated so as to be led out to a gate connection electrode, and an electric field concentrates on a part where a narrow part is arranged. <P>SOLUTION: The trench-type MOSFET is arranged on the bent pattern, and all trenches that terminate at the corner are made to terminate at a wide part. The narrow part formed of usual adjacent trenches is focused to serve as a part of an adjacent wide part. By this setup, the concentration of an electric field can be relaxed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は半導体装置に係り、特にオン抵抗を低減し、基板電位の安定性を向上してドレイン−ソース間のリーク電流を低減する半導体装置に関する。
【０００２】
【従来の技術】
従来、スイッチング素子としての半導体装置では、プレーナ構造よりもチップ単位面積あたりのセル数を増加でき、オン抵抗の低減を図れるトレンチ構造が広く知られている。
【０００３】
図４に従来のトレンチ型パワーＭＯＳＦＥＴの平面図を示す。尚、ソース電極は省略する。トレンチ型パワーＭＯＳＦＥＴの平面形状におけるトレンチパターンは、図４（Ａ）に示す格子状または図４（Ｂ）に示すストライプ状が一般的である。しかし、かかる従来のトレンチの形状では次のような問題があった。
【０００４】
まず、図４（Ａ）の如くトレンチを格子状に形成するパターンでは、１つのセル１８がトレンチ７に囲まれて島状になり、高集積化を図るためにボディコンタクト領域１５は微小な面積に形成される。
【０００５】
例えばＮチャネル型ＭＯＳＦＥＴの場合、ボディコンタクト領域１５はボロン（Ｂ）のイオン注入により形成される。ボロン（Ｂ）はヒ素（Ａｓ）またはリン（Ｐ）と比較して注入ダメージが小さいため、自然酸化膜の成長が少ない。つまり、ボロン（Ｂ）が注入された部分にはソース電極（Ａｌ）をスパッタするときに混入させるシリコンの粒が凝集しシリコンノジュールが成長しやすくなる。そしてこのシリコンノジュールが微小な面積のボディコンタクト領域１５を塞いでしまうことがある。その結果、島状の１つのセル１８でチャネル領域の電位が浮き、そのセル１８から電流がリークし、それがドレイン−ソース間のリーク電流の原因となると考えられる。
【０００６】
一方、図４（Ｂ）の如くトレンチ７をストライプ状に形成するパターンでは、１つのセル１８でボディコンタクト領域１５がコンタクト不良となっても複数のセル１８間でチャネル領域は連続している。そのため、シリコンノジュールの影響を受けず、基板の電位はトレンチ７を格子状に形成した場合よりも安定する。その結果、ドレイン−ソース間のリーク電流は発生しないと考えられる。
【０００７】
しかし、ストライプ状に形成するパターンでは各トレンチ７の間隔をボディコンタクト領域１５の大きさ（幅約２μｍ程度）に合わせて設計するので、格子状のトレンチに比べて単位面積あたりのチャネル領域を多くできない。従ってオン抵抗に関しては、格子状に形成した場合よりも不利となり、低オン抵抗化には不向きであった。
【０００８】
そこで、図４（Ｃ）に示すような曲折したトレンチパターンも開発されている。このトレンチ型ＭＯＳＦＥＴは、破線で示した部分がトレンチ型ＭＯＳＦＥＴの１つのセル１８である。
【０００９】
トレンチ７は、半導体基板表面にストライプ状に複数本形成される。このとき隣接するトレンチ７で挟まれる基板表面に幅広部Ｐｂと幅狭部Ｐｎができるようにトレンチ７を曲折させる。例えば、幅狭部Ｐｎはボディコンタクト領域１５よりも幅を狭め、幅広部Ｐｂはボディコンタクト領域１５よりも幅が充分広くなるように曲折させる。さらに隣接する幅狭部Ｐｎと幅広部Ｐｂを交互に配置する。
【００１０】
このパターンにおいてソース領域１３はトレンチ７に隣接して半導体基板表面に設けられる。曲折したストライプ状のトレンチ７の形状に沿って設けられるので、ソース領域１３は複数のセル間で連続しており、また幅狭部Ｐｎにはソース領域１３のみを設けるので、単位面積あたりのソース領域１３の周辺長が従来の格子状のパターンよりも増加する。つまり電流経路となる単位面積あたりのチャネル領域の幅（チャネル幅）を増やすことができるので、オン抵抗が低減できる。
【００１１】
このようなトレンチ型ＭＯＳＦＥＴでは、ストライプ状のパターンの利点である基板電位の安定化と、格子状のパターンの利点である単位面積あたりのチャネル領域の幅（チャネル幅）の増加による低オン抵抗化が実現できるものである（例えば、特許文献１参照。）。
【００１２】
【特許文献１】
特開２００２―５０７６０号公報
【００１３】
【発明が解決しようとする課題】
ところで、図５に、図４（Ｃ）に示した曲折パターンの、チップコーナー部分の平面図（図５（Ａ））およびその拡大図（図５（Ｂ））を示す。
【００１４】
図５（Ａ）の如く、多数のセル１８が配置される実動作領域３１は、ボディコンタクト領域１５を中心として線対称に曲折パターンのトレンチ７が配置される。チップ周辺部には、ゲートパッド電極（不図示）に接続するゲート連結電極３２が設けられる。トレンチ７は一部がゲート連結電極３２まで引き出されておりこれにより、トレンチ７内のゲート電極１２がゲート連結電極３２に接続する。
【００１５】
図５（Ｂ）の如く、例えばチップのコーナー部分に於いては、トレンチ７は直接ゲート連結電極３２に連結しない。つまりトレンチ７は隣り合うトレンチ７に連結して終端し、この連結を繰り返してゲート連結電極３２に接続する。しかし、曲折した形状のため、破線丸印で示すように、一部のトレンチ７は幅狭部Ｐｎで終端するものがある。そしてこのトレンチ内に設けられるゲート電極１２は、細く尖った形状になるため、この部分で電界集中を起こす問題があった。
【００１６】
【課題を解決するための手段】
本発明はかかる課題に鑑みてなされ、第１に、一導電型の半導体基板と、該基板の平面形状において曲折し前記基板周辺領域まで延在する複数のストライプ状のトレンチと、該トレンチ表面に設けた絶縁膜と、前記トレンチに埋め込まれた導電材料と、前記トレンチに隣接し前記基板表面に設けた一導電型領域と、隣り合う前記トレンチで挟まれる基板表面に設けられた幅広部および幅狭部とを具備し、前記周辺領域付近で隣り合う前記トレンチに連結する前記トレンチの終端部には全て幅広部を配置することにより解決するものである。
【００１７】
第２に、ドレイン領域となる一導電型の半導体基板と、該基板の平面形状において曲折し前記基板周辺領域まで延在する複数のストライプ状のトレンチと、前記基板表面に設けた逆導電型のチャネル層と、前記トレンチ表面に設けたゲート絶縁膜と、前記トレンチに埋め込まれたゲート電極と、前記トレンチに隣接し前記基板表面に設けた一導電型のソース領域と、隣り合う前記トレンチで挟まれる基板表面に設けられた幅広部および幅狭部と、前記幅広部に設けた逆導電型のボディコンタクト領域とを具備し、前記トレンチは、前記ゲート電極を引き出すゲート連結電極まで延在する第１のトレンチと、隣り合う前記トレンチに連結して終端する第２のトレンチからなり、該第２のトレンチの終端部は全て幅広部を配置することにより解決するものである。
【００１８】
また、前記第２のトレンチ内の前記ゲート電極は、隣り合う前記ゲート電極と連結して、前記ゲート連結電極に接続することを特徴とするものである。
【００１９】
また、前記トレンチの終端部に配置される前記幅広部は、他の幅広部よりも幅が広いことを特徴とするものである。
【００２０】
また、前記トレンチの延在方向の前記幅広部および幅狭部の前記ソース領域に連続してコンタクトするソース電極を設けることを特徴とするものである。
【００２１】
また、前記トレンチは平面形状において矩形波形状に曲折することを特徴とするものである。
【００２２】
【発明の実施の形態】
本発明の実施の形態を、トレンチ構造の半導体装置としてＮチャネル型パワーＭＯＳＦＥＴを例に、図１から図３を参照して詳細に説明する。
【００２３】
図１はトレンチ型パワーＭＯＳＦＥＴの平面図を示す。図１（Ａ）はチップ周辺領域の平面図であり、図１（Ｂ）は図１（Ａ）のＡ−Ａ線断面図である。尚、図１（Ａ）においては層間絶縁膜およびソース電極は省略してある。
【００２４】
トレンチ型ＭＯＳＦＥＴは、ドレイン領域２と、チャネル層４と、ストライプ状で曲折した複数のトレンチ７と、トレンチ７に埋め込まれたゲート電極１２と、トレンチ７に隣接し基板表面に設けたソース領域１３と、ソース領域１３に隣接して設けられたボディコンタクト領域１５とから構成される。
【００２５】
トレンチ７は、ストライプ状のパターンを半導体基板の平面形状において、矩形波形状に曲折したものであり、基板周辺領域まで延在して複数本形成される。このとき隣接するトレンチ７で挟まれる基板表面には曲折したトレンチのパターンにより幅広部Ｐｂと幅狭部Ｐｎが設けられる。ここで、後述するが、幅広部Ｐｂには、終端幅広部Ｐｂ１とそれ以外の幅広部Ｐｂ２とがある。
【００２６】
幅狭部Ｐｎはボディコンタクト領域１５よりも幅を狭めて例えば約１μｍとし、幅広部Ｐｂはボディコンタクト領域１５よりも幅が充分広くなるように曲折させて約６μｍとする。さらに隣接する幅狭部Ｐｎと幅広部Ｐｂを交互に配置する。トレンチ７内にはポリシリコンを埋設し、不純物を導入して低抵抗化を図ったゲート電極１２が設けられる。
【００２７】
ソース領域１３はトレンチ７に隣接して半導体基板表面に設けられる。曲折したストライプ状のトレンチ７の形状に沿って設けられるので、ソース領域１３は複数のセル間で連続している。また幅狭部Ｐｎにはソース領域１３のみを設けるため、この部分でソース領域を稼ぐことができ、単位面積あたりのソース領域１３の周辺長が従来の格子状のパターンよりも増加する。つまり電流経路となる単位面積あたりのチャネル領域の幅（チャネル幅）を増やすことができ、オン抵抗が低減できる。
【００２８】
ボディコンタクト領域１５は、基板の電位安定化のために曲折したトレンチ７の幅広部でソース領域１３に隣接して２μｍ四方程度の正方形またはそれに準じる形状に形成される。
【００２９】
図１（Ａ）の如く、チップ周辺には、実動作領域３１を囲んでゲートパッド電極に接続するゲート連結電極３２が設けられ、トレンチ７の一部をゲート連結電極３２まで延在してゲート電極１２が接続する（図３参照）。
【００３０】
つまり、チップのコーナー部を除く周辺領域では、トレンチ７の延在方向およびそれに直交する方向にトレンチ７が引き出され、チップの４辺でそれぞれゲート連結電極３２に連結する。一方、チップのコーナー部分に向って延在するトレンチ７はチップ周辺領域で終端し、直接ゲート連結電極３２に連結しない。
【００３１】
このように、トレンチ７は、延在方向に於いて直接ゲート連結電極に連結する第１のトレンチ７ａと、隣り合うトレンチに連結して終端する第２のトレンチ７ｂとからなる。第１のトレンチ７ａは、実動作領域３１外では曲折せず、平行なストライプパターンでゲート連結電極３２に直接連結する。第２のトレンチ７ｂは、例えばチップのコーナー部分では、隣り合う第１のトレンチ７ａまたは第２のトレンチ７ｂに連結して終端し、ゲート連結電極３２には直接連結しない。第２のトレンチ７ｂ内のゲート電極１２は、隣り合う第２のトレンチ７ｂ同士が連結を繰り返して第１のトレンチ７ａに接続することにより、ゲート連結電極３２と接続する。
【００３２】
また、トレンチ７延在方向に直交する方向でも、曲折したトレンチパターンから一部を引き出し、ゲート連結電極３２に連結させる。
【００３３】
図１（Ｂ）は、図１（Ａ）のＡ−Ａ線断面図を示す。半導体基板は、Ｎ＋型のシリコン半導体基板１の上にＮ−型のエピタキシャル層を積層したドレイン領域２からなる。チャネル層４は、半導体基板表面にＰ型のイオンを注入して設けられる。トレンチ７は、チャネル層４を貫通し、ドレイン領域２まで到達している。トレンチ７は曲折しており、隣接するトレンチ７により半導体基板表面には幅広部Ｐｂと幅狭部Ｐｎが設けられる。幅広部Ｐｂのチャネル層４表面にはトレンチ７に隣接してソース領域１３を設け、さらにソース領域１３に隣接してボディコンタクト領域１５を設ける。幅狭部Ｐｎのチャネル層４表面にはソース領域１３のみを設ける。さらに隣接する幅広部Ｐｂと幅狭部Ｐｎを交互に配置する。
【００３４】
ゲート酸化膜８は、トレンチ７内壁を熱酸化して駆動電圧に応じて数百Åの厚みに形成される。ゲート電極１２は、トレンチ７にポリシリコンを埋設して形成され、不純物を導入して低抵抗化を図る。
【００３５】
ソース領域１３はトレンチ７に隣接したチャネル層４表面にＮ＋型のイオンを注入して設けられる。また、図１（Ａ）の如く曲折したストライプ状のトレンチ７に沿って形成されるので、ソース領域１３は複数のセル１８間で連続しており、また幅狭部Ｐｎのソース領域１３により、従来のパターンに比べて単位面積あたりのソース領域１３の周辺長を稼ぐことができる。ソース領域１３の周辺長の増加は、電流経路であるチャネル幅を増加させることになる。
【００３６】
チャネル領域１４はソース領域１３からトレンチ７の深さ方向に、ゲート酸化膜８を介してゲート電極１２に隣接して形成される。ソース領域１３に沿って形成されるので、チャネル領域１４は複数のセル１８間で連続しており、１つのセル１８でボディコンタクト領域１５がコンタクト不良になる場合でもチャネル領域１４の電位が浮かず、ドレイン−ソース間のリーク電流を防げる。
【００３７】
ボディコンタクト領域１５は、トレンチ７によって設けられた幅広部のチャネル層４表面で隣接するソース領域１３の間にＰ＋型イオンを導入して幅２μｍ程度に形成され、基板の電位安定化のために用いられる。
【００３８】
ソース電極１７は全面にＡｌ−Ｓｉなどの金属膜をスパッタして形成する。層間絶縁膜１６は、各トレンチ毎に少なくともゲート電極１２上を覆うように酸化膜を堆積する。すなわち、隣り合うトレンチ間には層間絶縁膜１６が設けられず、ソース電極１７は、トレンチの延在方向の幅広部Ｐｂおよび幅狭部Ｐｎで連続して、ソース領域１３とコンタクトする。幅狭部Ｐｎにもソース領域１３は設けれらているため、ソース領域１３とソース電極１７とのコンタクト面積を稼ぐことができる。
【００３９】
一例をあげて比較すると、従来ではセル面積が格子状およびストライプ状ともに２５μｍ２で、トレンチ幅が１μｍであり、チャネル幅が格子状で１６μｍ、ストライプ状で１０μｍとなるので、単位面積あたりのチャネル幅は格子状の場合０．６４（１６／２５）μｍ、従来のストライプ状の場合が０．４（１０／２５）μｍとなる。本発明の実施の形態では、同一セルパターンが繰り返される実動作領域３１内では隣接する幅狭部Ｐｎのトレンチの間隔が１μｍ、セル面積３０μｍ２、トレンチ幅１μｍ、チャネル幅が２４μｍとなるので、単位面積あたりのチャネル幅は０．８（２４／３０）μｍとなる。
【００４０】
従って、本発明の実施の形態ではオン抵抗で有利であった格子状のパターンに比べて単位面積あたりのチャネル幅が２５％増加する。オン抵抗は単位面積あたりのチャネル幅に比例して低減するので、オン抵抗が２５％低減できることになる。
【００４１】
図２には、チップコーナー付近の拡大図および断面図を示す。図２（Ａ）はコーナー付近の平面図であり、図２（Ｂ）は、図２（Ａ）のＢ−Ｂ線断面図である。尚、実動作領域３１内の拡大図は、図４（Ｃ）と同様である。
【００４２】
図１（Ａ）、図２（Ａ）の如く、本実施形態においては、第２のトレンチ７ｂの終端部は全て幅広部Ｐｂ１が配置されるパターンとし、この終端部の幅広部Ｐｂ１を以下、終端幅広部と称する。この終端幅広部Ｐｂ１は、実動作領域３１内ではボディコンタクト領域１５を中心に線対称に配置されるトレンチ７ｂの曲折パターンを、終端部で変則的に変形させることにより設けられる。
【００４３】
つまり、従来隣り合う２本のトレンチにより形成されていた幅狭部Ｐｎは、この２本のトレンチ７ｂを１本に集束することで、終端幅広部Ｐｂ１の一部となる。すなわちこの終端幅広部Ｐｂ１の幅ｗ１は、実動作領域３１内の他の幅広部Ｐｂ２の幅ｗ２よりも、少なくとも幅狭部Ｐｎの分だけ広くなる。
【００４４】
この終端処理の方法として、例えば、従来の図５（Ｂ）のパターンにおいて単純に幅狭部Ｐｎを形成せずに幅広部Ｐｂ１で終端させ、終端の幅狭部Ｐｎがない構造にすることにより電界集中を緩和することができる。しかし、幅狭部Ｐｎを設けない部分では、トレンチ７の幅がその分広くなってしまい、この部分でゲート電極１２となるポリシリコンの埋設が不十分となり、ゲート−ドレイン間のショート等を引き起こす恐れがある。
【００４５】
そこで、本実施形態では幅狭部Ｐｎを含んだ終端幅広部Ｐｂ１を形成することで第２のトレンチ７ｂを終端させ、電界集中を緩和するものである。
【００４６】
このように、第２のトレンチ７ｂは全て終端幅広部Ｐｂ１を形成するように終端するので、従来の如く終端部に設けられる幅狭部Ｐｎがなくなる。これにより、ゲート電極の電界集中を抑制し、信頼性の高い半導体装置を提供できる。
【００４７】
図２（Ｂ）の如く、終端幅広部Ｐｂ１は、実動作領域３１内では、ボディコンタクト領域１５を中心に線対称に曲折していたトレンチ７のパターンを終端部のみ変則的に幅狭部Ｐｎを含むように設け、終端幅広部Ｐｂ１を形成する。すなわち終端幅広部Ｐｂ１の幅ｗ２は、実動作領域内の他の幅広部Ｐｂ２の幅ｗ１よりも大きいものとなる。ここで、ボディコンタクト領域１５の位置は、終端幅広部Ｐｂ１の中心に配置してもよい。
【００４８】
終端幅広部Ｐｂ１は、従来幅狭部Ｐｎとトレンチ７が形成されていた領域がソース領域１３となる。つまり、従来トレンチ７が設けられていた部分をソース領域１３として利用でき、ソース領域１３の面積を稼ぐことができる。
【００４９】
また、この部分のボディコンタクト領域１５の面積を大きくしても良い。ボディコンタクト領域１５の面積を大きくすることにより、アバランシェ耐量の劣化を防止できる。
【００５０】
ここで、図３（Ａ）にはチップの全体図を示し、図３（Ｂ）には実線の丸印部分の拡大図を示す。本実施形態のトレンチ７は、図の破線丸印で示すチップコーナー部分を除いて、チップの上下左右の４辺からゲート連結電極３２に接続する。このゲート連結電極３２は更にボンディングワイヤが圧着されるゲートパッド電極２０に接続する。上記の終端幅広部Ｐｂ１を設ける個所については、本実施形態では、チップコーナー部分を例に説明したが、パターンによってはこれ以外の個所にも設けられる。例えば、実線の丸印で示すゲートパッド電極２０が設けられるコーナー部等、ゲート連結電極３２に直接接続せずに終端するトレンチ７ｂには、終端幅広部Ｐｂ１を設けることとする。尚、終端幅広部Ｐｂ１を設けるのは、終端となる１つのセルのみでよい。
【００５１】
また、上述の如く、本発明の実施の形態ではＮチャネル型パワーＭＯＳＦＥＴを例に説明したが、導電型を逆にしたＭＯＳトランジスタにも適用できる。またバイポーラトランジスタとパワーＭＯＳＦＥＴを１チップ内にモノシリックで複合化したＩＧＢＴやＵ字型絶縁ゲートを利用した縦型パワー素子であるＧＴＢＴであっても同様に実施できる。
【００５２】
【発明の効果】
本発明に依れば、第１に、チップコーナー部を全て幅広部で終端させることにより、ゲート電極が細く尖ったパターンで配置されることがなくなるので、電界集中を抑制でき、信頼性の高い半導体装置を提供できる。
【００５３】
第２に、ソース電極は、トレンチに沿って幅広部、幅狭部のソース領域に連続してコンタクトするので、ソース領域とソース電極とのコンタクト面積を十分確保することができる。
【００５４】
第３に、トレンチを曲折させて幅広部と幅狭部を設けることにより、幅広部にソース領域とボディコンタクト領域を形成し、幅狭部にはソース領域のみを形成できる。つまり隣接するトレンチの間隔を幅狭部で従来より大幅に狭めることができ、総トレンチ長が増加する。
【００５５】
この結果、従来のパターンに比べて単位面積あたりのチャネル幅が増加し、オン抵抗が低減できる。具体的にはオン抵抗で有利であった従来の格子状のパターンに比べて単位面積あたりのチャネル幅が２５％増加するので、オン抵抗は２５％と大幅に低減できることになる。
【００５６】
第４に、曲折したストライプ状なのでソース領域およびチャネル領域は複数のセル間で連続しており、１つのセルでボディコンタクト領域がシリコンノジュールなどで塞がれた場合でもそのセルのチャネル領域の電位が浮かず、基板電位の安定性が向上する。従ってドレイン−ソース間のリーク電流を防ぐことができる。
【００５７】
第５に、本実施形態の曲折パターンであれば、同じデザインルールで単位面積あたりのチャネル幅を増やすことができる。
【００５８】
従って、基板の電位安定化と低オン抵抗化を兼ね備え、単位面積あたりのチャネル幅を向上させてもルール上有利となる絶縁ゲート型電界効果半導体装置を提供できる。
【図面の簡単な説明】
【図１】本発明の半導体装置を説明する（Ａ）平面図、（Ｂ）断面図である。
【図２】本発明の半導体装置を説明する（Ａ）平面図、（Ｂ）断面図である。
【図３】本発明の半導体装置を説明する平面図である。
【図４】従来の半導体装置を説明する平面図である。
【図５】従来の半導体装置を説明する平面図である。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that reduces on-resistance, improves stability of a substrate potential, and reduces leakage current between a drain and a source.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a semiconductor device as a switching element, a trench structure that can increase the number of cells per unit area of a chip as compared with a planar structure and reduce on-resistance is widely known.
[0003]
FIG. 4 shows a plan view of a conventional trench power MOSFET. The source electrode is omitted. The trench pattern in the planar shape of the trench type power MOSFET is generally a lattice shape shown in FIG. 4A or a stripe shape shown in FIG. However, the conventional trench has the following problems.
[0004]
First, in a pattern in which trenches are formed in a lattice shape as shown in FIG. 4A, one cell 18 is surrounded by the trenches 7 and has an island shape, and the body contact region 15 has a very small area for high integration. Formed.
[0005]
For example, in the case of an N-channel MOSFET, the body contact region 15 is formed by ion implantation of boron (B). Boron (B) has less implantation damage as compared with arsenic (As) or phosphorus (P), so that the growth of a native oxide film is small. That is, particles of silicon mixed in when the source electrode (Al) is sputtered are agglomerated in the portion where boron (B) is implanted, and silicon nodules easily grow. This silicon nodule may block the body contact region 15 having a small area. As a result, the potential of the channel region floats in one island-shaped cell 18, and a current leaks from the cell 18, which is considered to be a cause of a drain-source leak current.
[0006]
On the other hand, in the pattern in which the trenches 7 are formed in a stripe shape as shown in FIG. 4B, even if the body contact region 15 becomes defective in one cell 18, the channel region is continuous between the plurality of cells 18. Therefore, the substrate is not affected by the silicon nodules, and the potential of the substrate is more stable than when the trenches 7 are formed in a lattice shape. As a result, it is considered that no leakage current occurs between the drain and the source.
[0007]
However, in the pattern formed in a stripe shape, the spacing between the trenches 7 is designed according to the size of the body contact region 15 (approximately 2 μm in width). Can not. Therefore, the on-resistance is disadvantageous as compared with the case of forming in a lattice shape, and is not suitable for reducing the on-resistance.
[0008]
Therefore, a bent trench pattern as shown in FIG. 4C has been developed. In this trench MOSFET, a portion shown by a broken line is one cell 18 of the trench MOSFET.
[0009]
A plurality of trenches 7 are formed in a stripe shape on the surface of the semiconductor substrate. At this time, the trench 7 is bent so that the wide portion Pb and the narrow portion Pn are formed on the substrate surface sandwiched between the adjacent trenches 7. For example, the width of the narrow portion Pn is smaller than that of the body contact region 15, and the width of the wide portion Pb is bent so as to be sufficiently wider than the body contact region 15. Further, adjacent narrow portions Pn and wide portions Pb are alternately arranged.
[0010]
In this pattern, the source region 13 is provided on the surface of the semiconductor substrate adjacent to the trench 7. Since the source region 13 is provided along the shape of the bent striped trench 7, the source region 13 is continuous between a plurality of cells, and only the source region 13 is provided in the narrow portion Pn. The peripheral length of the region 13 is increased as compared with the conventional lattice pattern. That is, the width (channel width) of the channel region per unit area serving as a current path can be increased, so that the on-resistance can be reduced.
[0011]
In such a trench MOSFET, stabilization of the substrate potential, which is an advantage of the stripe pattern, and reduction of on-resistance due to an increase in the width of the channel region per unit area (channel width), which is an advantage of the lattice pattern, Can be realized (for example, see Patent Document 1).
[0012]
[Patent Document 1]
JP 2002-50760 A
[Problems to be solved by the invention]
FIG. 5 shows a plan view (FIG. 5A) of a chip corner portion of the bent pattern shown in FIG. 4C and an enlarged view thereof (FIG. 5B).
[0014]
As shown in FIG. 5A, in the actual operation region 31 in which a number of cells 18 are arranged, the trench 7 having a bent pattern is arranged line-symmetrically with the body contact region 15 as a center. A gate connection electrode 32 connected to a gate pad electrode (not shown) is provided at the periphery of the chip. The trench 7 is partially drawn out to the gate connection electrode 32, whereby the gate electrode 12 in the trench 7 is connected to the gate connection electrode 32.
[0015]
As shown in FIG. 5B, for example, at the corner of the chip, the trench 7 is not directly connected to the gate connection electrode 32. That is, the trench 7 is connected to the adjacent trench 7 and terminated, and this connection is repeated to connect to the gate connection electrode 32. However, due to the bent shape, some trenches 7 may be terminated at the narrow portions Pn as shown by the broken circles. Since the gate electrode 12 provided in the trench has a thin and sharp shape, there is a problem that electric field concentration occurs in this portion.
[0016]
[Means for Solving the Problems]
The present invention has been made in view of the above problems, and firstly, a semiconductor substrate of one conductivity type, a plurality of stripe-shaped trenches that bend in a planar shape of the substrate and extend to the peripheral region of the substrate, An insulating film provided, a conductive material embedded in the trench, a one conductivity type region provided on the substrate surface adjacent to the trench, and a wide portion and a width provided on the substrate surface sandwiched between the adjacent trenches The problem is solved by arranging a wide portion at the end of the trench connected to the adjacent trench near the peripheral region.
[0017]
Secondly, a semiconductor substrate of one conductivity type serving as a drain region, a plurality of stripe-shaped trenches bent in the planar shape of the substrate and extending to the peripheral region of the substrate, and a reverse conductivity type provided on the surface of the substrate. A channel layer, a gate insulating film provided on the surface of the trench, a gate electrode embedded in the trench, a source region of one conductivity type provided on the surface of the substrate adjacent to the trench, and sandwiched by the adjacent trench. A wide portion and a narrow portion provided on the substrate surface to be provided, and a body contact region of the opposite conductivity type provided in the wide portion, wherein the trench extends to a gate connection electrode extending from the gate electrode. A first trench and a second trench which is connected to and terminates with the adjacent trench, and the end portion of the second trench is entirely disposed by disposing a wide portion. Is shall.
[0018]
Further, the gate electrode in the second trench is connected to the adjacent gate electrode and connected to the gate connection electrode.
[0019]
The wide portion disposed at the terminal end of the trench is wider than other wide portions.
[0020]
Further, a source electrode is provided, which is in continuous contact with the source regions in the wide portion and the narrow portion in the extending direction of the trench.
[0021]
Further, the trench is bent in a rectangular wave shape in a planar shape.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3 by taking an N-channel type power MOSFET as an example of a semiconductor device having a trench structure.
[0023]
FIG. 1 shows a plan view of a trench type power MOSFET. 1A is a plan view of a chip peripheral region, and FIG. 1B is a cross-sectional view taken along line AA of FIG. 1A. Note that an interlayer insulating film and a source electrode are omitted in FIG.
[0024]
The trench MOSFET includes a drain region 2, a channel layer 4, a plurality of trenches 7 bent in a stripe shape, a gate electrode 12 buried in the trench 7, and a source region 13 provided on the substrate surface adjacent to the trench 7. And a body contact region 15 provided adjacent to the source region 13.
[0025]
The trench 7 is formed by bending a stripe pattern into a rectangular wave shape in the plane shape of the semiconductor substrate, and a plurality of trenches 7 are formed extending to the peripheral region of the substrate. At this time, a wide portion Pb and a narrow portion Pn are provided on the surface of the substrate sandwiched between the adjacent trenches 7 by a bent trench pattern. Here, as described later, the wide portion Pb includes a terminal wide portion Pb1 and other wide portions Pb2.
[0026]
The narrow portion Pn is narrower than the body contact region 15 to have a width of, for example, about 1 μm, and the wide portion Pb is bent to have a width sufficiently larger than the body contact region 15 to have a width of about 6 μm. Further, adjacent narrow portions Pn and wide portions Pb are alternately arranged. A gate electrode 12 is formed in the trench 7 by burying polysilicon and introducing impurities to reduce the resistance.
[0027]
Source region 13 is provided on the surface of the semiconductor substrate adjacent to trench 7. Since the source region 13 is provided along the shape of the bent stripe-shaped trench 7, the source region 13 is continuous between a plurality of cells. Further, since only the source region 13 is provided in the narrow portion Pn, a source region can be gained in this portion, and the peripheral length of the source region 13 per unit area is increased as compared with the conventional lattice pattern. That is, the width (channel width) of the channel region per unit area serving as a current path can be increased, and the on-resistance can be reduced.
[0028]
The body contact region 15 is formed in a wide portion of the trench 7 bent for stabilizing the potential of the substrate and adjacent to the source region 13 in a square of about 2 μm square or a shape similar thereto.
[0029]
As shown in FIG. 1A, a gate connection electrode 32 is provided around the chip and surrounding the actual operation area 31 and connected to the gate pad electrode. The electrodes 12 are connected (see FIG. 3).
[0030]
That is, in the peripheral region excluding the corners of the chip, the trenches 7 are drawn out in the direction in which the trenches 7 extend and in the direction orthogonal thereto, and are connected to the gate connection electrodes 32 on the four sides of the chip. On the other hand, the trench 7 extending toward the corner of the chip terminates in the peripheral region of the chip and is not directly connected to the gate connection electrode 32.
[0031]
As described above, the trench 7 includes the first trench 7a directly connected to the gate connection electrode in the extending direction and the second trench 7b connected to the adjacent trench and terminated. The first trench 7a is not bent outside the actual operation region 31 and is directly connected to the gate connection electrode 32 in a parallel stripe pattern. The second trench 7b is connected to the adjacent first trench 7a or the second trench 7b and terminated at, for example, a corner portion of the chip, and is not directly connected to the gate connection electrode 32. The gate electrode 12 in the second trench 7b is connected to the gate connection electrode 32 by connecting the adjacent second trenches 7b to the first trench 7a by repeating connection.
[0032]
In the direction orthogonal to the direction in which the trenches 7 extend, a part of the bent trench pattern is extracted and connected to the gate connection electrode 32.
[0033]
FIG. 1B is a cross-sectional view taken along the line AA of FIG. The semiconductor substrate includes a drain region 2 in which an N − -type epitaxial layer is stacked on an N + -type silicon semiconductor substrate 1. The channel layer 4 is provided by implanting P-type ions into the surface of the semiconductor substrate. The trench 7 penetrates the channel layer 4 and reaches the drain region 2. The trench 7 is bent, and a wide portion Pb and a narrow portion Pn are provided on the surface of the semiconductor substrate by the adjacent trench 7. A source region 13 is provided on the surface of the channel layer 4 of the wide portion Pb adjacent to the trench 7, and a body contact region 15 is provided adjacent to the source region 13. Only the source region 13 is provided on the surface of the channel layer 4 in the narrow portion Pn. Further, adjacent wide portions Pb and narrow portions Pn are alternately arranged.
[0034]
The gate oxide film 8 is formed by thermal oxidation of the inner wall of the trench 7 to have a thickness of several hundreds of mm according to the driving voltage. The gate electrode 12 is formed by burying polysilicon in the trench 7 and introducing an impurity to reduce the resistance.
[0035]
The source region 13 is provided by implanting N + -type ions into the surface of the channel layer 4 adjacent to the trench 7. 1A, the source region 13 is continuous between the plurality of cells 18, and is formed by the source region 13 in the narrow portion Pn. The peripheral length of the source region 13 per unit area can be increased as compared with the conventional pattern. Increasing the peripheral length of the source region 13 increases the channel width, which is a current path.
[0036]
The channel region 14 is formed adjacent to the gate electrode 12 via the gate oxide film 8 in the depth direction of the trench 7 from the source region 13. Since the channel region 14 is formed along the source region 13, the channel region 14 is continuous between the plurality of cells 18, and the potential of the channel region 14 does not float even when the body contact region 15 becomes defective in one cell 18. In addition, a leak current between the drain and the source can be prevented.
[0037]
The body contact region 15 is formed to a width of about 2 μm by introducing P + -type ions between adjacent source regions 13 on the surface of the wide channel layer 4 provided by the trench 7 and for stabilizing the potential of the substrate. Used for
[0038]
The source electrode 17 is formed by sputtering a metal film such as Al-Si on the entire surface. An oxide film is deposited on the interlayer insulating film 16 so as to cover at least the gate electrode 12 for each trench. That is, the interlayer insulating film 16 is not provided between the adjacent trenches, and the source electrode 17 contacts the source region 13 continuously at the wide portion Pb and the narrow portion Pn in the extending direction of the trench. Since the source region 13 is also provided in the narrow portion Pn, a contact area between the source region 13 and the source electrode 17 can be increased.
[0039]
By way of example, the cell area is 25 μm 2 for both the lattice and the stripe, the trench width is 1 μm, and the channel width is 16 μm for the lattice and 10 μm for the stripe. The width is 0.64 (16/25) μm in the case of a lattice, and 0.4 (10/25) μm in the case of a conventional stripe. In the embodiment of the present invention, in the actual operation region 31 where the same cell pattern is repeated, the interval between adjacent narrow portions Pn is 1 μm, the cell area is 30 μm 2 , the trench width is 1 μm, and the channel width is 24 μm. The channel width per unit area is 0.8 (24/30) μm.
[0040]
Therefore, in the embodiment of the present invention, the channel width per unit area is increased by 25% as compared with the lattice pattern which is advantageous in the on-resistance. Since the on-resistance decreases in proportion to the channel width per unit area, the on-resistance can be reduced by 25%.
[0041]
FIG. 2 shows an enlarged view and a cross-sectional view near the chip corner. FIG. 2A is a plan view near a corner, and FIG. 2B is a cross-sectional view taken along line BB of FIG. 2A. The enlarged view in the actual operation area 31 is the same as that in FIG.
[0042]
As shown in FIG. 1A and FIG. 2A, in the present embodiment, the end portions of the second trench 7b are all patterns in which the wide portions Pb1 are arranged, and the wide portions Pb1 of the end portions are hereinafter described. It is referred to as a wide end portion. The wide end portion Pb1 is provided in the actual operation region 31 by irregularly deforming the bent pattern of the trench 7b arranged line-symmetrically around the body contact region 15 at the end portion.
[0043]
In other words, the narrow portion Pn conventionally formed by two adjacent trenches becomes a part of the wide end portion Pb1 by converging the two trenches 7b into one. That is, the width w1 of the wide end portion Pb1 is wider than the width w2 of the other wide portion Pb2 in the actual operation area 31 by at least the width of the narrow portion Pn.
[0044]
As a method of the termination processing, for example, in the conventional pattern shown in FIG. 5B, by terminating at the wide portion Pb1 without simply forming the narrow portion Pn, a structure without the narrow portion Pn at the termination is provided. Electric field concentration can be reduced. However, in a portion where the narrow portion Pn is not provided, the width of the trench 7 is increased by that amount, and in this portion, the polysilicon serving as the gate electrode 12 is insufficiently buried, causing a short circuit between the gate and the drain. There is fear.
[0045]
Therefore, in the present embodiment, the second trench 7b is terminated by forming the wide end portion Pb1 including the narrow portion Pn, and the electric field concentration is reduced.
[0046]
As described above, all of the second trenches 7b are terminated so as to form the wide end portion Pb1, so that the narrow portion Pn provided at the end portion as in the related art is eliminated. Thus, the electric field concentration on the gate electrode is suppressed, and a highly reliable semiconductor device can be provided.
[0047]
As shown in FIG. 2B, in the actual operating region 31, the wide end portion Pb1 is formed by changing the pattern of the trench 7 which is bent line-symmetrically around the body contact region 15 in an irregular manner only in the end portion. To form a wide end portion Pb1. That is, the width w2 of the wide end portion Pb1 is larger than the width w1 of the other wide portion Pb2 in the actual operation area. Here, the position of the body contact region 15 may be arranged at the center of the wide end portion Pb1.
[0048]
In the wide end portion Pb1, the region where the narrow portion Pn and the trench 7 are formed in the past becomes the source region 13. That is, the portion where the trench 7 is provided conventionally can be used as the source region 13, and the area of the source region 13 can be increased.
[0049]
Further, the area of body contact region 15 in this portion may be increased. By increasing the area of the body contact region 15, deterioration of the avalanche resistance can be prevented.
[0050]
Here, FIG. 3A shows an overall view of the chip, and FIG. 3B shows an enlarged view of a solid circle portion. The trenches 7 of the present embodiment are connected to the gate connection electrode 32 from the four sides of the chip, except for the chip corners indicated by the broken circles in the figure. The gate connection electrode 32 is further connected to the gate pad electrode 20 to which the bonding wire is pressed. In the present embodiment, the location where the above-mentioned wide end portion Pb1 is provided has been described by taking the chip corner portion as an example. However, depending on the pattern, it may be provided in other locations. For example, a wide end portion Pb1 is provided in a trench 7b which terminates without being directly connected to the gate connection electrode 32, such as a corner portion where the gate pad electrode 20 indicated by a solid circle is provided. The wide end portion Pb1 may be provided only in one cell serving as the end.
[0051]
Further, as described above, in the embodiment of the present invention, an N-channel power MOSFET has been described as an example, but the present invention can also be applied to a MOS transistor having an inverted conductivity type. Further, the present invention can be similarly applied to an IGBT in which a bipolar transistor and a power MOSFET are monolithically combined in one chip or a GTBT which is a vertical power element using a U-shaped insulated gate.
[0052]
【The invention's effect】
According to the present invention, firstly, by terminating all the chip corners with the wide portions, the gate electrodes are not arranged in a thin and sharp pattern, so that the electric field concentration can be suppressed and the reliability is high. A semiconductor device can be provided.
[0053]
Second, since the source electrode is in continuous contact with the wide and narrow source regions along the trench, a sufficient contact area between the source region and the source electrode can be ensured.
[0054]
Third, by forming a wide portion and a narrow portion by bending the trench, a source region and a body contact region can be formed in the wide portion, and only the source region can be formed in the narrow portion. That is, the interval between adjacent trenches can be significantly reduced in the narrow portion compared with the conventional case, and the total trench length increases.
[0055]
As a result, the channel width per unit area increases as compared with the conventional pattern, and the on-resistance can be reduced. Specifically, the channel width per unit area is increased by 25% as compared with the conventional lattice-shaped pattern which is advantageous in the on-resistance, so that the on-resistance can be greatly reduced to 25%.
[0056]
Fourth, because of the bent stripe shape, the source region and the channel region are continuous between a plurality of cells, and even when the body contact region is closed by a silicon nodule or the like in one cell, the potential of the channel region of that cell is reduced. Does not float, and the stability of the substrate potential is improved. Therefore, leakage current between the drain and the source can be prevented.
[0057]
Fifth, with the bent pattern of the present embodiment, the channel width per unit area can be increased with the same design rule.
[0058]
Therefore, it is possible to provide an insulated gate field effect semiconductor device which has both the potential stabilization of the substrate and the low on-resistance and is advantageous in terms of rules even if the channel width per unit area is improved.
[Brief description of the drawings]
FIGS. 1A and 1B are a plan view and a cross-sectional view illustrating a semiconductor device of the present invention.
2A and 2B are a plan view and a cross-sectional view illustrating a semiconductor device of the present invention.
FIG. 3 is a plan view illustrating a semiconductor device of the present invention.
FIG. 4 is a plan view illustrating a conventional semiconductor device.
FIG. 5 is a plan view illustrating a conventional semiconductor device.

Claims (6)

一導電型の半導体基板と、
該基板の平面形状において曲折し前記基板周辺領域まで延在する複数のストライプ状のトレンチと、
該トレンチ表面に設けた絶縁膜と、
前記トレンチに埋め込まれた導電材料と、
前記トレンチに隣接し前記基板表面に設けた一導電型領域と、
隣り合う前記トレンチで挟まれる基板表面に設けられた幅広部および幅狭部とを具備し、
前記周辺領域付近で隣り合う前記トレンチに連結する前記トレンチの終端部には全て幅広部が配置されることを特徴とする半導体装置。A semiconductor substrate of one conductivity type;
A plurality of stripe-shaped trenches that bend in the planar shape of the substrate and extend to the substrate peripheral region;
An insulating film provided on the trench surface;
A conductive material embedded in the trench,
One conductivity type region provided on the substrate surface adjacent to the trench,
A wide portion and a narrow portion provided on the substrate surface sandwiched between the adjacent trenches,
The semiconductor device according to claim 1, wherein a wide portion is entirely disposed at an end portion of the trench connected to the trench adjacent to the peripheral region. ドレイン領域となる一導電型の半導体基板と、
該基板の平面形状において曲折し前記基板周辺領域まで延在する複数のストライプ状のトレンチと、
前記基板表面に設けた逆導電型のチャネル層と、
前記トレンチ表面に設けたゲート絶縁膜と、
前記トレンチに埋め込まれたゲート電極と、
前記トレンチに隣接し前記基板表面に設けた一導電型のソース領域と、
隣り合う前記トレンチで挟まれる基板表面に設けられた幅広部および幅狭部と、
前記幅広部に設けた逆導電型のボディコンタクト領域とを具備し、
前記トレンチは、前記ゲート電極を引き出すゲート連結電極まで延在する第１のトレンチと、隣り合う前記トレンチに連結して終端する第２のトレンチからなり、該第２のトレンチの終端部は全て幅広部が配置されることを特徴とする半導体装置。A semiconductor substrate of one conductivity type serving as a drain region,
A plurality of stripe-shaped trenches that bend in the planar shape of the substrate and extend to the substrate peripheral region;
A channel layer of a reverse conductivity type provided on the surface of the substrate,
A gate insulating film provided on the trench surface;
A gate electrode embedded in the trench;
A source region of one conductivity type provided on the substrate surface adjacent to the trench;
A wide portion and a narrow portion provided on the substrate surface sandwiched between the adjacent trenches,
A body contact region of the opposite conductivity type provided in the wide portion,
The trench includes a first trench that extends to a gate connection electrode from which the gate electrode is drawn, and a second trench that is connected to and terminates with the adjacent trench, and all the terminations of the second trench are wide. A semiconductor device, wherein a portion is disposed. 前記第２のトレンチ内の前記ゲート電極は、隣り合う前記ゲート電極と連結して、前記ゲート連結電極に接続することを特徴とする請求項２に記載の半導体装置。3. The semiconductor device according to claim 2, wherein the gate electrode in the second trench is connected to the adjacent gate electrode and connected to the gate connection electrode. 前記トレンチの終端部に配置される前記幅広部は、他の幅広部よりも幅が広いことを特徴とする請求項１または請求項２のいずれかに記載の半導体装置。3. The semiconductor device according to claim 1, wherein the wide portion disposed at the end of the trench is wider than other wide portions. 4. 前記トレンチの延在方向の前記幅広部および幅狭部の前記ソース領域に連続してコンタクトするソース電極を設けることを特徴とする請求項１または請求項２のいずれかに記載の半導体装置。3. The semiconductor device according to claim 1, wherein a source electrode is provided that is in continuous contact with the source regions of the wide portion and the narrow portion in the extending direction of the trench. 4. 前記トレンチは平面形状において矩形波形状に曲折することを特徴とする請求項１または請求項２のいずれかに記載の半導体装置。3. The semiconductor device according to claim 1, wherein the trench is bent into a rectangular wave shape in a planar shape. 4.
JP2003068102A 2003-03-13 2003-03-13 Semiconductor device Withdrawn JP2004281524A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007015500A1 (en) * 2005-08-03 2007-02-08 Sharp Kabushiki Kaisha Trench type misfet
JP2011061064A (en) * 2009-09-11 2011-03-24 Mitsubishi Electric Corp Semiconductor device for electric power
JP2012174726A (en) * 2011-02-17 2012-09-10 Semiconductor Components Industries Llc Insulated gate type semiconductor device
US8350322B2 (en) 2009-11-06 2013-01-08 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2015149402A (en) * 2014-02-06 2015-08-20 株式会社デンソー semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007015500A1 (en) * 2005-08-03 2007-02-08 Sharp Kabushiki Kaisha Trench type misfet
JP2011061064A (en) * 2009-09-11 2011-03-24 Mitsubishi Electric Corp Semiconductor device for electric power
US8350322B2 (en) 2009-11-06 2013-01-08 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2012174726A (en) * 2011-02-17 2012-09-10 Semiconductor Components Industries Llc Insulated gate type semiconductor device
US8981471B2 (en) 2011-02-17 2015-03-17 Semiconductor Components Industries, Llc Insulated gate semiconductor device
US10121887B2 (en) 2011-02-17 2018-11-06 Semiconductor Components Industries, Llc Insulated gate semiconductor device and method
JP2015149402A (en) * 2014-02-06 2015-08-20 株式会社デンソー semiconductor device

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