JP2015149402A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is easy to increase avalanche resistance while limiting an increase in on-resistance.SOLUTION: A semiconductor device 1 comprises: a semiconductor substrate 3 covered with a conductive layer 26 on a surface 3a side; and a connection member connected to a part of a top face 26a of the conductive layer 26. The semiconductor device comprises a high resistance part 5 with a structure having higher avalanche resistance than an outside part, which is arranged in a predetermined region of at least either of an internal position of a directly-below region AR located directly below a connection part 30a of the connection member 30 or a position adjacent to a peripheral part of the directly-below region AR and on the side farther from the directly-below region AR than the predetermined region.

Description

  The present invention relates to a semiconductor device.

  Conventionally, power MOSFETs or IGBTs having a so-called trench gate structure have been used. For example, Patent Document 1 discloses a trench gate type semiconductor device configured as a power semiconductor device. In this semiconductor device, a source region 4 is selectively formed on the surface of the base region 3, and a trench is provided so as to penetrate the source region 4 and the base region 3 to reach the drift region. A gate electrode 7 is buried in the trench.

JP 10-173170 A

  By the way, this type of semiconductor device is desired to have low on-resistance and high avalanche resistance as characteristics. However, there is generally a trade-off relationship between on-resistance and avalanche resistance. For example, if the trench spacing is narrowed and the channel density is increased, the on-resistance can be reduced, but the parasitic transistor is easily turned on. For this reason, there is a problem that the avalanche resistance tends to be low. Conversely, if the avalanche resistance is increased by widening the trench interval, the channel density is reduced correspondingly and the on-resistance is increased.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device that can easily increase the avalanche resistance while suppressing an increase in on-resistance.

The present invention includes a semiconductor substrate (3) having a predetermined surface (3a) and a back surface (3b), and having a plurality of element regions (Ca) on at least the surface (3a) side,
A conductive layer (26) covering the surface (3a) side of the semiconductor substrate (3);
A connection member (30) having conductive connection portions (30a, 50a) disposed above the conductive layer (26) and electrically connected to a part of the upper surface portion (26a) of the conductive layer (26). , 50)
With
The conductive layer (26) is provided with contact portions (26b) connected to the element regions (Ca) of the semiconductor substrate (3),
In the semiconductor substrate (3), the connection member (30, 50) is adjacent to an internal position of a region (AR) immediately below the connection portion (30a) or a peripheral portion of the region (AR) directly below. The high-tolerance part (5) having a structure in which the avalanche resistance is higher than that of the outer part (6) disposed on the side farther from the region (AR) immediately below the predetermined area. Is provided.

According to the first aspect of the present invention, in the semiconductor substrate, the semiconductor substrate is disposed outside at least one of the internal position of the region directly below the connection portion of the connection member and the position adjacent to the peripheral portion of the region directly below. A high withstand portion having a structure having a higher avalanche withstand capability than the portion to be formed (outer portion) is provided.
When a surge voltage is generated during or immediately after an OFF operation with an inductive load, and the surge voltage is applied to the semiconductor device, there is a concern that the surge current may be concentrated particularly in the region immediately below the connection portion of the connection member. . On the other hand, in the present invention, since a high withstand portion having a relatively increased avalanche withstand is provided in the vicinity of the region immediately below the connecting portion of the connecting member where current tends to concentrate, the off operation with an inductive load is performed. Even if a surge voltage is generated, destruction or the like due to the surge voltage or the like is less likely to occur in the vicinity of the region directly under concern. In the present invention, since the high withstand portion is selectively provided in the region where surge current concentration is a concern, all the regions have the same structure as the high withstand portion while effectively taking surge countermeasures. Compared with, it becomes easy to suppress on-resistance.

FIG. 1 is a plan view schematically illustrating the semiconductor device according to the first embodiment. FIG. 2 is a perspective view conceptually showing the semiconductor device of FIG. FIG. 3 is a front view conceptually showing the semiconductor device of FIG. FIG. 4 is a cross-sectional view conceptually illustrating a part of the cross-sectional configuration of the semiconductor device of FIG. 1 cut in the thickness direction. FIG. 5 is a cross-sectional view conceptually illustrating a part of a cross-sectional configuration obtained by cutting the semiconductor device of FIG. 1 in the horizontal direction. FIG. 6 is an explanatory diagram illustrating a part of FIG. 5 in an enlarged manner. FIG. 7 is a conceptual diagram conceptually showing a part of the semiconductor device of FIG. 1, and is an explanatory diagram for explaining a region directly under the connecting member. FIG. 8 is a cross-sectional view conceptually illustrating a part of a cross-sectional configuration in which the semiconductor device according to the second embodiment is cut in the horizontal direction. FIG. 9 is a cross-sectional view conceptually illustrating a part of a cross-sectional configuration in which the semiconductor device according to the second embodiment is cut in the thickness direction. FIG. 10 is a cross-sectional view conceptually illustrating a part of a cross-sectional configuration in which the semiconductor device according to the third embodiment is cut in the horizontal direction. FIG. 11 is a cross-sectional view conceptually illustrating a part of a cross-sectional configuration in which the semiconductor device according to the third embodiment is cut in the thickness direction. FIG. 12 is a cross-sectional view conceptually illustrating a part of a cross-sectional configuration in which the semiconductor device according to the fourth embodiment is cut in the horizontal direction. FIG. 13 is a cross-sectional view conceptually illustrating a part of a cross-sectional configuration in which the semiconductor device according to the fourth embodiment is cut in the thickness direction. FIG. 14 is a cross-sectional view conceptually illustrating a part of a cross-sectional configuration of the semiconductor device according to the fifth embodiment cut in the horizontal direction. FIG. 15 is a cross-sectional view conceptually illustrating a part of a cross-sectional configuration in which the semiconductor device according to the fifth embodiment is cut in the thickness direction. FIG. 16 is a cross-sectional view conceptually illustrating a part of a cross-sectional configuration in which the semiconductor device according to the sixth embodiment is cut in the horizontal direction. FIG. 17 is an enlarged view showing a part of FIG. FIG. 18 is a cross-sectional view conceptually illustrating a part of a cross-sectional configuration in which the semiconductor device according to the sixth embodiment is cut in the thickness direction. FIG. 19 is a cross-sectional view conceptually illustrating a part of a cross-sectional configuration of the semiconductor device according to the seventh embodiment cut in the horizontal direction. FIG. 20 is a cross-sectional view conceptually illustrating a part of a cross-sectional configuration in which the semiconductor device according to the eighth embodiment is cut in the thickness direction. FIG. 21 is an explanatory view illustrating Example 1 of the semiconductor device according to another embodiment, and is a perspective view conceptually illustrating a configuration using a wire pad as a connection member. FIG. 22 is a plan view schematically illustrating Example 2 of the semiconductor device according to another embodiment, and is a diagram illustrating a configuration in which corner portions of the semiconductor device of FIG. 1 are curved. FIG. 23 is a perspective view conceptually showing the semiconductor device of FIG.

[First Embodiment]
Hereinafter, a first embodiment of the present invention will be described in detail.
(1. Basic structure of semiconductor device)
As shown in FIG. 1, the semiconductor device 1 of the present invention has a rectangular appearance in a plan view, for example. As shown in FIGS. 1, 2, and 3, a conductive copper is formed on the upper surface of the semiconductor chip 2. Clips 30 are joined and electrically connected to each other.

  The semiconductor device 1 is configured as a trench gate type MOSFET. As shown in FIG. 4, in the semiconductor device 1, a trench portion 19 for embedding the gate electrode 23 is formed on the surface 3a (first main surface) side of the semiconductor substrate 3 having a predetermined surface 3a and a back surface 3b. A trench gate structure is formed.

  In this specification, the thickness direction of the semiconductor substrate 3 is a γ direction, and in FIG. 4, this γ direction is indicated by an arrow. Further, a predetermined direction orthogonal to the thickness direction of the semiconductor substrate 3 is defined as a lateral direction, this lateral direction is defined as an α direction, and in FIG. 4 and FIG. 5, this α direction is indicated by an arrow. In addition, a direction orthogonal to the thickness direction and the horizontal direction is a vertical direction, this vertical direction is a β direction, and in FIG. 5, this β direction is indicated by an arrow. 4 is a cross-sectional view schematically showing a cut surface at the position A2-A2 in FIG. 5, and this cut surface is a cut surface parallel to the α direction (lateral direction) and the γ direction (thickness direction). It has become. FIG. 5 is a cross-sectional view schematically showing a cut surface at the position A1-A1 in FIG. 4, and this cut surface is parallel to the α direction (lateral direction) and the β direction (longitudinal direction). The cut surface.

  As shown in FIG. 4 and the like, the semiconductor device 1 is mainly connected to the semiconductor substrate 3 having a predetermined surface 3a and a back surface 3b, a source electrode 26 covering the surface 3a side of the semiconductor substrate 3, and the source electrode 26. The copper clip 30 is provided.

  The semiconductor substrate 3 includes, for example, an N + type silicon substrate having a drain layer on the back side and an N− type drift layer for maintaining a withstand voltage thereon, and a P type base region (P type body region) on the surface side thereof. It is the composition provided with. In this specification, the N conductivity type corresponds to an example of the first conductivity type, and the P conductivity type corresponds to an example of the second conductivity type.

  The N − -type drift layer 15 is a portion corresponding to an example of a first semiconductor layer of the first conductivity type, and the trench portion 19 starts from a position shallower than a bottom portion of a trench portion 19 described later (that is, a position on the surface 3a side). It is formed so as to extend to a position deeper than the bottom of (i.e., the position on the back surface 3b side). An N + type drain layer 13 having an impurity concentration higher than that of the N− type drift layer 15 is provided on the back surface 3b side of the N− type drift layer 15, and the outer surface of the N + type drain layer 13 is a semiconductor. The back surface 3 b of the substrate 3 is configured. A drain electrode 11 made of a conductive layer such as an aluminum film is formed to cover the back surface 3b.

  A P-type body layer (base layer) 17 is formed on the surface 3 a side of the N − -type drift layer 15. The P type body layer 17 corresponds to an example of a second conductivity type second semiconductor layer, and is formed above the N − type drift layer 15 at least along the trench portion 19. The P-type body layer 17 functions as a channel. In this configuration, the P-type body layer is formed over the entire area between the trenches so as to fill the region partitioned by the trench portion 19 inside the semiconductor substrate 3. 17 are formed.

  Further, an N + type source layer 25 and a P + type contact layer 18 are provided on the surface 3a side of the P type body layer 17. The P + type contact layer 18 corresponds to an example of a second conductivity type fourth semiconductor layer, has a higher impurity concentration than the P type body layer 17, and is adjacent to the P type body layer 17. In addition, it is formed adjacent to a source electrode 26 described later. The P + type contact layer 18 is disposed in a surface layer portion of each cell portion Ca described later, surrounded by a trench portion 19 that forms a peripheral portion of each cell portion Ca. It is formed on the center side away from the surrounding trench portions 19 to some extent. The contact resistance is lowered by such a contact layer 18.

  An N + type source layer 25 is formed in the vicinity of the peripheral edge of the P + type contact layer 18. The N + type source layer 25 is a portion corresponding to an example of the first conductivity type third semiconductor layer, and on the surface 3 a side of the semiconductor substrate 3, above the P type body layer 17 and at the upper end of the trench portion 19. It is formed at a position adjacent to. The N + type source layer 25 is disposed on the surface layer side of each cell portion Ca to be described later, surrounded by a trench portion 19 that forms the peripheral portion of each cell portion Ca. Specifically, in each surface layer portion of each cell portion Ca, each N + type source layer 25 is annularly arranged in a configuration adjacent to the inside of the trench portion 19 forming the peripheral portion of each cell portion Ca. In addition, the contact layer 18 is provided in a form adjacent to the inner side (center side of each cell portion Ca) on the lower side of each N + type source layer 25 arranged annularly in each cell portion Ca in this way.

  In addition, a trench portion 19 is formed in the semiconductor substrate 3 so as to penetrate the body layer 17 from the front surface 3a side. As shown in FIGS. 5 and 6, the trench portion 19 includes a plurality of vertical trenches 19a extending in the vertical direction (β direction) and a plurality of horizontal trenches 19b extending in the horizontal direction (α direction). Yes. The vertical trench 19a is configured as a vertical groove, and is connected to the horizontal trench 19b at a plurality of positions. Moreover, the horizontal trench 19b is comprised as a groove | channel of a horizontal direction, and is connected with the vertical trench 19a in the several position. The vertical trenches 19a and the horizontal trenches 19b divide the surface layer portion on the surface 3a side of the semiconductor substrate 3 into a plurality of regions (regions having a square shape in plan view or a rectangular shape in plan view). 5 and 6, the region of the trench portion 19 is schematically shown by cross hatching.

  As shown in FIGS. 4, 5, and 6, the inside of the semiconductor substrate 3 is partitioned into a plurality of cell portions Ca (the cell portions Ca correspond to an example of an element region) by a trench portion 19. As described above, the semiconductor substrate 3 is formed with a plurality of vertical trenches 19a and a plurality of horizontal trenches 19b, and is a rectangular cell in plan view with a configuration separated by the vertical trenches 19a and the horizontal trenches 19b. A plurality of portions Ca are formed. Specifically, the position of each line L1 passing through the center position in the horizontal direction (width direction) of the region W of each vertical trench 19a is the vertical boundary of each cell portion Ca, and the region H of each horizontal trench 19b The position of each line L2 passing through the center position in the vertical direction (width direction) is the boundary in the horizontal direction of each cell portion Ca. In the semiconductor substrate 3, each region (region having a rectangular shape in plan view) divided by the boundaries L1 and L2 is each cell portion Ca. Each cell portion Ca functions as a MOSFET cell, and any cell portion Ca can pass a current between the drain electrode 11 and the source electrode 26 by applying a gate voltage. Yes.

A gate insulating film 21 made of an oxide film such as SiO ₂ is formed along the entire inner wall surface of the trench portion 19 formed in a groove shape. Further, a gate electrode 23 is formed inside the trench portion 19 inside the gate insulating film 21. Further, the gate electrode 23 is covered with a gate insulating film 21 and further covers the gate insulating film 21 disposed on the gate electrode 23, and an insulating film such as a PSG (Phosphorus-Silicate Glass) film. 24 is formed. Thus, between the gate electrode 23 in the trench portion 19 and the semiconductor substrate 3 (specifically, each of the N + type source layer 25, the P type body layer 17, the N− type drift layer 15 and the gate electrode) 23), the insulating property is maintained by interposing the gate insulating film 21, and the insulating property is maintained by interposing the gate insulating film 21 and the insulating film 24 between the gate electrode 23 and the source electrode 26. It is kept.

  A source electrode 26 is formed so as to cover the surface 3 a side of the semiconductor substrate 3. The source electrode 26 is a portion corresponding to an example of a conductive layer, and is in contact with each of the N + type source layer 25 and the contact layer 18. The source electrode 26 is electrically connected to the N + type source layer 25 and the contact layer 18. In the source electrode 26, a portion connected to each cell portion Ca of the semiconductor substrate 3 (specifically, a portion contacting each of the N + type source layer 25 and the contact layer 18 of each cell portion Ca) is in contact. This is a portion 26b.

  Although not shown in FIGS. 2 and 3 and the like, a gate pad 23a is provided on the upper surface of the semiconductor device 1 as shown in FIG. The gate pad 23 a is electrically connected to the gate electrode 23 through a gate wiring (not shown) provided in the semiconductor device 1.

(2. Configuration of connecting member and region immediately below)
Next, the connection member and the region immediately below will be described.
As shown in FIG. 1 and the like, the semiconductor device 1 is provided with a copper clip 30 as a connecting member. The copper clip 30 is disposed above the source electrode 26 and includes a conductive connection portion 30 a that is electrically connected to a part of the upper surface portion 26 a of the source electrode 26. And this connection part 30a is electrically connected with wiring (For example, unillustrated lead frame etc.) which is not illustrated. As described above, the copper clip 30 plays a role of electrically connecting a wiring (not shown) and the source electrode 26.

  The connection portion 30a of the copper clip 30 constitutes a part or the whole of the lower surface portion of the copper clip 30, and is connected to the upper surface portion 26a of the source electrode 26 so as to be electrically connected to each other. As shown in FIGS. 1, 2, and 7, the portion connected to the source electrode 26 in the copper clip 30 (that is, the connecting portion 30a joined to the upper surface portion 26a) includes corner portions 31a, 31b, 31c, and 31d. It has an outer shape. Specifically, the outer shape of the connection portion 30a is square or rectangular, and the outer shape of the joint surface between the upper surface portion 26a and the connection portion 30a is also square or rectangular.

  As conceptually shown in FIG. 7, the region AR immediately below is a region located directly below the connection portion 30a (portion connected to the source electrode 26 in the copper clip 30) in the semiconductor substrate 3, as shown in FIG. This is a region that overlaps with the connecting portion 30a when viewed in plan view. In FIG. 7, the outer edge frame of the immediately lower area AR is conceptually indicated by a thick line, and a rectangular parallelepiped area surrounded by such a thick line frame is the directly below area AR.

(3. Specific configuration of each cell part)
Next, a specific configuration of each cell unit will be described in detail.
As shown in FIGS. 4 and 5, in the semiconductor device 1, the high-tolerance portion 5 having a stripe structure is provided in the semiconductor substrate 3 immediately below the connection portion 30 a of the copper clip 30. In the present specification, the region where the high withstand portion is provided in the semiconductor substrate corresponds to the “predetermined region”. For example, in the configuration of the first embodiment, the region where the high withstand portion 5 is provided corresponds to a “predetermined region”. The high withstand portion 5 has a configuration in which cell portions (high withstand cell portion C1) having a predetermined structure in which the avalanche withstand capability is relatively increased among a plurality of cell portions Ca constituting the semiconductor device 1 are arranged. ing. On the other hand, the low on-resistance portion is located at a position outside the connection portion 30a in the semiconductor substrate 3 and at a position outside the high resistance portion 5 (a position outside the high resistance portion 5 when the semiconductor substrate 3 is viewed in plan view). 6 is provided. The low on-resistance portion 6 has a configuration in which cell portions (low withstand cell portion C2) having a channel density larger than that of the high withstand cell portion C1 among the plurality of cell portions Ca constituting the semiconductor device 1 are arranged. The on-resistance is suppressed. In the present specification, the portion of the semiconductor substrate that is further away from the region immediately below the high withstand portion corresponds to the “outer portion”. For example, in the configuration of the first embodiment, in the semiconductor substrate 3, the high withstand portion 5 is disposed in the region AR immediately below the connection portion 30a, and the high withstand portion 5 is thus disposed in the immediately below region AR. In this case, the “outer portion” is arranged on the side farther from the region AR directly below the high-tolerance portion 5 (specifically, the side farther from the central portion of the region AR just below the high-tolerance portion 5). As shown in FIG. 5, a part may be adjacent to the peripheral edge of the immediate area AR. This “outer part” is constituted by the low on-resistance part 6.

  In this configuration, as shown in FIG. 5, the entire interior of the immediate area AR is configured by the high-resistance cell portion C1 having a predetermined structure and functions as the high-resistance portion 5. On the other hand, outside the direct region AR, there is provided a low on-resistance portion 6 constituted by the low withstand cell portion C2 so as to surround the direct region AR.

  As shown in FIG. 5, the high-resistance cell portion C <b> 1 constituting the high-resistance portion 5 has a wider area than the low-resistance cell portion C <b> 2 constituting the low on-resistance portion 6. In the example of FIG. 5, each high withstand cell portion C <b> 1 has a longitudinal configuration extending in the lateral direction so as to extend from one lateral end to the other end of the immediate area AR. Then, such a long high-resistance cell portion C1 is arranged in parallel in the region immediately below. In this configuration, the direction in which each high-resistance cell portion C1 extends is the horizontal direction, and the direction in which the plurality of high-resistance cell portions C1 are arranged is the vertical direction. The length of the high withstand cell portion C1 is about several times the length of the low withstand cell portion C2. The width of the high withstand cell portion C1 is approximately the same as the width of the low withstand cell portion C2. Here, the longitudinal direction of each cell portion Ca when the semiconductor substrate 3 is viewed in plan is the length direction of the cell portion, and the short direction of each cell portion Ca is the width direction of the cell portion.

  The density of the semiconductor region connected to the contact portion 26b in each high withstand cell portion C1 is higher than the density of the semiconductor region connected to the contact portion 26b in each low withstand cell portion C2. That is, in the high withstand portion 5, the ratio of the contact region occupying the entire high withstand portion 5 (the connection region of the semiconductor substrate 3 connected to the contact portion 26 b in the high withstand portion 5) accounts for the entire low on-resistance portion 6. It is larger than the ratio of the region (connection region of the semiconductor substrate 3 connected to the contact portion 26b in the low on-resistance portion 6).

  Here, the area ratio will be described. In the high-resistance cell portion C1 constituting the high-resistance portion 5 of the plurality of cell portions Ca, the entire area X1 of the high-resistance cell portion C1 when viewed in plan in the thickness direction of the semiconductor substrate 3 (that is, the high resistance) The ratio of the contact area Y1 at which the contact layer 18 is in contact with the source electrode 26 in the high withstand cell portion C1 with respect to the cell portion C1 is an orthographic projection on the virtual plane parallel to the vertical and horizontal directions. 1 area ratio Y1 / X1. In the low-resistance cell portion C2 constituting the low on-resistance portion 6 of the plurality of cell portions Ca, the entire area X2 of the low-resistance cell portion C2 when viewed in plan in the thickness direction of the semiconductor substrate 3 (ie, The area of the figure in which the low-resistance cell portion C2 is orthographically projected onto a virtual plane parallel to the vertical and horizontal directions) is a contact area Y2 where the contact layer 18 contacts the source electrode 26 in the low-resistance cell portion C2. The ratio is the second area ratio Y2 / X2. When defined in this way, in the semiconductor device 1 of this configuration, the first area ratio Y1 / X1 is larger than the second area ratio Y2 / X2. That is, the high-resistance cell portion C1 has a contact area per unit area (contact area where the contact layer 18 contacts the source electrode 26), while the contact area per unit area in the low-resistance cell portion C2 (the contact layer 18 is the source). Therefore, the avalanche resistance can be increased more easily than the low-resistance cell portion C2.

  In other words, the low withstand cell portion C2 of the low on-resistance portion 6 has a relatively low avalanche resistance than the high withstand cell portion C1 of the high withstand portion 5. However, the low withstand cell portion C2 of the low on-resistance portion 6 has a narrower pitch than the high withstand cell portion C1, is finer than the high withstand cell portion C1, and has a higher channel density (cell) than the high withstand cell portion C1. Since the ratio of the channel region to the whole) is large, the on-resistance can be suppressed more easily than the high withstand cell portion C1. More specifically, the density of the trench portion 19 in the low on-resistance portion 6 is larger than the density of the trench portion 19 in the high withstand voltage portion 5, and the channel region (body layer formed along the trench portion 19 is formed. 17, the density of the portion adjacent to the trench portion 19 is also higher in the low on-resistance portion 6, so that the low on-resistance portion 6 can lower the channel resistance per unit area and can easily suppress the on-resistance.

As described above, in the present configuration, in the semiconductor substrate 3, the high-tolerance portion 5 having the cell portion having a predetermined structure is provided at the internal position of the region AR directly below the connection portion 30 a of the copper clip 30. .
When a surge voltage is generated during or immediately after the off operation with an inductive load, and the surge voltage is applied to the semiconductor device 1, the surge current may be concentrated particularly near the region immediately below the connection portion 30 a of the copper clip 30. Concerned. On the other hand, in this configuration, since the high-tolerance part 5 with relatively increased avalanche resistance is provided in the vicinity of the region immediately below the connection part 30a where current tends to concentrate, the off-operation with an inductive load is performed. Even if a surge voltage is generated, breakdown is less likely to occur in the vicinity of the region directly under concern.
Furthermore, in this configuration, a cell portion (low-resistance cell portion C2) having a channel density larger than that of the high-resistance portion 5 is arranged at a position outside the region AR directly below the connection portion 30a and outside the high-resistance portion 5. An on-resistance portion 6 is provided, and is made separately from the high withstand portion 5. For this reason, compared with the case where all make the same cell structure as the high withstand weight part 5, ON resistance can be reduced reliably. Further, since the low on-resistance portion 6 is provided in a region where current concentration is relatively easily relaxed (a position outside the region AR directly below the connection portion 30a and outside the high withstand portion 5), the low on-resistance portion 6 is turned on in this way. Even if a region where the resistance can be reduced is provided, breakdown is unlikely to occur in this region (low on-resistance portion 6).

  In the configuration of FIG. 5 and the like, the configuration in which the high withstand portion 5 is provided at the internal position of the region AR directly below the connection portion 30a is illustrated, but the configuration is not limited to this example. For example, even if it is outside the direct area AR, if it is located near the direct area AR (that is, near the periphery of the direct area AR), there is a concern about current concentration, so that it is close to the direct area AR outside the direct area AR. The same effect can be obtained even if the high-tolerance portion 5 is provided at a position (for example, a position adjacent to the peripheral edge of the region AR immediately below). In this case, the low on-resistance portion 6 corresponding to the “outer portion” may be disposed on the side farther from the region AR than the high withstand portion 5 disposed adjacent to the peripheral portion of the region AR.

  Further, the low on-resistance part 6 corresponding to the “outer part” is only required to be disposed on the side farther from the direct area AR than the high withstand part 5 at least outside the direct area AR, and is equivalent to the low on-resistance part 6. The cell portion having the configuration may be partially arranged in the region AR immediately below.

  Also, in this configuration, current concentration is achieved by a simple and easy-to-manufacture configuration in which a cell portion is separately formed in a region where current concentration is particularly a concern in the same semiconductor substrate and an external region, and the area ratio of the contact region is changed. Thus, it is possible to effectively increase the avalanche resistance in a region where there is a concern, and to suppress an increase in the on-resistance of the entire cell.

  Moreover, in this structure, the connection part 30a connected to the source electrode 26 in the copper clip 30 has an outer shape including corner parts 31a, 31b, 31c, 31d, and the corner parts 31a, 31b, A high withstand portion 5 is provided in the vicinity of a position directly below 31c and 31d. In the direct region AR, current is particularly likely to concentrate near the positions directly below the corners 31a, 31b, 31c, and 31d. Therefore, if the withstand capability at least near the positions directly below the corners 31a, 31b, 31c, and 31d is increased, the element The overall tolerance can be effectively increased. The positions immediately below the corner portions 31a, 31b, 31c, and 31d are positions on a straight line in the thickness direction (γ direction) passing through the corner positions of the apexes of the corner portions 31a, 31b, 31c, and 31d in the semiconductor substrate 3. is there. In the example of FIGS. 5 and 6, the positions directly below the corners 31 a, 31 b, 31 c, and 31 d on the upper surface portion of the semiconductor substrate 3 are conceptually indicated by symbols B <b> 1, B <b> 2, B <b> 3, and B <b> 4.

  In the configuration described above, as shown in FIG. 5, an example is shown in which the high withstand portion 5 is provided at the position immediately below the corners 31 a, 31 b, 31 c, 31 d in the semiconductor substrate 3 and at the inner position adjacent to the position immediately below. However, it is not limited to this example. For example, even if it is an outer position adjacent to the position immediately below the corners 31a, 31b, 31c, 31d, current concentration is a concern if it is in the vicinity of the immediately lower position. The same effect can be obtained even if the is provided.

  Further, in this configuration, all the cell portions Ca constituting the region AR directly below the semiconductor substrate 3 constitute the high withstand portion 5. Thus, the avalanche resistance of the entire device can be further effectively increased by setting the entire area AR immediately below the current concentration area to be the high resistance part 5.

  Further, the high-resistance cell portion C1 constituting the high-resistance portion 5 can reduce the mask opening ratio of the trench gate used in the manufacturing process as compared with the low-resistance cell portion C2, and the trench adjacent to the high-resistance cell portion C1. The part 19 can be configured to be deeper than the trench part 19 that is not adjacent to the high-tolerance cell part C1 but adjacent to only the low-tolerance cell part C2. As described above, by increasing the trench portion 19 adjacent to the high-resistance cell portion C1 to be deeper than the non-adjacent trench portion 19, an increase in the on-resistance of the high-resistance cell portion C1 can be suppressed.

[Second Embodiment]
Next, a semiconductor device 201 according to the second embodiment will be described with reference to FIGS. The semiconductor device 201 of the second embodiment is mainly different from the semiconductor device 1 of the first embodiment in the arrangement of the cell units and the specific configuration of the cell units. The semiconductor device 201 includes all the features of (1. Basic structure of semiconductor device) and (2. Configuration of connection member and region immediately below) described above in the first embodiment. For example, the basic configuration of each cell unit Ca is as described in (1. Basic structure of semiconductor device). Therefore, the description regarding (1. Basic structure of semiconductor device) and (2. Configuration of connection member and region immediately below) is omitted. In FIGS. 8 and 9, parts having substantially the same functions as those of the semiconductor device 1 of the first embodiment are denoted by the same reference numerals, and description thereof is omitted. 1 to 3 and FIG. 7 are the same as those in the first embodiment, and therefore, these drawings will be referred to as appropriate.

  8 and 9, the thickness direction of the semiconductor substrate 3 is the γ direction, and in FIG. 9, this γ direction is indicated by an arrow. Further, a predetermined direction orthogonal to the thickness direction of the semiconductor substrate 3 is defined as a lateral direction, this lateral direction is defined as an α direction, and in FIG. 8 and FIG. 9, this α direction is indicated by an arrow. In addition, a direction orthogonal to the thickness direction and the horizontal direction is a vertical direction, this vertical direction is a β direction, and in FIG. 8, this β direction is indicated by an arrow. 9 is a cross-sectional view schematically showing a cut surface at the position B2-B2 in FIG. 8, and this cut surface is a cut surface parallel to the α direction (lateral direction) and the γ direction (thickness direction). It has become. 8 is a cross-sectional view schematically showing a cut surface at the position B1-B1 in FIG. 9, and this cut surface is parallel to the α direction (lateral direction) and the β direction (vertical direction). The cut surface.

  In the semiconductor device 201 of this configuration, the high withstand portion 5 is provided in a part (peripheral portion) of the region AR immediately below the connection portion 30 a of the copper clip 30 in the semiconductor substrate 3. The high withstand portion 5 has a configuration in which cell portions Ca (high withstand cell portion C1) having a predetermined structure in which the avalanche withstand capability is relatively increased among a plurality of cell portions Ca constituting the semiconductor device 201 are arranged. It has become. On the other hand, in the semiconductor substrate 3, the low on-resistance part 6 is provided at a position outside the area AR directly below the connection part 30 a and at a position outside the high withstand voltage part 5. The low on-resistance portion 6 includes a cell portion (low withstand cell portion C2) having a lower avalanche resistance and a higher channel density than the high withstand cell portion C1 among the plurality of cell portions Ca constituting the semiconductor device 201. The on-resistance is suppressed.

  In this configuration, as shown in FIG. 8, cell portions (high withstand cell portions C <b> 1) having a predetermined structure in which the avalanche resistance is relatively increased are arranged along the entire periphery of the region AR directly below the semiconductor substrate 3. A high withstand portion 5 is provided in the configuration. In FIG. 8, the peripheral portion of the immediately lower region AR is shown as a rectangular figure by a two-dot chain line, and the position of the two-dot chain line is the peripheral position (outer edge position) of the direct region AR. And the high load resistance part 5 is comprised cyclically | annularly in the area | region AR directly under such a peripheral position.

  On the other hand, outside the directly under area AR, outside the high withstand portion 5 (outside the under area AR when the semiconductor substrate 3 is viewed in plan view), the low withstand cell portion C2 is formed so as to surround the under area AR. An on-resistance portion 6 is provided. The configuration of the low withstand cell portion C2 can be the same as the configuration of the low withstand cell portion C2 of the semiconductor device 1 of the first embodiment.

  Further, as shown in FIG. 8, the high-tolerance portion 5 is configured on the semiconductor substrate 3 on the center side of the region AR directly below the high-tolerance portion 5 (center side of the region AR directly below when the semiconductor substrate 3 is viewed in plan view). The inner side suppression part 7 in which the cell part (on-resistance suppression cell part C3) of a structure whose channel density is larger than the high withstand cell part C1 to be arranged is provided. In the example of FIG. 8, the on-resistance suppressing cell unit C3 constituting the inner-side suppressing unit 7 has the same configuration as the low-tolerance cell unit C2, and the on-resistance and avalanche resistance in cell units are low withstanding cell units. It is about the same as C2.

  Also in this example, the high withstand cell portion C1 constituting the high withstand portion 5 has a wider area than the low withstand cell portion C2 constituting the low on-resistance portion 6. Specifically, the high withstand cell portion C1 is configured by one of the first type cell unit C11 and the second type cell unit C12. Each of the first-type cell portions C11 has a longitudinal configuration extending in the lateral direction so as to extend from one end in the lateral direction to the other end of the region AR immediately below. The length of the second type cell unit C12 when viewed in plan is shorter than that of the first type cell unit C11, but is longer than the on-resistance suppression cell unit C3 and the low withstand cell unit C2. ing. In this case as well, the longitudinal direction of each cell portion Ca when the semiconductor substrate 3 is viewed in plan is the length direction of the cell portion, and the short direction of each cell portion Ca is the width direction of the cell portion.

  In each of the first type cell unit C11 and the second type cell unit C12, the density of the semiconductor region connected to the contact unit 26b is equal to the semiconductor region connected to the contact unit 26b in each low withstand cell unit C2. The density is higher than the density of the semiconductor region connected to the contact part 26b in each on-resistance suppression cell part C3. That is, in the high withstand portion 5, the high withstand portion 5 (the region in which the first type cell portion C11 and the second type cell portion C12 are arranged) occupies the contact region (in the high withstand portion 5 connected to the contact portion 26b). Of the semiconductor substrate 3 to be connected to the contact portion 26b in the contact region (the low on-resistance portion 6) occupying the entire low on-resistance portion 6 (region in which the low withstand cell portion C2 is arranged). The contact region (in the inner side suppressing portion 7, the contact area occupying the entire inner side suppressing portion 7 (region in which the on-resistance suppressing cell portion C 3 is arranged) is larger than the ratio of the connection region of the semiconductor substrate 3. The ratio of the connection region of the semiconductor substrate 3 connected to the portion 26b) is larger.

  Here, the area ratio will be described. In any high-resistance cell portion C1 constituting the high-resistance portion 5, the entire area X1 of the high-resistance cell portion C1 when viewed in plan in the thickness direction of the semiconductor substrate 3 (that is, the high-resistance cell portion C1) The ratio of the contact area Y1 where the contact layer 18 contacts the source electrode 26 in the high withstand cell portion C1 is defined as the first area ratio Y1 /. Let X1. And in any low withstand cell part C2 which comprises the low ON resistance part 6 among several cell parts Ca, the whole area of the said low withstand cell part C2 when planarly viewed in the thickness direction of the semiconductor substrate 3 Contact with which the contact layer 18 contacts the source electrode 26 in the low-resistance cell portion C2 with respect to X2 (that is, the area of a figure obtained by orthographic projection of the low-resistance cell portion C2 on a virtual plane parallel to the vertical and horizontal directions) The ratio of the area Y2 is defined as a second area ratio Y2 / X2. Further, in any of the on-resistance suppression cell portions C3 constituting the inner side suppression portion 7 of the plurality of cell portions Ca, the on-resistance suppression cell portion C3 when viewed in plan in the thickness direction of the semiconductor substrate 3 is used. With respect to the entire area X3 (that is, the area of the figure in which the on-resistance suppression cell unit C3 is orthographically projected on a virtual plane parallel to the vertical direction and the horizontal direction), the contact layer 18 is connected to the source electrode 26 in the on-resistance suppression cell unit C3. The ratio of the contact area Y3 in contact with the third area ratio Y3 / X3. When defined in this way, in the semiconductor device 201 of this configuration, the first area ratio Y1 is higher than the second area ratio Y2 / X2 regardless of the relationship between any high withstand cell portion C1 and any low withstand cell portion C2. / X1 is larger. Further, the first area ratio Y1 / X1 is larger than the third area ratio Y3 / X3 in any relationship between any high withstand cell portion C1 and any on-resistance suppression cell portion C3. That is, in both the first type cell unit C11 and the second type cell unit C12, the contact area per unit area (the contact area where the contact layer 18 is in contact with the source electrode 26) is any low withstand cell unit C2. Is larger than the contact area per unit area (contact area where the contact layer 18 contacts the source electrode 26), and the contact area per unit area (contact layer 18 is the source electrode 26) in any of the on-resistance suppression cell portions C3. Therefore, the avalanche resistance can be increased more easily than the low resistance cell portion C2 and the on-resistance suppression cell portion C3.

  In other words, the low-tolerance cell portion C2 and the on-resistance suppression cell portion C3 have a structure having a relatively low avalanche resistance compared to any of the first-type cell portion C11 and the second-type cell portion C12. However, the low-resistance cell portion C2 and the on-resistance suppression cell portion C3 are narrower than the first-type cell portion C11 and the second-type cell portion C12, and are finer than the high-resistance cell portion C1. In any case, since the channel density (the ratio of the channel region in the entire cell) is larger than that of the high withstand cell portion C1, the on-resistance can be suppressed more easily than with the high withstand cell portion C1. More specifically, the density of the trench portion 19 in the low on-resistance portion 6 and the density of the trench portion 19 in the inner side suppression portion 7 are larger than the density of the trench portion 19 in the high withstand portion 5, Since the density of the channel region (portion adjacent to the trench portion 19 in the body layer 17) formed along the trench portion 19 is also higher in the low on-resistance portion 6 and the inner side suppression portion 7, the low on-resistance portion 6 and The inner side suppression unit 7 can lower the channel resistance per unit area, and can easily suppress the on-resistance.

Even in this configuration, the same effect as in the first embodiment can be obtained.
Furthermore, in this configuration, the high-tolerance part 5 in which cell portions (high-tolerance cell parts C1) having a predetermined structure in which the avalanche resistance is relatively increased is arranged along the entire circumference of the region AR immediately below the semiconductor substrate 3. Is provided. In the semiconductor substrate 3, a cell portion (on-state) having a structure having a lower avalanche resistance and a higher channel density than the high-resistance cell portion C <b> 1 constituting the high-resistance portion 5 is provided at the center side of the region AR directly below the high-resistance portion 5. An inner side suppression unit 7 in which resistance suppression cell units C3) are arranged is provided. With this configuration, the high withstand portion 5 can be selectively provided at the peripheral portion, particularly in the region AR immediately below, where current tends to concentrate, so that the withstand capability of the entire element can be increased efficiently. On the other hand, since the cell part (on-resistance suppression cell part C3) that can reduce the on-resistance can be arranged not only on the outside of the high-tolerance part 5 but also on the center side of the region AR immediately below, the on-resistance of the entire element is reduced. It becomes easier to reduce.

  In the example of FIG. 8, in the semiconductor substrate 3, a part of the high withstand portion 5 protrudes outside the direct region AR, but the high withstand portion 5 may be entirely within the direct region AR. Alternatively, the high withstand portion 5 may be arranged outside the direct area AR along the peripheral edge of the direct area AR.

[Third Embodiment]
Next, a semiconductor device 301 according to the third embodiment will be described with reference to FIGS. The semiconductor device 301 of the third embodiment is mainly different from the semiconductor device 1 of the first embodiment in the arrangement of the cell units and the specific configuration of the cell units. The semiconductor device 301 includes all the features of (1. Basic structure of the semiconductor device) and (2. Configuration of the connection member and the region immediately below) described above in the first embodiment. For example, the basic configuration of each cell unit Ca is as described in (1. Basic structure of semiconductor device). Therefore, the description regarding (1. Basic structure of semiconductor device) and (2. Configuration of connection member and region immediately below) is omitted. In FIGS. 10 and 11, parts having substantially the same functions as those of the semiconductor device 1 of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. 1 to 3 and FIG. 7 are the same as those in the first embodiment, and therefore, these drawings will be referred to as appropriate.

  FIG. 11 is a cross-sectional view schematically showing a cut surface at the position C2-C2 in FIG. 10, and this cut surface is parallel to the α direction (lateral direction) and the γ direction (thickness direction). It is a cut surface. FIG. 10 is a cross-sectional view schematically showing a cut surface at the position C1-C1 in FIG. 11. This cut surface is parallel to the α direction (lateral direction) and the β direction (vertical direction). The cut surface.

  In the semiconductor device 301 of this configuration, the high-tolerance portion 5 having a mesh structure is provided in the region AR directly below the connection portion 30a of the copper clip 30 in the semiconductor substrate 3. The high withstand portion 5 has a configuration in which cell portions (high withstand cell portion C1) having a predetermined structure with relatively increased avalanche withstand among the plurality of cell portions Ca constituting the semiconductor device 301 are arranged. ing. On the other hand, in the semiconductor substrate 3, the low on-resistance part 6 is provided at a position outside the area AR directly below the connection part 30 a and at a position outside the high withstand voltage part 5. The low on-resistance portion 6 has a configuration in which cell portions (low withstand cell portion C2) having a channel density larger than that of the high withstand cell portion C1 among the plurality of cell portions Ca constituting the semiconductor device 301 are arranged. The on-resistance is suppressed. In this configuration, all the cell portions Ca that form the region AR immediately below the semiconductor substrate 3 constitute the high withstand portion 5. The high-resistance cell portion C1 constituting the high-resistance portion 5 is composed of a plurality of types of cell portions Ca, and a cell portion C13 of a type having a relatively high channel density in the vicinity of the central portion of the direct region AR. Is arranged. The cell portion C13 in the vicinity of the center has a smaller area ratio of the contact region and a higher channel density than other types of high-resistance cell portions C1 arranged around the cell portion C13. The channel density is smaller and the area ratio of the contact region is larger than that of the low withstand cell portion C2 disposed around the contact area. With this configuration, the withstand capability can be increased while reducing the on-resistance to some extent near the center of the region AR immediately below.

[Fourth Embodiment]
Next, a semiconductor device 401 according to the fourth embodiment will be described with reference to FIGS. The semiconductor device 401 of the fourth embodiment is mainly different from the semiconductor device 1 of the first embodiment in the arrangement of the cell units and the specific configuration of the cell units. The semiconductor device 401 includes all the features of (1. Basic structure of the semiconductor device) and (2. Configuration of the connection member and the region immediately below) described above in the first embodiment. For example, the basic configuration of each cell unit Ca is as described in (1. Basic structure of semiconductor device). Therefore, the description regarding (1. Basic structure of semiconductor device) and (2. Configuration of connection member and region immediately below) is omitted. In FIG. 12 and FIG. 13, parts having substantially the same functions as those of the semiconductor device 1 of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. 1 to 3 and FIG. 7 are the same as those in the first embodiment, and therefore, these drawings will be referred to as appropriate.

  13 is a cross-sectional view schematically showing a cut surface at a position D2-D2 in FIG. 12, and this cut surface is parallel to the β direction (longitudinal direction) and the γ direction (thickness direction). It is a cut surface. FIG. 12 is a cross-sectional view schematically showing a cut surface at the position D1-D1 in FIG. 13. This cut surface is parallel to the α direction (lateral direction) and the β direction (vertical direction). The cut surface.

  In the semiconductor device 401 of this configuration, the mesh structure and the annular high withstand portion 5 are provided in the region AR immediately below the connection portion 30 a of the copper clip 30 in the semiconductor substrate 3. The high withstand portion 5 has a configuration in which cell portions (high withstand cell portion C1) having a predetermined structure in which the avalanche withstand capability is relatively increased among a plurality of cell portions Ca constituting the semiconductor device 401 are arranged. ing. In this configuration, the high-resistance cell portion C1 having the same structure is annularly arranged along the peripheral edge of the region AR immediately below. And the inside side suppression part 7 by which the same on-resistance suppression cell part C3 of 2nd Embodiment is arranged is provided inside the high withstand amount part 5 comprised cyclically | annularly. The inner side suppression portion 7 has a configuration in which an on-resistance suppression cell portion C3 having a larger channel density and a smaller area ratio of the contact region than the high withstand cell portion C1 is arranged, and the on-resistance is suppressed. .

  On the other hand, the low-tolerance cell portions C2 similar to those of the second embodiment are arranged at positions outside the region AR directly below the connection portion 30a and outside the high-tolerance portion 5 in the semiconductor substrate 3. A low on-resistance portion 6 is provided. The low on-resistance portion 6 includes a plurality of cell portions Ca constituting the semiconductor device 401 in which low withstand cell portions C2 having a channel density larger than that of the high withstand cell portion C1 and an area ratio of the contact region are arranged. The on-resistance is suppressed.

[Fifth Embodiment]
Next, a semiconductor device 501 according to the fifth embodiment will be described with reference to FIGS. The semiconductor device 501 of the fifth embodiment is mainly different from the semiconductor device 1 of the first embodiment in the arrangement of the cell units and the specific configuration of the cell units. The semiconductor device 501 includes all the features of (1. Basic structure of semiconductor device) and (2. Configuration of connection member and region immediately below) described above in the first embodiment. For example, the basic configuration of each cell unit Ca is as described in (1. Basic structure of semiconductor device). Therefore, the description regarding (1. Basic structure of semiconductor device) and (2. Configuration of connection member and region immediately below) is omitted. In FIGS. 14 and 15, portions having substantially the same functions as those of the semiconductor device 1 of the first embodiment are denoted by the same reference numerals, and description thereof is omitted. 1 to 3 and FIG. 7 are the same as those in the first embodiment, and therefore, these drawings will be referred to as appropriate.

  14 and 15, the thickness direction of the semiconductor substrate 3 is the γ direction, and in FIG. 15, this γ direction is indicated by an arrow. Further, a predetermined direction orthogonal to the thickness direction of the semiconductor substrate 3 is defined as a horizontal direction, this horizontal direction is defined as an α direction, and in FIG. 14, this α direction is indicated by an arrow. Further, the direction orthogonal to the thickness direction and the horizontal direction is defined as a vertical direction, this vertical direction is defined as a β direction, and in FIGS. 14 and 15, this β direction is indicated by an arrow. FIG. 15 is a cross-sectional view schematically showing a cut surface at the position E2-E2 in FIG. 14, which is a cut surface parallel to the β direction (longitudinal direction) and the γ direction (thickness direction). It has become. 14 is a cross-sectional view schematically showing a cut surface at the position E1-E1 in FIG. 15. This cut surface is parallel to the α direction (lateral direction) and the β direction (vertical direction). The cut surface.

  Also in the semiconductor device 501 of this configuration, the high withstand portion 5 is provided in a part (peripheral portion) of the region AR immediately below the connection portion 30 a of the copper clip 30 in the semiconductor substrate 3. The high withstand portion 5 has a configuration in which cell portions Ca (high withstand cell portion C1) having a predetermined structure with relatively increased avalanche withstand among the plurality of cell portions Ca constituting the semiconductor device 501 are arranged. It has become. On the other hand, in the semiconductor substrate 3, the low on-resistance part 6 is provided at a position outside the area AR directly below the connection part 30 a and at a position outside the high withstand voltage part 5. The low on-resistance portion 6 has a configuration in which cell portions (low withstand cell portion C2) having a channel density larger than that of the high withstand cell portion C1 among the plurality of cell portions Ca constituting the semiconductor device 501 are arranged. The on-resistance is suppressed.

  Also in this configuration, as in the first embodiment, as shown in FIGS. 1 to 3 and 7, the connection portion 30 a of the copper clip 30 has an outer shape including corner portions 31 a, 31 b, 31 c, and 31 d). Yes. In FIG. 14, the peripheral portion of the immediate area AR is shown as a rectangular figure by a two-dot chain line, and the position of the two-dot chain line is the peripheral position (outer edge position) of the direct region AR. In this configuration, a high withstand voltage is selectively provided at positions immediately below the corners 31a, 31b, 31c, and 31d (positions B1, B2, B3, and B4 in FIG. 14) and positions immediately below the corners in the semiconductor substrate 3. A portion 5 is provided (see the vicinity of the region CR in FIG. 14). In the immediate area AR, the current tends to concentrate particularly near the positions immediately below the corners 31a, 31b, 31c, 31d. Therefore, the high withstand portion 5 is selectively formed near the positions directly below the corners 31a, 31b, 31c, 31d. If the resistance is increased by arranging the element, the tolerance of the entire element can be efficiently increased. The positions immediately below the corner portions 31a, 31b, 31c, and 31d are positions on a straight line in the thickness direction (γ direction) passing through the corner positions of the apexes of the corner portions 31a, 31b, 31c, and 31d in the semiconductor substrate 3. is there. In the example of FIG. 14, the positions immediately below the corners 31a, 31b, 31c, and 31d are conceptually indicated by reference numerals B1, B2, B3, and B4. Part 5 is provided. Further, as shown in FIG. 14, the avalanche resistance is lower and the channel density is higher than that of the high-resistance parts 5 at positions away from the positions directly below the corners 31a, 31b, 31c, and 31d in the peripheral part of the area AR. The peripheral portion side suppression portion 8 in which the cell portion (on-resistance suppression cell portion C4) is disposed is provided. In the example of FIGS. 14 and 15, the on-resistance suppression cell unit C4 that constitutes the peripheral side suppression unit 8 has the same configuration as the low-resistance cell unit C2, and the on-resistance and avalanche resistance in cell units are It is about the same as the low withstand cell portion C2.

  Further, as shown in FIG. 14, the high-tolerance part 5 is configured on the semiconductor substrate 3 on the center side of the region AR directly below the high-tolerance part 5 (center side of the region AR directly below when the semiconductor substrate 3 is viewed in plan view). The inner side suppression part 7 in which the cell part (on-resistance suppression cell part C3) of the structure where the avalanche resistance is lower and the channel density is larger than the high resistance cell part C1 to be arranged is provided. In the example of FIG. 14, the on-resistance suppressing cell unit C3 that constitutes the inner-side suppressing unit 7 has the same configuration as the low-tolerance cell unit C2, and the on-resistance and avalanche resistance in cell units are low withstanding cell units. It is about the same as C2.

  Further, on the outside of the directly under region AR, the low withstand cell portion C2 is formed on the outside of the high withstand portion 5 (outside of the directly under region AR when the semiconductor substrate 3 is viewed in plan view) so as to surround the directly under region AR. An on-resistance portion 6 is provided. The configuration of the low withstand cell unit C2 can be the same as the configuration of the low withstand cell unit C2 of the semiconductor device 1 in the first embodiment, and is more avalanche than the high withstand cell unit C1 that constitutes the high withstand unit 5. The structure has a low withstand amount and a high channel density.

Here, the area ratio will be described. In any high-resistance cell portion C1 constituting the high-resistance portion 5, the entire area X1 of the high-resistance cell portion C1 when viewed in plan in the thickness direction of the semiconductor substrate 3 (that is, the high-resistance cell portion C1) The ratio of the contact area Y1 where the contact layer 18 contacts the source electrode 26 in the high withstand cell portion C1 is defined as the first area ratio Y1 /. Let X1. And in any low withstand cell part C2 which comprises the low ON resistance part 6 among several cell parts Ca, the whole area of the said low withstand cell part C2 when planarly viewed in the thickness direction of the semiconductor substrate 3 Contact with which the contact layer 18 contacts the source electrode 26 in the low-resistance cell portion C2 with respect to X2 (that is, the area of a figure obtained by orthographic projection of the low-resistance cell portion C2 on a virtual plane parallel to the vertical and horizontal directions) The ratio of the area Y2 is defined as a second area ratio Y2 / X2. Further, in any of the on-resistance suppression cell portions C3 constituting the inner side suppression portion 7 of the plurality of cell portions Ca, the on-resistance suppression cell portion C3 when viewed in plan in the thickness direction of the semiconductor substrate 3 is used. With respect to the entire area X3 (that is, the area of the figure in which the on-resistance suppression cell unit C3 is orthographically projected on a virtual plane parallel to the vertical direction and the horizontal direction), the contact layer 18 is connected to the source electrode 26 in the on-resistance suppression cell unit C3. The ratio of the contact area Y3 in contact with the third area ratio Y3 / X3. And in any ON-resistance suppression cell part C4 which comprises the peripheral part side suppression part 8 among several cell part Ca, the said ON-resistance suppression cell part C4 when planarly viewed in the thickness direction of the semiconductor substrate 3 For the entire area X4 (that is, the area of the figure in which the on-resistance suppression cell unit C4 is orthographically projected on a virtual plane parallel to the vertical and horizontal directions), the contact layer 18 is the source electrode in the on-resistance suppression cell unit C4. The ratio of the contact area Y4 in contact with H is 26 as a fourth area ratio Y4 / X4.
When defined in this way, in the semiconductor device 501 of this configuration, the first area ratio Y1 is higher than the second area ratio Y2 / X2 regardless of the relationship between any high withstand cell portion C1 and any low withstand cell portion C2. / X1 is larger. Further, the first area ratio Y1 / X1 is larger than the third area ratio Y3 / X3 in any relationship between any high withstand cell portion C1 and any on-resistance suppression cell portion C3. Further, the first area ratio Y1 / X1 is larger than the fourth area ratio Y4 / X4 in any relationship between any high withstand cell portion C1 and any on-resistance suppression cell portion C4.

  As described above, the contact area per unit area (contact area where the contact layer 18 is in contact with the source electrode 26) of each of the high withstand cell portions C1 is the contact area per unit area of any low withstand cell portion C2. Is larger than the contact area per unit area in any of the on-resistance suppression cell portions C3, and larger than the contact area per unit area in any of the on-resistance suppression cell portions C4. The avalanche resistance can be increased more easily than the cell part C2, the on-resistance suppression cell part C3, and the on-resistance suppression cell part C4. On the other hand, the low-resistance cell portion C2, the on-resistance suppression cell portion C3, and the on-resistance suppression cell portion C4 are narrower and finer than the high-resistance cell portion C1, and are all smaller than the high-resistance cell portion C1. Since the channel density (the ratio of the channel region in the entire cell) is large, the on-resistance can be suppressed more easily than the high withstand cell portion C1.

Even in this configuration, the same effect as in the first embodiment can be obtained.
Further, in this configuration, the high withstand portion 5 is selectively provided in the vicinity of the corner instead of the entire periphery of the immediate area AR, and the high withstand amount is provided at a position away from the direct position in the peripheral portion of the immediately below area AR. A peripheral portion side suppression portion 8 in which a cell portion (on-resistance suppression cell portion C4) having a channel density larger than that of the portion 5 is disposed is provided. In this configuration, the high withstand portion 5 can be selectively provided at a position immediately below the corner portion so that the current tends to concentrate particularly in the peripheral portion of the immediately below region AR, so that the withstand capability of the entire element can be efficiently increased. . On the other hand, since the cell part (on-resistance suppressing cell part C4) capable of reducing the on-resistance can be arranged not only on the outside of the high-tolerance part 5 or the center side of the region AR directly below, but also on a part of the peripheral part, It becomes easier to further reduce the on-resistance of the entire element.

[Sixth Embodiment]
Next, a semiconductor device 601 according to the sixth embodiment will be described with reference to FIGS. The semiconductor device 601 of the sixth embodiment is mainly different from the semiconductor device 1 of the first embodiment in the arrangement of the cell units and the specific configuration of the cell units. The semiconductor device 601 includes all the features of (1. Basic structure of semiconductor device) and (2. Configuration of connection member and region immediately below) described above in the first embodiment. For example, the basic configuration of each cell unit Ca is as described in (1. Basic structure of semiconductor device). Therefore, the description regarding (1. Basic structure of semiconductor device) and (2. Configuration of connection member and region immediately below) is omitted. In FIGS. 16 to 18, parts having substantially the same functions as those of the semiconductor device 1 of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. 1 to 3 and FIG. 7 are the same as those in the first embodiment, and therefore, these drawings will be referred to as appropriate.

  Also in the examples of FIGS. 16 to 18, the thickness direction of the semiconductor substrate 3 is the γ direction, and in FIG. 18, this γ direction is indicated by an arrow. In addition, a predetermined direction orthogonal to the thickness direction of the semiconductor substrate 3 is defined as a lateral direction, and this lateral direction is defined as an α direction. In FIGS. 16 and 17, the α direction is indicated by an arrow. Further, the direction orthogonal to the thickness direction and the horizontal direction is defined as a vertical direction, the vertical direction is defined as a β direction, and in FIGS. 16 to 18, the β direction is indicated by an arrow. 18 is a cross-sectional view schematically showing a cut surface at the position F2-F2 in FIG. 17. This cut surface is a cut surface parallel to the β direction (longitudinal direction) and the γ direction (thickness direction). It has become. FIG. 16 is a cross-sectional view schematically showing a cut surface at the position F1-F1 in FIG. 18. This cut surface is parallel to the α direction (lateral direction) and the β direction (vertical direction). The cut surface.

  Also in the semiconductor device 601 of this configuration, the high withstand portion 5 is provided in a part (peripheral portion) of the region AR immediately below the connection portion 30 a of the copper clip 30 in the semiconductor substrate 3. The high withstand portion 5 has a configuration in which cell portions (high withstand cell portion C1) having a predetermined structure with relatively increased avalanche withstand among the plurality of cell portions Ca constituting the semiconductor device 601 are arranged. ing. On the other hand, in the semiconductor substrate 3, the low on-resistance part 6 is provided at a position outside the area AR directly below the connection part 30 a and at a position outside the high withstand voltage part 5. The low on-resistance portion 6 includes a cell portion (low resistance cell portion C2) having a smaller avalanche resistance and higher channel density than the high resistance cell portion C1 among the plurality of cell portions Ca constituting the semiconductor device 601. The on-resistance is suppressed.

  Also in this configuration, as in the first embodiment, the connection part 30a of the copper clip 30 has an outer shape including corners 31a, 31b, 31c, 31d) as shown in FIGS. Yes. In FIG. 16, the peripheral portion of the immediately lower region AR is shown as a rectangular figure by a two-dot chain line, and the position of the two-dot chain line is the peripheral position (outer edge position) of the direct region AR. In this configuration, a high withstand load is selectively provided at positions immediately below the corners 31a, 31b, 31c, and 31d (positions B1, B2, B3, and B4 in FIG. 16) and at positions immediately below the corners in the semiconductor substrate 3. Part 5 is provided. Further, as shown in FIG. 16, a cell portion (on-resistance suppression cell portion C <b> 4) having a structure in which the avalanche resistance is lower and the channel density is higher than that of the high-resistance portion 5 in the peripheral portion of the immediately lower region AR. ) Is disposed on the peripheral portion side suppressing portion 8. In the examples of FIGS. 16 to 18, the on-resistance suppression cell unit C4 that constitutes the peripheral side suppression unit 8 has the same configuration as the low-resistance cell unit C2, and has an on-resistance and avalanche resistance in units of cells. It is about the same as the low withstand cell portion C2.

  Further, as shown in FIG. 16, the high-tolerance portion 5 is configured on the semiconductor substrate 3 on the center side of the region AR directly below the high-tolerance portion 5 (center side of the region AR directly below when the semiconductor substrate 3 is viewed in plan view). The inner side suppression part 7 in which the cell part (on-resistance suppression cell part C3) of the structure where the avalanche resistance is lower and the channel density is larger than the high resistance cell part C1 to be arranged is provided. In the example of FIG. 16, the on-resistance suppressing cell unit C3 that constitutes the inner-side suppressing unit 7 has the same configuration as the low-tolerance cell unit C2, and the on-resistance and avalanche resistance in cell units are low withstanding cell units. It is about the same as C2.

  Further, on the outside of the directly under region AR, the low withstand cell portion C2 is formed on the outside of the high withstand portion 5 (outside of the directly under region AR when the semiconductor substrate 3 is viewed in plan view) so as to surround the directly under region AR. An on-resistance portion 6 is provided. The configuration of the low withstand cell portion C2 can be the same as that of the low withstand cell portion C2 of the semiconductor device 1 of the first embodiment, and is more avalanche than the high withstand cell portion C1 constituting the high withstand portion 5. The structure has a low withstand amount and a high channel density.

  Further, in this configuration, the high withstand portion 5 has a plurality of types of cell portions Ca, and is configured by the first high withstand portion 5a and the second high withstand portion 5b. The first high withstand portion 5a is provided in the semiconductor substrate 3 at a position immediately below the corners 31a, 31b, 31c, 31d (positions B1, B2, B3, B4) and a position immediately below the semiconductor substrate 3. 3 is constituted by the first cell portion Ca1 having the largest avalanche resistance among the plural types of cell portions Ca. Further, the second high withstand portion 5b is formed on the center side of the region AR directly below the first high withstand portion 5a, has a lower avalanche withstand capability than the first cell portion Ca1 of the first high withstand portion 5a, and the channel. This is a portion in which one or a plurality of types of second cell portions Ca2 having a high density structure are arranged. In the example of FIG. 16, the second high-resistance portion 5b is configured by one type of second cell portion Ca2, but the avalanche resistance is lower than that of the first cell portion Ca1, and the avalanche resistance is lower than that of the low-resistance cell portion C2. It may be constituted by a plurality of types of cell portions having a high height.

  Even in this configuration, when the area ratio is defined as in the fifth embodiment, the first area ratio Y1 / X1 of any high withstand cell portion C1 (first cell portion Ca1, second cell portion Ca2), and any The first area ratio Y1 / X1 is larger than the second area ratio Y2 / X2 also in relation to the second area ratio Y2 / X2 of the low withstand cell portion C2. Further, the relationship between the first area ratio Y1 / X1 of any high withstand cell portion C1 and the third area ratio Y3 / X3 of any on-resistance suppression cell portion C3 is greater than the third area ratio Y3 / X3. One area ratio Y1 / X1 is larger. Further, the relationship between the first area ratio Y1 / X1 of any high withstand cell portion C1 and the fourth area ratio Y4 / X4 of any on-resistance suppression cell portion C4 is greater than the fourth area ratio Y4 / X4. One area ratio Y1 / X1 is larger.

  In the first cell portion Ca1, the entire area X5 of the first cell portion Ca1 when viewed in plan in the thickness direction of the semiconductor substrate 3 (that is, the first cell portion Ca1 is parallel to the vertical direction and the horizontal direction). The ratio of the contact area Y5 where the contact layer 18 contacts the source electrode 26 in the first cell portion Ca1 is defined as a fifth area ratio Y5 / X5. Then, in the second cell portion Ca2, the entire area X6 of the second cell portion Ca2 when viewed in plan in the thickness direction of the semiconductor substrate 3 (that is, the second cell portion Ca2 is parallel to the vertical direction and the horizontal direction). The ratio of the contact area Y6 where the contact layer 18 is in contact with the source electrode 26 in the second cell portion Ca2 is defined as a sixth area ratio Y6 / X6. When defined in this way, the sixth area ratio Y6 / X5 is related to the fifth area ratio Y5 / X5 of any first cell portion Ca1 and the sixth area ratio Y6 / X6 of any second cell portion Ca2. The fifth area ratio Y5 / X5 is larger than X6.

  Even in this configuration, the same effect as in the first embodiment can be obtained. In addition, the high-resistance cell portion can be provided in at least two stages so that the avalanche resistance increases as the position near the corner portion where the current tends to concentrate particularly in the peripheral portion of the direct region AR. An increase in on-resistance can be effectively suppressed while increasing more efficiently.

[Seventh Embodiment]
Next, a semiconductor device 701 according to a seventh embodiment will be described with reference to FIG. The semiconductor device 701 of the seventh embodiment is mainly different from the semiconductor device 1 of the first embodiment in the arrangement of the cell units and the specific configuration of the cell units. The semiconductor device 701 includes all the features of (1. Basic structure of semiconductor device) and (2. Configuration of connection member and region immediately below) described above in the first embodiment. For example, the basic configuration of each cell unit Ca is as described in (1. Basic structure of semiconductor device). Therefore, the description regarding (1. Basic structure of semiconductor device) and (2. Configuration of connection member and region immediately below) is omitted. In FIG. 19, parts having substantially the same functions as those of the semiconductor device 1 of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. 1 to 3 and FIG. 7 are the same as those in the first embodiment, and therefore, these drawings will be referred to as appropriate.

  Also in the example of FIG. 19, the thickness direction of the semiconductor substrate 3 is the γ direction (not shown). Further, a predetermined direction orthogonal to the thickness direction of the semiconductor substrate 3 is defined as a horizontal direction, this horizontal direction is defined as an α direction, and in FIG. 19, this α direction is indicated by an arrow. In addition, a direction orthogonal to the thickness direction and the horizontal direction is a vertical direction, this vertical direction is a β direction, and in FIG. 19, this β direction is indicated by an arrow. In addition, FIG. 19 is a cut surface cut at the same position as FIG. 16 of the sixth embodiment.

  Also in the semiconductor device 701 having this configuration, the high withstand portion 5 is provided in a part (peripheral portion) of the region AR immediately below the connection portion 30 a of the copper clip 30 in the semiconductor substrate 3. The high withstand portion 5 has a configuration in which cell portions (high withstand cell portion C1) having a predetermined structure in which the avalanche withstand capability is relatively increased among a plurality of cell portions Ca constituting the semiconductor device 701 are arranged. ing. On the other hand, in the semiconductor substrate 3, the low on-resistance part 6 is provided at a position outside the area AR directly below the connection part 30 a and at a position outside the high withstand voltage part 5. The low on-resistance portion 6 includes a cell portion (low resistance cell portion C2) having a smaller avalanche resistance and a higher channel density than the high resistance cell portion C1 among the plurality of cell portions Ca constituting the semiconductor device 701. The on-resistance is suppressed.

  Also in this configuration, as in the first embodiment, the connection part 30a of the copper clip 30 has an outer shape including corners 31a, 31b, 31c, 31d) as shown in FIGS. Yes. In FIG. 19, the peripheral portion of the immediate area AR is shown as a rectangular figure by a two-dot chain line, and the position of the two-dot chain line is the peripheral position (outer edge position) of the direct area AR. In this configuration, the high withstand portion 5 is provided in an annular shape along the entire periphery of the immediately below area AR configured as described above.

  Further, as shown in FIG. 19, the high-tolerance portion 5 is configured on the center side of the region AR directly below the high-tolerance portion 5 in the semiconductor substrate 3 (the central side of the region AR directly below when the semiconductor substrate 3 is viewed in plan view). The inner side suppression part 7 in which the cell part (on-resistance suppression cell part C3) of the structure where the avalanche resistance is lower and the channel density is larger than the high resistance cell part C1 to be arranged is provided. In the example of FIG. 19, the on-resistance suppressing cell unit C3 that constitutes the inner-side suppressing unit 7 has the same configuration as the low-tolerance cell unit C2, and the on-resistance and avalanche resistance in cell units are low withstanding cell units. It is about the same as C2.

  Further, on the outside of the directly under region AR, the low withstand cell portion C2 is formed on the outside of the high withstand portion 5 (outside of the directly under region AR when the semiconductor substrate 3 is viewed in plan view) so as to surround the directly under region AR. An on-resistance portion 6 is provided. The configuration of the low withstand cell portion C2 can be the same as that of the low withstand cell portion C2 of the semiconductor device 1 of the first embodiment, and is more avalanche than the high withstand cell portion C1 constituting the high withstand portion 5. The structure has a low withstand amount and a high channel density.

  Further, in this configuration, the high withstand portion 5 has a plurality of types of cell portions Ca, and is configured by a first high withstand portion 5c and a second high withstand portion 5d. The first high withstand portion 5c is a portion constituted by the first cell portion Ca1 having a structure having the largest avalanche withstand among the plurality of types of cell portions Ca formed in the semiconductor substrate 3, and such a first cell. The part Ca <b> 1 is annularly arranged along the entire periphery of the region AR immediately below the semiconductor substrate 3. The second high withstand portion 5d is a portion where one or a plurality of types of second cell portions Ca2 having a structure having a lower avalanche withstand and a higher channel density than the first cell portion Ca1 of the first high withstand portion 5c. The semiconductor substrate 3 is formed in an annular shape along the inner edge of the annular first high resistance portion 5c on the center side of the region AR directly below the first high resistance portion 5c. In the example of FIG. 19, the second high withstand portion 5d is configured by one type of second cell portion Ca2, but the avalanche withstand is lower than the first cell portion Ca1, and the avalanche withstand is lower than the low withstand cell portion C2. It may be configured by a plurality of types of cell portions having a high height.

  Even in this configuration, when the area ratio is defined as in the fifth embodiment, the first area ratio Y1 / X1 of any high withstand cell portion C1 (first cell portion Ca1, second cell portion Ca2), and any The first area ratio Y1 / X1 is larger than the second area ratio Y2 / X2 also in relation to the second area ratio Y2 / X2 of the low withstand cell portion C2. Further, the relationship between the first area ratio Y1 / X1 of any high withstand cell portion C1 and the third area ratio Y3 / X3 of any on-resistance suppression cell portion C3 is greater than the third area ratio Y3 / X3. One area ratio Y1 / X1 is larger.

  Further, in the first cell portion Ca1, the entire area X7 of the first cell portion Ca1 when viewed in plan in the thickness direction of the semiconductor substrate 3 (that is, the first cell portion Ca1 is parallel to the vertical direction and the horizontal direction). The ratio of the contact area Y7 where the contact layer 18 contacts the source electrode 26 in the first cell portion Ca1 is defined as a seventh area ratio Y7 / X7. Then, in the second cell portion Ca2, the entire area X8 of the second cell portion Ca2 when viewed in plan in the thickness direction of the semiconductor substrate 3 (that is, the second cell portion Ca2 is parallel to the vertical direction and the horizontal direction). The ratio of the contact area Y8 where the contact layer 18 contacts the source electrode 26 in the second cell portion Ca2 is defined as an eighth area ratio Y8 / X8. When defined in this manner, the eighth area ratio Y8 / X7 is related to the relationship between the seventh area ratio Y7 / X7 of any first cell part Ca1 and the eighth area ratio Y8 / X8 of any second cell part Ca2. The seventh area ratio Y7 / X7 is larger than X8.

  Even in this configuration, the same effect as in the first embodiment can be obtained. In addition, since the high-resistance cell portion can be provided in at least two stages so that the avalanche resistance increases as it approaches the peripheral edge where current is likely to concentrate in the direct region AR, the resistance of the entire device can be increased more efficiently. Thus, an increase in on-resistance can be effectively suppressed.

[Other Embodiments]
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.

In the above-described embodiment, an example in which the semiconductor device 1 is applied to a DMOS has been described. 20 differs from the configuration of the semiconductor device 1 of the first embodiment shown in FIG. 4 only in that a P + type collector layer 63 is added, and is otherwise the same as the configuration of FIG. . The cross section of the semiconductor device 801 in FIG. 20 is the same as that in FIG. 5, for example. In the semiconductor device 801 shown in FIG. 20, each cell portion Ca is configured as a known trench gate type IGBT cell, and an emitter electrode 67 having the same configuration is used instead of the source electrode 26 in FIG. Instead of the drain electrode 11, a collector electrode 64 having the same configuration is used. Further, in the semiconductor substrate 3, an N + type emitter layer 65 having the same structure is used instead of the N + type source layer 25, and a P type body layer 17, an N− type drift layer 15 (epitaxial layer), a trench portion. 19, the gate insulating film 21, the gate electrode 23, the insulating film 24, the copper clip 30, and the like are the same as the configuration of FIG. 4 of the first embodiment. Further, an N + type field stop layer 61 is provided on the back surface 3b side of the N− type drift layer 15 (epitaxial layer), and a P + type collector layer 63 is provided on the back surface 3b side of the field stop layer 61. Yes. A collector electrode 64 is provided in a configuration connected to the P + type collector layer 63.
Even in the semiconductor device 801 having such an IGBT structure, in the semiconductor substrate 3, the internal position of the direct area AR located immediately below the connection portion 30 a of the copper clip 30 (connecting member) or the direct position directly below the direct area AR. The high withstand portion 5 can be provided at at least one of the positions near the area AR (for example, the position adjacent to the peripheral edge of the area AR immediately below). It should be noted that the configuration of any of the above-described embodiments may be used for the arrangement of the high withstand portion 5 and the configuration of the cell portion. In the semiconductor substrate 3, the low on-resistance portion 6 is provided at least at a position outside the region AR immediately below and outside the high withstand portion 5. The arrangement of the low on-resistance part 6 and the structure of the cell part may be any of those described above as long as the cell part Ca has a structure in which the avalanche resistance is lower and the channel density is higher than the cell part Ca of the high resistance part 5. The configuration of the embodiment may be used.

  In the said embodiment, although the structure using the copper clip 30 as a connection member and the example were shown, the structure and arrangement | positioning of a connection member are not limited to the example mentioned above. Further, the shape of the connecting portion is not limited to this, and the outer shape of the connecting portion may be a polygonal shape, a circular shape, an elliptical shape, or the like. For example, as in the semiconductor device 901 illustrated in FIG. 21, another connection member such as the bonding pad 50 may be used instead of the copper clip 30. Even in the configuration using the bonding pad 50 as described above, the region located immediately below the bonding pad 50 in the semiconductor substrate 3 is the directly below region AR, as in the above-described embodiment. In the example of FIG. 21, an example in which the outer shape of the connection portion 50a connected to the source electrode 26 in the bonding pad 50 is an elliptical shape is shown. However, the outer shape of the connection portion 50a is a square shape or a rectangular shape. You may comprise. In this case, as the configuration of the semiconductor chip 2, the configuration of any of the above-described embodiments can be applied. Moreover, in the examples of FIG. 1, FIG. 2, etc., the shape of the corners 31a, 31b, 31c, 31d of the connecting portion 30a in the copper clip 30 is a right angle or a substantially right angle when viewed in plan. However, as in the semiconductor device 1 of FIGS. 22 and 23, even if the shapes of the corners 31a, 31b, 31c, and 31d of the connection portion 30a are curved when viewed in plan (planar arc shape). Good. The semiconductor device 1 of FIGS. 22 and 23 is the same as the configuration of the first embodiment except that the corners 31a, 31b, 31c, and 31d of the connection portion 30a are curved. Moreover, when the connection part 30a is comprised in this way, as a structure of the semiconductor chip 2, the structure of any embodiment mentioned above is applicable. When such a connecting portion 30a is applied to the configuration of each embodiment, the region AR immediately below shown in FIGS. 5, 8, 10, 12, 12, 14, 16, 17, 19 and the like is a corner portion. Although the regions directly below 31a, 31b, 31c, and 31d have a slightly curved region structure, in this case as well, each cell portion Ca has these FIG. 5, FIG. 8, FIG. 10, FIG. 12, FIG. 17 and FIG. 19 may be used. Even in this case, the same effects as those of the above embodiments can be obtained.

  In the said embodiment, although the cell part Ca illustrated the structure which becomes a planar view rectangular shape, the shape of a cell area | region is not limited to this, For example, a polygonal shape, a circular shape, an elliptical shape etc. may be sufficient.

  In the above embodiment, the high-resistance cell portion C1 having a predetermined structure is exemplified as the cell portion of the high-resistance portion 5, and the low-resistance cell portion C2 having a higher channel density than this is exemplified as the cell portion of the low on-resistance portion 6. However, it is not limited to the example described above. The cell portion of the low on-resistance portion 6 has a larger channel density than the cell portion of the high withstand portion 5, and the cell portion of the high withstand portion 5 has a higher contact density than the cell portion of the low on-resistance portion 6. Other known configurations may be used as long as the area ratio increases.

  In the above embodiment, an N-channel type MOSFET or IGBT is exemplified, the N conductivity type is the first conductivity type, and the P conductivity type is the second conductivity type. However, the present invention is similarly applied to the P channel type MOSFET and IGBT. May be.

  In the above-described embodiment, in the semiconductor substrate 3, a configuration in which the high-tolerance portion is provided only in part or all of the internal position of the region immediately below the connection portion of the connection member, and the internal position of the region directly below and the region directly below The configuration in which the high-tolerance portion is provided at a position close to the immediate lower region (external position adjacent to the peripheral portion of the direct lower region) on the outside of the region is illustrated, but only the position adjacent to the peripheral portion of the direct lower region outside the direct region The high withstand portion 5 may be provided. In this case, it is only necessary to provide the low on-resistance portion 6 corresponding to the “outer portion” on the side farther from the region immediately below the high withstand portion 5, and inside the high withstand portion 5 (closer to the center of the immediately below region). The cell structure on the side) may be a cell structure equivalent to that of the low on-resistance portion 6 or may be a cell structure having a slightly larger tolerance than the low on-resistance portion 6.

1, 201, 301, 401, 501, 601, 701, 801, 901... Semiconductor device 3. Semiconductor substrate 5. High withstand portion 6. Low on-resistance portion 15 N-type drift layer (first conductivity type first Semiconductor layer)
17 P-type body layer (second conductivity type second semiconductor layer)
19 ... trench portion 25 ... N + type source layer (first conductivity type third semiconductor layer)
26 ... Source electrode (conductive layer)
30 ... Copper clip (connection member)
Ca ... cell part (element region)

Claims (9)

A semiconductor substrate (3) having a predetermined surface (3a) and a back surface (3b), and having a plurality of element regions (Ca) formed on at least the surface (3a) side;
A conductive layer (26) covering the surface (3a) side of the semiconductor substrate (3);
A connection member (30) having conductive connection portions (30a, 50a) disposed above the conductive layer (26) and electrically connected to a part of the upper surface portion (26a) of the conductive layer (26). , 50)
With
The conductive layer (26) is provided with contact portions (26b) connected to the element regions (Ca) of the semiconductor substrate (3),
In the semiconductor substrate (3), the connection member (30, 50) is adjacent to an internal position of a region (AR) immediately below the connection portion (30a) or a peripheral portion of the region (AR) directly below. The high-tolerance part (5) having a structure in which the avalanche resistance is higher than that of the outer part (6) disposed on the side farther from the region (AR) immediately below the predetermined area. A semiconductor device (1, 201, 301, 401, 501, 601, 701, 801, 901). A first semiconductor layer (15) of a first conductivity type provided in the semiconductor substrate (3);
A trench portion (19) formed by being dug down from the surface (3a) side of the semiconductor substrate (3);
A gate insulating film (21) formed along the inner wall surface of the trench portion (19);
A gate electrode (23) formed inside the gate insulating film (21) in the trench portion (19);
A second conductive type second semiconductor layer (17) formed above the first semiconductor layer (15) at least at a position along the trench portion (19);
On the surface (3a) side of the semiconductor substrate (3), a third semiconductor layer (first conductivity type) formed above the second semiconductor layer (17) and adjacent to the trench portion (19) ( 25)
With
The inside of the semiconductor substrate (3) is partitioned into a plurality of cell parts (Ca) by the trench part (19), and each of the cell parts (Ca) is configured as the element region, and the conductive layer (26) It is configured to be electrically connected to the contact portion (26b) of
The third semiconductor layer (25) is provided adjacent to the trench part (19) on the surface layer side of the cell part (Ca), and at least the cell part (25) than the third semiconductor layer (25). A fourth semiconductor layer (18) of the second conductivity type is provided on the center side of Ca),
In the high-resistance cell portion (C1) constituting the high-resistance portion (5) among the plurality of cell portions (Ca), the high-resistance cell when viewed in plan in the thickness direction of the semiconductor substrate (3) The ratio of the contact area where the fourth semiconductor layer (18) contacts the conductive layer (26) in the high withstand cell portion (C1) with respect to the entire area of the portion (C1) is defined as a first area ratio, In the low-resistance cell portion (C2) constituting the outer portion (6) of the cell portion (Ca), the low-resistance cell portion (C2) when viewed in plan in the thickness direction of the semiconductor substrate (3). ) When the ratio of the contact area of the fourth semiconductor layer (18) in contact with the conductive layer (26) in the low withstand cell portion (C2) is the second area ratio. The first area ratio is larger than the area ratio. The semiconductor device of claim 1, (1,201,301,401,501,601,701,801,901).   The low withstand cell portion (C2) constituting the outer portion (6) has a structure having a channel density larger than that of the high withstand cell portion (C1) constituting the high withstand portion (5). The semiconductor device (1, 201, 301, 401, 501, 601, 701, 801, 901) according to claim 2 characterized by the above-mentioned. The connection portion (30a) of the connection member (30) has an outer shape including corner portions (31a, 31b, 31c, 31d),
The high withstand portion at at least one of a position immediately below the corner (31a, 31b, 31c, 31d) in the semiconductor substrate (3) or a position adjacent to the position directly below the semiconductor substrate (3). (5) is provided, The semiconductor device (1, 201, 301, 401, 501, 601, 701) of Claim 2 or Claim 3 characterized by the above-mentioned. The high withstand portion (5) is provided along the entire circumference of the region (AR) directly below the semiconductor substrate (3),
In the semiconductor substrate (3), the avalanche resistance is lower than the cell part (Ca) of the high withstand portion (5) at the center side of the region (AR) immediately below the high withstand portion (5) and the channel density. The semiconductor device (201) according to any one of claims 2 to 4, further comprising an inner side suppressing portion (7) in which the cell portion (Ca) having a large structure is disposed. 301, 401, 501, 601, 701). The high withstand portion (5) has a plurality of types of the cell portions (Ca) having different avalanche resistance,
Along the entire periphery of the region (AR) immediately below the region (AR) of the semiconductor substrate (3), the first cell portion (Ca1) having a structure having the largest avalanche resistance among the plurality of types of cell portions (Ca). A first high withstand portion (5c) is provided,
In the semiconductor substrate (3), the avalanche is located closer to the center of the region (AR) immediately below the first high-resistance portion (5c) than the first cell portion (Ca1) of the first high-resistance portion (5c). The second high-tolerance part (5d) in which one or a plurality of types of second cell parts (Ca2) having a low withstand capacity and a large channel density is provided. 6. The semiconductor device (701) according to claim 5. The connection portion (30a) of the connection member (30) has an outer shape including corner portions (31a, 31b, 31c, 31d),
The high withstand portion at at least one of a position immediately below the corner (31a, 31b, 31c, 31d) in the semiconductor substrate (3) or a position adjacent to the position directly below the semiconductor substrate (3). (5) is provided In the peripheral portion of the region (AR) immediately below, the avalanche resistance is lower and the channel density is higher than the cell portion (Ca) of the high resistance portion (5) at a position away from the position immediately below. 4. The semiconductor device (501, 601) according to claim 2 or 3, wherein a peripheral edge side suppressing portion (8) in which the cell portion (Ca) of the structure is arranged is provided. The high withstand portion (5) has a plurality of types of the cell portions (Ca),
The plurality of types at least one of a position immediately below the corners (31a, 31b, 31c, 31d) in the semiconductor substrate (3) and a position adjacent to the position directly below the semiconductor substrate (3) A first high-resistance portion (5a) configured by the first cell portion (Ca1) having the largest avalanche resistance among the cell portions (Ca) of
In the semiconductor substrate (3), the avalanche is located closer to the center of the region (AR) immediately below the first high-resistance portion (5a) than the first cell portion (Ca1) of the first high-resistance portion (5a). 8. The second high-resistance portion (5 b) in which one or a plurality of types of second cell portions (Ca 2) having a low withstand capacity and a high channel density is provided. 9. Semiconductor device (601).   The whole cell portion (Ca) in the region (AR) directly below the semiconductor substrate (3) is configured as the high withstand portion (5). Semiconductor device (1, 301).

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