JP7263978B2 - semiconductor equipment - Google Patents

Description

The technology disclosed in this specification relates to a semiconductor device.

The semiconductor device disclosed in Patent Document 1 includes a semiconductor substrate having an element region and a peripheral region arranged around the element region. This semiconductor device includes a plurality of trenches provided on the upper surface of a semiconductor substrate within an element region, a gate insulating film covering the inner surface of each trench, a gate electrode disposed within each trench, and a semiconductor substrate within the element region. has an upper electrode in contact with the upper surface of the semiconductor substrate and a lower electrode in contact with the lower surface of the semiconductor substrate. The element region has an n-type emitter region, a p-type body region, an n-type drift region, and a p-type collector region. A peripheral drift region connected to the drift region in the element region is provided in the peripheral region.

JP 2017-028069 A

When a potential equal to or higher than the gate threshold is applied to the gate electrode, a channel is formed in the body region in contact with the gate insulating film. Then, electrons flow from the upper electrode to the lower electrode via the emitter region, channel, drift region and collector region. This turns on the semiconductor device. When the semiconductor device is on, holes are supplied from the collector region into the drift region and accumulated in the drift region.

When the semiconductor device turns off, holes accumulated in the drift region flow toward the upper electrode. At this time, the holes accumulated in the drift region of the outer peripheral region tend to flow to the upper electrode through the end of the body region in the element region (that is, the portion of the body region near the outer peripheral region). Therefore, in the element region near the outer peripheral region (hereinafter referred to as the peripheral portion), the density of holes flowing to the upper electrode is higher than in the central portion of the element region. As a result, avalanche breakdown is likely to occur in the peripheral portion. Since the area where holes can flow is narrower in the peripheral area than in the central area, if avalanche breakdown occurs in the peripheral area, the temperature in the peripheral area tends to rise. Therefore, if avalanche breakdown occurs in the peripheral portion, the avalanche resistance is low. This specification proposes a technique for reducing the load applied to the periphery and improving the avalanche resistance.

A semiconductor device disclosed in this specification includes a semiconductor substrate, an upper electrode, a lower electrode, a plurality of trenches, a gate insulating film, and a gate electrode. The semiconductor substrate has an element region and an outer peripheral region arranged around the element region. The upper electrode is in contact with the upper surface of the semiconductor substrate within the element region. The lower electrode is in contact with the lower surface of the semiconductor substrate. The plurality of trenches are provided on the upper surface of the semiconductor substrate within the element region. The gate insulating film covers the inner surface of each trench. The gate electrode is arranged in each trench and is insulated from the semiconductor substrate by the gate insulating film. The element region has an emitter region, a body region, a drift region and a collector region. The emitter region is an n-type region in contact with the upper electrode and in contact with the gate insulating film. The body region is a p-type region in contact with the upper electrode and in contact with the gate insulating film below the emitter region. The drift region is an n-type region in contact with the gate insulating film under the body region and separated from the emitter region by the body region. The collector region is a p-type region in contact with the bottom electrode and separated from the body region by the drift region. The outer peripheral region has an outer peripheral drift region connected to the drift region. The element region has a first element region and a second element region arranged around the first element region and adjacent to the outer peripheral region. A lifetime control region having a higher crystal defect density than the surrounding drift region is provided in the drift region in the second element region. The lifetime control region is not provided within the drift region within the first element region.

In the semiconductor device described above, the lifetime control region is provided within the drift region within the second element region (that is, the peripheral portion) adjacent to the outer peripheral region. The lifetime control region functions as a recombination center for holes. Therefore, holes have a short lifetime in the drift region in the second element region. Therefore, excessive accumulation of holes in the second element region (that is, the element region in the vicinity of the outer peripheral region) is suppressed when the semiconductor device is on. Therefore, when the semiconductor device is turned off, the density of holes flowing through the second element region to the upper electrode is reduced. As a result, avalanche breakdown is less likely to occur in the second element region. A lifetime control region is not provided in the drift region in the first element region. Therefore, in this semiconductor device, avalanche breakdown is more likely to occur in the first element region (that is, central portion) than in the second element region. In the first element region, the region through which holes can flow is wide. Therefore, if avalanche breakdown occurs in the central portion, the temperature in the central portion is unlikely to rise. Therefore, the above semiconductor device has a high avalanche resistance.

FIG. 2 is a plan view of the semiconductor device of Example 1; Sectional drawing in the II-II line of FIG. FIG. 3 is a cross-sectional view of the semiconductor device of Example 2 (a view corresponding to FIG. 2); FIG. 3 is a cross-sectional view of the semiconductor device of Example 3 (a view corresponding to FIG. 2);

(Example 1)
1 and 2 show a semiconductor device 10 of Example 1. FIG. The semiconductor device 10 is an IGBT (Insulated Gate Bipolar Transistor) and has a semiconductor substrate 12 . The semiconductor substrate 12 is made of a semiconductor material such as Si or SiC, for example. As shown in FIG. 1, the semiconductor substrate 12 has an element region 14 and an outer peripheral region 16 . The element region 14 is arranged in the central portion of the semiconductor substrate 12 . The peripheral region 16 is arranged around the element region 14 . The element region 14 is a region in which an IGBT structure is formed.

FIG. 2 is a cross-sectional view taken along line II-II of FIG. In FIG. 2 , the left side is the center side of the semiconductor substrate 12 and the right side is the outer peripheral side of the semiconductor substrate 12 . As shown in FIG. 2, an upper electrode 70 is arranged on the upper surface 12a of the semiconductor substrate 12. As shown in FIG. The upper electrode 70 is in contact with the upper surface 12 a of the semiconductor substrate 12 in a range extending from the element region 14 to part of the outer peripheral region 16 . A lower electrode 72 is arranged on the lower surface 12 b of the semiconductor substrate 12 . The lower electrode 72 covers substantially the entire lower surface 12 b of the semiconductor substrate 12 .

A plurality of trenches 22 are provided in the upper surface 12 a of the semiconductor substrate 12 . Each trench 22 extends parallel to each other in a direction perpendicular to the plane of FIG. A plurality of trenches 22 are provided in each of the element region 14 and the peripheral region 16 . Two adjacent trenches 22 may be connected at a position not shown. That is, when the semiconductor substrate 12 is viewed from above, the trenches 22 may be formed in a grid pattern. The inner surface of each trench 22 is covered with a gate insulating film 24 . A gate electrode 26 is disposed within each trench 22 . Each gate electrode 26 is insulated from the semiconductor substrate 12 by a gate insulating film 24 . The surface of each gate electrode 26 is covered with an interlayer insulating film 28 . Each gate electrode 26 is insulated from the upper electrode 70 by an interlayer insulating film 28 .

An emitter region 30 , a body region 32 , a drift region 34 and a collector region 36 are provided inside the semiconductor substrate 12 in the element region 14 .

Emitter region 30 is an n-type region. Each emitter region 30 is exposed on the upper surface 12 a of the semiconductor substrate 12 and is in ohmic contact with the upper electrode 70 . Each emitter region 30 is in contact with the gate insulating film 24 .

Body region 32 is a p-type region. A body region 32 abuts each emitter region 30 . Body region 32 extends from a range sandwiched between two emitter regions 30 to below each emitter region 30 . The body region 32 has a contact region 32a and a main body region 32b. Contact region 32a has a higher p-type impurity concentration than main body region 32b. The contact region 32 a is arranged in a range sandwiched between the two emitter regions 30 . The contact region 32 a is in ohmic contact with the upper electrode 70 . Main body region 32 b is in contact with gate insulating film 24 on the side surface of trench 22 . The main body region 32 b is in contact with the gate insulating film 24 below the emitter region 30 .

Drift region 34 is an n-type region. Drift region 34 is located below body region 32 and is separated from emitter region 30 by body region 32 . The drift region 34 is in contact with the gate insulating film 24 at the lower end portion of the trench.

Collector region 36 is a p-type region. Collector region 36 is arranged below drift region 34 . Collector region 36 is exposed at bottom surface 12 b of semiconductor substrate 12 . Collector region 36 is in ohmic contact with bottom electrode 72 .

An n-type region 31 , a breakdown voltage region 40 , and an outer drift region 42 are provided inside the semiconductor substrate 12 in the outer peripheral region 16 . The n-type region 31 has a structure similar to that of the emitter region 30 within the element region 14 . The breakdown voltage region 40 is a p-type region. Withstand voltage region 40 extends from upper surface 12 a of semiconductor substrate 12 to below trench 22 . Withstand voltage region 40 is arranged to cover n-type region 31 and trench 22 . The outer drift region 42 is an n-type region. The outer drift region 42 is arranged below the breakdown voltage region 40 . Perimeter drift region 42 does not contact trench 22 . The outer drift region 42 is connected to the drift region 34 within the device region 14 . The outer drift region 42 has substantially the same n-type impurity concentration as the drift region 34 within the element region 14 . A collector region 36 is provided below the outer drift region 42 .

The element region 14 has a first element region 14a and a second element region 14b. The first element region 14 a is arranged in the central portion of the element region 14 . The second element region 14 b is arranged around the first element region 14 a (that is, closer to the outer edge of the semiconductor substrate 12 than the first element region 14 a ) and is adjacent to the outer peripheral region 16 .

A lifetime control region 80 is provided in the drift region 34 in the second element region 14b. The lifetime control region 80 is a region with a higher crystal defect density than the drift region 34 surrounding it. The lifetime control regions 80 are distributed in layers in the planar direction of the semiconductor substrate 12 . Although the depth at which the lifetime control region 80 is provided is not particularly limited, in this embodiment, the lifetime control region 80 is located between the lower end of the trench 22 and the lower end of the withstand voltage region 40 in the outer peripheral region 16. provided in depth. The lifetime control region 80 is formed by implanting charged particles into the semiconductor substrate 12 . The lifetime control region 80 is not provided in the drift region 34 in the first element region 14a and in the outer drift region 42 .

When the semiconductor device 10 is used, a potential higher than that of the upper electrode 70 is applied to the lower electrode 72 . A channel is formed in the body region 32 in contact with the gate insulating film 24 when a potential higher than the gate threshold value (that is, a gate-emitter potential) is applied to the gate electrode 26 . In the device region 14, a channel connects the emitter region 30 and the drift region 34. FIG. Electrons therefore flow from the upper electrode 70 to the lower electrode 72 via the emitter region 30 , the channel, the drift region 34 and the collector region 36 . Also, holes flow into the drift region 34 from the collector region 36 . The inflow of holes into the drift region 34 reduces the resistance of the drift region 34 and allows electrons to flow through the drift region 34 with low loss. Also, in the outer peripheral region 16 , holes flow from the collector region 36 into the outer peripheral drift region 42 .

After that, when the potential of the gate electrode 26 is lowered, the channel disappears and the semiconductor device 10 is turned off. Then, holes accumulated in the drift region 34 and the outer drift region 42 while the semiconductor device 10 is on are discharged to the upper electrode 70 through the contact region 32a. At this time, the holes accumulated in the outer drift region 42 of the outer peripheral region 16 move through the edge of the body region 32 in the element region 14 (that is, the body region 32 of the second element region 14b) as indicated by an arrow 90. It tries to flow through to the upper electrode 70 . Holes accumulated in the drift region 34 in the second element region 14 b also flow to the upper electrode 70 through the body region 32 of the second element region 14 b as indicated by arrow 92 . Therefore, the hole density tends to increase in the second element region 14b. However, in this embodiment, the lifetime control region 80 is provided in the drift region 34 of the second element region 14b. Therefore, in the second element region 14b, holes have a short lifetime, and the accumulation of holes in the drift region 34 of the second element region 14b is suppressed when the semiconductor device 10 is on. . Therefore, in the semiconductor device 10 of this embodiment, the density of holes flowing through the second element region 14b to the upper electrode 70 is low when the semiconductor device 10 is turned off. As a result, avalanche breakdown is less likely to occur in the second element region 14b. On the other hand, the lifetime control region 80 is not provided in the drift region 34 in the first element region 14a. Therefore, in the semiconductor device 10, avalanche breakdown is more likely to occur in the first element region 14a than in the second element region 14b. The first element region 14a (that is, the central portion of the semiconductor substrate 12) has a wide region through which holes can flow. Therefore, even if avalanche breakdown occurs in the first element region 14a, the temperature of the first element region 14a is unlikely to rise excessively. Therefore, the semiconductor device 10 of this embodiment has a high avalanche resistance.

(Example 2)
FIG. 3 shows a semiconductor device 100 of Example 2. As shown in FIG. Below, the same reference numerals are given to the same elements as in the first embodiment, and the description thereof will be omitted. The semiconductor device 100 of Example 2 differs from the semiconductor device 10 of Example 1 in the configuration of the collector region 36 .

As shown in FIG. 3, in the semiconductor device 100, the collector region 36 in the element region 14 has a first collector region 36a and a second collector region 36b. The first collector region 36a is arranged within the first element region 14a. The second collector region 36b is arranged within the second element region 14b. The p-type impurity concentration of the second collector region 36b is lower than the p-type impurity concentration of the first collector region 36a. That is, in the semiconductor device 100 of this embodiment, the p-type impurity concentration of the second collector region 36b in the second element region 14b located near the outer peripheral region 16 is relatively low.

In the semiconductor device 100 of this embodiment, the second collector region 36b has a low p-type impurity concentration. Therefore, the amount of holes supplied from the second collector region 36b into the drift region 34 is small when the semiconductor device 100 is on. As a result, in the second element region 14b, compared to the central portion of the semiconductor substrate 12 (that is, the first element region 14a), the amount of holes accumulated in the drift region 34 is relatively small. The occurrence of avalanche breakdown in the two-element region 14b is further suppressed. Therefore, in the semiconductor device 100, avalanche breakdown is more likely to occur in the first element region 14a. Therefore, the semiconductor device 100 has high avalanche resistance.

(Example 3)
FIG. 4 shows a semiconductor device 200 of Example 3. As shown in FIG. In the semiconductor device 200 of Example 3, the spacing S1 between two adjacent trenches 22 in the first element region 14a and the spacing S2 between two adjacent trenches 22 in the second element region 14b are different. The spacing S2 within the second element region 14b is wider than the spacing S1 within the first element region 14a. Note that when the trenches 22 are provided in a grid pattern when the semiconductor substrate 12 is viewed from above, the area of the unit grid in the second element region 14b is the area of the unit grid in the first element region 14a. The trench 22 may be provided to be larger than .

In the semiconductor device 200 of this embodiment, since the space S2 is relatively wide, the holes supplied from the collector region 36 easily escape to the upper electrode 70 when the semiconductor device 200 is on. Therefore, holes are less likely to accumulate in the drift region 34 of the second element region 14b when the semiconductor device 200 is on. Furthermore, when the semiconductor device 200 is turned off, the holes accumulated in the drift region 34 of the second element region 14b flow toward the upper electrode 70 over a wide area, so the density of the holes flowing through the second element region 14b is high. hard to be Therefore, avalanche breakdown is less likely to occur in the second element region 14b, and the avalanche resistance can be improved. Note that the configuration of this embodiment may be employed in the semiconductor device 100 of the second embodiment.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or in the drawings exhibit technical utility either singly or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in this specification or drawings achieve multiple purposes at the same time, and achieving one of them has technical utility in itself.

10: Semiconductor device 12: Semiconductor substrate 12a: Upper surface 12b: Lower surface 14: Element region 14a: First element region 14b: Second element region 16: Peripheral region 22: Trench 24: Gate insulating film 26: Gate electrode 28: Interlayer insulation Film 30: emitter region 31: n-type region 32: body region 32a: contact region 32b: main body region 34: drift region 36: collector region 40: breakdown voltage region 42: peripheral drift region 70: upper electrode 72: lower electrode 80: Lifetime control area

Claims (3)

A semiconductor device,
a semiconductor substrate having an element region and a peripheral region arranged around the element region;
an upper electrode in contact with the upper surface of the semiconductor substrate within the element region;
a lower electrode in contact with the lower surface of the semiconductor substrate;
a plurality of trenches provided in the upper surface of the semiconductor substrate in the element region;
a gate insulating film covering the inner surface of each trench;
a gate electrode disposed in each trench and insulated from the semiconductor substrate by the gate insulating film;
and
the element region,
an n-type emitter region in contact with the upper electrode and in contact with the gate insulating film;
a p-type body region in contact with the upper electrode and in contact with the gate insulating film below the emitter region;
an n-type drift region in contact with the gate insulating film under the body region and separated from the emitter region by the body region;
a p-type collector region in contact with the bottom electrode and separated from the body region by the drift region;
and
The peripheral region has an n-type peripheral drift region connected to the drift region,
the element region includes a first element region and a second element region arranged around the first element region and adjacent to the outer peripheral region;
the collector region is distributed over the first element region, the second element region, and the outer periphery region under the drift region and the outer periphery drift region;
a lifetime control region having a higher crystal defect density than the drift region surrounding it is provided in the drift region in the second element region;
the lifetime control region is not provided in the drift region in the first element region;
semiconductor device. 2. The semiconductor device according to claim 1, wherein the p-type impurity concentration of said collector region in said second element region is lower than the p-type impurity concentration of said collector region in said first element region. 3. The semiconductor device according to claim 1, wherein an interval between two adjacent trenches in said second element region is wider than an interval between two adjacent trenches in said first element region.

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