JP2016225583A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new arrangement constitution with an SJ-MOSFET part and an IGBT part in one semiconductor chip, in addition to mounting of the SJ-MOSFET part and an IGBT part on one semiconductor chip.SOLUTION: The semiconductor device includes: a semiconductor substrate; at least two super-junction transistor regions mounted on the semiconductor substrate; and at least one IGBT region provided in a region sandwiched between at least two of the super-junction transistor regions in a cross section cut within a plane perpendicular to the semiconductor substrate.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device.

Conventionally, a semiconductor chip having a super-junction MOSFET and a semiconductor chip having an insulated gate bipolar transistor have been connected in parallel (for example, see Patent Document 1). Note that super junction is abbreviated as SJ below. The insulated gate bipolar transistor (Insulated Gate Bipolar Transistor) is abbreviated as IGBT below. Conventionally, an SJ-MOSFET structure having a p + collector layer is known (see, for example, Patent Document 2). Furthermore, conventionally, an IGBT and an SJ-MOSFET are connected in parallel (for example, see Patent Document 3).
[Prior art documents]
[Patent Literature]
[Patent Document 1] JP 2014-130909 [Patent Document 2] JP 2013-102111 [Patent Document 3] JP 2012-142537

  However, in Patent Document 1, a semiconductor chip having an SJ-MOSFET and a semiconductor chip having an IGBT are connected by wiring to form a module. Therefore, the module cannot be reduced in size compared with the case where the SJ-MOSFET and the IGBT are formed on one semiconductor chip. Further, in Patent Document 2, SJ-MOSFET cells including a p + collector layer are arranged in a staggered pattern or a stripe pattern in plan view. That is, the SJ-MOSFET cells including the p + collector layer in the semiconductor chip are uniformly arranged over the entire semiconductor chip. In the present specification, a novel configuration of an SJ-MOSFET and an IGBT is provided in one semiconductor chip having an SJ-MOSFET and an IGBT.

  In the first aspect of the present invention, a semiconductor substrate, two or more superjunction transistor regions provided on the semiconductor substrate, and two or more superjunction transistor regions in a cross section cut along a plane perpendicular to the semiconductor substrate. A semiconductor device is provided that includes one or more IGBT regions provided in a region sandwiched between the two.

  The IGBT region may be provided in a region surrounded by the superjunction transistor region. Moreover, you may further provide the pressure | voltage resistant structure part provided in the outer side of the outermost super junction type transistor area | region among super junction type transistor areas.

  The superjunction transistor region has a first conductivity type column and a second conductivity type column, and the breakdown voltage structure portion has a first breakdown voltage portion provided in the inner peripheral portion and a second breakdown voltage portion provided in the outer peripheral portion. The second breakdown voltage portion of the breakdown voltage structure section may include a first conductivity type region and a second conductivity type column. The depth of the end portion of the second conductivity type column in the second withstand voltage portion of the breakdown voltage structure portion may be shallower than the depth of the end portion of the second conductivity type column in the superjunction transistor region.

  The breakdown voltage of the IGBT region may be higher than the breakdown voltage of the super junction transistor region. An IGBT portion having two or more IGBT regions may be provided in a region sandwiched between superjunction transistor regions. Further, an SJ-MOSFET portion including two or more superjunction transistor regions may be provided on both sides of the IGBT portion.

  A lifetime killer may be injected into the drift region at the boundary between the IGBT region and the superjunction transistor region. Instead, the IGBT region has a drift region of the first conductivity type, and a second conductivity type column is provided at the boundary between the IGBT region and the superjunction transistor region from the front surface side to the back surface side of the drift region. May be. In place of this, a dummy gate electrode may be provided on the surface side of the semiconductor substrate in the drift region at the boundary between the IGBT region and the superjunction transistor region.

  Alternatively, a second conductivity type well extended in a direction parallel to the surface of the semiconductor substrate may be provided at the boundary between the IGBT region and the superjunction transistor region. Instead, the superjunction transistor region has a first conductivity type column and a second conductivity type column, and the second conductivity of the superjunction transistor region at the boundary between the IGBT region and the superjunction transistor region. You may have the 2nd conductivity type column of the edge part depth shallower than the depth of the edge part of a type | mold column. Furthermore, instead of this, at the boundary between the IGBT region and the super junction transistor region, there are two gate electrodes, a first conductivity type region provided between the two gate electrodes, and a first conductivity type region. A second conductivity type region that is ½ the depth of the second conductivity type column of the superjunction transistor region may be provided on the back side of the first conductivity type region.

  In the semiconductor device, the boundary portion between the IGBT portion having two or more IGBT regions and the SJ-MOSFET portion including two or more superjunction transistor regions may have a free-wheeling diode portion. A lifetime killer may be injected into the SJ-MOSFET section.

  The SJ-MOSFET section has a first conductivity type column and a second conductivity type column, the surface side of the first conductivity type column and the second conductivity type column in the SJ-MOSFET section, and a field stop layer in the SJ-MOSFET section A lifetime killer may be injected into at least one of the above.

  A lifetime killer may be injected from the surface side of the first conductivity type column and the second conductivity type column in the SJ-MOSFET portion to the field stop layer in the SJ-MOSFET portion.

  A lifetime killer may be injected at the boundary between the freewheeling diode portion and the SJ-MOSFET portion. A lifetime killer may be injected into the freewheeling diode section. A lifetime killer may be injected into at least one of the anode side and the field stop layer in the drift region of the free-wheeling diode portion.

  The semiconductor device may further include a repetitive structure portion in which a freewheeling diode portion and an SJ-MOSFET portion are periodically provided. A repetitive structure portion may be provided across the IGBT portion.

  A lifetime killer may be injected between at least one of the IGBT part and the repetitive structure part and the field stop layer in the IGBT part.

  The IGBT portion may be an SJ-IGBT portion in which the IGBT region is configured by a super junction transistor.

The SJ-IGBT section may include a first conductivity type column and a second conductivity type column each having an impurity concentration of 1E15 cm ⁻³ or more and 1E16 cm ⁻³ or less.

  The pitch between the second conductive type semiconductor layer provided on the back side of the SJ-IGBT part and the first conductive type semiconductor layer provided on the back side of the free wheel diode part and the SJ-MOSFET part is SJ-IGBT part. The pitch may be 5 to 1000 times the pitch between the first conductivity type column and the second conductivity type column.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

1 is a plan view of a semiconductor device 200 as viewed from the surface of a semiconductor substrate 100. FIG. FIG. 3 is a cross-sectional view of the semiconductor device 200 cut along A1-A2 in FIG. 1 in parallel with the xz plane. 2 is a plan view in which an end portion of a semiconductor device 200 is cut along C1-C2 in parallel with an xz plane in a region B of FIG. A plan view (a) cut along D1-D2 in FIG. 3 parallel to the xy plane in region B of FIG. 1, and E1-E2 in FIG. 3 parallel to the xy plane in region B of FIG. A cut plan view (b) is shown. 1 is a plan view of a semiconductor device 300 as viewed from the surface of a semiconductor substrate 100. FIG. 1 is a plan view of a semiconductor device 400 as viewed from the surface of a semiconductor substrate 100. FIG. This is a first modification of the boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20. This is a second modification of the boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20. This is a third modification of the boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20. This is a fourth modification of the boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20. This is a fifth modification of the boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20. 5 is a diagram illustrating a first example in which an FWD unit 13 is provided between an SJ-MOSFET unit 10 and an IGBT unit 20. FIG. It is the comparative example 1 which provided the FWD part 13 and the IGBT part 20. FIG. It is the comparative example 2 which provided the SJ-MOSFET part 10 and the IGBT part 20. FIG. It is a graph which shows the voltage-current characteristic at the time of the gate-off in FIGS. 5 is a diagram illustrating a second example in which an FWD unit 13 is provided between an SJ-MOSFET unit 10 and an IGBT unit 20. FIG. 2 is a diagram illustrating a first example of an SJ-MOSFET section 10 and an FWD section 13. FIG. 5 is a diagram illustrating a second example of an SJ-MOSFET section 10 and an FWD section 13. FIG. 6 is a diagram illustrating a third example of an SJ-MOSFET section 10 and an FWD section 13. FIG. 7 is a diagram illustrating a fourth example of an SJ-MOSFET section 10 and an FWD section 13. FIG. FIG. 10 is a diagram illustrating a fifth example of the SJ-MOSFET section 10 and the FWD section 13. It is a figure which shows the 6th example of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 7th example of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 8th example of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 9th example of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 10th example of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 11th example of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 12th example of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 13th example of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 14th example of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 15th example of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 16th example of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 17th example of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 18th example of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 19th example of the SJ-MOSFET part 10 and the FWD part 13. FIG. FIG. 5 is a diagram showing a first example having a repetitive structure portion 120 of an SJ-MOSFET portion 10 and an FWD portion 13. It is a figure which shows the 2nd example which has the repeating structure part 120 of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 3rd example which has the repeating structure part 120 of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the 4th example which has the repeating structure part 120 of the SJ-MOSFET part 10 and the FWD part 13. FIG. It is a figure which shows the example which replaced with the IGBT part 20 of FIG. 12, and provided the SJ-IGBT part 22. FIG. It is a figure which shows the relationship between the ratio (%) of electric charge imbalance, and a proof pressure (V) in simulation. It is a figure which shows the relationship between doping concentration (cm ^<-3 >) and pressure | voltage resistance (V) in simulation. It is a figure which shows the relationship between the distance (micrometer) from the surface 102 at the time of gate-on, and the strength of an electric field (V / cm) in simulation. It is a figure which shows the relationship between doping concentration (cm ^<-3 >) and ON voltage (V) in simulation. It is a figure which shows the relationship between ON voltage (V) and current density (A / cm < ² >) in simulation. It is a figure which shows the relationship between time (microsecond), collector-emitter voltage (V), and collector current (A) in simulation. It is the figure which expanded the part of time 0 (microsecond) or more and 1.0 (microsecond) or less of FIG.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

(First embodiment)
FIG. 1 is a plan view of the semiconductor device 200 as viewed from the surface of the semiconductor substrate 100. The semiconductor device 200 includes a semiconductor substrate 100. The semiconductor substrate 100 is provided with an SJ-MOSFET portion 10 and an IGBT portion 20. The semiconductor substrate 100 is provided with a breakdown voltage structure 30 so as to surround the SJ-MOSFET portion 10 and the IGBT portion 20 in the xy plane.

  In this specification, the x direction is a direction perpendicular to the y direction. The z direction is a direction perpendicular to a plane defined by the x direction and the y direction. The z direction is not necessarily parallel to the direction of gravity. The lengths of the semiconductor substrate 100 in the x direction and the y direction are sufficiently larger than the lengths in the z direction. In the present specification, for convenience, the + z side surface of the semiconductor substrate 100 is referred to as a front surface, and the opposite surface is referred to as a back surface. The xy plane is a plane parallel to the front surface and the back surface of the semiconductor substrate 100.

  The semiconductor device 200 of this example includes an SJ-MOSFET portion 10 and an IGBT portion 20 that are each longer in the y direction than in the x direction. That is, the SJ-MOSFET portion 10 and the IGBT portion 20 have a stripe shape that is long in the y direction. The semiconductor device 200 has a boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20.

  The semiconductor device 200 has the SJ-MOSFET portion 10 at the end in the x direction. The semiconductor device 200 has a repeated structure of the SJ-MOSFET portion 10 and the IGBT portion 20 along the x direction. In addition, the semiconductor device 200 includes the SJ-MOSFET portion 10 at the end on the opposite side in the x direction. That is, the semiconductor device 200 has the SJ-MOSFET portion 10 at both ends in the x direction in the repeating structure of the SJ-MOSFET portion 10 and the IGBT portion 20 in the x direction.

  Since the semiconductor device 200 repeatedly includes the SJ-MOSFET portion 10 and the IGBT portion 20 along the x direction, the SJ-MOSFET is cut in a cross section obtained by cutting the semiconductor device 200 along the xz plane perpendicular to the surface of the semiconductor substrate 100. An IGBT unit 20 is provided in a region sandwiched by the unit 10. The region sandwiched between the SJ-MOSFET portions 10 means a region where the IGBT portions 20 sandwiched between the two SJ-MOSFET portions 10 on both sides in the x direction are provided.

  The SJ-MOSFET portion 10 has one or more superjunction transistor regions. The IGBT unit 20 has one or more IGBT regions. However, the SJ-MOSFET portion 10 has only a superjunction transistor region and does not have an IGBT region. The IGBT unit 20 has only an IGBT region and does not have a super junction transistor region.

  In this specification, the superjunction transistor region means a minimum unit region constituting the superjunction transistor. The IGBT region means a minimum unit region constituting the IGBT. The breakdown voltage of the IGBT region is higher than the breakdown voltage of the super junction transistor region. For example, the breakdown voltage of the IGBT region is about 700V, and the breakdown voltage of the super junction transistor region is about 650V. The detailed configuration of the super junction transistor region and the IGBT region will be described in the description of the next figure.

  In this specification, a group of superjunction transistor regions having two or more superjunction transistor regions is referred to as an SJ-MOSFET portion 10. Similarly, a group of IGBT regions having two or more IGBT regions is defined as an IGBT unit 20.

  Since the semiconductor device 200 of this example repeatedly includes the SJ-MOSFET portion 10 and the IGBT portion 20 along the x direction, the superjunction transistor region and the IGBT region are provided at different locations on the semiconductor substrate 100, respectively. Specifically, one or more IGBT regions are provided in a region sandwiched by two or more superjunction transistor regions. Super junction transistor regions are provided at both ends of the semiconductor substrate 100 in the x direction.

When the power supply of the semiconductor device 200 is turned on and the drain-source voltage (V _DS ) in the superjunction transistor region and the collector-emitter voltage (V _CE ) in the IGBT region are gradually increased, a predetermined voltage value is obtained. At the boundary, the current (I _CE ) flowing through the IGBT region becomes larger than the current (I _DS ) flowing through the super junction transistor region. The load on the super junction transistor region and the IGBT region is determined by the product of the current (I _CE or I _DS ) and the voltage (V _DS or V _CE ). Therefore, when a voltage higher than the predetermined voltage value is applied, the load in the superjunction transistor region becomes smaller than the load in the IGBT region.

  When the power supply of the semiconductor device 200 is turned off, the superjunction transistor region and the IGBT region are in a reverse bias state. In reverse bias, the smaller the load in the on state, the higher the breakdown resistance. In an ON state in which a voltage higher than a predetermined voltage value is applied, the load in the superjunction transistor region is smaller than the load in the IGBT region. Therefore, at the time of reverse bias, the breakdown tolerance of the super junction transistor region is higher than the breakdown tolerance of the IGBT region.

  In the semiconductor substrate 100, the superjunction transistor region and the IGBT region are electrically connected in parallel. The superjunction transistor region functions as a diode during reverse recovery. If there are too few superjunction transistor regions, the semiconductor device 200 has hard recovery characteristics during reverse recovery. Therefore, a certain number of superjunction transistor regions are required to obtain a certain degree of soft recovery characteristics. Further, if the number of super junction transistor regions is more than the number of IGBT regions, the characteristics of the IGBT in the semiconductor device 200 are lost. Therefore, a balance between the two is required.

  The semiconductor device 200 includes an IGBT unit 20 having two or more IGBT regions in a region sandwiched between superjunction transistor regions. For example, in the SJ-MOSFET portion 10 and the IGBT portion 20, two super junction transistor regions and two IGBT regions may be provided, respectively. The ratio of the number of IGBT regions in the IGBT unit 20 and the number of superjunction transistor regions in the SJ-MOSFET unit 10 varies depending on the application of the product, but is preferably 1: 1 to 3: 1.

  In this example, instead of every other super junction transistor region and IGBT region, a plurality of super junction transistor regions and IGBT regions are provided. Thereby, the ratio of the boundary part 12 can be reduced compared with the case where both are provided every other.

  In the semiconductor device 200 having the superjunction transistor region and the IGBT region on the semiconductor substrate 100, the output characteristics of the superjunction transistor region can be obtained in the low voltage region, and the output characteristics of the IGBT region can be obtained in the high voltage region. Is preferred. However, in a configuration in which every other superjunction transistor region and IGBT region are alternately provided, abnormal voltage-current characteristics (that is, jumping in characteristics) occur due to interference between the superjunction transistor region and the IGBT region. Can occur. Therefore, a configuration in which every other super junction transistor region and IGBT region are alternately provided is not desirable. In this example, since the SJ-MOSFET portion 10 having two or more superjunction transistor regions and the IGBT portion 20 having two or more IGBT regions are provided, every other superjunction transistor region and IGBT region are alternately arranged. Compared with the configuration provided in the circuit, abnormal voltage-current characteristics (characteristic skip) can be suppressed.

  FIG. 2 is a cross-sectional view of the semiconductor device 200 cut along A1-A2 in FIG. 1 parallel to the xz plane. The semiconductor device 200 in the cross-sectional view includes an SJ-MOSFET portion 10, an IGBT portion 20, a boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20, and a breakdown voltage structure portion 30. In this example, the first conductivity type is described as n-type, and the second conductivity type is described as p-type. However, in another example, the first conductivity type may be p-type and the second conductivity type may be n-type by inverting it. Unless an element and a production method are particularly specified, the n-type and the p-type of the semiconductor substrate 100 can be formed using a known element and a known production method.

  The SJ-MOSFET portion 10 has two or more superjunction transistor regions 14. In this example, the SJ-MOSFET section 10 has five superjunction transistor regions 14. However, only the two superjunction transistor regions 14-1 and 14-2 are denoted by reference numerals in consideration of the visibility of the figure. Superjunction transistor region 14 includes a p-type base layer 42, a contact region 44, a source region 45, a gate electrode 50, a gate insulating film 52, and an n-type column 54 and a p-type column 56 that are adjacent in the x direction. .

  In this example, the p-type base layer 42 has a p− type impurity, the contact region 44 has a p + type impurity, and the source region 45 has an n + type impurity. Further, the n-type column 54 adjacent in the x direction has an n-type impurity, and the p-type column 56 has a p-type impurity.

  Two adjacent superjunction transistor regions 14-1 and 14-2 share one n-type column 54 or one p-type column 56. In this example, the superjunction transistor regions 14-1 and 14-2 share one n-type column 54. Two adjacent superjunction transistor regions 14-1 and 14-2 share one gate electrode 50 and gate insulating film 52.

  The IGBT unit 20 has two or more IGBT regions 24. In the portion shown in FIG. 2, the IGBT unit 20 has six IGBT regions 24. However, only the two IGBT regions 24-1 and 24-2 are denoted by reference numerals in consideration of the visibility of the figure. The IGBT region 24 includes a p-type base layer 42, a contact region 44, an emitter region 46, a gate electrode 50, a gate insulating film 52, and an n-type drift layer 40. The emitter region 46 has an n + type impurity.

  Two adjacent IGBT regions 24-1 and 24-2 share the n-type drift layer 40. Two adjacent IGBT regions 24-1 and 24-2 share one gate electrode 50 and gate insulating film 52.

  In order to make the breakdown voltage of the superjunction transistor region lower than the breakdown voltage of the IGBT region at the time of reverse bias, the interval between the gate electrodes 50 of the adjacent IGBT regions is set as necessary between the adjacent superjunction transistor regions. Adjustment can be made by making the distance between the gate electrodes 50 wider. Also, the breakdown voltage of the IGBT region can be increased by reducing the impurity concentration of the n-type drift layer 40 in the IGBT region.

  (Boundary part 12) The n-type drift layer 40 of the boundary part 12 of this example has a larger amount of carriers than the n-type column 54 of the SJ-MOSFET part 10 when a forward voltage is applied to the semiconductor device 200 to turn it on. This is a region having a smaller amount of carriers than the n-type drift layer 40 of the IGBT unit 20. The carriers in the IGBT region 24 are holes and electrons, and the carriers in the superjunction transistor region 14 are only electrons. Therefore, when the semiconductor device 200 is operated at a forward voltage, the amount of carriers in the IGBT region 24 is larger than the amount of carriers in the superjunction transistor region 14. For example, the amount of carriers in the IGBT region 24 is an order of magnitude greater than the amount of carriers in the superjunction transistor region 14.

  At the time of reverse bias, if there is no boundary 12 and the SJ-MOSFET portion 10 and the IGBT portion 20 are joined and continuous, the n-type drift at the boundary portion between the SJ-MOSFET portion 10 and the IGBT portion 20 The layer 40 is a portion where the carrier amount changes abruptly. In this case, since the electric field is strongly applied to the n-type drift layer 40 in the boundary portion, the semiconductor device 200 may be broken down and destroyed.

  Therefore, a region having an intermediate carrier amount between the carrier amount of the n-type column 54 and the carrier amount of the n-type drift layer 40 when a forward voltage is applied is provided in the n-type drift layer 40 of the boundary portion 12. In this example, the n-type drift layer 40 as a drift region in the boundary portion 12 between the IGBT region 24 and the superjunction transistor region 14 has a defect region 58 in which a lifetime killer is implanted. The lifetime killer is implanted means that a defect region having lattice defects in the n-type drift layer 40 by injecting an electron beam, proton or helium from the front surface side and / or the back surface side of the semiconductor substrate 100 in the manufacturing stage. 58 may be formed.

  Since the boundary portion 12 has the defect region 58, the change in the amount of carriers between the n-type column 54 and the n-type drift layer 40 can be smoothed when the semiconductor device 200 is reverse-biased. Therefore, it is possible to prevent electric field concentration in the n-type drift layer 40 in the boundary portion 12 during reverse bias and to prevent the semiconductor device 200 from being destroyed.

  (Surface Structure) The structure on the surface side of the semiconductor substrate 100 is the same between the SJ-MOSFET portion 10 and the IGBT portion 20. The gate electrode 50 of this example is a trench type gate electrode. The gate electrode 50 is electrically insulated from the semiconductor substrate 100 by the gate insulating film 52. The p-type base layer 42 and the contact region 44 are provided between the two gate electrodes 50.

  In the super junction transistor region 14, a source region 45 is provided between the contact region 44 and the gate electrode 50. In the IGBT region 24, an emitter region 46 is provided between the contact region 44 and the gate electrode 50.

  The insulating layer 60 is provided on the surface side of the gate electrode 50. The surface electrode 62 is provided on the surface side of the insulating layer 60. The surface electrode 62 is in contact with at least the contact region 44 among the contact region 44, the source region 45, and the emitter region 46.

  The structure on the surface side of the boundary portion 12 is substantially the same as that of the SJ-MOSFET portion 10 and the IGBT portion 20. However, the emitter region 46 is not provided between the boundary portion 12 and the IGBT portion 20. This prevents the boundary portion 12 from operating as the IGBT region 24.

(Back Structure) The FS layer 70 is a field stop layer. The FS layer 70 may be formed by performing heat treatment by dosing protons (H ⁺ ) or selenium (Se). The FS layer 70 in this example is an n + region. The FS layer 70 prevents the depletion layer from reaching the collector layer 80 when the semiconductor device 200 is reverse-biased. A part of the defect region 58 is formed in the FS layer 70.

  The collector layer 80 is provided on the back side of the FS layer 70. That is, the collector layer 80 is provided on the back surface side of the FS layer 70. The collector layer 80 functions as the collector layer of the IGBT unit 20. The collector layer 80 in this example is a layer having p + type impurities.

  The drain layer 82 is provided on the back side of the FS layer 70. The drain layer 82 functions as a drain layer of the SJ-MOSFET portion 10. The drain layer 82 in this example is an n + layer.

  (Operation of SJ-MOSFET section 10) The operation of the SJ-MOSFET section 10 will be briefly described. When a predetermined voltage is applied to the gate electrode 50 of the SJ-MOSFET portion 10, an inversion layer is formed in the vicinity of the boundary between the gate insulating film 52 and the p-type base layer 42. In addition, when a forward voltage is applied to the semiconductor device 200, a predetermined voltage higher than that of the drain layer 82 is applied to the source region 45. Thus, electrons pass from the front electrode 62 to the back electrode 90 through the contact region 44, the source region 45, the inversion layer formed in the p-type base layer 42, the n-type column 54, the FS layer 70, and the drain layer 82 in this order. Flowing.

  (Operation of IGBT Unit 20) The operation of the IGBT unit 20 will be briefly described. When a predetermined voltage is applied to the gate electrode 50 of the IGBT unit 20, an inversion layer is formed in the vicinity of the boundary between the gate insulating film 52 and the p-type base layer 42. In addition, when a forward voltage is applied to the semiconductor device 200, a predetermined voltage higher than that of the collector layer 80 is applied to the emitter region 46. As a result, electrons are supplied from the emitter region 46 to the n-type drift layer 40, and holes are supplied from the collector layer 80 to the n-type drift layer 40. As a result, a current flows from the back electrode 90 to the front electrode 62.

  (Withstand Voltage Structure 30) The semiconductor device 200 includes a withstand voltage structure 30 provided outside the outermost superjunction transistor region 14 in the superjunction transistor region 14. The breakdown voltage structure 30 includes a first breakdown voltage portion 32 provided on the inner periphery in the xy plane and a second breakdown voltage portion 34 provided on the outer periphery in the xy plane. The first pressure resistant portion 32 has a guard ring 47. The guard ring 47 of this example has p + type impurities. Guard ring 47 is provided on the surface side of n-type region 48. The first pressure-resistant part 32 has a field plate 64 connected to the guard ring 47 through a slit or hole provided in the insulating layer 60. The field plate 64 and the guard ring 47 are provided in a ring shape so as to surround the SJ-MOSFET portion 10 and the IGBT portion 20 in the xy plane.

  Similar to the SJ-MOSFET section 10, the first breakdown voltage section 32 has a repeating structure of an n-type column 54 and a p-type column 56. The n-type column 54 and the p-type column 56 exist from the back surface side end portion of the n type region 48 to the front surface side end portion of the FS layer 70. The repeated structure of the n-type column 54 and the p-type column 56 can prevent the depletion layer from spreading in the xy plane direction when the semiconductor device 200 is reverse-biased. Further, since the field plate 64 collects the surface charges collected on the surface of the semiconductor substrate 100, it is possible to prevent the breakdown voltage of the semiconductor device 200 from changing due to the surface charges.

  The second withstand voltage portion 34 has an n-type region 48 as a first conductivity type region. The second breakdown voltage unit 34 has a p-type region 49 as a second conductivity type column. An n-type drift layer 40 exists between the n-type region 48 of the second breakdown voltage unit 34 and the FS layer 70. The p-type region 49 is provided in the n-type drift layer 40 at an interval. The depth of the end portion of the p-type region 49 is provided shallower than the depth of the end portion of the p-type column 56 in the superjunction transistor region 14.

  Note that the depth of the end of the p-type column 56 means the z coordinate at the end of the p-type column 56 near the FS layer 70. The depth of the end portion of the p-type region 49 means the z coordinate at the end portion on the back surface side of the p-type region 49. The shallow depth of the end means that the end is located closer to the surface of the semiconductor substrate 100 when the z coordinates of the end located on the FS layer 70 side are compared.

  The pitch width P1 of the p-type column 56 in the first breakdown voltage portion 32 and the pitch width P1 of the p-type region 49 in the second breakdown voltage portion 34 are the same pitch width. The pitch width P1 is smaller than the pitch width P2 of the p-type column 56 in the SJ-MOSFET section 10. As a result, the depletion layer can be extended to the end of the semiconductor substrate 100 at the time of reverse bias, compared with the case where the pitch width P1 of the breakdown voltage structure portion 30 is made equal to the pitch width P2 of the SJ-MOSFET portion 10. The device 200 can have a high breakdown voltage.

  Further, by making the depth of the end portion of the p-type region 49 shallower than the depth of the end portion of the p-type column 56, the n-type region in the second breakdown voltage portion 34 becomes larger than the p-type region. . Therefore, when a depletion layer at the time of reverse bias of the semiconductor device 200 spreads from the first withstand voltage portion 32 to the second withstand voltage portion 34, carriers mainly composed of electrons from the n-type drift layer 40 are present in the depletion layer. Supplied. This can prevent the depletion layer from reaching the end of the semiconductor substrate 100 in the x direction.

  FIG. 3 is a plan view in which the end portion of the semiconductor device 200 is cut along C1-C2 in parallel with the xz plane in the region B of FIG. In FIG. 3, the breakdown voltage structure 30 is particularly shown. A region that is cut in parallel to the xy plane from the contact region 44 to the end portion in the + x direction of the semiconductor substrate 100 is defined as D1-D2. Further, a region that is cut in parallel to the xy plane from the p-type column 56 to the end in the + x direction of the semiconductor substrate 100 through the p-type region 49 is defined as E1-E2.

  4 is a plan view (a) cut along D1-D2 in FIG. 3 parallel to the xy plane in region B of FIG. 1, and FIG. 3 is parallel to the xy plane in region B of FIG. The top view (b) cut | disconnected by E1-E2 is shown. As shown in the plan view (a), the guard ring 47 is provided in a ring shape surrounding the SJ-MOSFET portion 10 and the IGBT portion 20 in the xy plane. In the plan view (a), the p-type region 49 is indicated by a dotted line for comparison with the plan view (b), but the p-type region 49 does not exist in the D1-D2 cross section. As shown in the plan view (b), the p-type region 49 is provided in the n-type drift layer 40 at intervals in a lattice pattern.

(Second Embodiment)
FIG. 5 is a plan view of the semiconductor device 300 as viewed from the surface of the semiconductor substrate 100. The semiconductor device 300 is different from the first embodiment in that the SJ-MOSFET portion 10 is provided so as to surround the IGBT portion 20. That is, the IGBT region 24 is provided in a region surrounded by the superjunction transistor region 14. In this specification, the SJ-MOSFET portion 10 surrounding the IGBT portion 20 means that the SJ-MOSFET portion 10 surrounds all or all of the four sides of the IGBT portion 20 in the xy plane. Other points are the same as in the first embodiment.

  The semiconductor device 300 of this example includes a rectangular SJ-MOSFET portion 10 and an IGBT portion 20 in the xy plane. Note that the SJ-MOSFET portion 10 and the IGBT portion 20 may be rectangular or square depending on the shape of the xy plane of the semiconductor substrate 100.

  The semiconductor device 300 includes a boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20. The boundary portion 12 may be the same defect region 58 as in the first embodiment. Thereby, the change in the amount of carriers between the n-type column 54 and the n-type drift layer 40 can be made gentle during reverse bias. Therefore, electric field concentration in the n-type drift layer 40 in the boundary portion 12 can be prevented.

  As in the first embodiment, the semiconductor device 300 includes the breakdown voltage structure 30 provided outside the outermost superjunction transistor region 14 among the superjunction transistor regions 14 provided in the SJ-MOSFET portion 10. Prepare. Since the breakdown voltage structure portion 30 suppresses the spread of the depletion layer to the end portion of the semiconductor substrate 100 at the time of reverse bias, the semiconductor device 300 can have a high breakdown voltage.

(Third embodiment)
FIG. 6 is a plan view of the semiconductor device 400 as viewed from the surface of the semiconductor substrate 100. The semiconductor device 400 is different from the first and second embodiments in that the SJ-MOSFET portion 10 is provided so as to surround the plurality of IGBT portions 20. Other points are the same as those in the first and second embodiments.

  In this example, the IGBT sections 20 provided in a plurality of lattice shapes are surrounded by the SJ-MOSFET section 10. That is, the SJ-MOSFET portion 10 including two or more superjunction transistor regions is provided on both sides of the IGBT portion 20 in the x direction and the y direction, respectively. Although only four IGBT units 20 are shown in the figure, the number of IGBT units 20 may be greater than four. That is, a set of two or more SJ-MOSFET sections 10 and IGBT sections 20 may be provided alternately in the x direction and the y direction.

  The semiconductor device 400 of this example includes a rectangular SJ-MOSFET portion 10 and an IGBT portion 20 in the xy plane. Note that the SJ-MOSFET portion 10 and the IGBT portion 20 may be rectangular or square depending on the shape of the xy plane of the semiconductor substrate 100.

  The semiconductor device 400 includes a boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20. The boundary portion 12 may be the same defect region 58 as in the first embodiment. Thereby, the change in the amount of carriers between the n-type column 54 and the n-type drift layer 40 can be made gentle during reverse bias. Therefore, electric field concentration in the n-type drift layer 40 in the boundary portion 12 can be prevented.

  Similar to the first embodiment, the semiconductor device 400 includes the breakdown voltage structure 30 provided outside the outermost superjunction transistor region 14 among the superjunction transistor regions 14 provided in the SJ-MOSFET portion 10. Prepare. Since the breakdown voltage structure portion 30 suppresses the spread of the depletion layer to the end portion of the semiconductor substrate 100 at the time of reverse bias, the semiconductor device 400 can have a high breakdown voltage.

(First modification)
FIG. 7 shows a first modification of the boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20. The configuration of the boundary portion 12 in this example can be applied to the first to third embodiments. In this example, the second conductivity type column is provided from the front surface side to the back surface side of the n-type drift layer 40 as a drift region at the boundary portion 12 between the IGBT region 24 and the superjunction transistor region 14. The second conductivity type column may be the same as the p-type column 56 of the SJ-MOSFET section 10. The collector layer 80 is also provided on the back side of the p-type column 56 in the boundary portion 12.

  In this example, the p-type column 56 at the boundary 12 does not function as the superjunction transistor region 14 or the IGBT region 24 when the forward voltage is applied. Therefore, electrons do not enter the p-type column 56. However, since the collector layer 80 is also provided on the back side of the p-type column 56 at the boundary portion 12, holes may enter the p-type column 56. As a result, the carrier amount in the order of the carrier amount of the n-type drift layer 40 in the IGBT region 24, the carrier amount of the p-type column 56 in the boundary portion 12, and the carrier amount of the n-type column 54 in the superjunction transistor region 14 is reduced. Can be reduced. Therefore, the change in the amount of carriers between the n-type column 54 and the n-type drift layer 40 can be made gentle. Therefore, electric field concentration at the boundary portion 12 can be prevented.

(Second modification)
FIG. 8 is a second modification of the boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20. The configuration of the boundary portion 12 of this example can also be applied to the first to third embodiments. In this example, a dummy gate electrode 51 is provided on the surface side of the semiconductor substrate 100 of the n-type drift layer 40 as a drift region at the boundary 12 between the IGBT region 24 and the superjunction transistor region 14. The boundary between the collector layer 80 and the drain layer 82 is provided on the back surface side of the dummy gate electrode 51 in the boundary portion 12.

  The dummy gate electrode 51 is a dummy gate electrode 51 that has the same structure as the gate electrode 50 of the superjunction transistor region 14 and the IGBT region 24 but does not function as a transistor. In this example, the contact region 44, the source region 45, or the emitter region 46 is not provided in the vicinity of the dummy gate electrode 51 in the x direction in the boundary portion 12. Thus, electrons do not enter the drain layer 82 from the vicinity of the gate of the boundary portion 12 when a forward voltage is applied.

  In the IGBT region 24 closest to the boundary portion 12, holes enter the emitter region 46 from the collector layer 80 when a forward voltage is applied. In particular, when a forward voltage is applied, holes enter the emitter region 46 of the IGBT region 24 closest to the boundary portion 12 from the collector layer 80 near the boundary between the collector layer 80 and the drain layer 82. Thereby, the carrier amount in the order of the carrier amount of the n-type drift layer 40 in the IGBT region 24, the carrier amount of the n-type drift layer 40 in the boundary portion 12, and the carrier amount in the n-type column 54 in the superjunction transistor region 14. Can be reduced. Thereby, the change of the carrier amount between the n-type column 54 and the n-type drift layer 40 can be made smooth. Therefore, electric field concentration at the boundary portion 12 can be prevented.

(Third Modification)
FIG. 9 is a third modification of the boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20. The configuration of the boundary portion 12 in this example can be applied to the first to third embodiments. In this example, an extended p-type well 104 as a second conductivity type well extended in a direction parallel to the surface of the semiconductor substrate 100 is provided at the boundary 12 between the IGBT region 24 and the superjunction transistor region 14. .

  In this example, the boundary between the collector layer 80 and the drain layer 82 is provided on the back side of the boundary between the boundary portion 12 and the SJ-MOSFET portion 10. Further, the emitter region 46 is not provided on the boundary 12 side at the boundary between the boundary 12 and the IGBT unit 20.

  When the forward voltage is applied, holes enter the n-type drift layer 40 from the collector layer 80 on the back side of the boundary portion 12 toward the extended p-type well 104. Thereby, also by the said structure, the change of the carrier amount between the n-type column 54 and the n-type drift layer 40 can be made smooth like the 2nd modification. Therefore, electric field concentration at the boundary portion 12 can be prevented.

(Fourth modification)
FIG. 10 shows a fourth modification of the boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20. The configuration of the boundary portion 12 in this example can be applied to the first to third embodiments. In this example, the boundary portion 12 between the IGBT region 24 and the superjunction transistor region 14 has a second conductivity having an end depth shallower than the depth of the end portion of the second conductivity type column of the superjunction transistor region 14. Has a mold column. The boundary portion 12 of this example has the n-type region 48 and the p-type region 49 described in the examples of FIGS. In this example, the boundary between the collector layer 80 and the drain layer 82 is provided on the back side of the boundary between the boundary portion 12 and the IGBT portion 20.

  When a forward voltage is applied, electrons enter the n-type drift layer 40 from the n-type region 48 in the boundary portion 12 toward the drain layer 82. Thereby, also by the said structure, the change of the carrier amount between the n-type column 54 and the n-type drift layer 40 can be made smooth like the 2nd modification. Therefore, electric field concentration at the boundary portion 12 can be prevented.

(5th modification)
FIG. 11 shows a fifth modification of the boundary portion 12 between the SJ-MOSFET portion 10 and the IGBT portion 20. The configuration of the boundary portion 12 in this example can be applied to the first to third embodiments. In this example, the boundary 12 between the IGBT region 24 and the superjunction transistor region 14 is ½ the depth of the end of the p-type column 56 that is the second conductivity type column of the superjunction transistor region 14. A p-type region 59 is provided as a second conductivity type region having a moderately shallow end depth. Note that a contact region 44 is provided on the front surface side between adjacent gate electrodes 50 of the boundary portion 12, and an n-type region 48 as a first conductivity type region is provided on the back surface side. The p-type region 59 may be provided in contact with the n-type region 48 on the back side of the n-type region 48. A source region 45 is provided on the surface side between the contact region 44 and two adjacent gate electrodes 50. However, the source region 45 or the emitter region 46 is not provided at the boundary between the boundary portion 12 and the IGBT portion 20 and at the boundary between the boundary portion 12 and the SJ-MOSFET portion 10. Further, the boundary between the collector layer 80 and the drain layer 82 may be provided at the boundary between the boundary portion 12 and the IGBT portion 20 or may be provided at the boundary between the boundary portion 12 and the SJ-MOSFET portion 10.

  When a forward voltage is applied, electrons enter the n-type drift layer 40 from the n-type region 48 in the boundary portion 12 toward the drain layer 82. Thereby, also by the said structure, the change of the carrier amount between the n-type column 54 and the n-type drift layer 40 can be made smooth like the 2nd modification. Therefore, electric field concentration at the boundary portion 12 can be prevented.

  FIG. 12 is a diagram illustrating a first example in which the FWD unit 13 is provided between the SJ-MOSFET unit 10 and the IGBT unit 20. The semiconductor device of this example includes an FWD unit 13 at the boundary between the IGBT unit 20 and the SJ-MOSFET unit 10. The n + -type drain layer 82 is provided from the SJ-MOSFET portion 10 to between the FWD portion 13 and the IGBT portion 20. The p-type base layer 42, the n-type drift layer 40, the FS layer 70, and the collector layer 80 constitute a pn junction. The semiconductor device of this example can obtain a low Von characteristic using the SJ-MOSFET portion 10 when the current is low. In addition, a large current characteristic using the IGBT unit 20 can be obtained at a high current. Furthermore, by integrating the SJ-MOSFET portion 10, the IGBT portion 20, and the FWD portion 13 on one semiconductor chip, the semiconductor module can be reduced in size.

  FIG. 13 shows a first comparative example in which the FWD unit 13 and the IGBT unit 20 are provided. The semiconductor device of Comparative Example 1 is an example that does not have the SJ-MOSFET portion 10. FIG. 14 is a comparative example 2 in which an SJ-MOSFET portion 10 and an IGBT portion 20 are provided. The semiconductor device of Comparative Example 2 is an example that does not have the IGBT unit 20.

  FIG. 15 is a graph showing the voltage-current characteristics when the gate is turned off in FIGS. The horizontal axis is time (sec). The left side of the vertical axis is the current (A) flowing between the front electrode 62 and the back electrode 90. The right side of the vertical axis is the voltage (V) between the front electrode 62 and the back electrode 90.

  In FIG. 15, the first example shows the example of FIG. 12, the comparative example 1 shows the example of FIG. 13, and the comparative example 2 shows the example of FIG. As is apparent from FIG. 15, the gate is turned off around 2.0E-07 (sec), and the current flowing through each semiconductor device starts to decrease. Note that E represents 10 folds. E-07 means 10 to the seventh power. As apparent from the value of current (A) in FIG. 15, the reverse recovery current (Irp) in the first example was smaller than that in Comparative Example 1. That is, the first example was able to obtain better soft recovery characteristics than Comparative Example 1. Further, as apparent from the value of the voltage (V) in FIG. 15, the first example was able to make the surge voltage smaller than those of Comparative Example 1 and Comparative Example 2. Thus, in the first example of FIG. 12, soft recovery characteristics and low surge voltage characteristics can be obtained.

  FIG. 16 is a diagram illustrating a second example in which the FWD unit 13 is provided between the SJ-MOSFET unit 10 and the IGBT unit 20. In the semiconductor device of this example, the IGBT unit 20 has an SJ structure. This is different from the example of FIG. Other points are the same as the example of FIG. The semiconductor device of this example also has the same effect as the example of FIG.

  The examples of FIGS. 12 and 16 can be applied to the semiconductor device 200 or the semiconductor device 300. In this case, the pitch between the p + -type collector layer 80 and the n + -type drain layer 82 may be 200 μm or more. The pitch between the p + -type collector layer 80 and the n + -type drain layer 82 may be 5 to 1,000 times the pitch between the n-type column 54 and the p-type column 56 in the SJ-MOSFET section 10.

  17 to 35 show configuration examples of the SJ-MOSFET unit 10 and the FWD unit 13 with the IGBT unit 20 omitted. An example in which the IGBT unit 20, the SJ-MOSFET unit 10, and the FWD unit 13 are combined is shown in FIGS.

  The examples of FIGS. 17 to 35 show defects by injecting a lifetime killer into at least one of the SJ-MOSFET portion 10, the FWD portion 13, and the boundary between the SJ-MOSFET portion 10 and the FWD portion 13. This is an example in which the region 110 is formed.

  FIG. 17 is a diagram illustrating a first example of the SJ-MOSFET section 10 and the FWD section 13. In the FS layer 70 in the SJ-MOSFET portion 10 of this example, a defect region 110 is formed by injecting a lifetime killer. Thereby, compared with the case where a lifetime killer is not inject | poured, the soft recovery characteristic of the SJ-MOSFET part 10 can be improved.

  In this example, the defect region 110 is formed by implanting a lifetime killer also in the FS layer 70 of the FWD portion 13. Thereby, compared with the case where a lifetime killer is not inject | poured, the soft recovery characteristic of the FWD part 13 can be improved. As with the defect region 58, the position where the defect region 110 is formed is indicated by a plurality of crosses. In this example, a defect region is provided in the entire FS layer 70 at a predetermined depth position on the back surface side of the FS layer 70. In other drawings, a plurality of crosses indicate that the defect region 110 is uniformly formed in the layer or region in the direction perpendicular to the paper surface.

  FIG. 18 is a diagram illustrating a second example of the SJ-MOSFET section 10 and the FWD section 13. In this example, the defect region 110 is not formed in the FS layer 70 of the FWD portion 13. This is different from the example of FIG.

  FIG. 19 is a diagram illustrating a third example of the SJ-MOSFET section 10 and the FWD section 13. In the SJ-MOSFET portion 10 of this example, a defect region 110 is formed by injecting a lifetime killer into both the surface side of the n-type column 54 and the p-type column 56 and the FS layer 70. Thereby, compared with the example of FIG. 17, the soft recovery characteristic of the SJ-MOSFET part 10 can further be improved.

  In this example, the defect region 110 is formed by injecting a lifetime killer into both the anode side and the FS layer 70 in the drift region of the FWD portion 13. The anode side in the drift region of the FWD portion 13 refers to the vicinity of the boundary between the n-type drift layer 40 and the p-type base layer 42 in the n-type drift layer 40 of the FWD portion 13. In this example, compared with the example of FIG. 17, the soft recovery characteristic of the FWD part 13 can further be improved.

  FIG. 20 is a diagram illustrating a fourth example of the SJ-MOSFET section 10 and the FWD section 13. In this example, in the SJ-MOSFET portion 10, the defect region 110 is not formed on the surface side of the n-type column 54 and the p-type column 56 and the FS layer 70 of the FWD portion 13. This is different from the example of FIG.

  FIG. 21 is a diagram illustrating a fifth example of the SJ-MOSFET section 10 and the FWD section 13. In this example, the defect region 110 is not formed in the FS layer 70 of the SJ-MOSFET portion 10 and the FWD portion 13. This is different from the example of FIG. However, the soft recovery characteristics of the SJ-MOSFET portion 10 and the FWD portion 13 can be improved as compared with the case where no lifetime killer is injected.

  FIG. 22 is a diagram illustrating a sixth example of the SJ-MOSFET section 10 and the FWD section 13. In this example, a defect region 110 is formed by implanting a lifetime killer on the surface side of the n-type column 54 and the p-type column 56 in the SJ-MOSFET section 10. Thereby, compared with the case where a lifetime killer is not inject | poured, the soft recovery characteristic of the SJ-MOSFET part 10 can be improved.

  FIG. 23 is a diagram illustrating a seventh example of the SJ-MOSFET portion 10 and the FWD portion 13. In this example, a defect region 110 is formed by injecting a lifetime killer at the boundary between the SJ-MOSFET portion 10 and the FWD portion 13. This is different from the example of FIG. Since the defect region 110 is provided at the boundary between the SJ-MOSFET portion 10 and the FWD portion 13, destruction during reverse recovery can be suppressed.

  FIG. 24 is a diagram illustrating an eighth example of the SJ-MOSFET portion 10 and the FWD portion 13. In this example, a defect region 110 is formed by injecting a lifetime killer at the boundary between the SJ-MOSFET portion 10 and the FWD portion 13. This is different from the example of FIG.

  FIG. 25 is a diagram illustrating a ninth example of the SJ-MOSFET portion 10 and the FWD portion 13. In this example, a defect region 110 is formed by injecting a lifetime killer at the boundary between the SJ-MOSFET portion 10 and the FWD portion 13. This is different from the example of FIG.

  FIG. 26 is a diagram illustrating a tenth example of the SJ-MOSFET portion 10 and the FWD portion 13. In this example, a defect region 110 is formed by injecting a lifetime killer at the boundary between the SJ-MOSFET portion 10 and the FWD portion 13. This is different from the example of FIG.

  FIG. 27 is a diagram illustrating an eleventh example of the SJ-MOSFET section 10 and the FWD section 13. In this example, a defect region 110 is formed by injecting a lifetime killer at the boundary between the SJ-MOSFET portion 10 and the FWD portion 13. This is different from the example of FIG.

  FIG. 28 is a diagram illustrating a twelfth example of the SJ-MOSFET section 10 and the FWD section 13. In this example, a defect region 110 is formed by injecting a lifetime killer at the boundary between the SJ-MOSFET portion 10 and the FWD portion 13. This is different from the example of FIG.

  FIG. 29 is a diagram illustrating a thirteenth example of the SJ-MOSFET section 10 and the FWD section 13. In this example, the defect region 110 is not formed in the FS layer 70 of the FWD portion 13. This is different from the example of FIG.

  FIG. 30 is a diagram illustrating a fourteenth example of the SJ-MOSFET section 10 and the FWD section 13. In this example, a defect region 110 is formed by injecting a lifetime killer at the boundary between the SJ-MOSFET portion 10 and the FWD portion 13. This is different from the example of FIG.

  FIG. 31 is a diagram illustrating a fifteenth example of the SJ-MOSFET section 10 and the FWD section 13. In this example, the defect region 110 provided on the front surface side of the n-type column 54 and the p-type column 56 is provided to the back surface side as compared with the example of FIG. Furthermore, in this example, the defect region 110 provided in the FS layer 70 of the SJ-MOSFET portion 10 is provided to the surface side as compared with the example of FIG. Thereby, the soft recovery characteristics of the SJ-MOSFET section 10 can be further improved as compared with the example of FIG.

  FIG. 32 is a diagram illustrating a sixteenth example of the SJ-MOSFET section 10 and the FWD section 13. In this example, a defect region is formed by injecting a lifetime killer from the surface side of the n-type column 54 and the p-type column 56 in the SJ-MOSFET portion 10 to the entire FS layer 70 in the SJ-MOSFET portion 10. 110 is formed. This is different from the example of FIG. Thereby, the soft recovery characteristic of the SJ-MOSFET section 10 can be further improved as compared with the example of FIG.

  FIG. 33 is a diagram illustrating a seventeenth example of the SJ-MOSFET section 10 and the FWD section 13. In this example, the defect region 110 is not formed on the anode side in the drift region of the FWD portion 13. This is different from the example of FIG.

  FIG. 34 is a diagram illustrating an eighteenth example of the SJ-MOSFET portion 10 and the FWD portion 13. In this example, the defect region 110 is not formed in the FS layer 70 of the FWD portion 13. This is different from the example of FIG.

  FIG. 35 is a diagram illustrating a nineteenth example of the SJ-MOSFET section 10 and the FWD section 13. In this example, the defect region 110 is not formed on the anode side in the drift region of the FWD portion 13 or in the FS layer 70 of the FWD portion 13. This is different from the example of FIG.

  FIG. 36 is a diagram illustrating a first example having the repetitive structure 120 of the SJ-MOSFET section 10 and the FWD section 13. The repetitive structure unit 120 is periodically provided with the FWD unit 13 and the SJ-MOSFET unit 10 in FIGS. 17 to 35. The repetitive structure 120 may be provided with the IGBT unit 20 interposed therebetween. Further, the repeating structure 120 may be provided so as to surround the IGBT part 20. Also in this example, a low Von characteristic using the SJ-MOSFET part 10 and a large current characteristic using the IGBT part 20 can be sold. Further, by integrating the SJ-MOSFET portion 10, the IGBT portion 20, and the FWD portion 13 on one semiconductor chip, the semiconductor module can be reduced in size.

  FIG. 37 is a diagram showing a second example having the repetitive structure portion 120 of the SJ-MOSFET portion 10 and the FWD portion 13. In this example, the defect region 110 is formed by injecting a lifetime killer into the FS layer 70 of the IGBT unit 20. This is different from the example of FIG. In this example, since the defect region 110 is included in the FS layer 70 of the IGBT unit 20, carrier injection from the back surface can be suppressed, so that switching speed can be increased.

  FIG. 38 is a diagram illustrating a third example having the repetitive structure portion 120 of the SJ-MOSFET portion 10 and the FWD portion 13. In this example, a defect region 110 is formed between the IGBT part 20 and the repetitive structure part 120 by injecting a lifetime killer. This is different from the example of FIG. In this example, since the defect region 110 is provided between the IGBT part 20 and the repetitive structure part 120, avalanche breakdown during turn-off can be suppressed.

  FIG. 39 is a diagram illustrating a fourth example including the repetitive structure portion 120 of the SJ-MOSFET portion 10 and the FWD portion 13. In this example, a defect region 110 is formed by injecting a lifetime killer between both the IGBT portion 20 and the repetitive structure portion 120 and in the FS layer 70 in the IGBT portion 20. This is different from the example of FIG. In this example, since the defect region 110 is provided between the IGBT part 20 and the repetitive structure part 120, the switching speed can be increased and the avalanche breakdown can be suppressed.

  The examples in FIGS. 36 to 39 can be applied to the semiconductor device 200 or the semiconductor device 300. In this case, the pitch between the p + -type collector layer 80 and the n + -type drain layer 82 may be 200 μm or more. The pitch between the p + -type collector layer 80 and the n + -type drain layer 82 may be 5 to 1,000 times the pitch between the n-type column 54 and the p-type column 56 in the SJ-MOSFET section 10.

  FIG. 40 is a diagram showing an example in which an SJ-IGBT unit 22 is provided instead of the IGBT unit 20 of FIG. Other configurations may be the same as the example of FIG. A configuration in which a lifetime killer is injected into at least one of the SJ-MOSFET portion 10 and the FWD portion 13 (an example shown in FIGS. 17 to 35) and a configuration of the repetitive structure portion 120 (an example shown in FIGS. 36 to 39) You may apply to.

  The SJ-IGBT section 22 has an IGBT region constituted by a superjunction transistor region 25 that is a superjunction transistor. The SJ-IGBT unit 22 includes an n-type column 54 as a first conductivity type column and a p-type column 56 as a second conductivity type column.

  The n-type column 54 of this example has n-type impurities, and the p-type column 56 has p-type impurities. In this example, the two superjunction transistor regions 25-1 and 25-2 are denoted by reference numerals in the SJ-IGBT portion 22 with priority given to the visibility of the drawing. In the SJ-IGBT section 22, two adjacent superjunction transistor regions 25 share one n-type column 54 or one p-type column 56. In this example, the superjunction transistor regions 25-1 and 25-2 share one n-type column 54. Also, two adjacent superjunction transistor regions 25-1 and 25-2 share one gate electrode 50 and gate insulating film 52.

In this example, the impurity concentration of the n-type column 54 and the p-type column 56 may be 1E15 (cm ⁻³ ) or more and 1E16 (cm ⁻³ ) or less. The n-type impurity concentration of the n-type column 54 and the p-type impurity concentration of the p-type column 56 may be equal. However, the impurity concentration of each column is 1E14 (cm ⁻³⁾ for both n-type and p-type impurity concentrations in order to obtain desired values for breakdown voltage (BV), on-voltage (Von), and off-loss (Eoff) described later. ) May be appropriately changed within the range of 1E16 (cm ⁻³ ) or less. In this example, the n-type impurity concentration of the n-type column 54 is 5E15 (cm ⁻³ ), and the p-type impurity concentration of the p-type column 56 is 5E15 (cm ⁻³ ). Note that E means 10 tiles. For example, 1E14 means 1 × 10 ¹⁴ .

  As described above, the semiconductor substrate 100 has the front (front) surface 102 which is the + z side surface and the back surface 103 which is the opposite surface. On the back surface 103 side of the SJ-IGBT portion 22, a collector layer 80 as a second conductivity type semiconductor layer is provided. The collector layer 80 of this example has p + type impurities. A drain layer 82 as a first conductivity type semiconductor layer is provided in common on the back surface 103 side of the FWD portion 13 and the SJ-MOSFET portion 10. The drain layer 82 has an n + type impurity. In the FWD portion 13, the drain layer 82 functions as an n-type layer constituting a pn junction.

  The pitch between the p + -type collector layer 80 and the n + -type drain layer may be 5 to 1000 times the pitch between the n-type column 54 and the p-type column 56 in the SJ-IGBT unit 22. In this example, the pitch between the p + -type collector layer 80 and the n + -type drain layer is 200 μm or more, and the pitch between the n-type column 54 and the p-type column 56 is 3 μm.

  FIG. 41 is a diagram showing the relationship between the charge imbalance ratio (%) and the withstand voltage (V) in the simulation. The ratio (%) of charge imbalance on the horizontal axis indicates the ratio of charge imbalance between the n-type column 54 and the p-type column 56. When the charge imbalance is zero (%), the charge amount of the n-type column 54 and the charge amount of the p-type column 56 are balanced. In this case, the n-type impurity concentration of the n-type column 54 and the p-type impurity concentration of the p-type column 56 are equal. When the charge imbalance is negative (%), the charge amount of the n-type column 54 is larger than the charge amount of the p-type column 56. When the charge imbalance is positive (%), the charge amount of the n-type column 54 is smaller than the charge amount of the p-type column 56.

  The breakdown voltage (V) on the vertical axis is the breakdown voltage of the semiconductor device 200, 300, or 400. In this example, the result of the non-SJ-IGBT part is only one point, and the breakdown voltage is 1160 (V) when the charge imbalance ratio is zero (%). Note that the non-SJ-IGBT portion corresponds to the IGBT portion 20 in the case of FIG. 12 where the IGBT region 24 is not a superjunction transistor. A plurality of withstand voltage curves of the SJ-IGBT section 22 in which several percentages of the charge imbalance are plotted positive and negative with the n-type impurity doping concentration (Nd) in the n-type column 54 as a parameter are shown. In the following examples, the n-type impurity concentration of the n-type column 54 and the p-type impurity concentration of the p-type column 56 are assumed to be equal.

  As is clear from FIG. 41, the withstand voltage curve of the SJ-IGBT section 22 is maximum when the charge imbalance ratio is zero (%). This is because the depletion layer between the n-type column 54 and the p-type column 56 is most easily spread when the rate of charge imbalance is zero (%). Also, the lower the doping concentration (Nd), the higher the breakdown voltage. This is because the depletion layer easily spreads as the doping concentration (Nd) is lower. The non-SJ-IGBT part has the n-type drift layer 40 doped with n-type impurities, but does not have the p-type column 56. Therefore, the non-SJ-IGBT part was plotted at the position where the rate of charge imbalance was zero (%).

In this example, the withstand voltage of the non-SJ-IGBT part is 1160 (V). Further, the breakdown voltage of Nd = 8E15 (cm ⁻³ ) when the charge imbalance ratio is zero (%) is 1260 (V). Thus, there is a difference in breakdown voltage of 100 (V) between the case where the non-SJ-IGBT part is provided and the case where the SJ-IGBT part 22 is provided.

FIG. 42 is a diagram showing the relationship between the doping concentration (cm ⁻³ ) and the breakdown voltage (V) in the simulation. Nd (cm ⁻³ ) on the horizontal axis represents the doping concentration (cm ⁻³ ). The breakdown voltage (V) on the vertical axis is the breakdown voltage of the semiconductor device 200, 300, or 400.

  The n-type drift layer 40 of the non-SJ-IGBT portion of this example has an n-type impurity concentration of 1.0E14. The n-type column 54 and the p-type column 56 of the SJ-IGBT section 22 were plotted at 14 points between 1.0E14 and 1.0E16. As is apparent from FIGS. 41 and 42, the use of the SJ-IGBT unit 22 can improve the breakdown voltage of the semiconductor device compared to the case where the IGBT unit 20 is a non-SJ-IGBT unit.

  FIG. 43 is a diagram showing the relationship between the distance (μm) from the surface 102 when the gate is turned on and the electric field strength (V / cm) in the simulation. The distance (μm) from the surface 102 on the horizontal axis indicates that the surface 102 of the semiconductor substrate 100 is zero (μm) and the back surface 103 is 100 (μm). That is, the thickness of the semiconductor substrate 100 of this example is 100 (μm). The vertical axis shows the strength of electric love (V / cm).

  In the superjunction transistor region 25 of the SJ-IGBT portion 22, X indicates the pitch of the n-type column 54 or the p-type column 56. When X = 1.5 (μm), the pitch of the superjunction transistor region 25 is 1.5 × 2 = 3.0 (μm), and when X = 3.0 (μm), the superjunction transistor The pitch of the region 25 is 3.0 × 2 = 6.0 (μm). There is no column pitch in the non-SJ-IGBT part. Therefore, the width of the n-type drift layer 40 in the x direction is set to X = 3.0 (μm) or X = 6.0 (μm). The trench depth of the gate electrode 50 is 3.5 (μm) in both the SJ-IGBT part 22 and the non-SJ-IGBT part.

  In the example of the non-SJ-IGBT part, the electric field is strongest at the bottom (near 3.5 (μm)) of the gate electrode 50, and the electric field strength decreases linearly from the bottom of the gate electrode 50 to the back surface 103. That is, in the non-SJ-IGBT portion, the bottom of the gate electrode 50 may be destroyed due to electric field concentration. On the other hand, in the example of the SJ-IGBT portion 22, the electric field strength is substantially constant from the bottom portion of the gate electrode 50 to the back surface 103. Also from this result, the withstand voltage of the semiconductor device can be improved by adopting the SJ-IGBT part 22 as compared with the case where the IGBT part 20 is a non-SJ-IGBT part. Note that the smaller the pitch between the n-type column 54 and the p-type column 56, the denser the pn junctions are formed, and thus the depletion layer tends to spread. Therefore, in the SJ-IGBT portion 22, the electric field can be made stronger when X = 1.5 (μm) than when X = 3.0 (μm).

FIG. 44 is a diagram showing the relationship between the doping concentration (cm ⁻³ ) and the on-voltage (V) in the simulation. The dope concentration (Nd) on the horizontal axis is the same as in the examples of FIGS. The on-voltage (Von) on the vertical axis is an applied voltage (V) to the gate electrode 50 that is necessary when a current of 100 (A / cm ⁻² ) flows from the back electrode 90 to the front electrode 62 of the semiconductor device. .

In this example, there is only one non-SJ-IGBT part, Nd is 1.0E14 (cm ⁻³ ), and Von is about 1.2 (V). In the SJ-IGBT part 22, Von tends to increase in the range where Nd is 1.0E14 (cm ⁻³ ) or more and 1.0E15 (cm ⁻³ ) or less. Moreover, in the range where Nd is 1.0E15 (cm ⁻³ ) or more and 1.0E16 (cm ⁻³ ) or less, Von tends to decrease.

In the SJ-IGBT section 22, Nd decreases from 1.0E15 (cm ⁻³ ) to 1.0E14 (cm ⁻³ ) because the electron injection is promoted (IE) as the concentration of the adjacent column decreases. This is because the effect becomes remarkable. The reason why Nd decreases from 1.0E15 (cm ⁻³ ) to 1.0E16 (cm ⁻³ ) is that the drift resistance reduction effect in the n-type column 54 becomes significant. In general, the higher the breakdown voltage, the higher the Von, but as is apparent from FIG. 44, even if the SJ-IGBT part 22 is adopted, Von can be maintained to the same extent as a semiconductor device having a non-SJ-IGBT part. it can. In this example, the maximum Von (Nd = 1.0E15) of the SJ-IGBT part 22 is about 2.1 (V), which is less than twice the Von of the non-SJ-IGBT part.

FIG. 45 is a diagram illustrating the relationship between the on-voltage (V) and the current density (A / cm ² ) in the simulation. The on-voltage (Von) on the horizontal axis is the same as in the example of FIG. The current density (A / cm ² ) on the vertical axis is the same as in the example of FIG. In this example, the concentration Nd of the n-type drift layer 40 in the non-SJ-IGBT part is 6.6E13 (cm ⁻³ ).

As is clear from FIG. 45, the SJ-IGBT part 22 and the non-SJ-IGBT part start to flow near 0.6 (V). That is, the SJ-IGBT part 22 and the non-SJ-IGBT part can obtain approximately the same Von. When Nd = 1E16 at J = 20 (A / cm ² ) is compared with the non-SJ-IGBT part, Von can be improved by 0.2V. Note that the same IE effect and drift resistance reduction effect as in the example of FIG. 44 are also confirmed.

FIG. 46 is a diagram showing the relationship between time (μs), collector-emitter voltage (V), and collector current (A) in the simulation. The horizontal axis is time (μs), the left vertical axis is the collector-emitter voltage: Vce (V), and the right vertical axis is the collector current: Ic (A). In this example, a semiconductor device having an SJ-IGBT portion 22 with Nd = 1E16 (cm ⁻³ ) and a semiconductor device having a non-SJ-IGBT portion with Nd = 6.6E13 (cm ⁻³ ) are set to 0 ( It is the result of comparing the cases of simultaneous turn-off at μs).

  As is clear from FIG. 46, the Ic of the SJ-IGBT part 22 decreases faster than the Ic of the non-SJ-IGBT part, despite being simultaneously turned off. Thereby, the off loss (Eoff) of the SJ-IGBT part 22 is smaller than that of the non-SJ-IGBT part. In this example, the off loss of the SJ-IGBT part 22 was 8.1 (mJ), and the off loss of the non-SJ-IGBT part was 29.2 (mJ). That is, the off loss of the SJ-IGBT part 22 is about ¼ of the off loss of the non-SJ-IGBT part. In this way, the SJ-IGBT unit 22 can reduce the off loss more than the non-SJ-IGBT unit. Regarding dV / dt, the SJ-IGBT part 22 was 8.7 (kV / μs), and the non-SJ-IGBT part was 1.9 (kV / μs). That is, the dV / dt of the SJ-IGBT part 22 can be about four times that of the non-SJ-IGBT part. By increasing dV / dt, the carrier can be swept out faster. As a result, the turn-off loss can be reduced.

FIG. 47 is an enlarged view of the portion of time 0 (μs) to 1.0 (μs) in FIG. Note that in FIG. 47, the Vce curve and the Ic curve are shown for nine of 1E15 (cm ⁻³ ) to 9E15 (cm ⁻³ ). The horizontal and vertical axes are the same as in FIG.

Regarding Ic, the n-type impurity concentration Nd (cm ⁻³ ) of the n-type column 54 of the SJ-IGBT section 22 is 1E16, 9E15, 8E15. However, 4E15 to 1E15 were not in this order from slow to fast. However, in all of 1E16 to 1E15, the timing at which Ic starts to decrease is later than that in the non-SJ-IGBT part. Therefore, it can be said that any example of 1E16 to 1E15 can reduce the off-loss as compared with the non-SJ-IGBT part.

  Regarding Vce, the non-SJ-IGBT part and the SJ-IGBT part 22 are 1E15, 2E15. In particular, from 1E15 to 5E15, a steep change in dV / dt was observed.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the operation flow in the claims, the description, and the drawings is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

10 SJ-MOSFET section, 12 boundary section, 13 FWD section, 14 superjunction transistor region, 20 IGBT section, 22 SJ-IGBT section, 24 IGBT area, 25 superjunction transistor area, 30 breakdown voltage structure section, 32 1st Withstand voltage section, 34 second breakdown voltage section, 40 n-type drift layer, 42 p-type base layer, 44 contact region, 45 source region, 46 emitter region, 47 guard ring, 48 n-type region, 49 p-type region, 50 gate electrode 51 dummy gate electrode, 52 gate insulating film, 54 n-type column, 56 p-type column, 58 defect region, 59 p-type region, 60 insulating layer, 62 surface electrode, 64 field plate, 70 FS layer, 80 collector layer , 82 Drain layer, 90 Back electrode, 100 Semiconductor substrate, 102 Surface, 103 Back , 104 extended p-type well, 110 defective area 120 repeating structural unit, 200 a semiconductor device, 300 a semiconductor device, 400 a semiconductor device

Claims (25)

A semiconductor substrate;
Two or more superjunction transistor regions provided on the semiconductor substrate;
A semiconductor device comprising: one or more IGBT regions provided in a region sandwiched by two or more of the superjunction transistor regions in a cross section cut along a plane perpendicular to the semiconductor substrate. The semiconductor device according to claim 1, wherein the IGBT region is provided in a region surrounded by the superjunction transistor region. 3. The semiconductor device according to claim 1, further comprising a breakdown voltage structure portion provided outside the outermost superjunction transistor region in the superjunction transistor region. The superjunction transistor region has a first conductivity type column and a second conductivity type column,
The pressure-resistant structure portion includes a first pressure-resistant portion provided on the inner peripheral portion and a second pressure-resistant portion provided on the outer peripheral portion,
The second breakdown voltage portion of the breakdown voltage structure has a first conductivity type region and a second conductivity type column,
The depth of the edge part of the 2nd conductivity type column in the said 2nd pressure | voltage resistant part of the said proof pressure structure part is shallower than the depth of the edge part of the said 2nd conductivity type column of the said super junction type transistor area. Semiconductor device. The semiconductor device according to claim 1, wherein a breakdown voltage of the IGBT region is higher than a breakdown voltage of the superjunction transistor region. 6. The semiconductor device according to claim 1, wherein an IGBT portion having two or more IGBT regions is provided in a region sandwiched between the super junction transistor regions. The semiconductor device according to claim 6, wherein SJ-MOSFET portions including two or more superjunction transistor regions are respectively provided on both sides of the IGBT portion. The semiconductor device according to claim 1, wherein a lifetime killer is injected into a drift region at a boundary portion between the IGBT region and the superjunction transistor region. The IGBT region has a drift region of a first conductivity type,
8. The semiconductor device according to claim 1, wherein a second conductivity type column is provided at a boundary portion between the IGBT region and the superjunction transistor region from the front surface side to the back surface side of the drift region. . The semiconductor device according to claim 1, further comprising a dummy gate electrode on a surface side of the semiconductor substrate in a drift region at a boundary portion between the IGBT region and the superjunction transistor region. 8. The second conductivity type well extended in a direction parallel to the surface of the semiconductor substrate is provided at a boundary portion between the IGBT region and the superjunction transistor region. Semiconductor device. The superjunction transistor region has a first conductivity type column and a second conductivity type column,
And a second conductivity type column having an end depth shallower than an end depth of the second conductivity type column of the super junction type transistor region at a boundary portion between the IGBT region and the super junction type transistor region. Item 8. The semiconductor device according to any one of Items 1 to 7. At the boundary between the IGBT region and the superjunction transistor region,
Two gate electrodes;
A first conductivity type region provided between the two gate electrodes;
A second conductivity type region which is in contact with the first conductivity type region and on the back side of the first conductivity type region is ½ the depth of the second conductivity type column of the super junction transistor region. Item 8. The semiconductor device according to any one of Items 1 to 7. The boundary part of the IGBT part which has two or more said IGBT area | regions, and the SJ-MOSFET part containing the two or more said super junction type transistor area | regions has a free-wheeling diode part. Semiconductor device. The semiconductor device according to claim 14, wherein a lifetime killer is injected into the SJ-MOSFET portion. The SJ-MOSFET part has a first conductivity type column and a second conductivity type column,
A lifetime killer is injected into at least one of the surface side of the first conductivity type column and the second conductivity type column in the SJ-MOSFET portion and the field stop layer in the SJ-MOSFET portion. Item 16. The semiconductor device according to Item 15. A lifetime killer is injected from the surface side of the first conductivity type column and the second conductivity type column in the SJ-MOSFET portion to the field stop layer in the SJ-MOSFET portion. Item 17. The semiconductor device according to Item 16. The semiconductor device according to any one of claims 14 to 17, wherein a lifetime killer is injected into a boundary between the freewheeling diode portion and the SJ-MOSFET portion. The semiconductor device according to any one of claims 14 to 18, wherein a lifetime killer is injected into the reflux diode portion. The semiconductor device according to claim 19, wherein a lifetime killer is injected into at least one of the anode side and the field stop layer in the drift region of the free-wheeling diode portion. It further comprises a repetitive structure part in which the freewheeling diode part and the SJ-MOSFET part are provided periodically,
The semiconductor device according to claim 14, wherein the repetitive structure portion is provided with the IGBT portion interposed therebetween. The semiconductor device according to claim 21, wherein a lifetime killer is injected into at least any of the space between the IGBT portion and the repetitive structure portion and the field stop layer in the IGBT portion. The semiconductor device according to any one of claims 14 to 22, wherein the IGBT unit is an SJ-IGBT unit in which the IGBT region is configured by a super junction transistor. 24. The semiconductor device according to claim 23, wherein the SJ-IGBT section includes a first conductivity type column and a second conductivity type column each having an impurity concentration of 1E15 cm ⁻³ or more and 1E16 cm ⁻³ or less. The pitch between the second conductive type semiconductor layer provided on the back side of the SJ-IGBT part and the first conductive type semiconductor layer provided on the back side of the free wheel diode part and the SJ-MOSFET part is The semiconductor device according to claim 24, wherein the pitch is 5 to 1000 times the pitch between the first conductivity type column and the second conductivity type column in an SJ-IGBT section.