JP7352151B2 - switching element - Google Patents

Description

The technology disclosed in this specification relates to a switching element.

The switching element disclosed in Patent Document 1 has an element formation region and a termination region. In the element formation region, a structure of a switching element such as a source region, a body region, a trench gate, etc. is provided. The termination region is provided with a p-type breakdown voltage region that extends below the bottom end of the trench. The drift region is distributed from the element formation region to the termination region. The drift region is arranged below the body region and the breakdown voltage region. By providing the breakdown voltage region, electric field concentration within the semiconductor substrate is suppressed. This improves avalanche resistance.

Japanese Patent Application Publication No. 2009-141185

In the structure of Patent Document 1, avalanche breakdown may occur within the drift region below the breakdown voltage region. In this case, an avalanche current flows to the source electrode through the end of the body region in the element formation region (that is, the portion of the body region near the breakdown voltage region). That is, the avalanche current flows in a concentrated manner at the end of the body region, and a high load is applied to this portion. This specification proposes a technique for further improving avalanche tolerance by reducing the load applied to a switching element during avalanche breakdown.

A switching element disclosed in this specification includes a semiconductor substrate and a source electrode disposed on an upper surface of the semiconductor substrate. The semiconductor substrate has a main part, a peripheral part arranged around the main part, and an intermediate part arranged between the main part and the peripheral part. The semiconductor substrate has a p-type body region distributed over the main portion and the intermediate portion. A plurality of trenches passing through the body region are provided on the upper surface of the semiconductor substrate such that an inter-trench semiconductor region sandwiched between adjacent trenches exists in each of the main portion and the intermediate portion. . A gate insulating film and a gate electrode insulated from the semiconductor substrate by the gate insulating film are arranged in each trench. The semiconductor substrate has a source region, a first contact region, a second contact region, and a breakdown voltage region. The source region is an n-type region disposed in the inter-trench semiconductor region in the main portion and in contact with the source electrode and the gate insulating film. The first contact region is disposed in the inter-trench semiconductor region in the main portion, is in contact with the source electrode, and is a p-type region having a higher p-type impurity concentration than the body region. The second contact region is disposed in the inter-trench semiconductor region in the intermediate portion, is in contact with the source electrode, and is a p-type region having a higher p-type impurity concentration than the body region. The breakdown voltage region is a p-type region disposed within the peripheral portion, in contact with the body region, and having a lower end portion located below a lower end of the trench. The body region is in contact with the gate insulating film below the source region in the main part, is in contact with the source region and the first contact region from below in the main part, and is in contact with the gate insulating film below the source region in the main part, It is in contact with the gate insulating film within the portion, and is in contact with the second contact region from below within the intermediate portion. The semiconductor substrate is distributed across the main part, the intermediate part, and the peripheral part, and is in contact with the gate insulating film below the body region in the main part and the intermediate part, an n-type drift region that is in contact with the body region and the breakdown voltage region from below and is separated from the source region, the first contact region, and the second contact region by the body region; have The depth of the second contact region is greater than the depth of the first contact region.

In this switching element, a source region, a body region, a drift region, and a trench gate structure are provided in the main portion. Therefore, the main section performs the switching operation. In this switching element, when avalanche breakdown occurs in the drift region below the breakdown voltage region, an avalanche current flows into the body region near the breakdown voltage region. That is, an avalanche current flows in the body region within the intermediate portion. Since the second contact region is provided in the intermediate portion, the avalanche current flows from the body region to the source electrode via the second contact region. Since the p-type impurity concentration of the second contact region is higher than the p-type impurity concentration of the body region, the resistivity of the second contact region is low. Further, the depth of the second contact region provided in the intermediate portion is deeper than the depth of the first contact region provided in the main portion. Therefore, the electrical resistance of the current path when an avalanche current flows through the intermediate portion is low. Therefore, when an avalanche current flows, the heat generated in the intermediate portion is small, and the load applied to the semiconductor substrate at this time is small. Therefore, this switching element has high avalanche resistance.

FIG. 2 is a cross-sectional view of a switching element according to an embodiment.

FIG. 1 shows a switching element 10 of this embodiment. The switching element 10 is a MOSFET (metal oxide field effect transistor) and has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. In FIG. 1, the left side is the center side of the semiconductor substrate 12, and the right side is the outer peripheral end side of the semiconductor substrate 12. A source electrode 60 is arranged on the upper surface 12a of the semiconductor substrate 12. A drain electrode 62 is arranged on the lower surface 12b of the semiconductor substrate 12.

The semiconductor substrate 12 has a main portion 90, an intermediate portion 92, and a peripheral portion 94. The main portion 90 is provided at the center of the semiconductor substrate 12. The peripheral portion 94 is provided near the outer peripheral edge of the semiconductor substrate 12 . Intermediate section 92 is arranged between main section 90 and peripheral section 94 .

A p-type body region 24 is provided inside the semiconductor substrate 12 . Body region 24 is arranged near upper surface 12 a of semiconductor substrate 12 . The body region 24 is distributed across a main portion 90, an intermediate portion 92, and a peripheral portion 94.

A plurality of trenches 40 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 40 extends parallel to each other. A plurality of trenches 40 are provided in each of the main portion 90, the intermediate portion 92, and the peripheral portion 94. Each trench 40 extends through body region 24 . Hereinafter, each semiconductor region sandwiched between adjacent trenches 40 will be referred to as an inter-trench semiconductor region 80. A plurality of inter-trench semiconductor regions 80 are present within the main portion 90 . A plurality of inter-trench semiconductor regions 80 are present within intermediate portion 92 .

The inner surface of each trench 40 is covered with a gate insulating film 42. A gate electrode 44 is arranged inside each trench 40 . Each gate electrode 44 is insulated from the semiconductor substrate 12 by a gate insulating film 42. The surface of each gate electrode 44 is covered with an interlayer insulating film 46. Each gate electrode 44 is insulated from the source electrode 60 by an interlayer insulating film 46.

The semiconductor substrate 12 has a source region 20 , a first contact region 21 , a second contact region 22 , a breakdown voltage region 34 , a drift region 26 , a drain region 32 , and an FLR (field limiting ring) 36 .

The source region 20 is provided in each inter-trench semiconductor region 80 of the main portion 90 . Each source region 20 is n-type. Each source region 20 is exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 20 is in ohmic contact with a source electrode 60. Each source region 20 is in contact with the gate insulating film 42. No source region 20 is present in each inter-trench semiconductor region 80 in the intermediate portion 92 and peripheral portion 94 .

The first contact region 21 is provided in each inter-trench semiconductor region 80 of the main portion 90 . Each first contact region 21 is p-type and has a higher p-type impurity concentration than body region 24 . Each first contact region 21 is exposed on the upper surface 12a of the semiconductor substrate 12 to the extent that the source region 20 is not present. Each first contact region 21 is in ohmic contact with the source electrode 60. Further, the first contact region 21 is also provided in each inter-trench semiconductor region 80 in the peripheral portion 94 .

The second contact region 22 is provided in each inter-trench semiconductor region 80 of the intermediate portion 92 . Each second contact region 22 is p-type and has a higher p-type impurity concentration than body region 24 . Each second contact region 22 is exposed on the upper surface 12a of the semiconductor substrate 12. Each second contact region 22 is in ohmic contact with the source electrode 60.

The p-type impurity concentration of the second contact region 22 is higher than the p-type impurity concentration of the first contact region 21. Therefore, the resistivity of the second contact region 22 is lower than the resistivity of the first contact region 21. Further, the depth D2 of the second contact region 22 (that is, the distance from the upper surface 12a to the lower end of the second contact region 22) is equal to the depth D1 of the first contact region 21 (that is, the distance from the upper surface 12a to the lower end of the first contact region 22). (distance to the bottom edge of). Furthermore, the width W2 of the portion where the second contact region 22 is in contact with the source electrode 60 is wider than the width W1 of the portion where the first contact region 21 is in contact with the source electrode 60.

As described above, the body region 24 is distributed across the main portion 90, the intermediate portion 92, and the peripheral portion 94. The body region 24 is disposed below the source region 20 , the first contact region 21 , and the second contact region 22 . and are in contact from the bottom. In the main portion 90 , the body region 24 is in contact with the gate insulating film 42 below each source region 20 . The body region 24 is in contact with the gate insulating film 42 within the intermediate portion 92 and the peripheral portion 94 .

The breakdown voltage region 34 is a p-type region into which boron is diffused, and has a p-type impurity concentration lower than that of the body region 24 . The breakdown voltage region 34 is provided within the peripheral portion 94 . The breakdown voltage region 34 is located below the body region 24 within the peripheral portion 94 . The breakdown voltage region 34 is in contact with the body region 24 from below. The breakdown voltage region 34 extends below the lower end of the trench 40 . The breakdown voltage region 34 covers the lower end of the trench 40 within the peripheral portion 94 .

Each FLR 36 is p-type. The body region 24 is not provided near the outer peripheral end of the peripheral portion 94 . Each FLR 36 is provided closer to the outer peripheral end than the body region 24 . Each FLR 36 is separated from body region 24. Each FLR 36 is exposed on the upper surface 12a of the semiconductor substrate 12. Although not shown, each FLR 36 extends around the main portion 90 and the intermediate portion 92 when the upper surface 12a of the semiconductor substrate 12 is viewed from above.

Drift region 26 is n-type. The drift region 26 is distributed across the main portion 90, the intermediate portion 92, and the peripheral portion 94. The drift region 26 is arranged below the body region 24 and the breakdown voltage region 34, and is in contact with the body region 24 and the breakdown voltage region 34 from below. In the main portion 90 and the intermediate portion 92 , the drift region 26 is in contact with the gate insulating film 42 below the body region 24 . Drift region 26 is separated from each source region 20 , each first contact region 21 , and each second contact region 22 by body region 24 . The drift region 26 is exposed on the upper surface 12 a of the semiconductor substrate 12 in a part of the region closer to the outer peripheral end than the body region 24 . A drift region 26 separates each FLR 36 from the body region 24 .

Drain region 32 is n-type and has a higher n-type impurity concentration than drift region 26 . The drain region 32 is distributed across the main portion 90 , the intermediate portion 92 , and the peripheral portion 94 . Drain region 32 is arranged below drift region 26 and is in contact with drift region 26 from below. Drain region 32 is exposed on lower surface 12b of semiconductor substrate 12. Drain region 32 is in ohmic contact with drain electrode 62 .

When the switching element 10 is used, a higher potential is applied to the drain electrode 62 than to the source electrode 60. When a potential equal to or higher than the gate threshold is applied to the gate electrode 44, a channel is formed in the body region 24 in the range that is in contact with the gate insulating film 42. In the main portion 90, the source region 20 and the drain region 32 are connected by a channel. Therefore, current flows from the drain electrode 62 to the source electrode 60 via the drain region 32, the drift region 26, the channel, and the source region 20. That is, the switching element 10 is turned on. Since the source region 20 is not present in the intermediate portion 92, no current flows through the intermediate portion 92. In the peripheral part 94, the lower end of the trench 40 is covered by the breakdown voltage region 34, so no current flows in the peripheral part 94.

Thereafter, when the potential of the gate electrode 44 is lowered to a potential lower than the gate threshold, the channel disappears and the current in the main portion 90 stops. That is, the switching element 10 is turned off. When switching element 10 is turned off, a depletion layer spreads from body region 24 and breakdown voltage region 34 into drift region 26 . Depleted drift region 26 maintains the voltage between drain electrode 62 and source electrode 60. Since the breakdown voltage region 34 extends below the lower ends of the trenches 40 in the main portion 90 and the intermediate portion 92, concentration of the electric field at the lower ends of these trenches 40 is suppressed.

When the switching element 10 is turned off, a high electric field is generated within the drift region 26 below the breakdown voltage region 34, and avalanche breakdown may occur. When avalanche breakdown occurs in the drift region 26 below the breakdown voltage region 34, holes generated by the avalanche breakdown flow toward the source electrode 60, thereby generating an avalanche current. Because the resistivity of the breakdown voltage region 34 is high, the avalanche current flows through the intermediate portion 92 to the source electrode 60, as shown by arrow 100 in FIG. More specifically, the avalanche current flows through the body region 24 of the intermediate portion 92 and the second contact region 22 to the source electrode 60. If the heat generated by the avalanche current is large, a high load is applied to the semiconductor substrate 12, resulting in a decrease in avalanche resistance. However, in the switching element 10 of the embodiment, the avalanche resistance is improved as described below.

As described above, the depth D2 of the second contact region 22 in the intermediate portion 92 is deeper than the depth D1 of the first contact region 21 in the main portion 90. In this manner, the second contact region 22 with low resistivity is provided deep in the intermediate portion 92, thereby reducing the electrical resistance of the current path shown by the arrow 100. This suppresses heat generation caused by avalanche current.

Further, as described above, the width W2 of the second contact region 22 in the intermediate portion 92 (the width of the portion in contact with the source electrode 60) is the width W1 of the first contact region 21 in the main portion 90 (the width of the portion in contact with the source electrode 60). Wider than the width of the touching part). In particular, since the source region 20 is not provided within the intermediate portion 92, it is possible to increase the width W2. Therefore, the width of the current path shown by arrow 100 is wide, thereby reducing the electrical resistance of this current path. This suppresses heat generation caused by avalanche current.

Furthermore, as described above, the intermediate portion 92 is provided with a plurality of inter-trench semiconductor regions 80 . Therefore, the avalanche current can flow in a distributed manner in each of the inter-trench semiconductor regions 80 in the intermediate portion 92. Therefore, the electrical resistance of the current path shown by arrow 100 is reduced. This suppresses heat generation caused by avalanche current.

As described above, in the switching element 10, the electrical resistance of the path of the avalanche current is reduced, so that heat generated by the avalanche current is suppressed. Therefore, the load applied to the semiconductor substrate 12 due to the avalanche current is reduced. Therefore, the switching element 10 of the embodiment has high avalanche resistance.

Furthermore, in the intermediate portion 92, the p-type impurity concentration of the second contact region 22 is high, the depth of the second contact region 22 is deep, and the source region 20 is not present. (for example, the phenomenon of reaching the upper surface 12a) becomes less likely to occur.

In addition, in the embodiment mentioned above, the trench 40 was provided in the peripheral part 94, but the trench 40 does not need to exist in the peripheral part 94. Even in this configuration, the switching element can operate in the same manner as in the embodiment described above.

Further, in the embodiment described above, the body region 24 was provided within the peripheral portion 94, and the pressure-resistant region 34 was provided below the body region 24. However, the body region 24 may not be provided in the peripheral portion 94, and the breakdown voltage region 34 may extend from the upper surface 12a to below the lower end of the trench 40. In this configuration, the withstand voltage region 34 contacts the body region 24 within the intermediate portion 92 . Even in this configuration, the switching element can operate in the same manner as in the embodiment described above.

Further, in the embodiment described above, the source region 20 was not provided within the intermediate portion 92, but the source region 20 may be provided within the intermediate portion 92. According to this configuration, when the switching element 10 is on, it is possible to flow current also to the intermediate portion 92.

Furthermore, in the embodiments described above, the structure between the element region that operates as a switching element and the end surface of the semiconductor substrate 12 has been described. However, in the case where the semiconductor substrate has two element regions, a structure similar to the above-described embodiment may be provided between the element regions.

The technical elements disclosed in this specification are listed below. Note that each of the following technical elements is independently useful.

In one example of the switching element disclosed in this specification, the width of the portion where the second contact region contacts the source electrode may be wider than the width of the portion where the first contact region contacts the source electrode.

According to this configuration, the current path when an avalanche current flows through the intermediate portion becomes wider, and the resistance of the current path can be lowered. Therefore, avalanche resistance can be further improved.

In one example of the switching element disclosed in this specification, a plurality of inter-trench semiconductor regions may exist within the intermediate portion.

According to this configuration, the current path when an avalanche current flows through the intermediate portion becomes wider, and the resistance of the current path can be lowered. Therefore, avalanche resistance can be further improved.

In one example of the switching element disclosed in this specification, the p-type impurity concentration in the second contact region may be higher than the p-type impurity concentration in the first contact region.

According to this configuration, the resistance of the current path when the avalanche current flows can be lowered. Therefore, avalanche resistance can be further improved.

In one example of the switching element disclosed in this specification, the source region does not need to exist in the intermediate portion.

According to this configuration, the degree of freedom in layout of the second contact region within the intermediate portion is increased, so that the current path when an avalanche current flows through the intermediate portion can be made wider. Therefore, avalanche resistance can be further improved.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The techniques described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness singly or in various combinations, and are not limited to the combinations described in the claims as filed. Furthermore, the techniques illustrated in this specification or the drawings simultaneously achieve multiple objectives, and achieving one of the objectives has technical utility in itself.

10: Switching element 12: Semiconductor substrate 20: Source region 21: First contact region 22: Second contact region 24: Body region 26: Drift region 32: Drain region 34: Withstand voltage region 40: Trench 42: Gate insulating film 44: Gate electrode 46 : Interlayer insulating film 60 : Source electrode 62 : Drain electrode 80 : Intertrench semiconductor region 90 : Main part 92 : Intermediate part 94 : Peripheral part

Claims (1)

A switching element,
a semiconductor substrate;
a source electrode disposed on the top surface of the semiconductor substrate;
has
The semiconductor substrate has a main part, a peripheral part arranged around the main part, and an intermediate part arranged between the main part and the peripheral part,
The semiconductor substrate has a p-type body region distributed over the main portion, the intermediate portion, and the peripheral portion,
A plurality of trenches passing through the body region are provided on the upper surface of the semiconductor substrate such that an inter-trench semiconductor region sandwiched between adjacent trenches exists in each of the main portion and the intermediate portion. ,
A gate insulating film and a gate electrode insulated from the semiconductor substrate by the gate insulating film are arranged in each trench,
The semiconductor substrate is
an n-type source region disposed in the inter-trench semiconductor region in the main portion and in contact with the source electrode and the gate insulating film;
a p-type first contact region disposed in the inter-trench semiconductor region in the main portion, in contact with the source electrode, and having a higher p-type impurity concentration than the body region;
a p-type second contact region disposed in the inter-trench semiconductor region in the intermediate portion, in contact with the source electrode, and having a higher p-type impurity concentration than the body region;
a p-type breakdown voltage region disposed within the peripheral portion, in contact with the body region, and having a lower end portion located below the lower end of the trench;
has
The body region is in contact with the gate insulating film below the source region in the main part, is in contact with the source region and the first contact region from below in the main part, and is in contact with the gate insulating film below the source region in the main part, is in contact with the gate insulating film within the portion, and is in contact with the second contact region from below within the intermediate portion;
The semiconductor substrate is distributed across the main part, the intermediate part, and the peripheral part, and is in contact with the gate insulating film below the body region in the main part and the intermediate part, an n-type drift region that is in contact with the body region and the breakdown voltage region from below and is separated from the source region, the first contact region, and the second contact region by the body region; have,
The depth of the second contact region is deeper than the depth of the first contact region,
The p-type impurity concentration of the second contact region is higher than the p-type impurity concentration of the first contact region.
switching element.

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