JP2021034625A - Switching element - Google Patents

Abstract

To improve avalanche resistance.SOLUTION: A switching element has a semiconductor substrate which has: a main portion, a peripheral portion; and an intermediate portion disposed between the main portion and the peripheral portion. The semiconductor substrate has a p-type body region distributed extending over the main portion and the intermediate portion. A plurality of trench type gates is provided on an upper surface of the semiconductor substrate. The semiconductor substrate has: an n-type source region disposed in an inter-trench semiconductor region in the main portion; a p-type first contact region disposed in the inter-trench semiconductor region in the main portion; a p-type second contact region disposed in the inter-trench semiconductor region in the intermediate portion; and a p-type voltage withstanding region which is disposed in the peripheral portion and whose lower end portion is disposed on a lower side than a lower end of the trench. The depth of the second contact region is deeper than the depth of the first contact region.SELECTED DRAWING: Figure 1

Description

The techniques disclosed herein relate to switching devices.

The switching element disclosed in Patent Document 1 has an element forming region and a terminal region. Within the element forming region, a structure of a switching element such as a source region, a body region, and a trench gate is provided. The terminal region is provided with a p-shaped pressure resistant region extending below the lower end of the trench. The drift region is distributed from the element forming region to the terminal region. The drift region is arranged below the body region and the pressure resistant region. By providing the withstand voltage region, the electric field concentration in the semiconductor substrate is suppressed. This improves the avalanche endurance.

Japanese Unexamined Patent Publication No. 2009-141185

In the structure of Patent Document 1, avalanche breakdown may occur in the drift region below the pressure resistant region. In this case, the avalanche current flows to the source electrode through the end of the body region in the device forming region (that is, the portion of the body region near the withstand voltage region). That is, the avalanche current is concentrated and flows at the end of the body region, and a high load is applied to this portion. This specification proposes a technique for further improving the avalanche withstand capability by reducing the load applied to the switching element at the time of avalanche breakdown.

The switching element disclosed in the present specification includes a semiconductor substrate and a source electrode arranged on the upper surface of the semiconductor substrate. The semiconductor substrate has a main portion, a peripheral portion arranged around the main portion, and an intermediate portion arranged between the main portion and the peripheral portion. The semiconductor substrate has a p-shaped body region distributed across the main portion and the intermediate portion. A plurality of trenches penetrating the body region are provided on the upper surface of the semiconductor substrate so that an inter-trench semiconductor region sandwiched between the adjacent trenches exists in each of the main portion and the intermediate portion. .. A gate insulating film and a gate electrode insulated from the semiconductor substrate by the gate insulating film are arranged in each of the trenches. The semiconductor substrate has a source region, a first contact region, a second contact region, and a withstand voltage region. The source region is an n-type region that is arranged in the inter-trench semiconductor region in the main portion and is in contact with the source electrode and the gate insulating film. The first contact region is a p-type region that is arranged in the inter-trench semiconductor region in the main portion, is in contact with the source electrode, and has a higher p-type impurity concentration than the body region. The second contact region is a p-type region that is arranged in the inter-trench semiconductor region in the intermediate portion, is in contact with the source electrode, and has a higher p-type impurity concentration than the body region. The pressure-resistant region is a p-shaped region that is arranged in the peripheral portion, is in contact with the body region, and the lower end portion is arranged below the lower end of the trench. The body region is in contact with the gate insulating film below the source region in the main portion, is in contact with the source region and the first contact region from below in the main portion, and is in the middle. It is in contact with the gate insulating film in the portion, and is in contact with the second contact region from below in the intermediate portion. The semiconductor substrate is distributed across the main portion, the intermediate portion, and the peripheral portion, and is in contact with the gate insulating film in the main portion and in the intermediate portion on the lower side of the body region. An n-type drift region that is in contact with the body region and the pressure resistant region from below and is separated from the source region, the first contact region, and the second contact region by the body region. Have. The depth of the second contact region is deeper than the depth of the first contact region.

In this switching element, a source region, a body region, a drift region, and a trench gate structure are provided in the main portion. Therefore, the main unit performs the switching operation. In this switching element, when avalanche breakdown occurs in the drift region below the withstand voltage region, the avalanche current flows to the body region near the withstand voltage region. That is, the avalanche current flows in the body region in the middle part. Since the second contact region is provided in the intermediate portion, the avalanche current flows from the body region to the source electrode via the second contact region. Since the p-type impurity concentration in the second contact region is higher than the p-type impurity concentration in the body region, the resistivity in the second contact region is low. Further, the depth of the second contact region provided in the intermediate portion is deeper than the depth of the first contact region provided in the main portion. Therefore, the electrical resistance of the current path when the avalanche current flows in the middle portion is low. Therefore, the heat generated in the intermediate portion when the avalanche current flows is small, and the load applied to the semiconductor substrate at this time is small. Therefore, this switching element has a high avalanche withstand capability.

Sectional drawing of the switching element of an embodiment.

FIG. 1 shows the switching element 10 of this embodiment. The switching element 10 is a MOSFET (metal oxide field effect transistor) and has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. In FIG. 1, the left side is the center side of the semiconductor substrate 12, and the right side is the outer peripheral end side of the semiconductor substrate 12. A source electrode 60 is arranged on the upper surface 12a of the semiconductor substrate 12. A drain electrode 62 is arranged on the lower surface 12b of the semiconductor substrate 12.

The semiconductor substrate 12 has a main portion 90, an intermediate portion 92, and a peripheral portion 94. The main portion 90 is provided on the central side of the semiconductor substrate 12. The peripheral portion 94 is provided near the outer peripheral edge of the semiconductor substrate 12. The intermediate portion 92 is arranged between the main portion 90 and the peripheral portion 94.

A p-type body region 24 is provided inside the semiconductor substrate 12. The body region 24 is arranged in the vicinity of the upper surface 12a of the semiconductor substrate 12. The body region 24 is distributed over the main portion 90, the intermediate portion 92, and the peripheral portion 94.

A plurality of trenches 40 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 40 extends parallel to each other. A plurality of trenches 40 are provided in each of the main portion 90, the intermediate portion 92, and the peripheral portion 94. Each trench 40 penetrates the body region 24. In the following, each semiconductor region sandwiched by adjacent trenches 40 will be referred to as an inter-trench semiconductor region 80. A plurality of inter-trench semiconductor regions 80 exist in the main portion 90. A plurality of inter-trench semiconductor regions 80 exist in the intermediate portion 92.

The inner surface of each trench 40 is covered with a gate insulating film 42. A gate electrode 44 is arranged inside each trench 40. Each gate electrode 44 is insulated from the semiconductor substrate 12 by a gate insulating film 42. The surface of each gate electrode 44 is covered with an interlayer insulating film 46. Each gate electrode 44 is insulated from the source electrode 60 by an interlayer insulating film 46.

The semiconductor substrate 12 has a source region 20, a first contact region 21, a second contact region 22, a pressure resistant region 34, a drift region 26, a drain region 32, and a FLR (field limiting ring) 36.

The source region 20 is provided in each trench-to-trench semiconductor region 80 of the main portion 90. Each source area 20 is n-type. Each source region 20 is exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 20 is in ohmic contact with the source electrode 60. Each source region 20 is in contact with the gate insulating film 42. The source region 20 does not exist in the inter-trench semiconductor region 80 of the intermediate portion 92 and the peripheral portion 94.

The first contact region 21 is provided in each trench-to-trench semiconductor region 80 of the main portion 90. Each first contact region 21 is p-type and has a higher p-type impurity concentration than the body region 24. Each first contact region 21 is exposed on the upper surface 12a of the semiconductor substrate 12 in a range where the source region 20 does not exist. Each first contact region 21 is in ohmic contact with the source electrode 60. Further, a first contact region 21 is also provided in each trench-to-trench semiconductor region 80 in the peripheral portion 94.

The second contact region 22 is provided in each trench-to-trench semiconductor region 80 of the intermediate portion 92. Each second contact region 22 is p-type and has a higher p-type impurity concentration than the body region 24. Each second contact region 22 is exposed on the upper surface 12a of the semiconductor substrate 12. Each second contact region 22 is in ohmic contact with the source electrode 60.

The p-type impurity concentration in the second contact region 22 is higher than the p-type impurity concentration in the first contact region 21. Therefore, the resistivity of the second contact region 22 is lower than the resistivity of the first contact region 21. Further, the depth D2 of the second contact region 22 (that is, the distance from the upper surface 12a to the lower end of the second contact region 22) is the depth D1 of the first contact region 21 (that is, the distance from the upper surface 12a to the first contact region 21). Deeper than (distance to the bottom edge of). Further, the width W2 of the portion where the second contact region 22 is in contact with the source electrode 60 is wider than the width W1 of the portion where the first contact region 21 is in contact with the source electrode 60.

As described above, the body region 24 is distributed over the main portion 90, the intermediate portion 92, and the peripheral portion 94. The body region 24 is arranged below the source region 20, the first contact region 21, and the second contact region 22, with respect to the source region 20, the first contact region 21, and the second contact region 22. It is in contact from the bottom. In the main portion 90, the body region 24 is in contact with the gate insulating film 42 on the lower side of each source region 20. In the intermediate portion 92 and the peripheral portion 94, the body region 24 is in contact with the gate insulating film 42.

The pressure-resistant region 34 is a p-type region in which boron is diffused, and has a p-type impurity concentration lower than the p-type impurity concentration in the body region 24. The pressure resistant region 34 is provided in the peripheral portion 94. The pressure resistant region 34 is arranged below the body region 24 in the peripheral portion 94. The pressure resistant region 34 is in contact with the body region 24 from below. The pressure-resistant region 34 extends below the lower end of the trench 40. The pressure-resistant region 34 covers the lower end of the trench 40 in the peripheral portion 94.

Each FLR36 is p-type. The body region 24 is not provided in the vicinity of the outer peripheral edge of the peripheral portion 94. Each FLR 36 is provided on the outer peripheral end side with respect to the body region 24. Each FLR36 is separated from the body region 24. Each FLR36 is exposed on the upper surface 12a of the semiconductor substrate 12. Although not shown, each FLR 36 extends around the main portion 90 and the intermediate portion 92 when the upper surface 12a of the semiconductor substrate 12 is viewed in a plan view.

The drift region 26 is n-type. The drift region 26 is distributed over the main portion 90, the intermediate portion 92, and the peripheral portion 94. The drift region 26 is arranged below the body region 24 and the pressure-resistant region 34, and is in contact with the body region 24 and the pressure-resistant region 34 from below. In the main portion 90 and the intermediate portion 92, the drift region 26 is in contact with the gate insulating film 42 on the lower side of the body region 24. The drift region 26 is separated from each source region 20, each first contact region 21, and each second contact region 22 by the body region 24. The drift region 26 is a part of the region on the outer peripheral end side of the body region 24 and is exposed on the upper surface 12a of the semiconductor substrate 12. Each FLR 36 is separated from the body region 24 by a drift region 26.

The drain region 32 is n-type and has an n-type impurity concentration higher than that of the drift region 26. The drain region 32 is distributed over the main portion 90, the intermediate portion 92, and the peripheral portion 94. The drain region 32 is arranged below the drift region 26 and is in contact with the drift region 26 from below. The drain region 32 is exposed on the lower surface 12b of the semiconductor substrate 12. The drain region 32 is in ohmic contact with the drain electrode 62.

When the switching element 10 is used, a potential higher than that of the source electrode 60 is applied to the drain electrode 62. When a potential equal to or higher than the gate threshold is applied to the gate electrode 44, a channel is formed in the body region 24 in the range in contact with the gate insulating film 42. In the main unit 90, the source area 20 and the drain area 32 are connected by a channel. Therefore, a current flows from the drain electrode 62 to the source electrode 60 via the drain region 32, the drift region 26, the channel, and the source region 20. That is, the switching element 10 is turned on. Since the source region 20 does not exist in the intermediate portion 92, no current flows through the intermediate portion 92. In the peripheral portion 94, since the lower end portion of the trench 40 is covered with the pressure resistant region 34, no current flows through the peripheral portion 94.

After that, when the potential of the gate electrode 44 is lowered to a potential lower than the gate threshold value, the channel disappears and the current of the main portion 90 is stopped. That is, the switching element 10 is turned off. When the switching element 10 is turned off, the depletion layer spreads from the body region 24 and the withstand voltage region 34 into the drift region 26. The depleted drift region 26 holds the voltage between the drain electrode 62 and the source electrode 60. Since the pressure-resistant region 34 extends below the lower end of the trench 40 in the main portion 90 and the intermediate portion 92, the concentration of the electric field on the lower end of these trench 40 is suppressed.

When the switching element 10 is turned off, a high electric field is generated in the drift region 26 below the withstand voltage region 34, and avalanche breakdown may occur. When avalanche breakdown occurs in the drift region 26 below the pressure-resistant region 34, the holes generated by the avalanche breakdown flow toward the source electrode 60, and an avalanche current is generated. Since the resistivity of the withstand voltage region 34 is high, the avalanche current flows to the source electrode 60 through the intermediate portion 92 as shown by the arrow 100 in FIG. More specifically, the avalanche current flows to the source electrode 60 through the body region 24 and the second contact region 22 of the intermediate portion 92. If the heat generated by the avalanche current is large, a high load is applied to the semiconductor substrate 12, so that the avalanche withstand capacity becomes low. However, in the switching element 10 of the embodiment, the avalanche withstand capacity is improved as described below.

As described above, the depth D2 of the second contact region 22 in the intermediate portion 92 is deeper than the depth D1 of the first contact region 21 in the main portion 90. As described above, in the intermediate portion 92, the second contact region 22 having a low resistivity is provided deeply, so that the electric resistance of the current path shown by the arrow 100 is reduced. This suppresses the heat generated by the avalanche current.

Further, as described above, the width W2 of the second contact region 22 in the intermediate portion 92 (the width of the portion in contact with the source electrode 60) is the width W1 of the first contact region 21 in the main portion 90 (to the source electrode 60). Wider than the width of the contacting part). In particular, since the source region 20 is not provided in the intermediate portion 92, the width W2 can be widened. Therefore, the width of the current path shown by the arrow 100 is wide, which reduces the electrical resistance of this current path. This suppresses the heat generated by the avalanche current.

Further, as described above, the intermediate portion 92 is provided with a plurality of inter-trench semiconductor regions 80. Therefore, the avalanche current can be dispersed and flow in the inter-trench semiconductor region 80 in the intermediate portion 92. Therefore, the electrical resistance of the current path shown by the arrow 100 is reduced. This suppresses the heat generated by the avalanche current.

As described above, in the switching element 10, the electric resistance of the avalanche current path is reduced, so that the heat generated by the avalanche current is suppressed. Therefore, the load applied to the semiconductor substrate 12 due to the avalanche current is reduced. Therefore, the switching element 10 of the embodiment has a high avalanche withstand capability.

Further, in the intermediate portion 92, since the p-type impurity concentration in the second contact region 22 is high, the depth of the second contact region 22 is deep, and the source region 20 does not exist, punch-through (the depletion layer is the source potential). A portion (for example, a phenomenon of reaching the upper surface 12a) is less likely to occur.

In the above-described embodiment, the trench 40 is provided in the peripheral portion 94, but the trench 40 may not exist in the peripheral portion 94. Even in this configuration, the switching element can operate in the same manner as in the above-described embodiment.

Further, in the above-described embodiment, the body region 24 is provided in the peripheral portion 94, and the pressure resistant region 34 is provided below the body region 24. However, the body region 24 is not provided in the peripheral portion 94, and the pressure resistant region 34 may extend from the upper surface 12a to the lower side of the lower end of the trench 40. In this configuration, the pressure resistant region 34 is in contact with the body region 24 in the intermediate portion 92. Even in this configuration, the switching element can operate in the same manner as in the above-described embodiment.

Further, in the above-described embodiment, the source region 20 is not provided in the intermediate portion 92, but the source region 20 may be provided in the intermediate portion 92. According to this configuration, when the switching element 10 is on, a current can be passed through the intermediate portion 92 as well.

Further, in the above-described embodiment, the structure between the element region operating as the switching element and the end face of the semiconductor substrate 12 has been described. However, when the semiconductor substrate has two element regions, a structure similar to that of the above-described embodiment may be provided between the element regions.

The technical elements disclosed herein are listed below. The following technical elements are useful independently.

In the switching element of the example disclosed in the present specification, the width of the portion where the second contact region is in contact with the source electrode may be wider than the width of the portion where the first contact region is in contact with the source electrode.

According to this configuration, the current path when the avalanche current flows in the intermediate portion becomes wide, and the resistance of the current path can be further lowered. Therefore, the avalanche withstand capacity can be further improved.

In the switching element of the example disclosed in the present specification, a plurality of inter-trench semiconductor regions may exist in the intermediate portion.

According to this configuration, the current path when the avalanche current flows in the intermediate portion becomes wide, and the resistance of the current path can be further lowered. Therefore, the avalanche withstand capacity can be further improved.

In the switching element of the example disclosed in the present specification, the p-type impurity concentration in the second contact region may be higher than the p-type impurity concentration in the first contact region.

According to this configuration, the resistance of the current path when the avalanche current flows can be made lower. Therefore, the avalanche withstand capacity can be further improved.

In the switching element of the example disclosed in the present specification, the source region may not exist in the intermediate portion.

According to this configuration, the degree of freedom in the layout of the second contact region in the intermediate portion is increased, so that the current path when the avalanche current flows in the intermediate portion can be made wider. Therefore, the avalanche withstand capacity can be further improved.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in the present specification or drawings achieve a plurality of objectives at the same time, and achieving one of the objectives itself has technical usefulness.

10: Switching element 12: Semiconductor substrate 20: Source region 21: First contact region 22: Second contact region 24: Body region 26: Drift region 32: Drain region 34: Withstand voltage region 40: Trench 42: Gate insulating film 44: Gate electrode 46: Interlayer insulating film 60: Source electrode 62: Drain electrode 80: Semiconductor region between trenches 90: Main part 92: Intermediate part 94: Peripheral part

Claims (5)

It is a switching element
With a semiconductor substrate
A source electrode arranged on the upper surface of the semiconductor substrate,
Have,
The semiconductor substrate has a main portion, a peripheral portion arranged around the main portion, and an intermediate portion arranged between the main portion and the peripheral portion.
The semiconductor substrate has a p-shaped body region distributed across the main portion and the intermediate portion.
A plurality of trenches penetrating the body region are provided on the upper surface of the semiconductor substrate so that an inter-trench semiconductor region sandwiched between the adjacent trenches exists in each of the main portion and the intermediate portion. ,
A gate insulating film and a gate electrode insulated from the semiconductor substrate by the gate insulating film are arranged in each of the trenches.
The semiconductor substrate
An n-type source region arranged in the inter-trench semiconductor region in the main portion and in contact with the source electrode and the gate insulating film, and an n-type source region.
A p-type first contact region which is arranged in the inter-trench semiconductor region in the main portion, is in contact with the source electrode, and has a p-type impurity concentration higher than that of the body region, and a p-type first contact region.
A p-type second contact region arranged in the inter-trench semiconductor region in the intermediate portion, in contact with the source electrode, and having a higher p-type impurity concentration than the body region,
A p-type pressure-resistant region, which is arranged in the peripheral portion, is in contact with the body region, and the lower end portion is arranged below the lower end of the trench.
Have,
The body region is in contact with the gate insulating film below the source region in the main portion, is in contact with the source region and the first contact region from below in the main portion, and is in the middle. It is in contact with the gate insulating film in the portion, and is in contact with the second contact region from below in the intermediate portion.
The semiconductor substrate is distributed across the main portion, the intermediate portion, and the peripheral portion, and is in contact with the gate insulating film in the main portion and in the intermediate portion on the lower side of the body region. An n-type drift region that is in contact with the body region and the pressure resistant region from below and is separated from the source region, the first contact region, and the second contact region by the body region. Have and
The depth of the second contact region is deeper than the depth of the first contact region.
Switching element. The switching element according to claim 1, wherein the width of the portion where the second contact region is in contact with the source electrode is wider than the width of the portion where the first contact region is in contact with the source electrode. The switching element according to claim 1 or 2, wherein a plurality of inter-trench semiconductor regions are present in the intermediate portion. The switching element according to claim 1, wherein the p-type impurity concentration in the second contact region is higher than the p-type impurity concentration in the first contact region. The switching element according to any one of claims 1 to 4, wherein the source region does not exist in the intermediate portion.

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