JP6513932B2 - Semiconductor device - Google Patents

Description

  The technology disclosed herein relates to a semiconductor device.

  Patent Document 1 discloses an insulated gate semiconductor device. A trench is formed on the surface of the semiconductor substrate of this semiconductor device. A gate insulating layer and a gate electrode are disposed in the trench. In addition, a p-type floating region is formed at a position in contact with the insulating layer covering the bottom of the trench. When the semiconductor device is turned off, the depletion layer extends from the p-type floating region to the periphery thereof, thereby achieving a high breakdown voltage of the semiconductor device.

JP, 2006-128507, A

  In an insulated gate semiconductor device having a trench as in Patent Document 1, it may be necessary to separate the trenches in the longitudinal direction. For example, in the case of providing a bonding pad on the surface of a semiconductor substrate, the bonding pad may be provided at a position where the trench does not exist in order to prevent a shock due to bonding from being applied to the trench. For this purpose, it may be desirable to separate the trenches in their longitudinal direction to provide an area in which the trenches do not exist. There are also other cases where it is desirable to separate the trenches longitudinally. However, when the trenches are separated in the longitudinal direction, the depletion layer does not easily extend in the region between the trenches separated from the p-type floating region, and the electric field tends to be concentrated in this region. Therefore, the withstand voltage of the semiconductor device is reduced. Therefore, it has been difficult to separate the trenches in the longitudinal direction.

  A semiconductor device disclosed in this specification includes a semiconductor substrate, a gate insulating layer, and a gate electrode. The semiconductor substrate has a front surface and a back surface. A gate trench is formed on the surface of the semiconductor substrate. The gate trench has a first trench and a second trench separated from the first trench and extending on a longitudinal extension of the first trench at the surface. The gate insulating layer covers the inner surface of the gate trench. The gate electrode is disposed in the gate trench and is insulated from the semiconductor substrate by the gate insulating layer. The semiconductor substrate has a first element region adjacent to the first trench and a second element region adjacent to the second trench. Each of the first element region and the second element region has a first region, a body region, a second region, and a bottom region. The first region is in contact with the side surface portion of the gate insulating layer covering the side surface of the gate trench extending along the longitudinal direction of the gate trench, and is a region of the first conductive type exposed to the surface. The body region is a region of a second conductivity type in contact with the side surface portion on the back surface side of the first region. The second region is a region of the first conductivity type that is in contact with the side surface portion on the back surface side of the body region and is separated from the first region by the body region. The bottom region is a region of a second conductivity type that is in contact with the bottom of the gate insulating layer covering the bottom of the gate trench and is separated from the body region by the second region. The semiconductor substrate is disposed between the first trench and the second trench and is separated from the body region of the first element region and the body region of the second element region from the surface The semiconductor device further includes a separation region of a second conductivity type extending to a position deeper than any of the body region of the first element region and the body region of the second element region.

  The separation region may be connected to the bottom region of the first element region. Also, the separation region may be connected to the bottom region of the second element region. The above "first conductivity type" means either n-type or p-type, and the above "second conductivity type" is different from the first conductivity type of n-type and p-type Means

  When the semiconductor device is turned off, a depletion layer extends from the body region to the second region in each of the first element region and the second element region. When this depletion layer reaches the bottom region, the depletion layer develops from the bottom region into the surrounding second region. When the depletion layer extending from each bottom region reaches the separation region, the depletion layer extends from the separation region to the periphery thereof. The depletion layer extending from the isolation region depletes the semiconductor region between the first trench and the second trench. Therefore, generation of a high electric field in this region can be prevented. Therefore, this semiconductor device has a high withstand voltage.

FIG. 2 is a top view of the semiconductor device 10; FIG. 7 is a top view of the semiconductor device 10 in a state in which the electrode on the surface 12 a of the semiconductor substrate 12 and the insulating layer are removed. Sectional drawing in the III-III line of FIG. Sectional drawing in the IV-IV line of FIG. Sectional drawing in the VV line | wire of FIG. FIG. 4 is a view showing the position of a depletion layer 76 in the same section as FIG. 3; FIG. 5 is a cross-sectional view corresponding to FIG. 4 of a semiconductor device of a modified example. FIG. 5 is a cross-sectional view corresponding to FIG. 4 of a semiconductor device of a modified example.

  As shown in FIGS. 3 to 5, the semiconductor device 10 according to the first embodiment includes a semiconductor substrate 12, electrodes formed on the surface 12 a and the back surface 12 b of the semiconductor substrate 12, an insulating layer, and the like. The semiconductor substrate 12 is made of 4H-type SiC. Hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z direction, one direction parallel to the surface 12 a of the semiconductor substrate 12 is referred to as the x direction, and a direction orthogonal to the x direction and the z direction is referred to as the y direction.

  As shown in FIGS. 3 to 5, the drain electrode 84 is formed on the back surface 12 b of the semiconductor substrate 12. The drain electrode 84 covers substantially the entire area of the back surface 12b.

  As shown in FIG. 1, an outer peripheral trench 60 extending in an annular shape is formed on the surface 12 a of the semiconductor substrate 12. A gate pad 62 and source electrodes 80 a and 80 b are formed on the surface 12 a of the semiconductor substrate 12 within the range surrounded by the outer periphery trench 60. The source electrode 80a and the source electrode 80b are arranged at intervals in the y direction. The gate pad 62 is disposed between the source electrode 80a and the source electrode 80b, and extends long in the x direction. The gate pad 62 is separated from the source electrodes 80a and 80b.

  FIG. 2 shows the surface of the semiconductor device 10 in which the electrodes on the surface, the insulating layer and the like are omitted. As shown in FIG. 2, in the surface 12a of the semiconductor substrate 12 below the source electrode 80a, a plurality of trenches 34a are formed. Each trench 34 a extends long in the y direction. The plurality of trenches 34 a are arranged at intervals in the x direction. As will be described in detail later, a switching element using a plurality of trenches 34a as a gate is formed under the source electrode 80a. Hereinafter, the semiconductor region under the source electrode 80a (the region in which the switching element is formed) is referred to as a first element region 90a.

  Further, a plurality of trenches 34 b are formed in the surface 12 a of the semiconductor substrate 12 below the source electrode 80 b. Each trench 34 b is elongated in the y direction. The plurality of trenches 34 b are arranged at intervals in the x direction. As will be described in detail later, below the source electrode 80b, a switching element using a plurality of trenches 34b as a gate is formed. Hereinafter, the semiconductor region under the source electrode 80b (the region in which the switching element is formed) is referred to as a second element region 90b. At surface 12a, each trench 34b in second element region 90b extends on an extension of a corresponding trench 34a in first element region 90a. That is, the pair of trenches 34a and 34b are arranged to extend on one straight line on the surface 12a. A trench is not formed in the region between the first element region 90a and the second element region 90b (that is, the region under the gate pad 62 in FIG. 1). That is, the trench 34b in the second element region 90b is separated from the trench 34a in the first element region 90a by the region between the first element region 90a and the second element region 90b.

  Next, the structure of the first element region 90a will be described. As shown in FIG. 3, the gate insulating layer 38 and the gate electrode 35 are formed in each trench 34a. The gate insulating layer 38 has a bottom insulating layer 38a and a side insulating film 38b. Bottom insulating layer 38 a is a thick insulating layer formed at the bottom of trench 34. The side surface of the trench 34 above the bottom insulating layer 38a is covered by the side insulating film 38b. A gate electrode 35 is disposed in the trench 34 above the bottom insulating layer 38a. The gate electrode 35 is insulated from the semiconductor substrate 12 by the side insulating film 38 b and the bottom insulating layer 38 a. The surface of the gate electrode 35 is covered by an interlayer insulating layer 36. Gate electrode 35 is insulated from source electrode 80 a by interlayer insulating layer 36.

  As shown in FIG. 3, a source region 22, a body region 26, a drift region 28, a drain region 30, and a bottom region 32 are formed in the semiconductor substrate 12 in the first element region 90a.

  A plurality of source regions 22 are formed in the first element region 90a. The source region 22 is an n-type region. Source region 22 is formed at a position adjacent to trench 34 a in the x direction. Source region 22 is in contact with side insulating film 38 b covering the side of trench 34 a. More specifically, source region 22 is in contact with side insulating film 38b covering the side of trench 34a extending along the y direction (longitudinal direction of trench 34a). Source region 22 is formed in a range exposed to surface 12 a of semiconductor substrate 12. Source region 22 is in ohmic contact with source electrode 80a.

  The body region 26 is formed on the side and the lower side of the source region 22 and is in contact with the source region 22. Body region 26 is a p-type region. Body region 26 is exposed to surface 12 a of semiconductor substrate 12 at a position where source region 22 is not formed. Body region 26 has a high p-type impurity concentration in the vicinity of surface 12 a and is in ohmic contact with source electrode 80 a. Body region 26 is in contact with side insulating film 38 b below source region 22. More specifically, body region 26 is in contact with side insulating film 38 b covering the side of trench 34 a extending along the y direction (longitudinal direction of trench 34 a). Body region 26 has a low p-type impurity concentration below source region 22.

  The drift region 28 is an n-type region containing an n-type impurity at a low concentration. The n-type impurity concentration of drift region 28 is lower than the n-type impurity concentration of source region 22. Drift region 28 is formed under body region 26. Drift region 28 is in contact with body region 26 and is separated from source region 22 by body region 26. Drift region 28 is in contact with side insulating film 38 b below body region 26. More specifically, drift region 28 is in contact with side insulating film 38 b covering the side of trench 34 a extending along the y direction (longitudinal direction of trench 34 a).

  The source region 22, the body region 26 and the drift region 28 described above face the gate electrode 35 via the side insulating film 38 b.

  The drain region 30 is an n-type region containing an n-type impurity at a high concentration. The n-type impurity concentration of drain region 30 is higher than the n-type impurity concentration of drift region 28. The drain region 30 is formed below the drift region 28. Drain region 30 is in contact with drift region 28 and is separated from body region 26 by drift region 28. The drain region 30 is formed in a range exposed on the back surface 12 b of the semiconductor substrate 12. The drain region 30 is in ohmic contact with the drain electrode 84.

  Bottom region 32 is a p-type region. Bottom region 32 is in contact with the bottom of each trench 34 (i.e., the lower end of bottom insulating layer 38a). Bottom region 32 is in contact with the entire bottom surface of trench 34. The bottom region 32 is surrounded by the drift region 28. Each bottom region 32 is separated from one another by a drift region 28. Also, each bottom region 32 is separated from the body region 26 by a drift region 28. The bottom region 32 is not connected to any electrode, and the potential of the bottom region 32 is a floating potential. Bottom region 32 is a p-type region formed by implanting Al (aluminum) into semiconductor substrate 12.

  Next, the structure of the second element region 90b will be described. The second element region 90 b has substantially the same structure as the first element region 90 a. A gate insulating layer 38 and a gate electrode 35 are formed in each trench 34 b in the second element region 90 b. A source region 22, a body region 26, a drift region 28, a drain region 30, and a bottom region 32 are formed in the semiconductor substrate 12 in the second element region 90b. The cross-sectional structure of the second element region 90b (that is, the cross-sectional structure along the line AA in FIG. 1) is equal to that in FIG.

  As shown in FIGS. 4 and 5, the surface 12a of the semiconductor substrate 12 in the region between the first element region 90a and the second element region 90b (hereinafter referred to as the boundary region 92) is covered with the interlayer insulating layer 40. There is. Gate pad 62 is formed on interlayer insulating layer 40. Gate pad 62 is insulated from semiconductor substrate 12 by interlayer insulating layer 40. As shown in FIG. 4, the gate pad 62 is connected to each gate electrode 35 via the wiring layer 42.

  As shown in FIGS. 4 and 5, a p-type isolation region 64 is formed under the gate pad 62. As shown in FIG. 2, the isolation region 64 extends along the x direction between the first element region 90a and the second element region 90b. That is, the isolation region 64 extends along the gate pad 62. The separation region 64 is exposed to the surface 12 a of the semiconductor substrate 12. As shown in FIG. 4, the separation region 64 is lower than the lower end of the bottom region 32 in the first element region 90 a from the surface 12 a and the lower end of the bottom region 32 in the second element region 90 b (that is, a deeper position). Has been extended to The isolation region 64 is a p-type region formed by implanting B (boron) into the semiconductor substrate 12. B has a larger diffusion coefficient in the semiconductor substrate 12 than Al. Therefore, by ion implantation of B, a p-type region distributed from the surface to a deep position like the separation region 64 can be formed.

  As shown in FIGS. 4 and 5, the drift region 28 and the drain region 30 are formed to extend from the first element region 90 a to the second element region 90 b through the lower side of the isolation region 64. That is, below the isolation region 64, the drift region 28 and the drain region 30 are formed. Also, the drift region 28 is formed on the side of the isolation region 64. As shown in FIG. 4, a drift region 28 is formed between the isolation region 64 and each of the trenches 34a and 34b. Isolation region 64 is separated from each bottom region 32 by drift region 28. Further, as shown in FIG. 5, a drift region 28 is formed between the isolation region 64 and each body region 26. Isolation region 64 is separated from each body region 26 by drift region 28.

  As shown in FIG. 4, the distance L1 between the separation region 64 and the bottom region 32 of the first element region 90a is substantially equal to the distance L2 between the separation region 64 and the bottom region 32 of the second element region 90b. Further, in the present embodiment, the isolation region 64 is disposed between the bottom region 32 of the first element region 90a and the bottom region 32 of the second element region 90b. Thus, both distance L1 and distance L2 are less than half the distance L3 between trench 34a and trench 34b.

  Further, in FIG. 4, the positions of the body regions 26 in contact with the trenches 34a and 34b are indicated by broken lines. As shown in FIG. 4, the distance L4 between the body region 26 and the bottom region 32 in the first element region 90a is substantially equal to the distance L5 between the body region 26 and the bottom region 32 in the second element region 90b. . Further, a distance L6 between isolation region 64 and body region 26 of first element region 90a is substantially equal to a distance L7 between isolation region 64 and body region 26 of second element region 90b. In the present embodiment, both of the distance L4 and the distance L5 are shorter than any of the distance L6 and the distance L7.

  A wire is bonded to the gate pad 62. Since the surface of the gate pad 62 is flat, a wire can be suitably bonded to the gate pad 62. That is, as shown in FIG. 3, the surface of the semiconductor device 10 in the first element region 90a and the second element region 90b has unevenness. This is because the trenches 34a and 34b are formed in the first element region 90a and the second element region 90b. On the other hand, as shown in FIGS. 4 and 5, in the boundary region 92 between the first element region 90a and the second element region 90b, the trench 34 is not formed, so the surface 12a of the semiconductor substrate 12 is flat. is there. Since the gate pad 62 is formed on the top of such a flat surface 12a, the surface of the gate pad 62 is also flat. Therefore, a wire can be suitably bonded to the gate pad 62.

  In addition, since the trenches 34 are not formed under the gate pads 62, it is difficult for the impact applied to the gate pads 62 at the time of wire bonding to be transmitted to the respective trenches 34. Thereby, high reliability of the semiconductor device 10 is secured.

  Next, the operation of the semiconductor device 10 will be described. In the first element region 90a and the second element region 90b, an n-channel MOSFET is formed by the source region 22, the body region 26, the drift region 28, the drain region 30, the gate electrode 35, the gate insulating layer 38 and the like. ing. When operating the semiconductor device 10, a potential higher than that of the source electrodes 80 a and 80 b is applied to the drain electrode 84. Approximately the same potential is applied to the source electrode 80a and the source electrode 80b. Furthermore, when a potential higher than the threshold is applied to the gate electrode 35, the MOSFET in the first element region 90a and the MOSFET in the second element region 90b are turned on. That is, a channel is formed in the body region 26 in the range in contact with the side insulating film 38 b. Thereby, electrons flow from the source electrodes 80 a and 80 b toward the drain electrode 84 via the source region 22, the channel, the drift region 28 and the drain region 30.

  When the potential of the gate electrode 35 is lowered to a potential lower than the threshold, the channel disappears, and the MOSFETs in the first element region 90a and the second element region 90b are turned off. Then, in each of the first element region 90a and the second element region 90b, a depletion layer spreads in the drift region 28 from the pn junction at the boundary between the body region 26 and the drift region 28. The depletion layer extending from the body region 26 reaches the bottom region 32. Then, a depletion layer spreads from bottom region 32 into drift region 28 therearound. Depletion layers extending from bottom regions 32 of first element region 90 a and second element region 90 b reach isolation region 64. Then, the depletion layer spreads from the isolation region 64 into the drift region 28 below it. As a result, the depletion layer extending from the bottom region 32 of the first element region 90a, the depletion layer extending from the bottom region 32 of the second element region 90b, and the depletion layer extending from the isolation region 64 are connected to each other. Region 28 is depleted. The dotted line 76 in FIG. 6 indicates the position of the lower end of the depletion layer at a certain timing when the depletion layer extends. That is, the depletion layer extends in the drift region 28 above the dotted line 76. As shown in FIG. 6, when the MOSFET is turned off, a depletion layer 76 extends across the first element region 90a, the second element region 90b, and the boundary region 92. Thus, the depletion layer extending from the isolation region 64 depletes the boundary region 92 between the first element region 90a and the second element region 90b. For this reason, generation of a high electric field in the boundary region 92 is prevented. Therefore, the semiconductor device 10 has a high withstand voltage.

  Further, as described above, when the distances L4 and L5 are shorter than the distances L6 and L7, the electric field in the vicinity of the isolation region 64 can be further relaxed. That is, if distances L6 and L7 are shorter than distances L4 and L5, the depletion layer extending from body region 26 reaches isolation region 64 earlier than bottom region 32. Then, the potential of the separation region 64 is close to the potential of the body region 26. On the other hand, in the present embodiment, since the distances L4 and L5 are shorter than the distances L6 and L7, the depletion layer extending from the body region 26 reaches the bottom region 32 earlier than the isolation region 64. Thus, the depletion layer extends from the body region 26 to the isolation region 64 via the bottom region 32. For this reason, the separation region 64 has a potential sufficiently higher than that of the body region 26. This further suppresses the occurrence of a high electric field in drift region 28 below isolation region 64. Also in this case, the withstand voltage of the semiconductor device 10 is improved.

  Further, when the semiconductor device 10 operates, the potential of the gate pad 62 changes. If the switching element is formed under the gate pad 62, the operation of the switching element may be unstable due to the change of the potential of the gate pad 62. On the other hand, in the semiconductor device 10 of the present embodiment, since the switching element (i.e., the gate structure such as the trench 34) is not formed under the gate pad 62, the operation of the switching element is prevented from becoming unstable. Be done.

  In the embodiment described above, as shown in FIG. 6, the separation region 64 extends from the surface 12 a to a position lower than the lower end of each bottom region 32. However, as shown in FIG. 7, the separation region 64 may be formed only on the upper side of the bottom region 32. In such a configuration, it is preferable to make the distances L1 and L2 between the isolation regions 64 and the respective bottom regions 32 shorter than half of the distance L3 between the trenches 34a and 34b. By setting the distances L1 and L2 in this manner, the depletion layers extending from the bottom regions 32 reach the separation regions 64 before the depletion layers extending from the bottom regions 32 are connected to each other, and the periphery from the separation regions 64 The depletion layer extends to the Therefore, the depletion layer can be extended more quickly between first element region 90a and second element region 90b compared to the case where isolation region 64 does not exist, and the electric field in boundary region 92 is more effectively suppressed. Be done. However, when the separation region 64 is positioned above the respective bottom regions 32, the depletion layer 76 is distributed in a concave shape on the upper side in the lower part of the separation region 64 as shown in the recess 72 of FIG. When the recess 72 is thus formed in the depletion layer 76, the electric field is likely to be concentrated in the recess 72. In order to prevent the formation of such a recess 72, the separation region 64 preferably extends below the bottom of each trench 34a, 34b. In addition, when the positions (positions in the thickness direction) of the depletion layer below the first element region 90a, the second element region 90b, and the isolation region 64 are the same, concentration of the electric field can be alleviated most. However, it is practically difficult to make the positions of these depletion layers identical. Therefore, as shown in FIG. 6, it is more preferable that the separation region 64 extend below the lower end of each bottom region 32. According to this configuration, the depletion layer 76 protrudes downward below the isolation region 64, as shown by the convex portion 74 in FIG. When the convex portion 74 is formed as described above, electric field concentration can be suppressed as compared with the case where the concave portion 72 is formed as shown in FIG. 7.

  Further, in the semiconductor device 10 of the above-described embodiment, the isolation region 64 is isolated from each bottom region 32. However, as shown in FIG. 8, the separation area 64 may be connected to each bottom area 32. In such a configuration, when the depletion layer extending from the body region 26 reaches the bottom region 32, the depletion layer extends from the entirety of each bottom region 32 and the isolation region 64 toward the surrounding drift region 28 substantially simultaneously. Therefore, even in this configuration, the depletion layer can be effectively extended between the first element region 90a and the second element region 90b.

  In the embodiment described above, the potential of the bottom region 32 is a floating potential. However, the bottom region 32 may be connected to a predetermined fixed potential.

  The relationship between the above-described embodiment and each element of the claims will be described. The first element region 90a in the embodiment is an example of a first element region in the claims. The first element region 90b in the embodiment is an example of a second element region in the claims. The y direction of the embodiment is an example of the longitudinal direction of the claims. The side insulating film 38 b of the embodiment is an example of “a side portion of the gate insulating layer covering the side of the gate trench extending along the longitudinal direction of the gate trench” in the claims. The bottom insulating layer 38a in the embodiment is an example of the “bottom of gate insulating layer covering the bottom of the gate trench” in the claims. The source region 22 in the embodiment is an example of a first region in claims. The drift region 28 in the embodiment is an example of a second region in the claims. The distance L1 in the embodiment is an example of the “distance between the separation region and the bottom region of the first element region” in the claims. The distance L2 in the embodiment is an example of the “distance between the separation region and the bottom region of the second element region” in the claims. The distance L3 in the embodiment is an example of the “distance between the first trench and the second trench” in the claims. The distance L4 in the embodiment is an example of the “distance between the body region of the first element region and the bottom region of the first element region” in the claims. The distance L5 in the embodiment is an example of the “distance between the body region of the second element region and the bottom region of the second element region” in the claims. The distance L6 in the embodiment is an example of the “distance between the isolation region and the body region of the first element region” in the claims. The distance L7 in the embodiment is an example of the “distance between the isolation region and the body region of the second element region” in the claims.

  The configurations of the semiconductor devices disclosed in the present specification are listed below. The separation region is separated from the bottom region of the first element region and separated from the bottom region of the second element region. Both the distance between the isolation region and the bottom region of the first element region and the distance between the isolation region and the bottom region of the second element region are more than half the distance between the first trench and the second trench. short.

  In the example semiconductor device disclosed in the present specification, the isolation region extends from the surface of the semiconductor substrate to a position deeper than any of the bottom of the first trench and the bottom of the second trench.

  In the present specification, the above-mentioned "deep position" means a position far from the surface of the semiconductor substrate.

  According to this configuration, the depletion layer can be easily connected from the bottom region to the isolation region.

  In one example of the semiconductor device disclosed in the present specification, the distance between the body region of the first element region and the bottom region of the first element region, and the body region of the second element region to the bottom region of the second element region. Both of the distances between them are shorter than both of the distance between the separation region and the body region of the first element region and the distance between the separation region and the body region of the second element region.

  According to this configuration, the depletion layer extending from the body region reaches the bottom region before reaching the separation region. That is, the depletion layer extends from the body region, via the bottom region, to the isolation region. By extending the depletion layer in this manner, a potential difference can be generated between the separation region and the body region, and electric field concentration around the separation region can be further suppressed.

  In the semiconductor device according to an example disclosed in this specification, the separation region is an end portion on the back surface side of the bottom region of the first element region and an end portion on the back surface side of the bottom region of the second device region It extends to a deeper position than either.

  When the end on the back surface side of the separation region is disposed at a position shallower than the end on the back surface side of the bottom region (closer to the surface of the semiconductor substrate), the depletion layer is distributed concavely in the vicinity of the separation region, The electric field is concentrated. As described above, when the separation region extends to a position deeper than the end on the back surface side of each bottom region, the depletion layer is distributed in a convex shape in the vicinity of the separation region, and electric field concentration can be suppressed.

  In the example semiconductor device disclosed in the present specification, the interlayer insulating layer is formed on the surface between the first trench and the second trench, and the bonding pad is formed on the interlayer insulating layer.

As mentioned above, although embodiment was described in detail, these are only examples and do not limit the range of a claim. The art set forth in the claims includes various variations and modifications of the specific examples illustrated above.
The technical elements described in the present specification or the drawings exhibit technical usefulness singly or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the techniques illustrated in the present specification or the drawings simultaneously achieve a plurality of purposes, and achieving one of the purposes itself has technical utility.

10: semiconductor device 12: semiconductor substrate 22: source region 26: body region 28: drift region 30: drain region 32: bottom region 34a, 34b: trench 35: gate electrode 38: gate insulating layer 62: gate pad 64: isolation region 80a, 80b: source electrode 84: drain electrode 90a: first element region 90b: second element region 92: boundary region

Claims (5)

A semiconductor device,
A semiconductor substrate having a front surface and a back surface;
A gate trench formed on the surface, comprising: a first trench; and a second trench separated from the first trench and extending on a longitudinal extension of the first trench on the surface. With the gate trench,
A gate insulating layer covering the inner surface of the gate trench;
A gate electrode disposed in the gate trench and insulated from the semiconductor substrate by the gate insulating layer;
Have
The semiconductor substrate has a first element region adjacent to the first trench and a second element region adjacent to the second trench,
Each of the first element region and the second element region is
A first region of a first conductivity type that is in contact with the side surface portion of the gate insulating layer covering the side surface of the gate trench that extends along the longitudinal direction of the gate trench, and exposed to the surface;
A body region of a second conductivity type in contact with the side surface portion on the back surface side of the first region;
A second region of a first conductivity type, which is in contact with the side surface on the back side of the body region and is separated from the first region by the body region;
A bottom region of a second conductivity type, in contact with the bottom portion of the gate insulating layer covering the bottom surface of the gate trench, separated from the body region by the second region;
And have
The semiconductor substrate is disposed between the first trench and the second trench, and is separated from the body region of the first element region and the body region of the second element region. A position separated from the bottom region of the element region and the bottom region of the second element region and deeper than any of the body region of the first element region and the body region of the second element region from the surface further have a separation region of a second conductivity type extends to,
A distance between the body region of the first element region to the bottom region of the first element region, and a distance between the body region of the second element region to the bottom region of the second element region Both are shorter than any of the distance between the separation region and the body region of the first element region and the distance between the separation region and the body region of the second element region,
Semiconductor device. The separation region is separated from the bottom region of the first element region and separated from the bottom region of the second element region,
Both the distance between the separation region and the bottom region of the first element region and the distance between the separation region and the bottom region of the second element region are the first trench and the second trench. The semiconductor device of claim 1, wherein the semiconductor device is shorter than half the distance between the two.   The semiconductor device according to claim 1, wherein the isolation region extends from the surface to a position deeper than any of the bottom surface of the first trench and the bottom surface of the second trench. The separation region extends from the surface to a position deeper than any of the end on the back surface side of the bottom region of the first element region and the end on the back surface side of the bottom region of the second element region. The semiconductor device according to any one of claims 1 to 3 . An interlayer insulating layer is formed on the surface between the first trench and the second trench,
Bonding pads are formed on the interlayer insulating layer,
The semiconductor device of any one of claims 1 to 4 .

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