JP4404709B2 - Insulated gate semiconductor device and manufacturing method thereof - Google Patents

Insulated gate semiconductor device and manufacturing method thereof Download PDF

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JP4404709B2
JP4404709B2 JP2004204880A JP2004204880A JP4404709B2 JP 4404709 B2 JP4404709 B2 JP 4404709B2 JP 2004204880 A JP2004204880 A JP 2004204880A JP 2004204880 A JP2004204880 A JP 2004204880A JP 4404709 B2 JP4404709 B2 JP 4404709B2
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floating
trench
body region
located
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JP2006032420A (en
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康嗣 大倉
恭輔 宮城
規仁 戸倉
知治 池田
秀史 高谷
晃 黒柳
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トヨタ自動車株式会社
株式会社デンソー
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an insulation gate semiconductor device capable of surely attaining a high withstanding voltage and a low on-resistance and easily being made compact. <P>SOLUTION: The semiconductor device 100 includes an n<SP>+</SP>source region 31, an n<SP>+</SP>drain region 11, a p<SP>-</SP>body region 41, a p<SP>-</SP>floating body region 42, and an n<SP>-</SP>drift region 12. Further, the termination area of the semiconductor device 100 includes a termination trench 61 surrounding a cell area. Then a p<SP>-</SP>floating embedded region 51 and a p<SP>-</SP>floating embedded region 52 are provided to a lower part of each trench. An interval d1 between the p<SP>-</SP>body region 41 and the p<SP>-</SP>floating body region 42 is selected narrower than an interval d2 between the p<SP>-</SP>body region 41 and the p<SP>-</SP>floating embedded region 51. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

  The present invention relates to an insulated gate semiconductor device having a trench gate structure and a method for manufacturing the same. More specifically, the present invention relates to an insulated gate semiconductor device that achieves both high breakdown voltage and low on-resistance by relaxing electric field concentration on a semiconductor layer, and a method for manufacturing the same.

  Conventionally, a trench gate type semiconductor device having a trench gate structure has been proposed as an insulated gate type semiconductor device for power devices. In this trench gate type semiconductor device, a high breakdown voltage and a low on-resistance are generally in a trade-off relationship.

  As a semiconductor device paying attention to this problem, for example, there is a semiconductor device disclosed in Patent Document 1. In this semiconductor device, electric field concentration can be alleviated by providing a P-type buried layer in an N-type semiconductor layer in a semiconductor substrate. Further, the electric field concentration applied to the semiconductor layer occurs not only in the cell area but also in the terminal area surrounding the cell area. Therefore, in the semiconductor device disclosed in Patent Document 1, electric field concentration is reduced by providing a P-type guard ring layer in the termination area. This P-type guard ring layer is also provided at a position where the P-type buried layer is formed in consideration of a depletion layer extending in the drift layer. That is, the P-type buried layer can increase the breakdown voltage of the cell area, and the P-type guard ring layer can increase the breakdown voltage of the termination area.

  However, in order to increase the breakdown voltage in the P-type guard ring layer as in the semiconductor device disclosed in Patent Document 1, it is equal to or more than the depletion layer that extends toward the termination area in the N-type semiconductor layer of the semiconductor device. It is necessary to secure an area of a size of as a guard ring layer area. For this reason, the termination area is widened, which hinders downsizing of the entire semiconductor device.

Therefore, the present applicant has proposed an insulated gate semiconductor device 900 as shown in FIG. 23 as a trench gate type semiconductor device that solves the trade-off problem between high breakdown voltage and low on-resistance (special feature). Application No. 2003-349806). In this insulated gate semiconductor device 900, a gate trench 21 penetrating the P body region 41 is provided in the cell area. A P floating buried region 51 formed by implanting impurities (boron or the like) from the bottom of the gate trench 21 is provided. The P floating buried region 51 increases the breakdown voltage in the cell area.

Further, a termination trench 61 penetrating the P body region 41 is also provided in the termination area in the insulated gate semiconductor device 900 as in the cell area. This termination trench 61 blocks the spread of the depletion layer extending in the N drift region 12 in the plate surface direction (lateral direction and depth direction in FIG. 23), thereby reducing electric field concentration. Further, a P floating buried region 52 formed by implanting impurities from the bottom of the termination trench 61 is also provided below the termination trench 61. The P floating buried region 52 increases the breakdown voltage in the termination area in the same manner as the cell area.
JP-A-9-191109

However, in the above-described trench gate type semiconductor device 900, the provision of the termination trench 61 causes the following problems. That is, in the trench gate type semiconductor device 900, as shown in FIG. 24, the gate trenches 21 in the cell area (inside the broken line frame X in FIG. 24) are provided in stripes. A termination trench 61 in the termination area (outside the broken line frame X in FIG. 24) is formed so as to surround the cell area. Furthermore, the termination trench 61 in the termination area is formed so as not to intersect with the gate trench 21 in the cell area. Therefore, there is a break in the gate trench 21 near the boundary between the cell area and the termination area. Then, in the vicinity of the cut (within the broken line frame Y in FIG. 24), the gap between the wall surface of the termination trench 61 and the end portion in the longitudinal direction of the gate trench 21 varies. That, P cell area - variations in the distance between the floating buried region 52 - P floating buried region 51 and the terminal area. As a result, a portion having a breakdown voltage different from the design breakdown voltage in the cell area is generated, and the breakdown voltage is lowered.

  In addition, as shown in FIG. 25, each trench may be formed so as to connect the termination trench 61 in the termination area and the gate trench 21 in the cell area. By arranging the trenches in this way, the cuts in the trenches can be eliminated. However, in this arrangement, since the ease of entering the etching gas differs between the joint portion of the trench and other portions, the depth of the trench becomes non-uniform. That is, the depth of the P floating region becomes non-uniform and the withstand voltage decreases.

  The present invention has been made to solve the problems of the conventional insulated gate semiconductor device described above. That is, an object of the present invention is to provide an insulated gate semiconductor device that can surely achieve a high breakdown voltage and a low on-resistance and can be easily made compact.

  An insulated gate semiconductor device for solving this problem includes a drift region which is a first conductivity type semiconductor located on the main surface side of a semiconductor substrate, and a second conductivity type semiconductor located on the upper surface side of the drift region. A first floating region that is surrounded by a drift region and at least partly located below the body region, and is a second conductivity type semiconductor; The body region penetrates in the thickness direction of the semiconductor substrate and its bottom portion is located in the first floating region, the first trench portion group containing the gate electrode, and the upper surface side of the drift region, the main surface of the semiconductor substrate A second conductivity type semiconductor that is located around the body region as viewed from the side and that is at least partially opposed to the body region across the drift region and is a second conductive semiconductor. A third floating region that is surrounded by the drifting region and the drift region and is located below the second floating region, penetrates the body region in the thickness direction of the semiconductor substrate and the bottom of the body region Is located in the first floating region, a part of the wall surface is provided with a second trench portion facing the end of each trench of the first trench portion group, and the body region and the second floating region are opposed to each other. The space between the body region and the second floating region at the portion being located is narrower than the space between the body region and the first floating region.

  That is, in the insulated gate semiconductor device of the present invention, the body region of the second conductivity type semiconductor is located on the upper surface side of the drift region of the first conductivity type semiconductor. Furthermore, a first trench portion group penetrating the body region in the thickness direction is provided, and the bottom of each trench portion of the first trench portion group is located in the first floating region that is the second conductivity type semiconductor. Yes. In other words, in the thickness direction of the semiconductor device, the first floating region faces the body region with the drift region interposed therebetween. Further, a second floating region of a second conductivity type semiconductor is provided on the main surface side of the semiconductor substrate, at least a part of which is opposed to the body region with the drift region interposed therebetween. That is, there is a portion where the second floating region faces the body region across the drift region when viewed from the main surface side of the semiconductor substrate. Specifically, a portion that separates the body region and the second floating region is provided in the vicinity of both ends in the longitudinal direction of the first trench portion group. The interval between the body region and the second floating region is narrower than the interval between the body region and the first floating region.

  In the drift region of this insulated gate semiconductor device, when a voltage is applied between the drain and source, a depletion layer spreads from the boundary with the body region. The depletion layer is located closer to the termination area than the first floating region located below the body region because the interval between the body region and the second floating region is narrower than the interval between the body region and the first floating region. The second floating area to be reached first. Therefore, in the insulated gate semiconductor device of the present invention, the electric field strength can be more reliably reduced in the plate surface direction than in the thickness direction. As a result, even if there is some variation in the distance between the first floating region and the third floating region, breakdown does not occur before the cell area. Therefore, the breakdown voltage of the entire semiconductor device is determined by the design of the cell area (thickness direction). Therefore, it is possible to suppress the occurrence of a part having a breakdown voltage different from the design breakdown voltage in the cell area, and to surely increase the breakdown voltage of the entire semiconductor device.

  In addition, by providing the second trench portion facing each trench of the first trench portion group in the termination area, the spread of the depletion layer toward the termination area is blocked. As a result, the shape of the tip of the depletion layer is flattened and the electric field concentration is relaxed. Then, the peak of the electric field strength can be further reduced by the third floating region provided below the second trench portion. That is, a high breakdown voltage can be achieved without increasing the size of the termination area, and the entire semiconductor device can be easily made compact.

  In order to increase the breakdown voltage of the semiconductor device, as viewed from the main surface side of the semiconductor substrate, each trench portion of the first trench portion group penetrates the drift region, and its end portion is in the second floating region. It is preferable to be located at. That is, it is preferable that the distance between the first floating region in the cell area and the third floating region in the termination area is narrow. This is because, if this interval is too wide, the withstand voltage between them will decrease.

  Another insulated gate semiconductor device of the present invention includes a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate, and a body that is a second conductivity type semiconductor located on an upper surface side of the drift region. An insulated gate semiconductor device provided with a region, surrounded by a drift region and at least partially positioned below the body region, wherein the first floating region, which is a second conductivity type semiconductor, and the body region It penetrates in the thickness direction of the semiconductor substrate and its bottom is located in the first floating region, is located on the upper surface side of the first trench portion group incorporating the gate electrode and the drift region, and is viewed from the main surface side of the semiconductor substrate. A second floating region that is located around the body region and at least partly faces the body region across the drift region and is a second conductivity type semiconductor, Surrounded by the drift region and positioned below the second floating region, the third floating region, which is a second conductivity type semiconductor, penetrates the body region in the thickness direction of the semiconductor substrate, and its bottom portion becomes the third floating region. A part of the wall surface of which is located in the trench part of the first trench part group, the second trench part facing the end of each trench of the first trench part group, and the body region and the first part 2 A conductor portion facing at least a part of a drift region separating the floating region is provided.

  That is, in this insulated gate type semiconductor device, a conductor portion that is opposed to at least a part of the drift region between the body region and the second floating region is provided in each trench portion of the first trench portion group. By providing this conductor portion, the spread of the depletion layer is promoted by the field plate effect in the portion of the drift region facing the conductor portion. For this reason, the depletion layer spreading in the plate surface direction spreads faster than the depletion layer spreading in the thickness direction. Accordingly, the interval between the body region and the second floating region is such that the depletion layer extending in the plate surface direction is larger than the drain-source voltage for the depletion layer extending in the thickness direction to reach the first floating region in the second floating region. It may be designed so that the drain-source voltage to reach is lower. Therefore, this insulated gate type semiconductor device has a higher degree of design freedom.

  In order to promote the spread of the depletion layer extending in the plate surface direction, it is sufficient if there is a conductor region facing the drift region. That is, the conductor region may be provided on the main surface of the semiconductor substrate in addition to the trench portion. For example, the gate wiring may be arranged on the main surface of the semiconductor substrate so as to straddle between the body region and the second floating region, and the gate wiring may be a conductor portion facing the drift region.

  Another insulated gate semiconductor device of the present invention includes a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate, and a body that is a second conductivity type semiconductor located on an upper surface side of the drift region. An insulated gate semiconductor device provided with a region, surrounded by a drift region and at least partially positioned below the body region, and a first floating region as a second conductivity type semiconductor, and a drift region A second floating region that is located on the upper surface side and is located in the termination area, at least part of which faces the body region with the drift region interposed therebetween when viewed from the main surface side of the semiconductor substrate; In the thickness direction of the semiconductor substrate, its bottom is located in the first floating region, its longitudinal end is located in the second floating region, and the gate It is characterized in that the trench portion group having a built-in electrode is provided.

  That is, in this insulated gate type semiconductor device, the end portion in the longitudinal direction of each trench portion is provided in the second floating region located in the termination area facing the body region. Furthermore, the bottom part of the trench part whose end part is provided up to the termination area is located in the first floating region. That is, the breakdown voltage structure in the cell area is built as it is to the termination area. Therefore, the interval between adjacent first floating regions is constant up to the termination area. Therefore, there is no variation in the spacing between the floating regions, and a decrease in breakdown voltage is suppressed. In addition, it is better that the first floating region and the second floating region are connected. In other words, it is possible to suppress variations in the portion where the breakdown voltage decreases by setting the potentials of both floating regions to the same potential.

  The method for manufacturing an insulated gate semiconductor device according to the present invention includes a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate, and a second conductivity type semiconductor located on an upper surface side of the drift region. A method of manufacturing an insulated gate semiconductor device provided with a certain body region, comprising: a drift region forming step for forming a drift region which is a first conductivity type semiconductor on a substrate; and a drift region forming step. By implanting impurities into the drift region, a body region that is a second conductivity type semiconductor and a first diffusion region that is a second conductivity type semiconductor that is at least partially opposed to the body region across the drift region A first impurity implantation step for forming a first trench portion, a first trench portion group penetrating the body region formed in the first impurity implantation step in the thickness direction of the semiconductor substrate, and a first impurity A trench portion forming step for forming the second trench portion penetrating the first diffusion region formed in the entry step, and each of the trench portions and the second trench portion of the first trench portion group formed in the trench portion forming step. And a second impurity implantation step of forming a second diffusion region which is a second conductivity type semiconductor by implanting impurities from each bottom.

  In this manufacturing method, in the drift region forming step, the drift region which is the second conductivity type semiconductor is formed on the substrate by epitaxial growth or the like. Then, in the first impurity implantation step, an impurity is implanted into the drift region, thereby forming a body region and a first diffusion region that are the first conductivity type semiconductor. Further, in the trench portion forming step, a first trench portion group that penetrates the body region and a second trench portion that penetrates the first diffusion region are formed. Then, in the second impurity implantation step, the second diffusion region is formed by implanting impurities from each trench portion. That is, since the second diffusion region is formed after the formation of the drift region or the like, it is not necessary to form a single crystal silicon layer by epitaxial growth again after the formation of the second diffusion region. Therefore, an insulated gate semiconductor device having a floating region can be easily manufactured. In addition, the first diffusion region located in the termination area is formed together with the body region located in the cell area. Moreover, the termination | terminus trench part located in a termination | terminus area is formed with the trench part located in a cell area. Therefore, the number of processes does not increase due to the formation of the components of the termination area.

  Further, another method of manufacturing an insulated gate semiconductor device according to the present invention includes a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate, and a second conductivity type located on an upper surface side of the drift region. A method of manufacturing an insulated gate semiconductor device provided with a body region that is a semiconductor, comprising: a drift region forming step of forming a drift region that is a first conductivity type semiconductor on a substrate; and a drift region forming step By implanting impurities into the formed drift region, a body region that is a second conductivity type semiconductor and a first conductivity type semiconductor that is at least partially opposed to the body region with the drift region interposed therebetween. A first impurity implantation step for forming a diffusion region; a body region formed in the first impurity implantation step through the thickness direction of the semiconductor substrate; A trench portion forming step for forming a trench portion group located in the diffusion region, and by implanting impurities from the bottom and longitudinal ends of each trench portion formed in the trench portion forming step, And a second impurity implantation step for forming a certain second diffusion region.

  According to the present invention, the termination area near the end of the trench located in the cell area has a two-stage floating structure due to the presence of the second floating region and the third floating region. High breakdown voltage. Therefore, even if there is some variation in the distance between the first floating region in the cell area and the third floating region in the termination area, the breakdown voltage of the entire semiconductor device does not decrease. According to another invention, the termination area is configured while maintaining the floating structure of the cell area. That is, there is no variation between the floating regions, and the breakdown voltage of the entire semiconductor device does not decrease. Therefore, an insulated gate semiconductor device that can surely achieve high breakdown voltage and low on-resistance and can be easily made compact is realized.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below in detail with reference to the accompanying drawings. In the present embodiment, the present invention is applied to a power MOS that controls conduction between a drain and a source (between DS) by applying a voltage to an insulated gate.

[First embodiment]
An insulated gate semiconductor device 100 (hereinafter referred to as “semiconductor device 100”) according to the first embodiment has a structure shown in a plan perspective view of FIG. 1 and a sectional perspective view of FIG. Note that in this specification, the whole of the starting substrate and the single crystal silicon portion formed by epitaxial growth on the starting substrate is referred to as a semiconductor substrate. In FIG. 1 and FIG. 2, the source electrode, the drain electrode, and the interlayer insulating film are omitted to simplify the description. Moreover, the cross-sectional perspective view of FIG. 2 shows the inside of the broken line frame Y in FIG.

  In the semiconductor device 100 of the present embodiment, as shown in FIG. 1, a plurality of gate trenches 21 are provided in the cell area (inside the broken line frame X in FIG. 1), and a plurality of gate trenches 21 are provided in the termination area (outside the broken line frame X in FIG. 1). A termination trench 61 is provided. The gate trench 21 is formed in a stripe shape, and the termination trench 61 is formed in a concentric ring shape so as to surround the cell area. Further, the gate trench 21 and the termination trench 61 are not connected, and there is no trench connection. Therefore, in the semiconductor device 100 of this embodiment, there is no problem due to the nonuniformity of the trench depth.

Further, as shown in FIG. 2, the semiconductor device 100 is provided with an N + source region 31 on the upper surface side and an N + drain region 11 on the lower surface side. In the cell area of semiconductor device 100, P body region 41 and N drift region 12 are provided from the upper surface side. The P body region 41 is surrounded by the N drift region 12 and the termination trench 61 when viewed from the upper surface of the semiconductor substrate (see FIG. 1).

In the cell area of the semiconductor device 100, a gate trench 21 penetrating the P body region 41 is formed by digging a part on the upper surface side. A deposited insulating layer 23 is formed at the bottom of the gate trench 21 by depositing an insulator. Specifically, the deposited insulating layer 23 is formed by depositing silicon oxide. Furthermore, a gate electrode 22 is formed on the deposited insulating layer 23 by depositing a conductor (for example, polysilicon). The lower end of gate electrode 22 is located below the lower surface of P body region 41. The gate electrode 22 faces the N + source region 31 and the P body region 41 of the semiconductor substrate with a gate insulating film 24 formed on the wall surface of the gate trench 21 interposed therebetween. That is, the gate electrode 22 is insulated from the N + source region 31 and the P body region 41 by the gate insulating film 24. In FIG. 1, the N + source region 31 and the gate electrode 22 are omitted.

In the semiconductor device 100 having such a structure, a channel effect is generated in the P body region 41 by applying a voltage to the gate electrode 22, thereby controlling conduction between the N + source region 31 and the N + drain region 11. is doing.

Further, a P floating buried region 51 surrounded by the N drift region 12 is formed in the semiconductor device 100. The P floating buried region 51 has a substantially circular shape centered on the bottom of the gate trench 21 as viewed from the front in FIG. In addition, there is sufficient space between adjacent P floating buried regions 51 and 51. Therefore, in the ON state, the presence of the P floating buried region 51 does not hinder the drain current. Further, the radius of the P floating buried region 51 is equal to or less than the thickness of the deposited insulating layer 23. Therefore, the upper end of the deposited insulating layer 23 is located above the upper end of the P floating buried region 51. Therefore, the gate electrode 22 deposited on the deposited insulating layer 23 and the P floating buried region 51 do not face each other.

Further, in the termination area of the semiconductor substrate, there is a P floating body region 42 that is located on the upper surface side of the semiconductor substrate and faces the P body region 41 and the N drift region 12 when viewed from the upper surface of the semiconductor substrate. Provided (see FIG. 1). That, P - is a floating body region 42, N - - and the body region 41 P are separated by a drift region 12 - Part N with located on the upper surface of the drift region 12. Therefore, the P floating body region 42 is not connected to the P body region 41. The thickness of the P floating body region 42 is equal to the thickness of the P body region 41 (see FIG. 2).

An annular termination trench 61 that penetrates the P floating body region 42 and surrounds the cell area is formed. Further, a P floating buried region 52 is provided below the termination trench 61 and surrounds the cell area in the same manner as the termination trench 61. The P floating buried region 52 has a substantially circular shape centered on the bottom of the termination trench 61 when viewed from the side in FIG. The pitch between adjacent P floating buried regions 52 and 52 is narrower than the pitch between P floating buried regions 51 and 51. This is because the P floating buried region 52 is provided in the termination area, and the presence of the P floating buried region 52 does not hinder the drain current. That is, the pitch of the P floating buried regions 52 and 52 is set to an appropriate size in order to achieve a high breakdown voltage.

Further, the end of the gate trench 21 in the longitudinal direction reaches the P floating body region 42 as shown in FIG. In addition, a gap d1 is provided between the P body region 41 and the P floating body region 42. This interval d1 is narrower than the interval d2 between the P body region 41 and the P floating buried region 51. The reason why the interval d1 is narrower than the interval d2 will be described later.

FIG. 3 is a diagram showing a cross-sectional structure of the AA portion of the semiconductor device 100 shown in FIG. In the semiconductor device 100, the source electrode 30 is provided on the upper surface side of the semiconductor substrate in FIG. 3, and the drain electrode 10 is provided on the lower surface side. An interlayer insulating film 32 is provided between the source electrode 30 and the semiconductor substrate. Further, contact is made between the source electrode 30 and the N + source region 31 through a contact region 33 penetrating the interlayer insulating film 32 (see the broken line portion in FIG. 2).

In the termination area, a plurality of termination trenches 61 are provided. The bottom of each termination trench is surrounded by a P floating buried region 52. Further, a dummy electrode 62 connected to the gate wiring is provided in the termination trench 61 adjacent to the cell area. The other termination trench is filled with an insulator such as silicon oxide. The dummy electrode 62 is provided in order to match the spread of the depletion layer in the boundary area between the cell area and the termination area with the cell area.

Note that the P floating buried region 51 shown by a broken line in FIG. 3 is for indicating the position in the thickness direction of the P floating buried region 51 in FIG. Does not exist in the cross section.

Next, characteristics of the semiconductor device 100 will be described. FIG. 4 shows the state transition of the depletion layer 80 that spreads from the PN junction between the N drift region 12 and the P body region 41 toward the drain electrode 10 when a voltage is applied across the DS. At the time when no voltage is applied between the DSs (FIG. 4A), the depletion layer 80 is only slightly formed near the boundary between the N drift region 12 and the P body region 41.

When a voltage is applied across the DS, the depletion layer 80 begins to spread in the thickness direction and the plate surface direction of the semiconductor device. First, since the interval d1 is narrower than the interval d2 (see FIG. 3), the tip of the depletion layer 80 reaches the P floating body region 42 before the P floating buried region 51 (see (b) of FIG. )). That is, the DS voltage for the depletion layer 80 extending in the plate direction to reach the P floating body region 42 is greater than the DS voltage for the depletion layer 80 extending in the thickness direction to reach the P floating buried region 51. Low. As a result, the electric field strength between P body region 41 and P floating body region 42 is relaxed.

Further, the depletion layer 80 continues to expand toward the drain electrode 10 side ((c) in FIG. 4). In addition to the PN junction portion between the N drift region 12 and the P body region 41, the electric field intensity peak is also present at the PN junction portion between the N drift region 12 and the P floating body region 42. It is formed. That is, the electric field peak can be formed at two locations, and the maximum withstand voltage can be increased by reducing the maximum peak value. Further, the depletion layer 80 cannot be spread in the plate surface direction because the spread is blocked by the terminal trench 61 having the minimum diameter. Therefore, the depletion layer 80 extending from the lower end of the P floating body region 42 extends in the thickness direction.

Thereafter, the depletion layer 80 continues to expand toward the drain electrode 10 side, thereby reaching the P floating buried region 51 ((d) in FIG. 4). As a result, a high breakdown voltage can be achieved in the cell area. That is, in the cell area, the electric field strength is relaxed after the termination area. Therefore, the withstand voltage is reliably increased in the termination area, and the withstand voltage as a semiconductor device is determined by the design of the cell area.

Thereafter, the depletion layer 80 continues to expand toward the drain electrode 10 side to reach the P floating buried region 52 ((e) of FIG. 4). This further reduces the electric field concentration in the termination area. That is, the termination area has a two-stage floating structure of the P floating body region 42 and the P floating buried region 52, and the breakdown voltage is more reliably suppressed as compared with the cell area.

Subsequently, a manufacturing process of the semiconductor device 100 will be described. First, an N type silicon layer is formed on the N + substrate to be the N + drain region 11 by epitaxial growth. Thereby, a semiconductor substrate having an epitaxial layer on the N + drain region 11 is manufactured.

Next, ion implantation of impurities (boron or the like) and thermal diffusion treatment are performed on a predetermined place of the N type silicon layer (epitaxial layer) to thereby form the P body region 41 and the P floating body region 42. Form. As a result, a semiconductor substrate having a P body region 41 and a P floating body region 42 on the upper surface side of the semiconductor substrate as shown in FIG. 5 is obtained.

Next, a trench forming mask is formed on the semiconductor substrate. After that, dry etching is performed from the surface of the mask material, and a trench portion is formed by digging down a part of the semiconductor substrate. That is, as shown in FIG. 6, a gate trench 21 and a termination trench 61 are formed, each penetrating the P body region 41 or the P floating body region 42 and having the bottom reaching the N drift region 12. Thereafter, the wall surface of each trench is smoothed by using an isotropic etching method such as CDE (Chemical Dry Etching). Note that the mask material formed of an oxide film or the like is not shown in FIG.

  Thereafter, a thermal oxidation process is performed to form a sacrificial oxide film having a thickness of about 50 nm on the wall surface of each trench. Next, impurity ions are implanted from the bottom of each trench. The reason why the ion implantation is performed after the oxide film is formed is to prevent the influence of the ion implantation from remaining on the side wall of each trench. After the ion implantation, the sacrificial oxide film in each trench is removed.

Next, insulators (silicon oxide film or the like) 23, 63 are deposited in each trench by CVD. Specifically, for example, a reactive gas is a mixed gas containing TEOS and O 2 , a film forming temperature is 600 ° C. to 680 ° C., and a TEOS-based oxide film is formed by a low pressure CVD method. Thereafter, a thermal diffusion process is performed for both the baking of the insulator and the formation of the P floating buried region 51 and the P floating buried region 52. As a result, a P floating buried region 51 and a P floating buried region 52 are formed in the N drift region 12 as shown in FIG. Before depositing the insulator, pre-embedding oxidation treatment may be performed in order to eliminate the influence of the interface state.

Next, a mask for forming a gate electrode is formed on the semiconductor substrate. Thereafter, the insulators 23 and 63 deposited in each trench are etched back. Thereby, as shown in FIG. 8, a part of the insulator 23 in the gate trench 21 is removed, and a space for forming the gate electrode 22 is secured. In addition, the insulator 63 in the termination trench 61 is similarly removed, and a space for forming the dummy electrode 62 is secured. As an etch back means, for example, an RIE (reactive ion etching) method capable of high selective etching is used. The etching gas used for etch back is appropriately selected depending on the material to be etched. For example, C 4 F 8 is used to remove the silicon oxide film. Further, other gases such as O 2 and Ar may be added to the etching gas.

  Note that a mask is formed on the termination trench 61 other than the termination trench 61 having the smallest diameter, and the insulator 63 is not etched back. That is, the inside of the termination trench 61 remains filled with the insulator 63.

  Next, an oxide film 24 is formed on the upper surface of the semiconductor substrate and the wall surface of the gate trench 21 by thermal oxidation. This becomes the gate oxide film 24. Similarly, an oxide film is also formed on the wall surface of the termination trench 61. Then, as shown in FIG. 9, the gate electrode 22 and the dummy electrode 62 are formed by depositing a conductor (polysilicon or the like) in the space secured in the previous step. As a method of forming the gate electrode 22, there is a method of depositing a conductor directly in the gate trench 21 or a method of once depositing a high resistance semiconductor and then diffusing impurities into the insulating layer.

Thereafter, a wiring for the gate electrode is formed on the upper surface of the semiconductor substrate. Then, through the formation of the N + source region 31, the deposition of the interlayer insulating film 32, the formation of contact holes, the formation of the source electrode 30 and the drain electrode 10, a semiconductor element 100 as shown in FIG. 10 is fabricated.

In the first embodiment of the semiconductor device 100 as described above in detail, in the longitudinal end side of the gate trench 21, N - across the drift region 12 P - P facing the body region 41 - floating body region 42 is provided. The distance d1 between the P body region 41 and the P floating body region 42 is made narrower than the distance d2 between the P body region 41 and the P floating buried region 51. As a result, a depletion layer extending from the PN junction between the P body region 41 and the N drift region 12 into the N drift region 12 precedes the P floating body region 42 rather than the P floating buried region 51. To reach. Therefore, in the terminal area, the electric field intensity can be more reliably reduced than in the cell area. Further, in the termination area, a P floating buried region 52 is provided below the termination trench 61. As a result, the terminal area has a two-stage floating structure. Therefore, the termination area has a higher breakdown voltage than the cell area, and even if there is some variation in the distance between the P floating buried region 51 and the P floating buried region 52, breakdown does not occur. Therefore, the breakdown voltage of the semiconductor device 100 is determined by the design of the cell area, and the generation of a portion having a breakdown voltage different from the design breakdown voltage in the cell area is suppressed.

Also, a termination trench 61 is provided in the termination area to block the spread of the depletion layer. Therefore, the depletion layer extends to the lower surface side along the termination trench 61. Further, in the semiconductor device 100, a P floating buried region 52 is provided below the termination trench 61. Then, the depletion layer reaches the P floating buried region 52, so that the electric field concentration can be further reduced. That is, it is possible to prevent the breakdown voltage from decreasing while suppressing the spread of the depletion layer in the plate surface direction. Therefore, a high breakdown voltage is achieved without increasing the termination area.

In the manufacturing process of the semiconductor device 100 of the first embodiment, the P floating body region 42 is formed together with the P body region 41. Therefore, an increase in the number of processes due to the formation of the P floating body region 42 does not occur. Further, the P floating buried region 52 is formed together with the P floating buried region 51. Further, the termination trench 61 is formed together with the gate trench 21. Therefore, the number of processes does not increase due to the configuration of the termination area. The P floating buried regions 51 and 52 are formed by ion implantation from the bottom of each trench after the epitaxial layer is formed. That is, each floating region can be formed without repeating the formation of the silicon layer by epitaxial growth. Therefore, an insulated gate semiconductor device with a high breakdown voltage can be easily manufactured.

In the semiconductor device 100, the end portion in the longitudinal direction of the gate trench 21 is located in the P floating body region 42 as viewed from the upper surface side, but it is not necessarily required to be located in the P floating body region 42. There is no. However, if the end of the gate trench 21 is too far from the P floating body region 42, the P floating buried region 51 is too far from the P floating buried region 52, and the effect of the present invention may not be obtained. Is done. In addition, there is a possibility that a new problem may occur that the electric field concentrates at the end of the gate trench 21 and the withstand voltage decreases. Therefore, the end of gate trench 21 is preferably located in P floating body region 42.

[Second form]
The semiconductor device 200 according to the second embodiment has a structure in which the end of the gate electrode 22 reaches the P floating body region 42 as shown in FIG. That is, the gate electrode 22 has a structure facing the N drift region 12 with the gate insulating film 24 interposed therebetween. In this regard, the end portion of the gate electrode 22 the N - only a little protruding the drift region 12 side, the gate electrode 22 and the N - different from the semiconductor device 100 of the first embodiment and the drift region 12 does not face almost .

Thus, when the gate electrode 22 is provided so as to straddle between the P body region 41 and the P floating body region 42 when viewed from the upper surface side of the semiconductor substrate, the gate electrode 22 is provided with the gate insulating film 24. Opposite to the N drift region 12. In the portion of the N drift region 12 facing the gate electrode 22, the depletion layer is likely to spread due to the field plate effect. Therefore, it is not always necessary to make the interval d1 narrower than the interval d2. That is, the depletion layer extending from the P body region 41 in the plate surface direction reaches the P floating body region 42 until the depletion layer extending in the thickness direction from the P body region 41 reaches the P floating buried region 51. If the distance d1 is long, the distance d1 may be wider than the distance d2. Therefore, the distance d1 may be designed in consideration of the voltage between DSs for the depletion layer extending toward the plate surface direction to reach the P floating body region. Therefore, the semiconductor device 200 of the second embodiment has a high degree of design freedom.

This is the same even if the gate wiring 29 is disposed on the surface of the semiconductor substrate so as to straddle between the P body region 41 and the P floating body region 42 as shown in FIG. That is, the gate wiring 29 and the N drift region 12 are opposed to each other with the insulating film provided on the surface of the semiconductor substrate, not the insulating film on the wall surface of the gate trench 21. Even in such a case, the depletion layer easily spreads at a portion facing the gate wiring 29 due to the field plate effect. Therefore, even in the semiconductor device 201 shown in FIG. 12, P - to reach the floating buried region 51, P - - depletion layer extending in the thickness direction from the body region 41 is P in the plate surface direction from the body region 41 The distance d1 may be such that the expanding depletion layer reaches the P floating body region 42.

[Third embodiment]
As shown in FIG. 13, the semiconductor device 300 of the third embodiment includes a P floating buried region 53 surrounding the bottom of the gate trench 21 and a P floating body region 43 surrounding the cell area at the end of the gate trench 21. It has a connected structure. This is different from the semiconductor device 100 of the first embodiment in which the P floating regions are separate regions and are not connected. In FIG. 13, the source electrode, the drain electrode, and the interlayer insulating film are omitted in order to simplify the description.

Specifically, a P floating buried region 53 surrounded by the N drift region 12 is formed below the P body region 41 in the cell area of the semiconductor device 300. The P floating buried region 53 has a substantially circular shape centered on the bottom of the gate trench 21 when viewed from the front in FIG. 13. The P floating buried region 53 is provided so as to surround the bottom and end portions of the gate trench 21. Further, there is a sufficient space between the adjacent P floating buried regions 53 and 53 as viewed from the front of FIG. Therefore, the presence of the P floating buried region 53 does not hinder the drain current.

Further, a P floating body region 43 surrounding the cell area is provided on the upper surface side of the termination area of the semiconductor device 300. The P floating body region 43 is opposed to the P body region 41 with the N drift region 12 interposed therebetween as viewed from the upper surface side of the semiconductor substrate. The P body region 41 is covered with the N drift region 12 except for the upper surface. Therefore, P floating body region 43 and P body region 41 are not connected.

Further, the end of the gate trench 21 in the longitudinal direction is located in the P floating body region 43 when viewed from the upper surface side of the semiconductor substrate. Therefore, since the P floating buried region 53 is provided along the bottom and end of the gate trench 21, the P floating body region 43 and the P floating buried region 53 are connected. In the portion of the semiconductor device 300 located in the cell area, it is necessary to provide a sufficient space between the P floating buried regions 53 and 53 in order to secure a current path. This is not necessary because it is not a route. That is, it is not necessary to isolate the P floating body region 43.

FIG. 14 is a diagram showing a cross-sectional structure of the BB portion of the semiconductor device 300 shown in FIG. In the semiconductor device 300, the source electrode 30 is provided on the upper surface side of the semiconductor substrate, and the drain electrode 10 is provided on the lower surface side. An interlayer insulating film 32 is provided between the source electrode 30 and the semiconductor substrate. Note that the P floating buried region 53 shown by the broken line in FIG. 14 indicates the position in the thickness direction of the P floating buried region 53, and does not exist in the cross section of the actual BB portion. .

According to the semiconductor device 300 of this embodiment, since the P floating buried region 53 is present at the bottom of the gate trench 21, a mechanism for realizing a high breakdown voltage by dividing the peak of the electric field strength in the vertical direction into two locations is provided. It can be applied continuously in the direction (near the Si surface), and the portion where the breakdown voltage is reduced can be eliminated at the terminal portion of the gate trench 21. In order to obtain this effect to maximum, P - the distance d2 between the floating buried region 53, P - - a body region 41 P and the body region 41 P - the distance d1 between the floating body region 43, It should be as equal as possible.

Next, a manufacturing process of the semiconductor device 300 will be described. First, an N type silicon layer is formed on the N + substrate to be the N + drain region 11 by epitaxial growth. Thereafter, impurity ion implantation and thermal diffusion treatment are performed on predetermined locations of the N type silicon layer, thereby forming P body region 41 and P floating body region 43. As a result, a semiconductor substrate having a P body region 41 and a P floating body region 43 on the upper surface side of the semiconductor substrate as shown in FIG. 15 is obtained.

Next, a trench forming mask is formed on the semiconductor substrate. After that, as shown in FIG. 16, a gate trench 21 is formed which penetrates the P body region 41 from the surface of the mask material and reaches its bottom to the N drift region 12. Further, gate trench 21 is formed so that the end in the longitudinal direction is located in P floating body region 43. Note that the mask material formed of an oxide film or the like is not shown in FIG.

  Thereafter, a sacrificial oxide film having a thickness of about 50 nm is formed on the wall surface of the gate trench 21 by performing a thermal oxidation process. Next, impurity ions are implanted from the bottom and end portions of the gate trench 21. Specifically, as shown in FIG. 17, ion implantation is performed at an angle so that only the bottom and end portions of the gate trench 21 are implanted. After the ion implantation, the sacrificial oxide film in the gate trench 21 is removed.

Next, an insulator (silicon oxide film or the like) 23 is deposited in the gate trench 21 by the CVD method. Thereafter, a thermal diffusion process is performed for both the baking of the insulator and the formation of the P floating buried region 53. As a result, a P floating region 53 surrounding the bottom and end portions of the gate trench 21 is formed as shown in FIG.

  Next, a mask for forming a gate electrode is formed on the semiconductor substrate. Thereafter, the insulator 23 deposited in the gate trench 21 is etched back. Thereby, as shown in FIG. 19, a part of the insulator in the gate trench 21 is removed, and a space for forming the gate electrode 22 is secured.

Next, an oxide film 24 is formed on the upper surface of the semiconductor substrate and the wall surface of the gate trench 21 by thermal oxidation. This becomes the gate oxide film 24. Then, as shown in FIG. 20, a gate electrode 22 is formed by depositing a conductor (polysilicon or the like) in the space secured in the previous step. Thereafter, a wiring for the gate electrode is formed on the upper surface of the semiconductor substrate. Then, through the formation of the N + source region 31, the deposition of the interlayer insulating film 32, the formation of contact holes, the formation of the source electrode 30 and the drain electrode 10, a semiconductor element 300 as shown in FIG. 21 is fabricated.

As described above in detail, in the semiconductor device 300 of the present embodiment, the end portion in the longitudinal direction of the gate trench 21 is located in the termination area, and the interval between the P floating buried regions 53 and 53 is always constant. That is, there is no variation in the interval between adjacent P floating buried regions 53. Further, the P floating buried region 53 and the P floating body region 43 in the termination area are connected. Therefore, there is no problem of variation in the spacing between adjacent P floating buried regions. Therefore, a decrease in breakdown voltage is suppressed.

Further, depending on the performance of each semiconductor device, the depletion layer from the P body region 41 may reach the P floating region different from the design first. Therefore, if the P floating buried region 53 and the P floating body region 43 are not connected, there is a possibility of breakdown at a location different from the design. However, if both P floating regions are connected, that is, set to the same potential, the portion where the depletion layer breaks down is constant regardless of which P floating region reaches first. That is, by connecting the P floating buried region 53 and the P floating body region 43, it is possible to suppress the variation in the breakdown location.

  Furthermore, in the semiconductor device 300 of this embodiment, it is not necessary to form a termination trench in the longitudinal direction of the trench 21 in the cell area. Therefore, there is no problem of a break or a joint between the trench in the cell area and the trench in the termination area. Moreover, in the annular termination trench surrounding the termination area, an arc-shaped trench is unavoidably provided. In this arc-shaped portion, the width of the trench varies, so that the insulating property is poor. However, since it is not necessary to provide the arc-shaped terminal trench in the semiconductor device 300 of this embodiment, such a problem does not occur and the trench can be easily embedded. It is possible to further increase the breakdown voltage by combining the semiconductor device 300 of this embodiment with a structure in which the termination trench 61 as shown in the first embodiment is added or a conventional guard ring structure.

  Note that this embodiment is merely an example, and does not limit the present invention. Therefore, the present invention can naturally be improved and modified in various ways without departing from the gist thereof. For example, for each semiconductor region, P-type and N-type may be interchanged. Further, the gate insulating film 24 is not limited to an oxide film, and may be another type of insulating film such as a nitride film or a composite film. Also, the semiconductor is not limited to silicon, but may be other types of semiconductors (SiC, GaN, GaAs, etc.). The insulated gate semiconductor device of the embodiment can also be applied to a conductivity modulation type power MOS using a P type substrate.

In the semiconductor device according to the embodiment (for example, FIG. 1), the N drift region 12 is provided beyond the termination trench 61 to the termination area on the main surface side, but the present invention is not limited to this. For example, as shown in FIG. 22, the N drift region 12 may be located on the main surface side in the region surrounded by the termination trench 61. The P floating body region 42 is separated from the P body region 41 by the termination trench 61.

1 is a perspective plan view showing a structure of an insulated gate semiconductor device according to a first embodiment. It is a cross-sectional perspective view which shows the structure of the insulated gate semiconductor device which concerns on a 1st form. It is a figure which shows the cross-section of the AA part of the insulated gate semiconductor device shown in FIG. It is a figure which shows the state transition of the depletion layer extended in the drift region of the insulated gate semiconductor device shown in FIG. It is a figure which shows the starting board | substrate of the manufacturing process of a 1st form. It is a figure which shows the state of the semiconductor substrate after the trench formation which concerns on the manufacturing process of a 1st form. It is a figure which shows the state of the semiconductor substrate after oxide film CVD which concerns on the manufacturing process of a 1st form. It is a figure which shows the state of the semiconductor substrate after the etch back which concerns on the manufacturing process of a 1st form. It is a figure which shows the state of the semiconductor substrate after conductor deposition which concerns on the manufacturing process of a 1st form. It is a figure which shows the state of the semiconductor substrate after the electrode formation which concerns on the manufacturing process of a 1st form. It is a perspective sectional view showing the structure of the insulated gate semiconductor device concerning the 2nd form. It is sectional drawing which shows the application example of the insulated gate semiconductor device which concerns on a 2nd form. It is a perspective sectional view showing the structure of the insulated gate semiconductor device concerning the 3rd form. It is a figure which shows the cross-section of the BB part of the insulated gate semiconductor device shown in FIG. It is a figure which shows the starting board | substrate of the manufacturing process of a 3rd form. It is a figure which shows the state of the semiconductor substrate after trench formation which concerns on the manufacturing process of the 3rd form. It is a figure which shows the image at the time of the ion implantation which concerns on the manufacturing process of a 3rd form. It is a figure which shows the state of the semiconductor substrate after oxide film CVD which concerns on the manufacturing process of the 3rd form. It is a figure which shows the state of the semiconductor substrate after the etch back which concerns on the manufacturing process of the 3rd form. It is a figure which shows the state of the semiconductor substrate after the conductor deposition which concerns on the manufacturing process of the 3rd form. It is a figure which shows the state of the semiconductor substrate after the electrode formation which concerns on the manufacturing process of the 3rd form. It is a plane perspective view which shows the modification of the insulated gate semiconductor device which concerns on embodiment. It is sectional drawing which shows the structure of the conventional insulated gate semiconductor device. It is a plane perspective view which shows the structure (with a cut | interruption) of the conventional insulated gate semiconductor device. It is a plane perspective view which shows the structure (with a joint) of the conventional insulated gate semiconductor device.

Explanation of symbols

10 drain electrode 11 N + drain region 12 N drift region (drift region)
21 Gate trench (first trench part group, trench part group)
22 Gate electrode (gate electrode, conductor)
23 Deposited insulating layer 24 Gate insulating film 29 Gate wiring (conductor portion)
30 Source electrode 31 N + source region 41 P - body region (body region)
42 P - floating body region (second floating region)
43 P - floating body region (second floating region)
51 P - floating embedded region (first floating region)
52 P - floating embedded region (third floating region)
53 P - floating embedded region (first floating region)
61 Terminal trench (second trench part)
62 Dummy electrode 63 Deposited insulating layer 100 Insulated gate type semiconductor device

Claims (11)

  1. In an insulated gate semiconductor device in which a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate and a body region that is a second conductivity type semiconductor located on an upper surface side of the drift region are provided. ,
    A first floating region that is surrounded by the drift region and at least partially located below the body region and is a second conductivity type semiconductor;
    A first trench portion group penetrating the body region in the thickness direction of the semiconductor substrate and having a bottom portion located in the first floating region and incorporating a gate electrode;
    A second conductivity type semiconductor which is located on the upper surface side of the drift region, located on the periphery of the body region as seen from the main surface side of the semiconductor substrate, and at least partly facing the body region with the drift region interposed therebetween; A second floating region,
    A third floating region surrounded by the drift region and positioned below the second floating region and being a second conductivity type semiconductor;
    A second trench penetrating the body region in the thickness direction of the semiconductor substrate, a bottom portion thereof being positioned in the third floating region, and a part of a wall surface of which is opposed to an end portion of each trench of the first trench portion group Are provided, and
    An interval between the body region and the second floating region at a portion where the body region and the second floating region face each other is narrower than an interval between the body region and the first floating region. An insulated gate semiconductor device.
  2. In an insulated gate semiconductor device in which a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate and a body region that is a second conductivity type semiconductor located on an upper surface side of the drift region are provided. ,
    A first floating region that is surrounded by the drift region and at least partially located below the body region and is a second conductivity type semiconductor;
    A first trench portion group penetrating the body region in the thickness direction of the semiconductor substrate and having a bottom portion located in the first floating region and incorporating a gate electrode;
    A second conductivity type semiconductor which is located on the upper surface side of the drift region, located on the periphery of the body region as seen from the main surface side of the semiconductor substrate, and at least partly facing the body region with the drift region interposed therebetween; A second floating region,
    A third floating region surrounded by the drift region and positioned below the second floating region and being a second conductivity type semiconductor;
    A second trench penetrating the body region in the thickness direction of the semiconductor substrate, a bottom portion thereof being positioned in the third floating region, and a part of a wall surface of which is opposed to an end portion of each trench of the first trench portion group Part,
    A conductor portion that is located in the trench portion of the first trench portion group and that faces at least a part of a drift region that separates the body region and the second floating region across an insulating film is provided. An insulated gate semiconductor device.
  3. In an insulated gate semiconductor device in which a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate and a body region that is a second conductivity type semiconductor located on an upper surface side of the drift region are provided. ,
    A first floating region that is surrounded by the drift region and at least partially located below the body region and is a second conductivity type semiconductor;
    A first trench portion group penetrating the body region in the thickness direction of the semiconductor substrate and having a bottom portion located in the first floating region and incorporating a gate electrode;
    A second conductivity type semiconductor which is located on the upper surface side of the drift region, located on the periphery of the body region as seen from the main surface side of the semiconductor substrate, and at least partly facing the body region with the drift region interposed therebetween; A second floating region,
    A third floating region surrounded by the drift region and positioned below the second floating region and being a second conductivity type semiconductor;
    A second trench penetrating the body region in the thickness direction of the semiconductor substrate, a bottom portion thereof being positioned in the third floating region, and a part of a wall surface of which is opposed to an end portion of each trench of the first trench portion group Part,
    Insulation characterized in that a conductor portion is provided on the main surface of the semiconductor substrate and opposed to at least a part of a drift region separating the body region and the second floating region with an insulating film interposed therebetween. Gate type semiconductor device.
  4. In the insulated gate semiconductor device according to claim 2 or 3,
    A drain-source voltage for a depletion layer extending from the junction between the body region and the drift region toward the second floating region to reach the second floating region is a junction between the body region and the drift region. A predetermined depletion layer extending from the location toward the first floating region is lower than a drain-source voltage for reaching the first floating region by a predetermined amount between the body region and the second floating region. An insulated gate semiconductor device, characterized in that an interval is provided.
  5. In the insulated gate semiconductor device according to any one of claims 1 to 4,
    Each of the trench portions of the first trench portion group penetrates the drift region when viewed from the main surface side of the semiconductor substrate, and an end portion thereof is located in the second floating region. Semiconductor device.
  6. In an insulated gate semiconductor device in which a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate and a body region that is a second conductivity type semiconductor located on an upper surface side of the drift region are provided. ,
    A first floating region that is surrounded by the drift region and at least partially located below the body region and is a second conductivity type semiconductor;
    A second conductivity type semiconductor which is located on the upper surface side of the drift region and located in the termination area, and at least a part of the semiconductor substrate faces the body region across the drift region when viewed from the main surface side of the semiconductor substrate. A floating area,
    A trench portion group penetrating the body region in the thickness direction of the semiconductor substrate, a bottom portion thereof being located in the first floating region, a longitudinal end portion thereof being located in the second floating region, and incorporating a gate electrode And an insulated gate semiconductor device.
  7. In the insulated gate semiconductor device according to claim 6,
    An insulated gate semiconductor device, wherein the first floating region and the second floating region are connected.
  8. An insulated gate semiconductor device comprising: a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate; and a body region that is a second conductivity type semiconductor located on an upper surface side of the drift region. In the manufacturing method,
    Forming a drift region which is a first conductivity type semiconductor on a substrate;
    By implanting impurities into the drift region formed in the drift region forming step, the body region that is the second conductivity type semiconductor and the second region at least partially facing the body region with the drift region interposed therebetween. A first impurity implantation step for forming a first diffusion region which is a conductive semiconductor;
    A first trench portion group penetrating the body region formed in the first impurity implantation step in a thickness direction of the semiconductor substrate; and a second trench portion penetrating the first diffusion region formed in the first impurity implantation step. A trench part forming step for forming the trench part;
    A second diffusion region which is a second conductivity type semiconductor is formed by injecting impurities from each trench portion of the first trench portion group and each bottom portion of the second trench portion formed in the trench portion forming step. A method for manufacturing an insulated gate semiconductor device, comprising: an impurity implantation step.
  9. In the manufacturing method of the insulated gate semiconductor device according to claim 8,
    A method of manufacturing an insulated gate semiconductor device, comprising: a conductor deposition step of depositing a conductor in each trench portion of the first trench portion group formed in the trench portion formation step after the second impurity implantation step.
  10. In the manufacturing method of the insulated gate semiconductor device according to claim 8,
    A conductor deposition step of depositing a conductor on the main surface of the semiconductor substrate at a position facing at least a part of the drift region separating the body region and the first diffusion region after the second impurity implantation step; A method of manufacturing an insulated gate semiconductor device, comprising:
  11. An insulated gate semiconductor device comprising: a drift region that is a first conductivity type semiconductor located on a main surface side of a semiconductor substrate; and a body region that is a second conductivity type semiconductor located on an upper surface side of the drift region. In the manufacturing method,
    Forming a drift region which is a first conductivity type semiconductor on a substrate;
    By implanting impurities into the drift region formed in the drift region forming step, the body region that is the second conductivity type semiconductor and the second region at least partially facing the body region with the drift region interposed therebetween. A first impurity implantation step for forming a first diffusion region which is a conductive semiconductor;
    A trench portion forming step of forming a trench portion group penetrating the body region formed in the first impurity implantation step in the thickness direction of the semiconductor substrate and having an end portion in the longitudinal direction located in the first diffusion region;
    A second impurity implantation step of forming a second diffusion region, which is a second conductivity type semiconductor, by implanting impurities from the bottom and the longitudinal end of each trench formed in the trench formation process A method of manufacturing an insulated gate semiconductor device, comprising:
JP2004204880A 2004-07-12 2004-07-12 Insulated gate semiconductor device and manufacturing method thereof Expired - Fee Related JP4404709B2 (en)

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