JP4561747B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device such as a unidirectional trench lateral power MOSFET (unidirectional TLPM) and a bidirectional trench lateral power MOSFET (bidirectional TLPM).

A power MOSFET built in a power IC such as a power supply IC or a battery protection IC requires a low on-resistance for chip size and power saving.
FIG. 8 is a plan view of a main part of a conventional bidirectional trench lateral power MOSFET, FIG. 9 is a detailed view of a C part in FIG. 8, (a) is a plan view of the main part, and (b) of FIG. FIG. 10 is a main part sectional view cut along line X2-X2 in FIG. 10A, and FIG. 10 is a main part sectional view cut along line X1-X1 in FIG.

  In FIG. 8, the first source region 67, the second source region 68 and the p base pickup region 69 shown in FIG. 9 are omitted. In FIG. 9A, the first source electrode wiring 74, the second source electrode wiring 75, the first polysilicon gate wiring 79, and the second polysilicon gate wiring 80 shown in FIG. 8 are omitted. In FIG. 2B, an interlayer insulating film that fills the trench 63 and insulates the plug 73 from the first and second gate electrodes 71 and 72 is not shown. Also in FIG. 10, the interlayer insulating film is not shown.

  The configuration of this conventional bidirectional trench lateral power MOSFET will be described. This conventional bidirectional trench lateral power MOSFET includes an n-well region 62 formed in the surface layer of the p-substrate 61, a closed-loop meandering trench 63 formed from the surface of the n-well region 62, and A first p base region 64 formed in the surface layer of the n well region 62 outside the trench 63, and a second p formed in the surface layer of the n well region 62 simultaneously with the first p base region 64 and surrounded by the first trench 63. And a base region 65.

  The first n source region 67 selectively formed on the surface layer of the first p base region 64 and in contact with the sidewall of the first trench 63 and the first trench 63 selectively formed on the surface layer of the second p base region 65. A second n source region 68 in contact with the sidewall, a p base pickup region 69 in contact with the first n source region 67 and formed in a surface layer of the first p base region 64, and a surface of the second p base region 65 in contact with the second n source region 68 P base pickup region 69 formed in the layer.

Also, an n drain region 66 formed at the bottom of the first trench 63, a first gate electrode 71 formed on the side of the first p base region 64 on the side wall of the first trench 63 via the gate insulating film 70, and a trench And a second gate electrode 72 formed on the second p base region 65 side through the gate insulating film 70.
Further, a contact hole 76 opened in an interlayer insulating film (not shown), a first source electrode wiring 74 in contact with the first n source region 67 and the p base pickup region 69 via the plug 73, a second n source region 68 and the p base pickup. The second source electrode wiring 75 is in contact with the region 69 through the plug 73.

Further, the first polysilicon gate wiring 79 in contact with the first gate electrode 71, the second polysilicon gate wiring 80 in contact with the second gate electrode 12, and the first gate in contact with the first polysilicon gate wiring 79 through the contact hole 81. An electrode wiring 77 and a second gate electrode wiring 78 in contact with the second polysilicon gate wiring 80 through a contact hole 81 are provided.
A first source terminal S1 connected to the first source electrode wiring 74; a second source terminal S2 connected to the second source electrode wiring 75; a first gate terminal G1 connected to the first gate metal wiring 77; A second gate terminal G2 connected to the second gate metal wiring 78;

FIG. 11 is an equivalent circuit diagram of the bidirectional trench lateral power MOSFET shown in FIG. The first MOSFET 91 and the second MOSFET 92 are connected by a drain region 66, and the drain region 66 is not connected to other terminals. The first and second MOSFETs 91 and 92 and the first and second parasitic pn diodes 93 and 94 are connected in antiparallel.
FIG. 10 shows a peripheral region that is not a device region. The first p base region 64 on the left side of the trench 63 shown in FIG. 10 is connected to the first p base region 64 of the first MOSFET 91. When a high voltage is applied to the second MOSFET 92 in a state where the p substrate 61 is set to the ground potential, the potentials of the first and second gate electrodes 71 and 72 are lowered and both the first MOSFET 91 and the second MOSFET 92 of FIG. As shown in FIG. 10, the pn junction 95 of the n well region 62 and the first p base region 64 of the first MOSFET 91 and the pn junction 96 of the n well region 62 and the p substrate 61 are reverse-biased. Depletion layers spread in the first p base region 64 and the p substrate 61, respectively. At this time, since it is a diffusion termination (mask edge) in the vicinity of the surface layer, the impurity concentration is lower than in the depth direction, and the depletion layer is likely to spread.

  In Patent Document 1, an n extended drain region (n drain region) is formed on the bottom surface of a trench, a p offset region (p base region) is formed in a divided semiconductor region, and first and second n source regions are formed on the surface thereof. The planar distance between the first and second n source regions is shortened to increase the density of the cells, and the breakdown voltage is maintained along the trenches to increase the breakdown voltage. The voltage of the gate electrode is changed to the first and second n source electrodes. It is disclosed that a channel is formed on the side wall of the trench by setting the voltage higher than 11 and 12, and a bidirectional LMOSFET having a high breakdown voltage and a low on-voltage in which a current flows in both directions is disclosed.

In Patent Document 2, in a semiconductor device in which a gate electrode is embedded in a groove, the end part of each groove is connected by a new groove, thereby eliminating a peculiar structure (sharpness) of the terminal part and generating at the terminal part of the groove It is disclosed to prevent the drain-source breakdown voltage from decreasing.
In Patent Document 3, a plurality of trenches are formed so as to surround the periphery of the main junction of the semiconductor device, p ⁺ layers or Schottky contacts are provided between the bottoms of the trenches, and trench bottom p ⁺ layers 2 are provided. It is disclosed that the n ^- layer 4 between the trenches is provided so that a depletion layer spreads between the p ⁺ layer 3 between the trenches and the termination portion is configured to reduce the occupied area and increase the breakdown voltage.

In Patent Document 4, the breakdown voltage structure formed in the outer peripheral portion of the semiconductor chip is formed of a guard groove, and the plane orientation of the single crystal exposed inside the groove is all (100), thereby causing uniform epitaxial growth and defects. It is disclosed that it is possible to fill in a guard area without a gap.
JP 2004-274039 A FIG. Japanese Patent Laid-Open No. 11-97689 FIG. Japanese Patent Laid-Open No. 11-87698 FIG. Japanese Patent Laid-Open No. 2004-128293 FIG.

In the conventional bidirectional trench lateral power MOSFET shown in FIG. 8, in the 20V class device, the interval L1 between the trench 63 and the first p base region 64 end is about 5 μm, and the interval between the first p base region 64 end and the n well region 62 end. L2 needs to be opened by about 10 μm.
That is, as shown in FIG. 10, in the conventional structure, the distance L1 from the trench 63 to the end of the first p base region 64 is 5 μm or more on the outer periphery of the trench 63 forming the device in order to ensure the breakdown voltage. Thus, it is necessary to form the n-well region 62 so that the distance L2 from the end of the first p-base region 64 to the end of the n-well region 62 is 10 μm or more.

That is, when cut in the X1-X1 line direction, the withstand voltage can be reliably ensured by setting the distance L3 from the trench 63 located on the outermost periphery to the n-well region 62 to be 15 μm or more.
For example, in the conventional structure shown in FIGS. 8 to 10, a high potential is applied to the second n source region 68 (second source electrode wiring 75 and S2), and the first n source region 67 (first source electrode wiring 74 and S1). When the p substrate 61 is set to the ground potential, the pn junctions 95 and 96 are reverse-biased, and the depletion layer extends in the n-well region 62 and the first p base region 64 with the pn junction 95 interposed therebetween. And spreads in the n-well region 62 and the p-substrate 61. In order to prevent the depletion layer extending from the pn junction 96 (or pn junction 95) from reaching the pn junction 95 (or pn junction 96) and punching through, the distance from the first p base region 64 end to the n well region 62 end L2 is 10 μm or more. Further, in order to prevent the depletion layer from spreading over the entire first p base region 64 and the electric field strength at the pn junction 95 from becoming too high, the interval L1 from the trench 63 to the end of the first p base region 64 is set to 5 μm or more. Therefore, the total distance L1 + L2 = L3 needs to be 15 μm or more.

  That is, in order to prevent punch-through, the first p base region 64 and the n-well region 62 of about 15 μm have to be formed on the outer periphery of the device (active region). The unidirectional TLPM and the bidirectional TLPM are low on-resistance devices. However, if a wide region for maintaining a breakdown voltage is formed in an inactive region (a region where a main current does not flow: a breakdown voltage structure portion), the chip size increases. On the other hand, when the chip sizes are the same, the active region (region where the main current flows) is narrowed and the on-resistance is increased.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that solves the above-described problems and narrows the inactive region, thereby widening the active region and reducing the on-resistance.

In order to achieve the above object, a well region of a first conductivity type selectively formed on a surface layer of a semiconductor substrate of a second conductivity type and a planar shape formed on the surface layer of the well region are in a closed loop shape. A first base region of a second conductivity type having a shallower depth than the first trench formed in a surface layer of the well region surrounding the first trench and in contact with the first trench, A planar shape formed surrounding the first trench and the first base region and in contact with the first base region is formed in a second loop having a closed loop shape and a surface layer of the well region surrounded by the first trench. said second base region depth of the shallow second conductive type than the first trench, said second base region second source region of the first conductivity type formed in contact with the first trench in the surface layer of When the first base A first insulating film formed in the first source region of the first conductivity type formed in contact with the first trench in the surface layer of the region, on the inner surface of the first trench, formed on the inner surface of the second trench A first gate electrode formed on the first insulating film on a side wall of the first trench on the first source region side, and a second source region side of the first trench on the second source region side. A second gate electrode formed on the first insulating film on the side wall; and a second gate electrode formed on the second insulating film on the first base region side wall of the second trench, and electrically connected to the first gate electrode. A third gate electrode connected to the first gate electrode; a polysilicon film formed on the second insulating film on a side wall of the second trench facing the third gate electrode; and filling the first trench and the second trench. The first gate electrode and the second gate An interlayer insulating film for insulating the polysilicon film and electrode and the third gate electrode, a first source electrode electrically connected to the second base region and the second source region, said first base region And a second source electrode electrically connected to the first source region, and a current is bidirectionally passed along the first trench between the first source electrode and the second source electrode. It is configured with a bidirectional MOSFET that flows .

Further, a first conductivity type well region, a first trench planar shape formed on the surface layer is a closed loop of said well region is selectively formed in the surface layer of the second conductivity type semiconductor substrate, wherein A base region of a second conductivity type having a shallower depth than the first trench formed in a surface layer of the well region surrounding the first trench and in contact with the first trench; and surrounding the first trench and the base region A second trench having a closed loop shape formed in contact with the base region ; a first conductivity type first semiconductor region formed in a surface layer of the well region surrounded by the first trench; a first conductivity type second semiconductor region, said base region a first conductivity type source region formed in contact with the first trench in the surface layer formed on the surface layer of the first semiconductor region, said first One trench A first insulating film formed on the surface, a second insulating film formed on the inner surface of the second trench, and a first insulating film formed on the side wall of the first trench on the source region side. A gate electrode; a conductive film formed on the first insulating film on a side wall of the first trench on the second semiconductor region side; and a second conductive film formed on the side wall of the second trench on the first base region side. A second gate electrode formed on the insulating film and electrically connected to the first gate electrode; and a polysilicon formed on the second insulating film on a side wall of the second trench facing the second gate electrode. A silicon film; an interlayer insulating film that fills the first trench and the second trench and insulates the first gate electrode, the conductive film, and the second gate electrode from the polysilicon film; the second semiconductor region; electrically to a conductive film Drain connected electrode, and a source electrode electrically connected to said base region and said source region, a current flows along the first trench between the source electrode and the drain electrode It is configured by a MOSFET .

A first conductivity type well region selectively formed on the surface layer of the second conductivity type semiconductor substrate;
A first trench having a closed-loop planar shape formed in the surface layer of the well region;
A first base region of a second conductivity type having a depth smaller than that of the first trench formed in a surface layer of the well region surrounding the first trench and in contact with the first trench;
A second trench having a closed loop shape and a planar shape formed surrounding the first trench and the first base region and in contact with the first base region;
A second base region of a second conductivity type having a shallower depth than the first trench formed in a surface layer of the well region surrounded by the first trench;
A second source region of a first conductivity type formed on a surface layer of the second base region in contact with the first trench;
A first source region of a first conductivity type formed on a surface layer of the first base region in contact with the first trench;
A first insulating film formed on the inner surface of the first trench; a second insulating film formed on the inner surface of the second trench;
A first gate electrode formed on the first insulating film on a side wall of the first trench on the first source region side;
A second gate electrode formed on the first insulating film on a side wall of the first trench on the second source region side;
A third gate electrode formed on the second insulating film on a side wall of the second trench on the first base region side;
A polysilicon film formed on the second insulating film on a side wall of the second trench facing the third gate electrode;
An interlayer insulating film that fills the first trench and the second trench and insulates the first gate electrode, the second gate electrode, the third gate electrode, and the polysilicon film;
A first source electrode electrically connected to the second base region and the second source region;
A second source electrode electrically connected to the first base region and the first source region;
A first gate wiring in contact with the first gate electrode disposed on a surface of the semiconductor substrate in a region sandwiched between the first trench and the second trench;
A second gate wiring that is in contact with the second gate electrode disposed on the surface of the semiconductor substrate in a region surrounded by the first trench, and a plurality of the first trenches are formed adjacent to each other. And an arcuate part connecting the elongated parts adjacent to each other in the plurality of elongated parts,
In the arc-shaped portion, the first gate wiring and the first gate electrode are connected, and in the arc-shaped portion, the second gate wiring and the second gate electrode are connected,
The first source electrode and the second source electrode are configured by a bidirectional MOSFET that allows current to flow bidirectionally along the first trench.

In addition, a sidewall of the first trench located outside the arc of the arc-shaped portion has a first protruding portion protruding into the first base region, and the first protruding portion includes the first gate electrode and the first gate electrode. 1 gate wiring is connected, and the side wall of the first trench located outside the arc of the arc-shaped portion has a second protrusion protruding into the second base region, and the second protrusion includes the second protrusion It is assumed that the gate electrode and the second gate wiring are connected .
In addition, the interval between the plurality of elongated portions in the meandering portion and the interval between the elongated portion adjacent to the second trench in the elongated portion and the second trench are the same.

According to the present invention, by forming trenches at the pn junction surface end portions of the n well region and the p base region, the depletion layer that has spread from the pn junction to the n well region in the outer peripheral portion in the conventional structure is prevented from spreading. By doing so, the inactive region (region of the breakdown voltage structure portion) in the outer peripheral portion of the trench can be narrowed, and the chip size can be reduced.
When the chip size is the same, the active region can be expanded, so that the on-resistance can be reduced.

  Embodiments will be described in the following examples.

FIG. 1 is a plan view of an essential part of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a detailed view of a part A in FIG. 1. FIG. FIG. 3 is a cross-sectional view of main parts cut along line X2-X2 in FIG. 3A, and FIG. 3 is a cross-sectional view of main parts cut along line X1-X1 in FIG. This semiconductor device is an example of a bidirectional trench lateral power MOSFET.
In FIG. 1, the first source region 7, the second source region 8, and the p base pickup region 9 are omitted. In FIG. 2A, the first source electrode wiring 14, the second source electrode wiring 15, the first polysilicon gate wiring 19, and the second polysilicon gate wiring 20 are omitted. In FIG. The interlayer insulating film that fills the plug 13 and insulates the plug 13 from the first and second gate electrodes 11 and 12 is not shown. Also in FIG. 3, the interlayer insulating film is not shown.

  The configuration of this bidirectional trench lateral power MOSFET will be described. This bidirectional trench lateral power MOSFET includes an n-well region 2 formed in the surface layer of the p-substrate 1, a closed-loop meandering first trench 3 formed inside from the surface of the n-well region 2, A closed-loop second trench 25 that is formed simultaneously with the first trench 3 and surrounds the first trench 3 (the interval between the second trench 24 and the first trench 3 on the X1-X1 line is the same as the interval between the first trenches 3). ).

  Also, a first p base region 4 surrounded by the first trench 3 and the second trench 25 and formed in the surface layer of the n well region 2, and formed in the surface layer of the n well region 2 simultaneously with the first p base region 4, The second p base region 5 surrounded by the first trench 3, the first n source region 7 formed in the surface layer of the first p base region 4 and in contact with the side wall of the first trench 3, and the surface layer of the second p base region 5 The second n source region 8 in contact with the side wall of the first trench 3, the p base pickup region 9 in contact with the first n source region 7 and formed in the surface layer of the first p base region 4, and the second n source region 8 in contact with the second n source region 8. The second base pickup region 9 is formed in the surface layer of the 2p base region 5.

  Further, the n drain region 6 formed at the bottom of the first trench 3, the n region 26 formed simultaneously with the n drain region 6 at the bottom of the second trench 25, and the gate insulating film 10 on the side wall of the first trench 3. The first gate electrode 11 of polysilicon formed on the first p base region 4 side through the gate electrode and the polysilicon formed on the second p base region 5 side through the gate insulating film 10 on the side wall of the first trench 3. And a second gate electrode 12.

Further, a polysilicon film 28 (formed simultaneously with the gate electrodes 11 and 12) formed on the first p base region 4 side through an insulating film 27 formed simultaneously with the gate insulating film 10 on the side wall of the second trench 25. And a polysilicon film 29 (formed simultaneously with the gate electrodes 11 and 12) formed on the n-well region 2 side.
Further, a contact hole 16 opened in an interlayer insulating film (not shown), a first source electrode wiring 14 in contact with the first n source region 7 and the p base pickup region 9 via a plug 13 formed of tungsten or the like, and a second n source region 8 and p base pickup region 9 and second source electrode wiring 15 in contact with plug 13.

  Further, the first polysilicon gate wiring 19 in contact with the first gate electrode 11 and the polysilicon film 28, the second polysilicon gate wiring in contact with the second gate electrode 12, and the first polysilicon gate wiring 19 through the contact hole 21. A first gate electrode wiring 17 in contact; a second gate electrode wiring 18 in contact with the second polysilicon gate wiring 20 through a contact hole 21; a first source terminal S1 connected to the first source electrode wiring 14; A second source terminal S 2 connected to the source electrode wiring 15, a first gate terminal G 1 connected to the first gate metal wiring 17, and a second gate terminal G 2 connected to the second gate metal wiring 18 are included. The polysilicon film 29 is not connected to other portions and is in a floating potential state.

  As described above, in the bidirectional trench lateral power MOSFET of this embodiment, the first and second gate electrodes 11 and 12 are formed on the side walls of the closed-loop meandering first trench 3, and the remaining trench portions on both sides are formed. The first and second n source regions 7 and 8 of the bidirectional MOSFET are formed. A closed-loop second trench 25 is formed on the outermost periphery, and the first p base region 4 and the n-well region 2 are separated by the second trench 25.

In the structure of the present invention, by forming the second trench 25, the pn junction between the n well region 2 and the p base region 4 disappears from the surface, and the pn junction between the n well region 62 and the p base region 64 corresponding to FIG. Since the spread of the lateral depletion layer from 95 is not shown in FIG. 3, the inactive region can be narrowed.
Specifically, the necessary interval T3 from the first trench 3 to the end of the n-well region 2 is a total of 2.5 μm of the trench 1 pitch T1 and 5 μm of the interval T2 from the second trench 25 to the end of the n-well region 2 7.5 μm, which is half of the distance L3 of 15 μm required in the conventional structure, and the chip size can be reduced.

Further, when the chip size is not changed, the active region can be expanded, so that the on-resistance can be reduced.
As shown in FIG. 4, the first and second n source regions 7 and 8 are not formed so as to surround the p base pickup region 9 as shown in FIG. It doesn't matter.

FIG. 5 is a plan view of the main part of the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a detailed view of the A part of FIG. 5A, FIG. 5A is a plan view of the main part, and FIG. FIG. 7 is a cross-sectional view of main parts cut along line X2-X2 in FIG. 7A, and FIG. 7 is a cross-sectional view of main parts cut along line X1-X1 in FIG. This semiconductor device is an example of a unidirectional trench lateral power MOSFET.
In FIG. 5, the source region 37, the drain region 8 and the p pickup region 39 shown in FIG. 6 are omitted. In FIG. 6A, the source electrode wiring 44, drain electrode wiring 45, polysilicon gate wiring 49, and polysilicon wiring 50 described in FIG. 5 are omitted, and in FIG. 6B, the trench 33 is filled. An interlayer insulating film for insulating the plug 43 from the first and second gate electrodes 41 and 42 is not shown. Also in FIG. 3, the interlayer insulating film is not shown.

  The configuration of this unidirectional trench lateral power MOSFET will be described. This unidirectional trench lateral power MOSFET includes an n-well region 32 formed in the surface layer of the p-substrate 31, a closed loop-shaped meandering first trench 33 formed from the surface of the n-well region 32, and A closed-loop second trench 55 is formed at the same time as the first trench 33 and surrounds the first trench 33.

Further, the p base region 34 surrounded by the first trench 34 and the second trench 55 and formed in the surface layer of the n well region 52 and the n layer surrounded by the first trench 33 are formed in the surface layer of the n well region 32. ⁺ Region 35, n source region 37 formed in the surface layer of p base region 34 and in contact with the sidewall of first trench 33, and n ⁺⁺ region formed in the surface layer of n ⁺ region 35 and in contact with the sidewall of first trench 33 37 and a p base pickup region 39 formed in the surface layer of the p base region 34 in contact with the n source region 37.

The n drain region 36 formed at the bottom of the first trench 33, the n region 56 formed simultaneously with the n drain region 36 at the bottom of the second trench 55, and the gate insulating film 40 on the side wall of the first trench 33. And a gate electrode 41 formed on the p base region 34 side.
Further, a polysilicon film 42 formed simultaneously with the gate electrode 41 on the n ⁺ region 35 side via the gate insulating film 40 on the side wall of the first trench 33 and formed simultaneously with the gate insulating film 40 on the side wall of the second trench 55. A polysilicon film 58 (formed simultaneously with the gate electrode 41) formed on the p base region 34 side through the insulating film 57 formed, and a polysilicon film 59 (formed simultaneously with the gate electrode 41) formed on the n well region 32 side. Forming).

Further, a contact hole 46 opened in an interlayer insulating film (not shown), a source electrode wiring 44 in contact with the n source region 37 and the p base pickup region 39 through a plug 43, and polysilicon in contact with the gate electrode 41 and the polysilicon film 58 Gate wiring 49, polysilicon wiring 50 in contact with polysilicon film 42, gate electrode wiring 47 in contact with polysilicon gate wiring 49 through contact hole 51, polysilicon wiring 50 in contact with contact hole 51, and n ⁺⁺ 38 And a drain electrode wiring 45 in contact with each other through a plug 43.

Further, it has a source terminal S connected to the source electrode wiring 44, a drain terminal D connected to the drain electrode wiring 45, and a gate terminal G connected to the gate metal wiring 47. The polysilicon film 59 is not connected to other portions and is in a floating potential state.
Also in this case, since the p base region 34 is separated by the second trench 55 as in the first embodiment, the pn junction formed by the n well region 32 and the p base region 34 is not the surface. Since the lateral depletion layer does not spread from the pn junction 95 formed by the corresponding n well region 62 and p base region 64, the inactive region can be narrowed.

  In the second embodiment, the drain side and the source side may be interchanged. Further, as shown in FIG. 4, n source regions 37 may be formed alternately with p base pickup regions 39.

The principal part top view of the semiconductor device of 1st Example of this invention 1A is a detailed view of a part A in FIG. 1, (a) is a plan view of the main part, and (b) is a cross-sectional view of the main part taken along line X2-X2 of (a). Sectional drawing of the principal part cut | disconnected by the X1-X1 line | wire of FIG. FIG. 3 is a plan view of a main part in which first and second n source regions 7 and 8 are formed alternately with a p base pickup region 9. The principal part top view of the semiconductor device of 1st Example of this invention 5A is a detailed view of a part B in FIG. 5, (a) is a plan view of the main part, and (b) is a cross-sectional view of the main part taken along line X2-X2 of (a). Sectional drawing of the principal part cut | disconnected by the X1-X1 line | wire of FIG. Plan view of main part of conventional bidirectional trench lateral power MOSFET FIG. 8 is a detailed view of a portion C in FIG. 8, where (a) is a plan view of the main portion, and (b) is a cross-sectional view of the main portion taken along line X2-X2 of (a). Sectional drawing of the principal part cut | disconnected by the X1-X1 line | wire of FIG. Equivalent circuit diagram of the bidirectional trench lateral power MOSFET shown in FIG.

Explanation of symbols

1, 31 p substrate 2, 32 n well region 3, 33 first trench 4 first p base region 5 second p base region 6, 36 n drain region 7 first n source region 8 second n source region 9, 39 p base pickup region 10, 40 Gate insulating film 11 First gate electrode 12 Second gate electrode 13, 43 Plug 14 First source electrode wiring 15 Second source electrode wiring 16, 21, 46, 51 Contact hole 17 First gate metal wiring 18 Second Gate metal wiring 19 First polysilicon gate wiring 20 Second polysilicon gate wiring 25, 55 Second trench 26, 56 n region 27, 57 Insulating film 28, 29, 58, 59 Polysilicon film 34 p base region 35 n ⁺ region 37 n source region 38 n ⁺⁺ region 41 a gate electrode 42 of polysilicon 44 Seo Source electrode wiring 45 a drain electrode wiring 47 gate metal wiring 49 polysilicon gate wiring 50 of polysilicon wirings

Claims (9)

  A first conductivity type well region selectively formed in a surface layer of a second conductivity type semiconductor substrate; a first trench having a closed loop shape formed in a surface layer of the well region; A first base region of a second conductivity type having a shallower depth than the first trench formed in a surface layer of the well region surrounding the trench and in contact with the first trench; and the first trench and the first base region A planar shape formed in contact with the first base region and having a closed loop shape, and a depth greater than that of the first trench formed in the surface layer of the well region surrounded by the first trench. A second base region of the second conductivity type shallow, a second source region of the first conductivity type formed in a surface layer of the second base region in contact with the first trench, and a surface of the first base region The first tray A first source region of a first conductivity type formed in contact with the groove, a first insulating film formed on the inner surface of the first trench, a second insulating film formed on the inner surface of the second trench, A first gate electrode formed on the first insulating film on the side wall of the first trench on the first source region side, and a first gate electrode formed on the side wall of the first trench on the second source region side. A second gate electrode formed on the second insulating film on a side wall of the second trench on the first base region side and electrically connected to the first gate electrode A polysilicon film formed on the second insulating film on a side wall of the second trench facing the third gate electrode, and filling the first trench and the second trench with the first gate electrode and the first trench. Two gate electrodes and the third gate electrode An interlayer insulating film for insulating the polysilicon film; a first source electrode electrically connected to the second base region and the second source region; and the first base region and the first source region. An electrically connected second source electrode, and a bidirectional MOSFET that allows current to flow bidirectionally along the first trench between the first source electrode and the second source electrode. A featured semiconductor device. A first conductivity type well region selectively formed in a surface layer of a second conductivity type semiconductor substrate; a first trench having a closed loop shape formed in a surface layer of the well region; A base region of a second conductivity type having a shallower depth than the first trench formed in a surface layer of the well region surrounding the trench and in contact with the first trench; surrounding the first trench and the base region; A second trench having a closed loop shape formed in contact with the region; a first semiconductor region of a first conductivity type formed in a surface layer of the well region surrounded by the first trench; A first conductivity type second semiconductor region formed in a surface layer of the semiconductor region; a first conductivity type source region formed in contact with the first trench on a surface layer of the base region; and the first trench. On the inside A first insulating film formed; a second insulating film formed on an inner surface of the second trench; and a first gate formed on the first insulating film on a side wall of the first trench on the source region side. electrodes and said a first said second semiconductor region side of the first insulating film conductive formed on the film on the side wall of the trench, the second insulation on the side walls of the front Kibe over source region side of said second trench A second gate electrode formed on the film and electrically connected to the first gate electrode; and a polysilicon formed on the second insulating film on a side wall of the second trench facing the second gate electrode. A film, an interlayer insulating film that fills the first trench and the second trench and insulates the first gate electrode, the conductive film, and the second gate electrode from the polysilicon film, the second semiconductor region, and the conductive film Electrically connected to the membrane A drain electrode; a source electrode electrically connected to the base region and the source region; and a MOSFET that allows current to flow along the first trench between the source electrode and the drain electrode. A semiconductor device. 2. The semiconductor device according to claim 1, further comprising a sixth semiconductor region of a first conductivity type formed at a bottom portion of the first trench and the second trench and in contact with the first base region and the second base region . Semiconductor device. 3. The semiconductor device according to claim 2, further comprising: a sixth semiconductor region of a first conductivity type formed at a bottom portion of the first trench and the second trench and in contact with the base region and the first semiconductor region. . A first conductivity type well region selectively formed in a surface layer of a second conductivity type semiconductor substrate;
A first trench having a closed-loop planar shape formed in the surface layer of the well region;
A first base region of a second conductivity type having a shallower depth than the first trench formed in a surface layer of the well region surrounding the first trench and in contact with the first trench;
A second trench having a closed loop shape and a planar shape formed surrounding the first trench and the first base region and in contact with the first base region;
A second base region of a second conductivity type having a shallower depth than the first trench formed in a surface layer of the well region surrounded by the first trench;
A second source region of a first conductivity type formed on a surface layer of the second base region in contact with the first trench;
A first source region of a first conductivity type formed on a surface layer of the first base region in contact with the first trench;
A first insulating film formed on the inner surface of the first trench; a second insulating film formed on the inner surface of the second trench;
A first gate electrode formed on the first insulating film on a side wall of the first trench on the first source region side;
A second gate electrode formed on the first insulating film on a side wall of the first trench on the second source region side;
A third gate electrode formed on the second insulating film on a side wall of the second trench on the first base region side;
A polysilicon film formed on the second insulating film on a side wall of the second trench facing the third gate electrode;
An interlayer insulating film that fills the first trench and the second trench and insulates the first gate electrode, the second gate electrode, the third gate electrode, and the polysilicon film;
A first source electrode electrically connected to the second base region and the second source region;
A second source electrode electrically connected to the first base region and the first source region;
A first gate wiring in contact with the first gate electrode disposed on a surface of the semiconductor substrate in a region sandwiched between the first trench and the second trench;
A second gate wiring that is in contact with the second gate electrode disposed on the surface of the semiconductor substrate in a region surrounded by the first trench, and a plurality of the first trenches are formed adjacent to each other. And an arcuate part connecting the elongated parts adjacent to each other in the plurality of elongated parts,
In the arcuate part, the first gate wiring and the first gate electrode are connected, and in the arcuate part, the second gate wiring and the second gate electrode are connected,
A semiconductor device comprising a bidirectional MOSFET that allows current to flow bidirectionally along the first trench between the first source electrode and the second source electrode. A sidewall of the first trench located outside the arc of the arc-shaped portion has a first protrusion that protrudes into the first base region, and the first gate electrode and the first gate are formed in the first protrusion. A wiring is connected, and a side wall of the first trench located outside the arc of the arc-shaped portion has a second protruding portion protruding into the second base region, and the second gate electrode The semiconductor device according to claim 5 , wherein the second gate wiring is connected to the semiconductor device. 7. The semiconductor device according to claim 5 , wherein an interval between the plurality of elongated portions at the meandering portion is equal to an interval between the elongated portion adjacent to the second trench of the elongated portion and the second trench. . The first trench and the second trench are formed at the same time, the first insulating film and the second insulating film are formed at the same time, and the first gate electrode, the second gate electrode, 3 the semiconductor device according to claim 1 or 5, wherein the gate electrode and the polysilicon film are those which are formed at the same time.   The first trench and the second trench are formed at the same time, the first insulating film and the second insulating film are formed at the same time, the first gate electrode, the conductive film, the second 3. The semiconductor device according to claim 2, wherein the gate electrode and the polysilicon film are formed simultaneously.

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