JP2007134500A - Bidirectional semiconductor device - Google Patents

Bidirectional semiconductor device Download PDF

Info

Publication number
JP2007134500A
JP2007134500A JP2005326130A JP2005326130A JP2007134500A JP 2007134500 A JP2007134500 A JP 2007134500A JP 2005326130 A JP2005326130 A JP 2005326130A JP 2005326130 A JP2005326130 A JP 2005326130A JP 2007134500 A JP2007134500 A JP 2007134500A
Authority
JP
Japan
Prior art keywords
trench
region
contact
remaining portion
electrode wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2005326130A
Other languages
Japanese (ja)
Inventor
Mutsumi Kitamura
睦美 北村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Holdings Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Holdings Ltd filed Critical Fuji Electric Holdings Ltd
Priority to JP2005326130A priority Critical patent/JP2007134500A/en
Publication of JP2007134500A publication Critical patent/JP2007134500A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bidirectional semiconductor device such as a bidirectional trench horizontal power MOSFET capable of reducing on-resistance while enhancing channel density. <P>SOLUTION: An n-well region 2 is formed on a surface layer of a p-substrate 1 (a p-type semiconductor substrate). A plurality of stripe-shaped trenches 3 are formed on the surface of the n-well region 2. Wide parts 21 and narrow parts 22 are formed by bending the trenches 3 into a square-wave shape. First/second source electrode wirings 18, 19 are respectively formed so as to intersect the trenches 3. Consequently, it is possible to reduce the on-resistance while increasing the channel density by reducing a device pitch T1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は、双方向トレンチ横型パワーＭＯＳＦＥＴ（双方向ＴＬＰＭ）などの双方向半導体装置に関する。   The present invention relates to a bidirectional semiconductor device such as a bidirectional trench lateral power MOSFET (bidirectional TLPM).

バッテリーなどの電源装置では、バッテリーを充電する場合と、バッテリーを放電する場合の双方を制御して、バッテリーの過充電や過放電を防止している。そのため、交流信号や交流電力のオン・オフできる双方向の半導体スイッチが必要となる。この双方向の半導体スイッチとして双方向トレンチ横型パワーＭＯＳＦＥＴがある。
図４から図６は、従来の双方向トレンチ横型パワーＭＯＳＦＥＴの構成図であり、図４は要部平面図、図５は図４のＤ部の詳細図、図６は、図５のＸ−Ｘ線で切断した要部断面図である。これはｎチャネルＭＯＳＦＥＴの場合である。
図４および図５において、一本の蛇行して形成されるストライプ状のトレンチ５３を形成し、このトレンチ５３の側壁（トレンチ残し箇所７０の側壁でもある）にゲート絶縁膜５６を介して第１、第２ゲート電極５７、５８を形成する。トレンチ５３が形成されないトレンチ残りの箇所７０は、直線のストライプ状をしており、この箇所には第１、第２ｎソース領域５９、６１および第１、第２ｐコンタクト領域６０、６２をそれぞれ形成し、その上の層間絶縁膜６４（図６参照）を形成し、この層間絶縁膜６４に第１、第２コンタクトホール６５、６６を形成し、この第１、第２コンタクトホール６５、６６を介して第１、第２ｎソース領域５９、６１および第１、第２ｐコンタクト領域６０、６２と櫛の歯状の第１、第２ソース電極配線６８、６９とそれぞれ接続する。この第１、第２ソース電極配線６８、６９はソース電極とソース配線を兼ねている。第１、第２ゲート電極５７、５８は第１、第２ゲートポリシリコン配線７３、７５にそれぞれ接続し、この第１、第２ゲートポリシリコン配線７３、７５は第１、第２ゲート金属配線７４、７６とコンタクトホール７７を介してそれぞれ接続する。 In a power supply device such as a battery, overcharging and overdischarging of the battery are prevented by controlling both when the battery is charged and when the battery is discharged. Therefore, a bidirectional semiconductor switch that can turn on / off an AC signal and AC power is required. There is a bidirectional trench lateral power MOSFET as the bidirectional semiconductor switch.
4 to 6 are configuration diagrams of a conventional bidirectional trench lateral power MOSFET. FIG. 4 is a plan view of a main part, FIG. 5 is a detailed view of a portion D in FIG. 4, and FIG. It is principal part sectional drawing cut | disconnected by X-ray | X_line. This is the case for an n-channel MOSFET.
In FIG. 4 and FIG. 5, a stripe-shaped trench 53 formed in a meandering manner is formed, and the first side wall of the trench 53 (also the side wall of the remaining trench portion 70) is interposed via the gate insulating film 56. Second gate electrodes 57 and 58 are formed. The remaining trench portion 70 where the trench 53 is not formed has a straight stripe shape, and the first and second n source regions 59 and 61 and the first and second p contact regions 60 and 62 are formed in this portion, respectively. An interlayer insulating film 64 (see FIG. 6) is formed thereon, and first and second contact holes 65 and 66 are formed in the interlayer insulating film 64, and the first and second contact holes 65 and 66 are interposed therebetween. The first and second n source regions 59 and 61 and the first and second p contact regions 60 and 62 are connected to comb-shaped first and second source electrode wirings 68 and 69, respectively. The first and second source electrode wirings 68 and 69 serve as a source electrode and a source wiring. The first and second gate electrodes 57 and 58 are connected to the first and second gate polysilicon wirings 73 and 75, respectively. The first and second gate polysilicon wirings 73 and 75 are the first and second gate metal wirings. 74 and 76 are connected to each other through a contact hole 77.

図６において、ｐ基板５１（ｐ型半導体基板）の表面層にｎウェル領域５２を形成し、ｎウェル領域５２の表面から内部に向かってトレンチ５３を形成し、トレンチ５３の底部のｐ基板５１にｎドレイン領域５４を形成する。トレンチ５３の側壁にゲート絶縁膜５６を介してポリシリコンで第１、第２ゲート電極５７、５８をそれぞれ形成し、トレンチ残り箇所７０のｐ基板１の表面層にトレンチ５３と接するｐオフセット領域５５を形成し、ｐオフセット領域５５の表面層にトレンチ５３と接する第１、第２ｎソース領域５９、６１および第１、第２ｎソース領域５９、６１を選択的にそれぞれ形成し、この第１、第２ｎソース領域５９、６１と接する第１、第２ｐコンタクト領域６０、６２をｐオフセット領域５５の表面層にそれぞれ形成し、トレンチ５３の内部を絶縁膜６３で充填する。第１、第２ｎソース領域５９、６１は層間絶縁膜６４の第１、第２コンタクトホール６５、６６を充填したタングステン６７により第１、第２ソース電極配線６８、６９にそれぞれ接続する。第１、第２ソース電極配線６８、６９をアルミニウム膜でそれぞれ形成する。第１、第２ソース電極配線６８、６９はソース電極とソース配線を兼ねている。第１、第２ソース電極配線６８、６９はソース端子Ｓ１、Ｓ２とそれぞれ接続し、第１、第２ゲート電極５７、５８は第１、第２ゲートポリシリコン配線７３、７５および第１、第２ゲート金属配線７４、７６を介して第１、第２ゲート端子Ｇ１、Ｇ２とそれぞれ接続する。尚、図中の７８、７９は、トレンチ横型パワーＭＯＳＦＥＴ（ＴＬＰＭ）の第１ＭＯＳＦＥＴと第２ＭＯＳＦＥＴであり、８０、８１はｐオフセット領域５５とｎウェル領域５２で形成される第１、第２寄生ｐｎダイオードである。   In FIG. 6, an n-well region 52 is formed on the surface layer of a p-substrate 51 (p-type semiconductor substrate), a trench 53 is formed from the surface of the n-well region 52 to the inside, and the p-substrate 51 at the bottom of the trench 53 is formed. An n drain region 54 is formed in First and second gate electrodes 57 and 58 are formed of polysilicon on the side wall of the trench 53 through a gate insulating film 56, and a p offset region 55 in contact with the trench 53 on the surface layer of the p substrate 1 in the remaining trench portion 70. The first and second n source regions 59 and 61 and the first and second n source regions 59 and 61 in contact with the trench 53 are selectively formed on the surface layer of the p offset region 55, respectively. First and second p contact regions 60 and 62 in contact with the 2n source regions 59 and 61 are formed on the surface layer of the p offset region 55, respectively, and the inside of the trench 53 is filled with an insulating film 63. The first and second n source regions 59 and 61 are connected to the first and second source electrode wirings 68 and 69 by tungsten 67 filling the first and second contact holes 65 and 66 of the interlayer insulating film 64, respectively. First and second source electrode wirings 68 and 69 are formed of aluminum films, respectively. The first and second source electrode wirings 68 and 69 serve as the source electrode and the source wiring. The first and second source electrode wirings 68 and 69 are connected to the source terminals S1 and S2, respectively. The first and second gate electrodes 57 and 58 are the first and second gate polysilicon wirings 73 and 75 and the first and second gate electrodes 57 and 58, respectively. The first and second gate terminals G1 and G2 are connected through two-gate metal wirings 74 and 76, respectively. In the figure, 78 and 79 are the first MOSFET and the second MOSFET of the trench lateral power MOSFET (TLPM), and 80 and 81 are the first and second parasitic pn formed by the p offset region 55 and the n well region 52, respectively. It is a diode.

図７は、図４〜図６で示した双方向トレンチ横型パワーＭＯＳＦＥＴの等価回路図である。第１ＭＯＳＦＥＴ７８と第２ＭＯＳＦＥＴ７９はドレインＤ（ｎドレイン領域５４）で接続されており、このドレインＤはその他の端子と接続していない。また第１、第２ＭＯＳＦＥＴ７８、７９と第１、第２寄生ｐｎダイオード８０、８１はそれぞれ逆並列に接続する。
Ｓ１がＳ２に対して高電位の状態にあるとき、第２ゲート端子Ｇ２に正のゲート信号を与えて第２ＭＯＳＦＥＴオンさせると、Ｓ１−第１寄生ダイオード８０−Ｄ−第２ＭＯＳＦＥＴ７９−Ｓ２の経路で主電流がＳ１からＳ２に向かって流れる。一方、Ｓ２がＳ１に対して高電位の状態にあるとき、第１ゲート端子Ｇ１に正のゲート信号を与えて第１ＭＯＳＦＥＴオンさせると、Ｓ２−第２寄生ダイオード８１−Ｄ−第１ＭＯＳＦＥＴ７８−Ｓ１の経路で主電流がＳ２からＳ１に向かって流れる。このように、この素子は双方向に主電流を流すことができる。 FIG. 7 is an equivalent circuit diagram of the bidirectional trench lateral power MOSFET shown in FIGS. The first MOSFET 78 and the second MOSFET 79 are connected by a drain D (n drain region 54), and the drain D is not connected to other terminals. The first and second MOSFETs 78 and 79 and the first and second parasitic pn diodes 80 and 81 are connected in antiparallel.
When S1 is in a high potential state with respect to S2, a positive gate signal is applied to the second gate terminal G2 to turn on the second MOSFET, thereby causing a path of S1-first parasitic diode 80-D-second MOSFET 79-S2 to pass. The main current flows from S1 to S2. On the other hand, when S2 is in a high potential state with respect to S1, a positive gate signal is applied to the first gate terminal G1 to turn on the first MOSFET, and S2-second parasitic diode 81-D-first MOSFET 78-S1. A main current flows from S2 to S1 along the path. Thus, this element can flow the main current in both directions.

つぎに、図４において、各部の寸法について説明する。トレンチ残し箇所７０は第１、第２ソース領域５９、６１と第１、第２ソース電極配線６８、６９と接続させるため、第１、第２コンタクトホール６５、６６を形成する必要がある。そのため、トレンチ残し箇所７０の幅Ｋ１としては、コンタクトホール幅Ｋ２とマスクアライメントなどのプロセスマージンの幅Ｎを合わせた幅が必要である。例えば、０．６μｍルールで設計する場合、Ｋ１＝０．６μｍ（コンタクトホール幅Ｋ２）＋０．４μｍ×２（コンタクトホールの両側のプロセスマージンＮ×２）＝１．４μｍが必要になる。
コンタクトホールの両側のプロセスマージンＮ×２は、コンタクトホールのパターニング時のマスクアライメントの他、トレンチエッチング時の加工精度マージンおよびトレンチ側壁の酸化膜の膜厚マージンなどを含んでいる。 Next, referring to FIG. 4, the dimensions of each part will be described. In order to connect the first and second source regions 59 and 61 to the first and second source electrode wirings 68 and 69 in the remaining trench portion 70, it is necessary to form first and second contact holes 65 and 66. Therefore, the width K1 of the trench remaining portion 70 needs to be a width obtained by combining the contact hole width K2 and the width N of the process margin such as mask alignment. For example, when designing with the 0.6 μm rule, K1 = 0.6 μm (contact hole width K2) +0.4 μm × 2 (process margin N × 2 on both sides of the contact hole) = 1.4 μm is required.
The process margin N × 2 on both sides of the contact hole includes a mask alignment at the time of patterning the contact hole, a processing accuracy margin at the time of trench etching, a film thickness margin of the oxide film on the trench side wall, and the like.

一方、トレンチ幅Ｐは、耐圧を保持するために、例えば、２０Ｖクラスデバイスの場合、１．０μｍ程度のトレンチ幅Ｐが必要になりデバイス１ユニット（繰り返し単位）のデバイスピッチＴ２は、１．４μｍ（トレンチ残し箇所の幅Ｋ１）＋１．０μｍ（トレンチ幅Ｐ）＝２．４μｍとなる。
図４では、ストライプ状のトレンチが蛇行する一本のトレンチで形成され、トレンチ残り箇所７０が櫛の歯状になっており歯の箇所が直線のストライプ状となっている。
これに対して、特許文献１では、トレンチ残り箇所をトレンチで取り囲んだセル状になっている双方向トレンチ横型パワーＭＯＳＦＥＴの例が記載されている。
特許文献２には、単方向トレンチ縦型ＭＯＳＦＥＴで、トレンチの配列パターンおよびソースとベースにおける同時改善によりチャネル密度の向上を図ることが記載されている。 On the other hand, in order to maintain the breakdown voltage, for example, in the case of a 20V class device, the trench width P requires a trench width P of about 1.0 μm, and the device pitch T2 of the device 1 unit (repeating unit) is 1.4 μm. (Width K1 of the trench remaining portion) +1.0 μm (trench width P) = 2.4 μm.
In FIG. 4, the stripe-shaped trench is formed by a single meandering trench, the remaining trench portion 70 has a comb-tooth shape, and the tooth portion has a straight stripe shape.
On the other hand, Patent Document 1 describes an example of a bidirectional trench lateral power MOSFET having a cell shape in which the remaining portion of the trench is surrounded by a trench.
Patent Document 2 describes that in a unidirectional trench vertical MOSFET, channel density is improved by improving the trench arrangement pattern and the source and base simultaneously.

特許文献３には、単方向トレンチ縦型ＭＯＳＦＥＴで、トレンチを屈曲させて平面、アターンとして幅広部と幅狭部を設け、幅広部にソース領域とボディコンタクト領域を形成し、幅狭部にはソース領域のみを形成することで、単位面積当たりのチャネル幅を増加させて、オン抵抗を減少させたことが記載されている。
特開２００４−２７３０３９号公報 特開平１１─１１１９７６号公報 特許第３５２４８５０号公報 In Patent Document 3, a unidirectional trench vertical MOSFET is formed by bending a trench to provide a flat surface and a wide portion and a narrow portion as a turn, forming a source region and a body contact region in the wide portion, It is described that the channel width per unit area is increased and the on-resistance is decreased by forming only the source region.
JP 2004-273039 A Japanese Patent Laid-Open No. 11-111976 Japanese Patent No. 3524850

図４のように、トレンチ５３の直線のストライプ状の箇所では、微細化して、トレンチ残し箇所の幅Ｋ１を狭めると第１、第２コンタクトホール６５、６６の面積が小さく成りすぎて、コンタクト抵抗が増大する。また、第１、第２ソース電極配線６８、６９の幅が狭く成りすぎてパターニングが困難になり、第１、第２ソース電極配線６８、６９の電気抵抗が増大して、オン抵抗が増大する。
つまり、前記したように、０．６μｍルール（パターン設計する場合の尺度）とした場合には、デバイス１ユニットのデバイスピッチＴ２は２．４μｍが最小にできる限界であり、これ以上狭くすることができず、チャネル密度を高くすることが困難になる。
また、特許文献１に示すセル状のトレンチ残り箇所の場合も、図４と同じように大きくなる。 As shown in FIG. 4, in the straight stripe-shaped portion of the trench 53, when the width K1 of the remaining portion of the trench is reduced and the area of the first and second contact holes 65 and 66 becomes too small, the contact resistance is reduced. Will increase. In addition, the width of the first and second source electrode wirings 68 and 69 becomes too narrow and patterning becomes difficult, the electrical resistance of the first and second source electrode wirings 68 and 69 increases, and the on-resistance increases. .
That is, as described above, when the 0.6 μm rule (scale for pattern design) is used, the device pitch T2 of one device unit is the limit that 2.4 μm can be minimized, and can be narrowed further. It is impossible to increase the channel density.
In the case of the remaining portion of the cellular trench shown in Patent Document 1, it becomes larger as in FIG.

また特許文献２、３では単一方向のトレンチ縦型パワーＭＯＳＦＥＴについての記載はあるが、第１、第２ソース領域がある双方向トレンチ横型パワーＭＯＳＦＥＴについての記載はされていない。
この発明の目的は、前記の課題を解決して、チャネル密度を高め、オン抵抗の低減を図ることができる双方向トレンチ横型パワーＭＯＳＦＥＴなどの双方向半導体装置を提供することである。 Patent Documents 2 and 3 describe a unidirectional trench vertical power MOSFET, but do not describe a bidirectional trench lateral power MOSFET with first and second source regions.
An object of the present invention is to solve the above-described problems and provide a bidirectional semiconductor device such as a bidirectional trench lateral power MOSFET that can increase channel density and reduce on-resistance.

前記の目的を達成するために、第１導電型の第１領域と、該第１領域の表面から内部に向かって形成した閉ループのトレンチと、該閉ループの内側と外側で分割され、前記第１領域の表面層に形成された第１トレンチ残り箇所および第２トレンチ残り箇所と、該トレンチの底部の前記第１領域に形成した第１導電型の第２領域と、前記第１トレンチ残り箇所および第２トレンチ残り箇所のそれぞれの表面層に形成した第２導電型の第３領域と、前記第１トレンチ残り箇所の前記第３領域の表面層に形成した前記トレンチの側壁と接する第１導電型の第４領域と、前記第１トレンチ残り箇所の前記第３領域の表面層に形成した第２導電型の第５領域と、前記第２トレンチ残り箇所の前記第３領域の表面層に形成した前記トレンチの側壁と接する第１導電型の第６領域、前記第２トレンチ残り箇所の前記第３領域の表面層に形成した前記トレンチの側壁と接する第２導電型の第７領域と、前記第１トレンチ残り箇所の側壁にゲート絶縁膜を介して形成された第１ゲート電極と、前記第２トレンチ残り箇所の側壁にゲート絶縁膜を介して形成された第２ゲート電極と、前記第１トレンチ残り箇所および前記第２トレンチ残し箇所上に形成され、前記第４領域上および前記第５領域上に第１開口部を有し、かつ前記第６領域上および前記第７領域上に第２開口部を有する層間絶縁膜と、前記第１開口部を介して前記第４領域および第５領域にそれぞれ接する第１電極配線と、前記第２開口部を介して前記第６領域および第７領域にそれぞれ接する第２電極配線と、を具備する双方向半導体装置において、
前記第１トレンチ残し箇所と前記第２トレンチ残し箇所が対向し、第１トレンチ残し箇所の平面形状が第１幅広部と第１幅狭部からなり、第２トレンチ残り箇所の平面形状が第２幅広部と第２幅狭部からなり、第１幅広部と第２幅狭部とが対向し、第１幅狭部と第２幅広部が対向し、前記第１電極配線が前記第１トレンチおよび前記第２トレンチを横切るように配置され、前記第２電極配線が前記第１トレンチおよび前記第２トレンチを横切るように配置される構成とする。 In order to achieve the above object, a first region of a first conductivity type, a closed-loop trench formed inward from the surface of the first region, and an inner side and an outer side of the closed loop are divided into the first region. A first trench remaining portion and a second trench remaining portion formed in the surface layer of the region; a first conductivity type second region formed in the first region at the bottom of the trench; and the first trench remaining portion and A third region of the second conductivity type formed in each surface layer of the remaining portion of the second trench, and a first conductivity type in contact with the sidewall of the trench formed in the surface layer of the third region of the remaining portion of the first trench A fourth region of the second conductivity type, a fifth region of the second conductivity type formed in the surface layer of the third region of the remaining portion of the first trench, and a surface layer of the third region of the remaining portion of the second trench. In contact with the trench sidewalls A first conductivity type sixth region; a second conductivity type seventh region in contact with a sidewall of the trench formed on a surface layer of the third region of the second trench remaining portion; and a sidewall of the first trench remaining portion. A first gate electrode formed through a gate insulating film; a second gate electrode formed through a gate insulating film on a side wall of the second trench remaining portion; and the first trench remaining portion and the second trench. An interlayer insulating film formed on the remaining portion, having a first opening on the fourth region and the fifth region, and having a second opening on the sixth region and the seventh region; A first electrode wiring in contact with the fourth region and the fifth region through the first opening, and a second electrode wiring in contact with the sixth region and the seventh region through the second opening, respectively. A bi-directional semiconductor device comprising In,
The first trench remaining portion and the second trench remaining portion are opposed to each other, the planar shape of the first trench remaining portion is composed of the first wide portion and the first narrow portion, and the planar shape of the second trench remaining portion is the second. It consists of a wide part and a second narrow part, the first wide part and the second narrow part face each other, the first narrow part and the second wide part face each other, and the first electrode wiring is in the first trench. The second electrode wiring is disposed so as to cross the second trench, and the second electrode wiring is disposed so as to cross the first trench and the second trench.

また、前記閉ループのトレンチの平面形状が直線のストライプ状となる箇所があり、前記第１電極配線および第２電極配線が前記第１トレンチおよび前記第２トレンチの前記直線箇所上をそれぞれ該直角に横切る構成とするとよい。
また、前記第１幅広部の幅が徐々に狭まって前記第１幅狭部の幅になるとよい。
また、前記第１電極配線および第２電極配線の幅が前記第１幅広部上および前記第２幅広部上で広く、前記第１幅狭部上および第２幅狭部上で狭いとよい。 Further, there is a portion where the planar shape of the closed-loop trench is a straight stripe, and the first electrode wiring and the second electrode wiring are respectively perpendicular to the straight portions of the first trench and the second trench. It is better to have a crossing configuration.
Further, it is preferable that the width of the first wide portion is gradually reduced to be the width of the first narrow portion.
Preferably, the first electrode wiring and the second electrode wiring are wide on the first wide portion and the second wide portion and narrow on the first narrow portion and the second narrow portion.

この発明によれば、半導体層の表面に設けたストライプ状の複数のトレンチと、該トレンチの底部の前記半導体基板に設けたドレイン領域と前記トレンチ表面に設けたゲート絶縁膜と、前記トレンチに埋め込まれたゲート電極と、前記トレンチに隣接した前記半導体層の一方の表面に設けた第１ソース領域および他方の表面に設けた第２ソース領域と、前記第１ソース領域とコンタクトする第１ソース電極配線と、前記第２ソース領域とコンタクトする第２ソース電極配線とを具備する双方向半導体装置において、前記トレンチを曲折させて隣接するトレンチで挟まれる半導体層表面に幅広部と幅狭部を設け、トレンチを横切って幅広部に第１、第２ソース電極配線を形成することで、デバイスピッチを狭くできて、チャネル密度の増加とオン抵抗の低減を図ることができる。
また、幅広部の幅が徐々に狭まって幅狭部の幅になることで、トレンチ幅をほぼ一定にできて、トレンチ深さを均一化できて、良好な耐圧を得ることができる。 According to the present invention, the plurality of stripe-shaped trenches provided on the surface of the semiconductor layer, the drain region provided on the semiconductor substrate at the bottom of the trench, the gate insulating film provided on the surface of the trench, and embedded in the trench A gate electrode, a first source region provided on one surface of the semiconductor layer adjacent to the trench, a second source region provided on the other surface, and a first source electrode in contact with the first source region In a bidirectional semiconductor device comprising a wiring and a second source electrode wiring that contacts the second source region, a wide portion and a narrow portion are provided on a surface of the semiconductor layer that is sandwiched between adjacent trenches by bending the trench. By forming the first and second source electrode wirings in the wide part across the trench, the device pitch can be narrowed, and the channel density can be increased and turned off. Reduction in resistance can be achieved.
Further, since the width of the wide portion is gradually reduced to become the width of the narrow portion, the trench width can be made substantially constant, the trench depth can be made uniform, and a good breakdown voltage can be obtained.

また、ソース電極配線の幅が幅広部上で広く、幅狭部上で狭くすることで、ソース領域とソース電極配線とコンタクトする間隔を縮小できて、オン抵抗の低減を図ることができる。   In addition, since the width of the source electrode wiring is wide on the wide portion and narrowed on the narrow portion, the distance between the source region and the source electrode wiring can be reduced, and the on-resistance can be reduced.

実施の形態をつぎの実施例で説明する。   The embodiment will be described in the following examples.

図１は、この発明の第１実施例の半導体装置の構成図であり、同図（ａ）は要部平面図、同図（ｂ）は同図（ａ）のＸ−Ｘ線で切断した要部断面図である。図１は図４の直線のストライプ状のトレンチ５３がある箇所に相当する平面図である。
同図（ａ）、同図（ｂ）において、ｐ基板１（ｐ型半導体基板）の表面層にｎウェル領域２を形成し、ｎウェル領域２の表面にストライプ状のトレンチ３を複数形成し、トレンチ３を方形波状に屈曲させて幅広部２１と幅狭部２２を形成する。交互に第１ｎソース領域９と第２ｎソース領域１１を形成し、第１ｎソース領域９と第１ｐコンタクト領域１０に層間絶縁膜１４に開け第１コンタクトホール１５を介して接する第１ソース電極配線１８を形成し、第２ｎソース領域１１と第２ｐコンタク領域１６に層間絶縁膜１４に開けた第２コンタクトホール１６を介して接する第２ソース電極配線１９を形成する。この第１、第２コンタクト領域１０、１２および第１、第２コンタクトホール１５、１６は幅広部２１に形成し、第１、第２ソース領域９、１１は幅広部２１と幅狭部２２の双方に形成する。第１、第２ソース電極配線１８、１９はソース電極とソース配線と兼ねている。前記の第１ソース電極配線１８および第２ソース電極配線１９はそれぞれトレンチ３を横切るように形成する。この図では、ストライプ状のトレンチ３およびストライプ状のトレンチ残り箇所２０と第１、第２ソース電極配線１８、１９は直角に交わった場合を示しているが、おおよそ直交（９０°±１０°程度以内）していればよい。。つぎの同図（ｂ）の説明では同図（ａ）の平面図の説明と一部重複する箇所があるが再度説明する。 FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 1 (a) is a plan view of an essential part, and FIG. 1 (b) is cut along line XX in FIG. It is principal part sectional drawing. FIG. 1 is a plan view corresponding to a portion where the straight stripe-shaped trench 53 of FIG. 4 is present.
1A and 1B, an n well region 2 is formed on the surface layer of a p substrate 1 (p type semiconductor substrate), and a plurality of stripe-shaped trenches 3 are formed on the surface of the n well region 2. The trench 3 is bent into a square wave shape to form the wide portion 21 and the narrow portion 22. A first n source region 9 and a second n source region 11 are alternately formed, and a first source electrode wiring 18 is formed in the interlayer insulating film 14 in contact with the first n source region 9 and the first p contact region 10 through the first contact hole 15. The second source electrode wiring 19 is formed in contact with the second n source region 11 and the second p contact region 16 through the second contact hole 16 opened in the interlayer insulating film 14. The first and second contact regions 10 and 12 and the first and second contact holes 15 and 16 are formed in the wide portion 21, and the first and second source regions 9 and 11 are formed in the wide portion 21 and the narrow portion 22. Form on both sides. The first and second source electrode wirings 18 and 19 also serve as a source electrode and a source wiring. The first source electrode wiring 18 and the second source electrode wiring 19 are formed so as to cross the trench 3. This figure shows a case where the stripe-shaped trench 3 and the stripe-shaped trench remaining portion 20 and the first and second source electrode wirings 18 and 19 intersect at right angles, but are approximately orthogonal (about 90 ° ± 10 °). Within). . In the next description of FIG. 2B, there is a part which overlaps with the description of the plan view of FIG.

同図（ｂ）において、この双方向半導体装置（双方向ＴＬＰＭ）は、ｐ基板１の表面層に形成したｎウェル領域２と、ｎウェル領域２の表面に形成したトレンチ３と、トレンチ３の底部のｎウェル領域２に形成したｎドレイン領域４と、トレンチ残りの箇所２０のｎウェル領域２の表面層に形成したトレンチ３と接するｐオフセット領域５と、トレンチ３を挟んで一方のｐオフセット領域５の表面層に形成したトレンチ３と接する第１ｎソース領域９と、他方のｐオフセット領域５の表面層に形成したトレンチ３と接する第２ｎソース領域１１と、第１ｎソース領域９と接して形成した第１ｐコンタクト領域１０と、第２ｎソース領域１１と接して形成した第２ｐコンタクト領域１２と有する。
また、トレンチ３の側壁にゲート絶縁膜６を介して形成した第１、第２ゲート電極７、８と、トレンチ３内に充填した絶縁膜１３と、第１ｎソース領域９上と第１ｐコンタクト領域１０上に形成した第１ソース電極配線１８と、第２ｎソース領域１１上と第２ｐコンタクト領域１２上に形成した第２ソース電極配線１９を有する。 In FIG. 2B, this bidirectional semiconductor device (bidirectional TLPM) includes an n well region 2 formed in the surface layer of the p substrate 1, a trench 3 formed in the surface of the n well region 2, An n drain region 4 formed in the bottom n well region 2, a p offset region 5 in contact with the trench 3 formed in the surface layer of the n well region 2 in the remaining portion 20 of the trench, and one p offset across the trench 3 A first n source region 9 in contact with the trench 3 formed in the surface layer of the region 5, a second n source region 11 in contact with the trench 3 formed in the surface layer of the other p offset region 5, and a contact with the first n source region 9 The first p contact region 10 is formed, and the second p contact region 12 is formed in contact with the second n source region 11.
In addition, first and second gate electrodes 7 and 8 formed on the side wall of the trench 3 via the gate insulating film 6, an insulating film 13 filled in the trench 3, the first n source region 9 and the first p contact region 10 and a second source electrode wiring 19 formed on the second n source region 11 and the second p contact region 12.

第１、第２ｎソース領域９、１１上と第１、第２ｐコンタクト領域１０、１２と第１、第２ソース電極配線１８、１９は層間絶縁膜１４に形成した第１、第２コンタクトホール１５、１６を充填するタングステン１７を介して接続する。尚、このタングステン１７は、ソース電極配線１８、１９と同一金属（例えば、アルミニウムなど）であっても構わない。
図１に示すように、トレンチ残り箇所２０の幅広部２１と幅狭部２２を互いに入り組むように配置し、第１、第２ｐコンタクト領域１０、１２と第１、第２コンタクトホール１５、１６を幅広部２１に形成し、幅狭部２２には第１、第２ソース領域９、１１のみを形成することで、トレンチ残し箇所２０の繰り返し幅を狭くできて、デバイスピッチＴ１を上げることができる。デバイスピッチＴ１が上がることで、チャネル密度が増大してオン抵抗の低減を図ることができる。尚、トレンチ残り箇所２０の幅狭部２２の幅は、第１、第２ｎソース領域９、１１を形成するためのイオン注入のフォト加工限界で決まり、０．６μｍルールで設計すると０．８μｍとなる。 The first and second n-type source regions 9 and 11 and the first and second p contact regions 10 and 12 and the first and second source electrode wirings 18 and 19 are formed in the interlayer insulating film 14 in the first and second contact holes 15. , 16 through tungsten 17 filling. The tungsten 17 may be the same metal as the source electrode wirings 18 and 19 (for example, aluminum).
As shown in FIG. 1, the wide portion 21 and the narrow portion 22 of the remaining trench portion 20 are arranged so as to be intertwined with each other, and the first and second p contact regions 10 and 12 and the first and second contact holes 15 and 16 are formed. By forming only the first and second source regions 9 and 11 in the wide portion 21 and in the narrow portion 22, the repetition width of the trench remaining portion 20 can be narrowed, and the device pitch T 1 can be increased. . As the device pitch T1 increases, the channel density increases and the on-resistance can be reduced. The width of the narrow portion 22 of the remaining trench portion 20 is determined by the photo-processing limit of ion implantation for forming the first and second n source regions 9 and 11, and is 0.8 μm when designed by the 0.6 μm rule. Become.

第１、第２ｎソース領域９、１１を形成するｎ型不純物イオンは、トレンチ残し箇所２０のみイオン注入され、トレンチ３底部にはイオン注入されないようにする。これは、トレンチ３底部のｎドレイン領域４にｎ型不純物イオンが打ち込まれるとｎドレイン領域４の不純物濃度が増大して、空乏層の広がりを阻止するため、耐圧が低下してしまう。また、トレンチ３肩部から第１、第２ｎソース領域９、１１が離れると、チャネルが形成できずトランジスタとして動作しない。
つぎに、平面形状での寸法について説明する。コンタクトを取らない幅狭部２２の幅を０．８μｍとすると、前記のデバイス１ユニットに対応するデバイスピッチＴ１は、１．８μｍ（幅広部の幅）／２＋０．８μｍ（幅狭部２２の幅）／２＋０．６μｍ（トレンチ幅）＝１．９μｍとなる。抵抗は面積に反比例するので、デバイスピッチＴ１を図４のデバイスピッチＴ２である２．４μｍから１．９μｍとすることで、２．４μｍ／１．９μｍ＝１．２６、つまり、２６％の低オン抵抗化を図ることができる。 The n-type impurity ions forming the first and second n source regions 9 and 11 are ion-implanted only at the remaining trench portion 20 and are not implanted into the bottom of the trench 3. This is because when n-type impurity ions are implanted into the n drain region 4 at the bottom of the trench 3, the impurity concentration in the n drain region 4 increases to prevent the depletion layer from spreading, and the breakdown voltage decreases. If the first and second n source regions 9 and 11 are separated from the shoulder of the trench 3, a channel cannot be formed and the transistor does not operate.
Next, dimensions in a planar shape will be described. If the width of the narrow portion 22 that does not contact is 0.8 μm, the device pitch T1 corresponding to the device 1 unit is 1.8 μm (width of the wide portion) /2+0.8 μm (width of the narrow portion 22). ) /2+0.6 μm (trench width) = 1.9 μm. Since the resistance is inversely proportional to the area, by changing the device pitch T1 from 2.4 μm to 1.9 μm, which is the device pitch T2 in FIG. 4, 2.4 μm / 1.9 μm = 1.26, that is, 26% low. On-resistance can be achieved.

ところで、トレンチエッチングにおけるトレンチ形状は、トレンチ幅の違いにより深さが異なることがある。例えば、幅０．４μｍと幅２μｍのパターンが混在するパターンで、幅２μｍのトレンチの深さを２μｍとする条件でトレンチエッチングした場合、幅０．４μｍのトレンチは深さ１．５μｍと浅くなる。つまりトレンチ幅の狭い方がトレンチは浅くなる。そのため、図１のようなレイアウトの場合、トレンチ３を直角に曲げるとその箇所でトレンチ幅Ｂが広くなり、トレンチの深さが深くなってしまう。トレンチが深くなるとこの箇所で電流経路が長くなりオン抵抗が増大し、電流が均一に流れなくなりため、オン電圧は上昇する。また、この箇所で空乏層の広がりが不均一となり電界集中が起きやすくなる。つぎに角部でのトレンチ幅Ｂの広がりを抑える方法について説明する。   By the way, the trench shape in trench etching may be different in depth due to the difference in trench width. For example, in the case where a pattern having a width of 0.4 μm and a width of 2 μm is mixed, and trench etching is performed under the condition that the depth of the trench having a width of 2 μm is 2 μm, the trench having a width of 0.4 μm becomes shallow at a depth of 1.5 μm. . In other words, the narrower the trench, the shallower the trench. Therefore, in the case of the layout as shown in FIG. 1, if the trench 3 is bent at a right angle, the trench width B is widened at that point, and the depth of the trench is increased. When the trench becomes deeper, the current path becomes longer at this point, the on-resistance increases, and the current does not flow uniformly, so the on-voltage increases. In addition, the depletion layer spreads unevenly at this location, and electric field concentration tends to occur. Next, a method for suppressing the spread of the trench width B at the corner will be described.

図２は、この発明の第２実施例の半導体装置の要部平面図である。この図は図１（ａ）に相当する平面図である。
図１との違いは、トレンチを４５°に曲げてレイアウトした点である。こうすることで、角部（Ｃ部）の幅を直角にした場合より狭めることができて、トレンチ３の深さをほぼ均一に形成することができる。
ところで、第１コンタクトホール１５間および第２コンタクトホール１６間の間隔（以下、コンタクトホール間の間隔Ｌ１という）が長いと、オン抵抗が上がってしまう。例えば、図２において、コンタクトホールがない箇所の第１、第２ｎソース領域９、１１を流れる電流がコンタクトホール１５、１６から吸い上げられるまでに、ｎソース領域の拡散抵抗が上乗せされオン抵抗が増大する。つぎに、第１コンタクトホール１５同士および第２コンタクトホール１６同士の間の間隔Ｌ１を短くする方法について以下の実施例で説明する。 FIG. 2 is a plan view of an essential part of a semiconductor device according to a second embodiment of the present invention. This figure is a plan view corresponding to FIG.
The difference from FIG. 1 is that the trench is laid out at 45 °. By doing so, the width of the corner (C portion) can be made narrower than when the width is made to be a right angle, and the depth of the trench 3 can be formed almost uniformly.
By the way, if the interval between the first contact holes 15 and the second contact hole 16 (hereinafter referred to as the interval L1 between the contact holes) is long, the on-resistance increases. For example, in FIG. 2, the diffusion resistance of the n source region is increased and the on-resistance is increased until the current flowing through the first and second n source regions 9 and 11 in the portion where there is no contact hole is sucked up from the contact holes 15 and 16. To do. Next, a method for shortening the distance L1 between the first contact holes 15 and the second contact holes 16 will be described in the following examples.

図３は、この発明の第３実施例の半導体装置の要部平面図である。この図は図２に相当する平面図である。
図２との違いは、第１、第２コンタクトホール１５、１６付近の第１、第２ソース電極配線１８、１９の幅Ｍ２を広くし、それ以外の箇所の幅Ｍ３を狭くすることで、図２のコンタクトホール間の間隔Ｌ１よりコンタクトホール間の間隔Ｌ２を短くした点である。これは、縦方向（図面では上下方向）に配置される幅広部２１同士の間隔を縮めることを意味する。コンタクトホール間の間隔Ｌ２を短くすることで、第１、第２ｎソース領域９、１１の拡散抵抗を低減することでオン抵抗を低減することができる。オン抵抗を低減することでオン電圧を低減することができる。例えば、０．６μｍルールで設計した場合、Ｌ２＝３．０μｍ程度となり、図２の場合のＬ１より３０％程度短くできる。 FIG. 3 is a plan view of an essential part of a semiconductor device according to a third embodiment of the present invention. This figure is a plan view corresponding to FIG.
The difference from FIG. 2 is that the width M2 of the first and second source electrode wirings 18 and 19 near the first and second contact holes 15 and 16 is increased, and the width M3 of the other portions is decreased. This is because the distance L2 between the contact holes is shorter than the distance L1 between the contact holes in FIG. This means that the interval between the wide portions 21 arranged in the vertical direction (vertical direction in the drawing) is reduced. By shortening the distance L2 between the contact holes, the on-resistance can be reduced by reducing the diffusion resistance of the first and second n source regions 9 and 11. By reducing the on-resistance, the on-voltage can be reduced. For example, when designing with the 0.6 μm rule, L2 = about 3.0 μm, which is about 30% shorter than L1 in the case of FIG.

また、コンタクトホール間の間隔Ｌ２を短くすることで、チャネル密度が増大し、オン電圧を低減することができる。
また、第１、第２ソース電極配線１８、１９の幅に狭い箇所があっても、例えば、アルミニウムなどの金属配線のためオン電圧の上昇は殆ど起こらない。 Further, by shortening the distance L2 between the contact holes, the channel density can be increased and the on-voltage can be reduced.
Further, even if the first and second source electrode wirings 18 and 19 are narrow in width, the ON voltage hardly increases because of metal wiring such as aluminum.

この発明の第１実施例の半導体装置の構成図であり、（ａ）は要部平面図、（ｂ）は（ａ）のＸ−Ｘ線で切断した要部断面図BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device of 1st Example of this invention, (a) is a principal part top view, (b) is principal part sectional drawing cut | disconnected by the XX line of (a). この発明の第２実施例の半導体装置の要部平面図The principal part top view of the semiconductor device of 2nd Example of this invention この発明の第３実施例の半導体装置の要部平面図The principal part top view of the semiconductor device of 3rd Example of this invention 従来の双方向トレンチ横型パワーＭＯＳＦＥＴの要部平面図Plan view of main part of conventional bidirectional trench lateral power MOSFET 図４のＤ部の詳細図Detailed view of part D in FIG. 図５のＸ−Ｘ線で切断した要部断面図Sectional drawing of the principal part cut | disconnected by the XX line of FIG. 図４〜図６で示した双方向トレンチ横型パワーＭＯＳＦＥＴの等価回路図Equivalent circuit diagram of the bidirectional trench lateral power MOSFET shown in FIGS.

符号の説明Explanation of symbols

１ ｐ基板
２ ｎウェル領域
３ トレンチ
４ ｎドレイン領域
５ ｐオフセット領域
６ ゲート絶縁膜
７ 第１ゲート電極
８ 第２ゲート電極
９ 第１ｎソース領域
１０ 第１ｐコンタクト領域
１１ 第２ｎソース領域
１２ 第２ｐコンタクト領域
１３ 絶縁膜
１４ 層間絶縁膜
１５ 第１コンタクトホール
１６ 第２コンタクトホール
１７ タングステン
１８ 第１ソース電極配線
１９ 第２ソース電極配線
２０ トレンチ残し箇所
２１ 幅広部
２２ 幅狭部
Ｔ１ デバイスピッチ
Ｍ１ ソース電極配線
Ｍ２ ソース電極配線（幅広部）
Ｍ３ ソース電極配線（幅狭部） 1 p substrate 2 n well region 3 trench 4 n drain region 5 p offset region 6 gate insulating film 7 first gate electrode 8 second gate electrode 9 first n source region 10 first p contact region 11 second n source region 12 second p contact Region 13 Insulating film 14 Interlayer insulating film 15 First contact hole 16 Second contact hole 17 Tungsten 18 First source electrode wiring 19 Second source electrode wiring 20 Trench remaining portion 21 Wide portion 22 Narrow portion T1 Device pitch M1 Source electrode wiring M2 Source electrode wiring (wide part)
M3 Source electrode wiring (narrow part)

Claims (4)

第１導電型の第１領域と、該第１領域の表面から内部に向かって形成した閉ループのトレンチと、該閉ループの内側と外側で分割され、前記第１領域の表面層に形成された第１トレンチ残り箇所および第２トレンチ残り箇所と、該トレンチの底部の前記第１領域に形成した第１導電型の第２領域と、前記第１トレンチ残り箇所および第２トレンチ残り箇所のそれぞれの表面層に形成した第２導電型の第３領域と、前記第１トレンチ残り箇所の前記第３領域の表面層に形成した前記トレンチの側壁と接する第１導電型の第４領域と、前記第１トレンチ残り箇所の前記第３領域の表面層に形成した第２導電型の第５領域と、前記第２トレンチ残り箇所の前記第３領域の表面層に形成した前記トレンチの側壁と接する第１導電型の第６領域、前記第２トレンチ残り箇所の前記第３領域の表面層に形成した前記トレンチの側壁と接する第２導電型の第７領域と、前記第１トレンチ残り箇所の側壁にゲート絶縁膜を介して形成された第１ゲート電極と、前記第２トレンチ残り箇所の側壁にゲート絶縁膜を介して形成された第２ゲート電極と、前記第１トレンチ残り箇所および前記第２トレンチ残り箇所上に形成され、前記第４領域上および前記第５領域上に第１開口部を有し、かつ前記第６領域上および前記第７領域上に第２開口部を有する層間絶縁膜と、前記第１開口部を介して前記第４領域および第５領域にそれぞれ接する第１電極配線と、前記第２開口部を介して前記第６領域および第７領域にそれぞれ接する第２電極配線と、を具備する双方向半導体装置において、
前記第１トレンチ残し箇所と前記第２トレンチ残し箇所が対向し、第１トレンチ残し箇所の平面形状が第１幅広部と第１幅狭部からなり、第２トレンチ残り箇所の平面形状が第２幅広部と第２幅狭部からなり、第１幅広部と第２幅狭部とが対向し、第１幅狭部と第２幅広部が対向し、前記第１電極配線が前記第１トレンチおよび前記第２トレンチを横切るように配置され、前記第２電極配線が前記第１トレンチおよび前記第２トレンチを横切るように配置されることを特徴とする双方向半導体装置。 A first region of the first conductivity type, a closed-loop trench formed inward from the surface of the first region, and a first layer formed on a surface layer of the first region, divided into an inner side and an outer side of the closed loop. 1 trench remaining location and 2nd trench remaining location, a second region of the first conductivity type formed in the first region at the bottom of the trench, and the respective surfaces of the first trench remaining location and the second trench remaining location A third region of a second conductivity type formed in a layer, a fourth region of a first conductivity type in contact with a sidewall of the trench formed in a surface layer of the third region in the remaining portion of the first trench, and the first region A fifth conductivity-type fifth region formed in the surface layer of the third region at the remaining portion of the trench, and a first conductivity in contact with the sidewall of the trench formed in the surface layer of the third region at the remaining portion of the second trench. The sixth region of the mold, the first A seventh region of the second conductivity type that is in contact with the sidewall of the trench formed in the surface layer of the third region at the remaining portion of the trench, and a first region that is formed on the sidewall of the remaining portion of the first trench through a gate insulating film. A gate electrode; a second gate electrode formed on a side wall of the second trench remaining portion via a gate insulating film; and the fourth region formed on the first trench remaining portion and the second trench remaining portion. An interlayer insulating film having a first opening on the upper region and the fifth region, and having a second opening on the sixth region and the seventh region; and the first insulating portion through the first opening. In a bidirectional semiconductor device comprising: a first electrode wiring in contact with each of the fourth region and the fifth region; and a second electrode wiring in contact with each of the sixth region and the seventh region through the second opening,
The first trench remaining portion and the second trench remaining portion are opposed to each other, the planar shape of the first trench remaining portion is composed of the first wide portion and the first narrow portion, and the planar shape of the second trench remaining portion is the second. It consists of a wide part and a second narrow part, the first wide part and the second narrow part face each other, the first narrow part and the second wide part face each other, and the first electrode wiring is in the first trench. The bidirectional semiconductor device is disposed so as to cross the second trench, and the second electrode wiring is disposed so as to cross the first trench and the second trench. 前記閉ループのトレンチの平面形状が直線のストライプ状となる箇所があり、前記第１電極配線および第２電極配線が前記第１トレンチおよび前記第２トレンチの前記直線箇所上をそれぞれ該直角に横切ることを特徴とする請求項１に記載する双方向半導体装置。 The closed loop trench has a portion where the planar shape is a linear stripe, and the first electrode wiring and the second electrode wiring cross the straight portions of the first trench and the second trench at right angles, respectively. The bidirectional semiconductor device according to claim 1. 前記第１幅広部の幅が徐々に狭まって前記第１幅狭部の幅になることを特徴とする請求項１または２に記載する双方向半導体装置。 3. The bidirectional semiconductor device according to claim 1, wherein a width of the first wide portion is gradually reduced to be a width of the first narrow portion. 4. 前記第１電極配線および第２電極配線の幅が前記第１幅広部上および前記第２幅広部上で広く、前記第１幅狭部上および第２幅狭部上で狭いことを特徴とする請求項１〜３のいずれか一項に記載する双方向半導体装置。 The widths of the first electrode wiring and the second electrode wiring are wide on the first wide portion and the second wide portion, and narrow on the first narrow portion and the second narrow portion. The bidirectional semiconductor device according to any one of claims 1 to 3.
JP2005326130A 2005-11-10 2005-11-10 Bidirectional semiconductor device Withdrawn JP2007134500A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005326130A JP2007134500A (en) 2005-11-10 2005-11-10 Bidirectional semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005326130A JP2007134500A (en) 2005-11-10 2005-11-10 Bidirectional semiconductor device

Publications (1)

Publication Number Publication Date
JP2007134500A true JP2007134500A (en) 2007-05-31

Family

ID=38155911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005326130A Withdrawn JP2007134500A (en) 2005-11-10 2005-11-10 Bidirectional semiconductor device

Country Status (1)

Country Link
JP (1) JP2007134500A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104701380A (en) * 2014-12-23 2015-06-10 电子科技大学 Dual-direction MOS-type device and manufacturing method thereof
CN107942615A (en) * 2017-12-22 2018-04-20 江苏宏微科技股份有限公司 A kind of IGBT or MOSFET domain structures used for electric vehicle
CN110164974A (en) * 2018-06-28 2019-08-23 华为技术有限公司 A kind of semiconductor devices and manufacturing method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0955506A (en) * 1995-02-24 1997-02-25 Motorola Inc Longitudinal type igfet structure that has low on resistanceand method
JPH11111976A (en) * 1997-09-30 1999-04-23 Toshiba Corp Semiconductor device
JP2002050760A (en) * 2000-08-03 2002-02-15 Sanyo Electric Co Ltd Insulating gate field effect transistor
JP2004274039A (en) * 2003-02-17 2004-09-30 Fuji Electric Device Technology Co Ltd Bilateral device, manufacturing method thereof, and semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0955506A (en) * 1995-02-24 1997-02-25 Motorola Inc Longitudinal type igfet structure that has low on resistanceand method
JPH11111976A (en) * 1997-09-30 1999-04-23 Toshiba Corp Semiconductor device
JP2002050760A (en) * 2000-08-03 2002-02-15 Sanyo Electric Co Ltd Insulating gate field effect transistor
JP2004274039A (en) * 2003-02-17 2004-09-30 Fuji Electric Device Technology Co Ltd Bilateral device, manufacturing method thereof, and semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104701380A (en) * 2014-12-23 2015-06-10 电子科技大学 Dual-direction MOS-type device and manufacturing method thereof
CN107942615A (en) * 2017-12-22 2018-04-20 江苏宏微科技股份有限公司 A kind of IGBT or MOSFET domain structures used for electric vehicle
CN107942615B (en) * 2017-12-22 2024-03-22 江苏宏微科技股份有限公司 IGBT or MOSFET layout structure for electric automobile
CN110164974A (en) * 2018-06-28 2019-08-23 华为技术有限公司 A kind of semiconductor devices and manufacturing method
CN110164974B (en) * 2018-06-28 2020-09-18 华为技术有限公司 Semiconductor device and manufacturing method

Similar Documents

Publication Publication Date Title
US8227854B2 (en) Semiconductor device having first and second resurf layers
JP4635067B2 (en) Semiconductor device and manufacturing method thereof
US8344457B2 (en) Insulated-gate semiconductor device with protection diode
US7936013B2 (en) Charge balance techniques for power devices
US20180097094A1 (en) Semiconductor device
JP5298488B2 (en) Semiconductor device
JP5297706B2 (en) Semiconductor device
US7329921B2 (en) Lateral semiconductor transistor
JP2015213141A (en) Vertical semiconductor device and method of manufacturing the same
US7816741B2 (en) Semiconductor device
JP2012064849A (en) Semiconductor device
JP2005333068A (en) Semiconductor device
US9190504B2 (en) Semiconductor device
CN103681785A (en) Semiconductor device
EP2643853B1 (en) Vertical dmos field-effect transistor and method of making the same
JP4966351B2 (en) Semiconductor device
US9704954B2 (en) Semiconductor device and a method for forming a semiconductor device
US20160079350A1 (en) Semiconductor device and manufacturing method thereof
US11018251B2 (en) Semiconductor device
JP2007134500A (en) Bidirectional semiconductor device
TWI714749B (en) Vertical sic mosfet
TW201714305A (en) High voltage semiconductor device and method for manufacturing the same
JP4756084B2 (en) Semiconductor device
JP4561747B2 (en) Semiconductor device
JP5309427B2 (en) Semiconductor device

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20080204

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080916

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20081216

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20090219

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20091112

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20110422

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110707

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110712

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20110912