JP2009021308A - Trench type mosfet and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a trench type MOSFET which can be made fast by shortening a delay time and enables the Chip area thereof to be reduced, and its manufacturing method. <P>SOLUTION: The trench type MOSFET 10 is formed by laminating a P type highly-doped drain section 1, a P type lightly-doped drain section 2, an N channel body section 3, and a P type source diffusion section 4 in this order and a trench gate electrode 6 is formed in a trench reaching the lightly-doped drain section 2 from a substrate surface. Here, a plurality of gate electrode lead out sections 7 and 17 for obtaining a potential from the trench gate electrode 6 are arrayed along the length of the trench gate electrode 6 almost at right angles to the trench gate electrode 6, so that parasitic resistance generated by the trench gate electrode 6 can be divided. The delay time is therefore shortened to make the trench type MOSFET fast and the Chip area is reducible. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a structure of a MOS type FET (field effect transistor) and a manufacturing method thereof, and more particularly to a trench type MOSFET useful for application to a power supply device such as a DC-DC converter and a high side load drive and the manufacturing thereof. It is about the method.

  The trench MOSFET is a vertical MOSFET having a source on the substrate surface, a drain on the bottom surface of the substrate, and a channel in a direction along the buried (trench) gate electrode so that a large current can flow in the vertical direction of the substrate. . Conventionally, trench MOSFETs have been widely used as electronic devices for power supply control because of their advantages of high structural efficiency and low on-resistance. There are roughly two types of patterns for forming the gate electrode of the trench MOSFET. One is a square type in which individual cells are surrounded by gate electrodes, and the other is a stripe type in which a plurality of gate electrodes are formed in parallel.

  FIG. 7 shows a Square Type trench-type MOSFET 60. FIG. 7A is a plan view of the MOSFET 60, and FIG. 7B is a cross-sectional view of the MOSFET 60 taken along the broken line AA. The MOSFET 60 includes a highly doped drain portion 61, a lightly doped drain portion 62, a channel body portion 63, a source diffusion portion 64, a gate insulating film 65, a trench gate electrode 66, a gate electrode lead portion 67, an element isolation insulating film 68, and a high concentration body. A portion 69 is provided. The trench gate electrode 66 is formed in a trench extending from the substrate surface to the lightly doped drain portion 62. As a result, a channel for flowing current in the vertical direction of the substrate is formed.

  Further, the square type MOSFET 60 has the advantage that the parasitic resistance generated by the trench gate electrode 66 can be reduced because the trench gate electrode 66 is formed in a mesh shape. On the other hand, in order to increase the density of the integrated circuit and reduce the on-resistance, it is essential to make the cell finer. However, the channel body portion 63 and the source diffusion portion are formed in each cell surrounded by the trench gate electrode 66. 64, it is difficult to reduce the on-resistance due to cell reduction.

  FIG. 8A shows a stripe type MOSFET 70 of a stripe type. The MOSFET 70 has a highly doped drain portion 71, a lightly doped drain portion 72, a channel body portion 73, a source diffusion portion 74, a gate insulating film 75, a trench gate electrode 76, a gate electrode leading portion 77, and an element isolation insulating film 78. In addition, a contact portion 79 is formed in the gate electrode lead portion 77. Thus, in the MOSFET 70, the trench gate electrode 76 is formed in a plurality of stripe patterns.

  Most of the current flowing in the MOSFET 70 flows in the channel formed at the interface between the channel body portion 73 and the gate insulating film 75, and the other portion is a wasteful region for the current. In order to flow as much current per unit area as possible when viewed from the substrate surface side, it is necessary to reduce the width of the trench gate electrode 76 (trench width) and the interval between the trench gate electrodes 76 (trench pitch).

  Here, since the current handled by the MOSFET 70 is a large value of several tens of amperes or more, the chip size is also a large one of several millimeters square or more, and the FET occupies most of the surface of the chip. Other than the FET portion, there are a circuit for controlling the FET, a temperature sensor, and the like, but their sizes are relatively small compared to the FET portion so as to be negligible. Therefore, the MOSFET 70 can reduce the distance between the trenches to the limit, in addition to being able to share the body region of a plurality of cells, so that it is effective in reducing the individual cells and can easily reduce the on-resistance. Have.

  On the other hand, the MOSFET 70 has the following disadvantages because each trench gate electrode 76 is longer than the square type. That is, the reduction of the trench width further increases the parasitic resistance per unit area generated by the trench gate electrode 76. As a result, degradation of transistor characteristics such as degradation of operation speed due to extension of the delay time occurs due to the effect of increasing the resistance of the trench gate electrode 76 itself, increasing the contact resistance, adding parasitic resistance, and the like.

  FIG. 8B is an equivalent circuit diagram of the MOSFET 70. In the MOSFET 70, since the trench gate electrode 76 is long, as indicated by a broken line, the trench gate electrode 76 is equal to a state in which a large number of resistors Res1 to ResN are connected in series, and has a large parasitic resistance per unit area.

  At present, a device in which the trench width is reduced to about 0.5 μm and the trench pitch to about 1.0 μm in the Stripe Type MOSFET is also in practical use. In such a device, it is difficult to form a contact directly with the gate electrode.

  On the other hand, in the MOSFET 70, it can be considered that the material of the trench gate electrode 76 is formed so as to cover the entire surface. However, in actuality, since it is necessary to secure a portion to contact the channel body portion 73 and the source diffusion portion 74, the material of the trench gate electrode 76 cannot be spread over the entire surface. Therefore, a technique for alternately forming trench portions and contact portions in a stripe pattern has been proposed.

  FIG. 9 is a plan view showing a general trench MOSFET 80 in which trench portions and contact portions are alternately formed in a stripe pattern. In MOSFET 80, trench portions 81 corresponding to gate electrodes and contact portions 82 corresponding to body portions or source diffusion portions are alternately formed.

  However, in the MOSFET 80, the potential of the gate electrode can be taken only from the outer periphery of the element portion. Therefore, in the central part of the element, there arises an inconvenience that the situation is the same as when the gate electrode is connected through a large resistance.

  Therefore, as shown in FIG. 10, it is conceivable to reduce the parasitic resistance of the trench gate electrode by dividing the trench gate electrode. FIG. 10A is a plan view of the MOSFET 90, and FIG. 10B is a cross-sectional view of the MOSFET 90.

  As shown in FIG. 10A, in the MOSFET 90, the resistance is reduced by cutting the pattern of the trench gate electrode 96 in some places and making contact with the metal. As shown in FIG. 10B, the trench gate electrode 96 is formed on the lightly doped drain part 92 formed on the highly doped drain part 91 via the gate insulating film 95 or the element isolation insulating film 98. Has been.

  However, in the MOSFET 90, the trench gate electrode 96 is formed on the field region, and further, the gate wiring needs to be formed in a region different from the active region. Therefore, since it is necessary to form the contact region of the trench gate electrode 96 at certain intervals, an increase in the chip area and an increase in cost occur.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to realize a trench MOSFET capable of shortening the chip time and reducing the delay time and the manufacturing method thereof. There is.

  In order to solve the above problems, a trench MOSFET according to the present invention includes a first conductivity type semiconductor substrate, an epitaxial layer provided on the semiconductor substrate and having a lower doping concentration than the semiconductor substrate, and the epitaxial layer. A channel layer of a second conductivity type opposite to the first conductivity type provided above, a source diffusion layer of the first conductivity type formed on a surface layer of the channel layer; A trench penetrating the channel layer from the surface of the source diffusion layer and reaching the epitaxial layer; a gate electrode provided in the trench through a gate insulating film; and provided on the gate electrode and the source diffusion layer A trench type MOSFET having a gate electrode lead portion which is a line-shaped pattern for taking a potential from the gate electrode, the length of the gate electrode being The longitudinal direction of direction and the gate electrode lead-out portions substantially perpendicular to each other, the gate electrode lead-out portion is characterized by being arrayed along a longitudinal direction of the gate electrode.

  Moreover, in order to solve the above-described problem, the method for manufacturing a trench MOSFET according to the present invention includes a first step of forming an epitaxial layer having a lower doping concentration than the semiconductor substrate on the semiconductor substrate of the first conductivity type. A second step of forming a channel layer of a second conductivity type opposite to the first conductivity type on the epitaxial layer, and the first conductivity on the surface layer of the channel layer. A third step of forming a source diffusion layer of the type, a fourth step of forming a trench that penetrates the channel layer from the surface of the source diffusion layer and reaches the epitaxial layer, and a gate insulating film is formed in the trench A fifth step; a sixth step of forming a gate electrode by embedding a gate electrode material in the trench; and applying a potential from the gate electrode on the gate electrode and the source diffusion layer. A seventh step of forming a gate electrode lead portion which is a line-shaped pattern, and the longitudinal direction of the gate electrode and the longitudinal direction of the gate electrode lead portion are substantially orthogonal to each other, and the gate electrode lead portion Are characterized by being arranged in a plurality along the longitudinal direction of the gate electrode.

  According to the above configuration, the first conductive type semiconductor substrate, the first conductive type epitaxial layer, the second conductive type channel layer, and the first conductive type source diffusion layer are stacked in this order, and the gate The electrode is formed in a trench reaching the epitaxial layer from the substrate surface, thereby forming a channel for flowing a current in the vertical direction of the substrate. Here, since a plurality of gate electrode lead portions for taking a potential from the gate electrode are arranged along the longitudinal direction of the gate electrode substantially orthogonal to the gate electrode, the parasitic resistance generated by the gate electrode can be divided. it can. Furthermore, since the gate electrode lead-out portion needs to be formed so as to enable contact between the source and the body, it is formed on the source diffusion layer in the MOS region. By performing such a structure and layout, the delay time can be shortened and the speed can be increased, and it is possible to realize a trench MOSFET capable of reducing the chip area and a manufacturing method thereof.

  In the trench MOSFET according to the present invention, when the gate electrode lead portion is made of a semiconductor material, it is preferable that silicide is formed on the surface of the gate electrode lead portion.

  According to the above configuration, the gate lead-out wiring resistance can be reduced.

  In the trench MOSFET according to the present invention, when the gate electrode lead portion is made of polysilicon, it is preferable that tungsten is laminated on the surface of the gate electrode lead portion.

  According to the above configuration, the resistance of the gate electrode lead portion can be further reduced.

  In the trench MOSFET according to the present invention, it is preferable that the gate electrode and the gate electrode lead portion are formed of the same material.

  In the method for manufacturing a trench MOSFET according to the present invention, the sixth step and the seventh step can be performed simultaneously because the material of the gate electrode and the material of the gate electrode lead portion are the same. preferable.

  According to said structure, formation of a gate electrode and formation of a gate electrode extraction part can be performed in the same process, and a gate electrode and a gate electrode extraction part are obtained integrally.

  As described above, the trench MOSFET according to the present invention is provided on the semiconductor substrate of the first conductivity type, the epitaxial layer provided on the semiconductor substrate and having a lower doping concentration than the semiconductor substrate, and on the epitaxial layer. A channel layer of a second conductivity type opposite to the first conductivity type formed, a source diffusion layer of the first conductivity type formed on a surface layer of the channel layer, and the source diffusion A trench which penetrates the channel layer from the surface of the layer and reaches the epitaxial layer, a gate electrode provided in the trench via a gate insulating film, and the gate provided on the gate electrode and the source diffusion layer A trench type MOSFET having a gate electrode lead portion which is a line pattern for taking a potential from an electrode, the longitudinal direction of the gate electrode and the gate electrode. Since the plurality of gate electrode lead portions are arranged along the longitudinal direction of the gate electrode, the delay time can be shortened and the speed can be increased. The chip area can be reduced.

  An embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1 shows a schematic structure of a trench MOSFET 10 according to the present embodiment. The MOSFET 10 is a trench MOSFET formed on a semiconductor substrate, and includes a P-type highly doped drain portion 1, a P-type lightly doped drain portion 2, an N-type channel body portion 3, a P-type source diffusion portion 4, A gate insulating film 5, a trench gate electrode 6, a gate electrode lead portion 7, an element isolation insulating film 8 and a contact portion 9 are provided. The heavily doped drain portion 1, the lightly doped drain portion 2, the channel body portion 3, and the source diffusion portion 4 may each have a conductivity type opposite to that described above.

  The highly doped drain portion 1 is formed by doping the back side of the semiconductor substrate. The lightly doped drain portion 2 is also called an epitaxial layer, and is formed so as to be in contact with the heavily doped drain portion 1. The source diffusion portion 4 is formed on the uppermost surface of the semiconductor substrate, and the channel body portion 3 is formed between the lightly doped drain portion 2 and the source diffusion portion 4.

The gate insulating film 5 is formed on the substrate surface and the inner wall of the trench penetrating from the substrate surface to the lightly doped drain portion 2. The trench gate electrode 6 is made of a semiconductor or metal, and a plurality of stripe patterns are formed so as to fill the trench. When the trench gate electrode 6 is a semiconductor, it may be polysilicon, and the doping concentration is 1 × 10 ^{19 to} 5 × 10 ¹⁹ [atoms / cm ³ ].

  The gate electrode lead-out portion 7 is formed at the end of the plurality of trench gate electrodes 6 in order to take a potential from the trench gate electrode 6 and is further connected to the contact portion 9. Further, at least one gate electrode lead portion 17 that is substantially orthogonal to the longitudinal direction of the trench gate electrode 6 is formed in a portion other than the end portion of the trench gate electrode 6. The gate electrode lead-out portion 17 is a line pattern for taking a potential from the trench gate electrode 6. Each gate electrode lead-out portion 17 is connected to the outside through a contact portion 19. An insulating film 15 is formed between the gate electrode lead portions 8 and 17 and the source diffusion portion 4. Similarly to the trench gate electrode 6, the gate electrode lead portions 7 and 17 are made of a semiconductor or metal.

  FIG. 2 is an equivalent circuit diagram of the MOSFET 10. In the MOSFET 10, the parasitic resistance generated by the trench gate electrode 6 can be divided by providing the gate electrode lead portions 7 and 17. That is, since the potential of the trench gate electrode 6 can be taken without passing through the parasitic resistances Res1 to ResN, the parasitic resistance generated by the trench gate electrode 6 can be reduced. Therefore, the delay time can be shortened and the speed can be increased.

  In the MOSFET 10, unlike the MOSFET 90 shown in FIG. 10, the gate electrode lead-out portion 17 is formed on the MOS region, and the gate wiring can be formed on the active region. Therefore, the chip area can be reduced and the cost can be reduced.

  The gate electrode lead portion 17 is preferably made of the same material as the trench gate electrode 6. In this case, since the step of embedding the material of the trench gate electrode 6 in the trench and the step of forming the gate electrode lead portions 7 and 17 can be performed simultaneously, the trench gate electrode 6 and the gate electrode lead portion 17 are integrated. Is obtained.

  In the case where the gate electrode lead-out portions 7 and 17 are made of a semiconductor, silicide may be formed on the surface of the gate electrode lead-out portions 7 and 17 and connected to the contact portions 9 and 19 through the silicide. Thereby, the gate lead-out wiring resistance can be reduced.

  Further, when the gate electrode lead portions 7 and 17 are made of polysilicon, tungsten may be formed on the surfaces of the gate electrode lead portions 7 and 17. Thereby, the resistance of the gate electrode lead-out portions 7 and 17 can be reduced.

  Hereinafter, a cross-sectional structure of the MOSFET 10 will be described.

  FIG. 3 shows a schematic structure of the MOSFET 10. The MOSFET 10 is the same as the MOSFET 10 shown in FIG. 1, and the MOSFET 10 is illustrated again in order to avoid complication of the drawing.

  FIG. 4 is a cross-sectional view of the MOSFET 10. 4A is a cross-sectional view taken along the gate electrode lead-out portion 17 (broken line BB) as shown in FIG. 3, and FIG. 4B is as shown in FIG. FIG. 5 is a cross-sectional view taken along the trench of the trench gate electrode 6 (broken line CC).

  As shown in FIG. 4A, since the trench gate electrode 6 and the gate electrode lead-out portion 17 are made of the same material, both can be formed integrally. Similarly, as shown in FIG. 4B, the gate electrode lead-out portion 7 is also preferably made of the same material as that of the trench gate electrode 6, whereby the trench gate electrode 6 and the gate electrode lead-out portions 7 and 17 are integrated. Can be formed.

  Hereinafter, based on FIG. 5, the manufacturing process of MOSFET10 is demonstrated in steps.

5A to 5G are cross-sectional views showing a schematic configuration of the trench MOSFET 10 at each stage of the manufacturing process. First, a silicon substrate having a thickness of about 500 μm to 650 μm is subjected to a resistivity of 0.01Ω. cm to 0.005 Ω. Highly doped drain portion 1 is formed by P-type doping so as to be in the range of cm. Further, a low-doped drain portion 2 (epitaxial layer) is formed on the highly doped drain portion 1 by epitaxially growing a P layer doped lower than the highly doped drain portion 1 (first step). Thereafter, phosphorus atoms are implanted and activated by heat treatment so that the doping concentration is in the range of 5 × 10 ^{16 to} 7 × 10 ¹⁷ [atoms / cm ³ ] on the silicon surface, so that the N-type channel body 3 is formed. Form (second step).

In this way, as shown in FIG. 5A, a highly doped drain portion 1, a P-type lightly doped drain portion 2, and an N-type channel body portion 3 are formed. The doping concentrations of the highly doped drain portion 1 and the lightly doped drain portion 2 are about 5 × 10 ¹⁵ [atoms / cm ³ ] and about 1 × 10 ¹⁹ [atoms / cm ³ ], respectively.

  Here, the thickness Xepi and the resistance value ρepi of the lightly doped drain portion 2 may be set according to the final electrical characteristics required for the MOSFET 10. In general, in order to reduce the on-resistance of the trench MOSFET, the resistance of the lightly doped drain should be lowered, but there is a trade-off relationship with the breakdown voltage. Note that the thickness of the highly doped drain portion 1 is reduced to about 100 μm to 150 μm by backside polishing after the MOSFET 10 is manufactured.

  Next, as shown in FIG. 5B, an element isolation insulating film 8 is formed on the channel body portion 3. Specifically, a nitride film having a thickness of about 100 nm to 200 nm is first formed on the wafer surface. Thereafter, a resist pattern is formed with a photoresist, and the nitride film is etched. After removing the resist pattern, an element isolation insulating film 8 having a thickness of about 500 nm to 700 nm is formed by an oxidation process.

Next, as shown in FIG. 5C, a P-type source diffusion portion 4 is formed on the channel body portion 3 (third step). Specifically, a resist pattern is formed with a photoresist, and a doping concentration in the range of 5 × 10 ^{19 to} 5 × 10 ²⁰ [atoms / cm ³ ] is formed on the surface of the N-type channel body 3. Boron atoms are implanted and activated by heat treatment to form the source diffusion portion 4.

  Next, as shown in FIG. 5D, a resist pattern is formed with a photoresist, silicon etching is performed, and the trench portion 11 that penetrates the source diffusion portion 4 and the channel body portion 3 and reaches the lightly doped drain portion 2 is formed. Is formed (fourth step).

  Next, as shown in FIG. 5E, the gate insulating film 5 is formed on the inner wall of the trench portion 11 by thermal oxidation or plasma oxidation (fifth step). An insulating film 15 is also formed on the source diffusion portion 4.

  Next, a semiconductor or metal is buried in the trench portion 11 to form the trench gate electrode 6 (sixth step). Further, a line pattern perpendicular to the trench gate electrode 6 is formed with a photoresist (seventh step), and the buried semiconductor or metal is etched back. Thereby, as shown in FIGS. 5F and 5G, the trench gate electrode 6 and the gate electrode lead portions 7 and 17 are formed. Here, when both the trench gate electrode 6 and the gate electrode lead-out portions 7 and 17 are made of the same material, the formation of the trench gate electrode 6 and the formation of the gate electrode lead-out portions 7 and 17 can be performed in the same process.

  Next, after the interlayer insulating film 12 is deposited on the wafer surface by the CVD method, a resist pattern is formed in the contact region with a photoresist, the interlayer insulating film 12 is etched, and the contact region is opened. Thereafter, a metal wiring layer 13 (Al or the like) is formed by sputtering, a resist pattern is formed with a photoresist, the metal wiring layer 13 is etched, and metal wirings such as a source and a gate are formed. Thereby, the MOSFET 10 is formed as shown in FIG.

Note that when the contact is formed on the channel body portion 3 to take the potential of the channel body portion 3 and the concentration of the channel body portion 3 is low, the contact made of metal and the channel body portion 3 are in Schottky. Contact (rectifying). Therefore, in order to make the semiconductor and the metal ohmic contact (non-rectifying property), it is necessary to increase the concentration of the region where the contact is formed. Therefore, a resist pattern is formed with a photoresist on the surface of the channel body portion 3, and arsenic atoms or phosphorus atoms are added so as to have a doping concentration in the range of 5 × 10 ^{19 to} 5 × 10 ²⁰ [atoms / cm ³ ]. The N-type high-concentration body portion 14 may be formed by being driven and activated by heat treatment.

  FIG. 6 is a cross-sectional view of the MOSFET 10 cut along a region other than the trench (broken line DD shown in FIG. 3) in the direction in which the trench gate electrode 6 extends. As shown in FIG. 6A, when the high-concentration body portion 14 is formed at substantially the same intervals as the gate electrode lead-out portion 7, the area of the high-concentration body portion 14 is increased, so that the effective gate width is reduced. The on-resistance increases due to. Further, as shown in FIG. 6B, when the high-concentration body portion 14 is formed only near both ends of the trench gate electrode 6, the resistance of the channel body portion 3 increases, resulting in a decrease in avalanche resistance and the like. . Therefore, it is necessary to form the high concentration body portion 14 in accordance with the purpose.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The trench type MOSFET of the present invention can be applied to applications such as switching.

It is a perspective view which shows the structure of the trench type MOSFET which concerns on this invention. It is an equivalent circuit diagram of the trench type MOSFET. It is a perspective view which shows the structure of the said trench type MOSFET. (A) is sectional drawing at the time of cutting the said trench type MOSFET along a gate electrode extraction part, (b) is sectional drawing at the time of cutting the said trench type MOSFET along the trench of a trench gate electrode It is. (A)-(h) is sectional drawing which shows schematic structure in each step of the manufacturing process of the said trench type MOSFET. (A) (b) is sectional drawing at the time of cutting the said trench type MOSFET along the area | regions other than a trench in the direction where a trench gate electrode is extended, (a) is substantially the same as the space | interval of a gate electrode drawer | drawing-out part. (B) is a configuration in which the high-concentration body part is formed only near both ends of the trench gate electrode. (A) is a top view which shows trench type MOSFET of Square Type, (b) is sectional drawing of the said trench type MOSFET. (A) is a perspective view which shows the structure of the trench type MOSFET of a general Stripe type, (b) is an equivalent circuit schematic of the said trench type MOSFET. It is a top view which shows the conventional trench type MOSFET. (A) is a top view which shows the other conventional trench type MOSFET, (b) is sectional drawing of the said trench type MOSFET.

Explanation of symbols

1 Highly doped drain (semiconductor substrate)
2 Low doped drain (epitaxial layer)
3 Channel body (channel layer)
4 Source diffusion part (source diffusion layer)
5 Gate insulating film 6 Trench gate electrode (gate electrode)
7, 17 Gate electrode lead-out part 10 MOSFET (trench MOSFET)
11 Trench (Trench)
15 Insulating film

Claims (6)

A semiconductor substrate of a first conductivity type, an epitaxial layer provided on the semiconductor substrate and having a lower doping concentration than the semiconductor substrate, and a conductivity type opposite to the first conductivity type provided on the epitaxial layer A channel layer of the second conductivity type, a source diffusion layer of the first conductivity type formed in the surface layer of the channel layer, and penetrates the channel layer from the surface of the source diffusion layer to the epitaxial layer. A trench that reaches the gate, a gate electrode provided in the trench through a gate insulating film, and a gate that is provided on the gate electrode and the source diffusion layer and has a linear pattern for taking a potential from the gate electrode A trench type MOSFET having an electrode lead portion,
A trench type characterized in that a longitudinal direction of the gate electrode and a longitudinal direction of the gate electrode lead portion are substantially orthogonal to each other, and a plurality of the gate electrode lead portions are arranged along the longitudinal direction of the gate electrode. MOSFET.   2. The trench MOSFET according to claim 1, wherein when the gate electrode lead portion is made of a semiconductor material, silicide is formed on the surface of the gate electrode lead portion.   2. The trench MOSFET according to claim 1, wherein when the gate electrode lead portion is made of polysilicon, tungsten is laminated on the surface of the gate electrode lead portion.   The trench MOSFET according to any one of claims 1 to 3, wherein the gate electrode and the gate electrode lead portion are formed of the same material. A first step of forming an epitaxial layer having a lower doping concentration than the semiconductor substrate on a semiconductor substrate of the first conductivity type;
A second step of forming a channel layer of a second conductivity type opposite to the first conductivity type on the epitaxial layer;
A third step of forming a source diffusion layer of the first conductivity type on the surface layer of the channel layer;
A fourth step of forming a trench that penetrates the channel layer from the surface of the source diffusion layer and reaches the epitaxial layer;
A fifth step of forming a gate insulating film in the trench;
A sixth step of forming a gate electrode by embedding a gate electrode material in the trench;
A seventh step of forming a gate electrode lead portion, which is a line pattern for taking a potential from the gate electrode, on the gate electrode and the source diffusion layer;
A trench type characterized in that a longitudinal direction of the gate electrode and a longitudinal direction of the gate electrode lead portion are substantially orthogonal to each other, and a plurality of the gate electrode lead portions are arranged along the longitudinal direction of the gate electrode. MOSFET manufacturing method.   6. The method of manufacturing a trench MOSFET according to claim 5, wherein the sixth step and the seventh step are performed simultaneously because the material of the gate electrode and the material of the gate electrode lead portion are the same. Method

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