JP2009176884A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of enhancing the tolerance as a whole, by enhancing the tolerance of a sensing part. <P>SOLUTION: This semiconductor device 1 comprises: a first main current region 11; a first main current control region 131 placed in a main face part of the first main current region; a second main current region 141 placed in a main face part of the first main current control region 131; a first transistor T1 of a main part 2 having the first main current region 11, the first main current control region and the second main current region 141; a third main current region 11 having a plane area smaller than that of the first main current region 11; a second main current control region 132 placed in a main face part of the third main current region and having a junction depth larger than that of the first main current control region 131; a fourth main current region 142 placed in a main face part of the second main current control region; and a second transistor T2 of a sensing part 3 having the third main current region 11, the second main current control region 132 and the fourth main current region 142. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a current sense function for detecting a current flowing through a transistor.

  Development of power semiconductor devices incorporating a current sensing function is underway. In this power semiconductor device, a transistor that performs on / off control of current, such as a power MOSFET (metal oxide semiconductor field effect transistor) and an insulated gate bipolar transistor (IGBT), is mounted as a main part. The current sensing function detects the current flowing through the transistor in the main part, and is mounted on the power semiconductor device together with the main part.

  For example, in the case of a power transistor, the transistor in the main part of the power semiconductor device includes an n-type drain region, a p-type body region, an n-type source region, a gate insulating film, and a gate electrode. The n-type drain region is constituted by an n-type semiconductor region on the n-type silicon single crystal substrate. The n-type semiconductor region is formed by implanting or diffusing an n-type impurity in a silicon single crystal layer grown on an n-type silicon single crystal substrate by, for example, an epitaxial growth method. The n-type semiconductor region is formed by implanting or diffusing n-type impurities into the main surface portion of the n-type silicon single crystal substrate. The p-type body region is formed by implanting or diffusing p-type impurities in the main surface portion of the n-type drain region. The n-type source region is formed by injecting or diffusing n-type impurities into the main surface portion of the p-type body region. The gate insulating film is disposed on the surface of the p-type body region, and the gate electrode is disposed on the gate insulating film.

  The transistor of the sense part is formed on the same n-type silicon single crystal substrate as the transistor of the main part with the same structure and the same manufacturing process. That is, the transistor in the sense section includes an n-type drain region, a p-type body region, an n-type source region, a gate insulating film, and a gate electrode, as in the main portion transistor, and is configured by a power transistor. ing.

  The n-type drain region of the main portion transistor and the n-type drain region of the sense portion transistor are shared, and both are electrically connected in parallel. Further, the gate electrode of the transistor in the main part and the gate electrode of the transistor in the sense part are electrically connected in parallel.

For example, the following Non-Patent Document 1 discloses the power transistor current sensing method.
“Current Sensing Power MOSFETs”. Semiconductor Components Industries, LLC, 2002. July, 2002-Rev. 5. Publication Order Number AND8093 / D, pp.1-10.

  However, in the above-described power semiconductor device, the following points have not been considered. When a current sensing function is mounted in a power semiconductor device, most of the main surface of the n-type silicon single crystal substrate (semiconductor chip) is constituted by a main portion that controls on / off of the main current. On the other hand, the sense portion that detects the current of the transistor in the main portion is configured in a partial region of the main surface of the n-type silicon single crystal substrate. For example, the area of the sense portion is about 1000, which is 1 with respect to the area (planar area) of the main portion. Since the transistors in the main part and the transistors in the sense part are configured in the same structure and in the same manufacturing process (same manufacturing condition), the breakdown voltage of both is the same, but the area of the sense part is smaller than that of the main part. Since it is extremely small, avalanche breakdown is likely to occur in the transistor of the sense portion. For this reason, the withstand capability of the transistor in the sense section is weak, and as a result, the overall withstand capability of the power semiconductor device is weakened.

  The present invention has been made to solve the above problems. Accordingly, the present invention is to provide a semiconductor device capable of increasing the tolerance of the sense portion and improving the tolerance of the entire device.

  In order to solve the above-described problem, a first feature according to an embodiment of the present invention is that, in a semiconductor device, a first main current region having a first conductivity type and a main surface portion of the first main current region. And a first main current control region having a second conductivity type opposite to the first conductivity type, and a main surface portion of the first main current control region. A second main current region having a type, a first transistor having a first main current region, a first main current control region, and a second main current region, and a first conductivity type, A third main current region having a smaller plane area than the plane area of the first main current region, and a main surface portion of the third main current region, having a second conductivity type, A second main current control region having a junction depth deeper than the junction depth of the current control region, and a main surface portion of the second main current control region; It has the fourth main current region having a conductivity type, the third main current region, and a second transistor having a second main current control region and the fourth main current region.

  A second feature according to the embodiment of the present invention is that a first main current region having a first conductivity type, a first main current region disposed on the first main current region and opposite to the first conductivity type. A first main current control region having a conductivity type of 2 and a second main current region having a first conductivity type disposed on the first main current control region and performing switching control of the main current A main portion having a first transistor, a third main current region having a first conductivity type, and a first main current control having a second conductivity type disposed on the third main current region A second main current control region having a junction depth deeper than the junction depth of the region, and a fourth main current region having a first conductivity type disposed on the second main current control region. And a sense unit having a second transistor for detecting the current of the first transistor.

  In the semiconductor device according to the first feature or the second feature, a first gate electrode disposed via a first gate insulating film along the first main current control region of the first transistor, And a second gate electrode disposed through a second gate insulating film along the second main current control region of the second transistor, and the second main electrode and the second main current region of the first transistor It is preferable that the third main current region of the transistor is electrically connected, and the first gate electrode and the second gate electrode are electrically connected.

  In the semiconductor device according to the first feature or the second feature, the second main current control region is a main current path through which a main current flows between the third main current region and the fourth main current region. And a contact region portion to which the upper layer electrode is connected, which is a region different from the main current path portion, and the junction depth of the contact region portion of the second main current control region is It is preferable that the first main current control region be deeper than the junction depth. In the semiconductor device according to the first feature or the second feature, the junction depth of the main current path portion of the second main current control region is equal to the junction depth of the first main current control region. Is preferred.

  In the semiconductor device according to the first feature or the second feature, the entire main surface portion of the first main current region has the same conductivity type as the first main current region and the first main current. A first semiconductor region having a higher impurity density than that of the region is provided, and the main surface portion of the third main current region has the first main region in addition to the contact region portion between the second main current control region and the upper layer electrode. Preferably, a second semiconductor region having the same conductivity type as that of the third main current region and having a higher impurity density than the third main current region is provided.

  Furthermore, in the semiconductor device according to the first feature or the second feature, it is preferable that a resistor of 800 ohm or less is electrically connected to the fourth main current region of the second transistor.

  According to the present invention, it is possible to provide a semiconductor device capable of increasing the tolerance of the sense portion and improving the tolerance of the entire device.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic and different from actual ones. In addition, there may be a case where the dimensional relationships and ratios are different between the drawings.

  Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is to arrange the components and the like as follows. Not specific. The technical idea of the present invention can be variously modified within the scope of the claims.

(First embodiment)
The first embodiment of the present invention describes an example in which the present invention is applied to a power semiconductor device equipped with a power transistor and a current sense function.

[Circuit Configuration of Semiconductor Device]
As shown in FIG. 2, the semiconductor device 1 according to the first embodiment includes a main unit 2 having a first transistor T <b> 1 that performs on / off control of a main current, and a first transistor of the main unit 2. And a sense unit 3 having a second transistor T2 for detecting a main current flowing in T1. The main part 2 and the sense part 3 are mounted on the same substrate (semiconductor chip). The sense unit 3 constructs a current sense function, and the semiconductor device 1 according to the first embodiment incorporates a current sense function.

  In the first embodiment, a power MISFET (metal insulator field effect transistor) is used for the first transistor T1 of the main section 2. Here, the MISFET means a transistor in which an insulator is used for the gate insulating film, and is used in the meaning including a MOSFET (metal oxide field effect transistor). One first main current region (here, drain region) of the first transistor T1 is electrically connected to the drain terminal D, and the other second main current region (here, source region) is electrically connected. It is electrically connected to the source terminal S1. The source terminal S1 is a Kelvin source terminal. The gate electrode is electrically connected to the gate terminal G.

  The second transistor T2 of the sense unit 3 includes a power MISFET having a second main current control region (132) having a junction depth deeper than the first main current control region (131) of the first transistor T1. Is used. One third main current region (here, drain region) of the second transistor T2 is electrically connected to the first main current region of the first transistor T1, and the same (shared) drain. It is electrically connected to the terminal D. The other fourth main current region (here, the source region) is electrically connected to the source terminal S2. The source terminal S2 is a source terminal of the sense unit 3. The gate electrode of the second transistor T2 is electrically connected to the gate electrode of the first transistor T1, and is electrically connected to the same (shared) gate terminal G.

  An external resistor R as an external element of the semiconductor device 1 is electrically connected in series to the source terminal S2. In the first embodiment, the external resistor R has a resistance value of 800 ohms or less, and an external resistor R having a resistance value of 100 ohms is used here.

[Chip layout of semiconductor devices]
As shown in FIG. 3, the substrate (semiconductor chip) 10 in the semiconductor device 1 according to the first embodiment has a planar rectangular shape. The substrate 10 is obtained by manufacturing a plurality of identical circuit patterns on a semiconductor wafer in the manufacturing process of the semiconductor device 1 and cutting out each circuit pattern by a dicing process.

  The main portion 2 is disposed on most of the main surface of the substrate 10 and is sufficiently smaller than the main portion 2, and a part of the pole on the main surface of the substrate 10 here is a part of the pole on the left side in FIG. A sense unit 3 is provided. In the first embodiment, the occupied area of the main portion 2 on the main surface of the substrate 10 (the total occupied area of the plurality of first transistors T1) and the occupied area of the sense portion 3 (the plurality of second transistors). The ratio of the total occupied area of T2 is, for example, about 1000 to 1. Here, the main surface of the substrate 10 is the surface (the upper surface in FIG. 1) of the substrate 10 on which the gate insulating films and gate electrodes of the first transistor T1 and the second transistor T2 are formed. And is used to mean the primary surface on which the transistor is built.

  In the main portion 2, a plurality of first transistors T1 share the first main current region, the second main current region, and the gate electrode, respectively, and are electrically connected in parallel. Similarly, in the sense unit 3, a plurality of second transistors T2 share the third main current region, the fourth main current region, and the gate electrode, respectively, and are electrically connected in parallel. ing.

[Cross-sectional structure of semiconductor device]
As shown in FIG. 1, the semiconductor device 1 according to the first embodiment includes a plurality of first transistors T <b> 1 that construct a main unit 2 on a main surface of a substrate 10, and a plurality that constructs a sense unit 3. Second transistors T2. As the substrate 10, an n-type silicon single crystal substrate is used in the first embodiment. An n-type semiconductor region 11 is disposed on the main surface of the substrate 10. In the n-type semiconductor region 11, a silicon single crystal layer is grown on the entire main surface of the substrate 10 on the main surface of the substrate 10 using an epitaxial growth method, and an implantation method or a diffusion method is applied to the entire surface of the silicon single crystal layer. It is formed by introducing n-type impurities. The n-type semiconductor region 11 is formed by introducing an n-type impurity into the main surface portion (surface portion) of the substrate 10 using an implantation method or a diffusion method. For example, the n-type semiconductor region 11 is set to an impurity density of 1 × 10 ¹⁴ atoms / cm ³ −3 × 10 ¹⁴ atoms / cm ³ .

  As shown on the left side in FIG. 1, the first transistor T1 of the main portion 2 is disposed on the first main current region having the first conductivity type and the main surface portion of the first main current region, A first main current control region having a second conductivity type opposite to the first conductivity type, and a second main surface region disposed on a main surface portion of the first main current control region and having the first conductivity type Main current region, and a first gate electrode 161 disposed via a first gate insulating film 151 along the first main current control region. Here, in the first embodiment, the first conductivity type is n-type, and the second conductivity type is p-type.

The first main current region of the first transistor T1 is an n-type drain region, and is mainly composed of an n-type semiconductor region 11. The main portion 2 includes a region where the first main current control region is disposed, and the n-type semiconductor region 11, that is, the main surface portion of the first main current region, has the same conductivity as the first main current region. In the mold, a first semiconductor region (surface n layer) 121 having an impurity density higher than that of the first main current region is provided. In other words, the first semiconductor region 121 is disposed in the entire main surface portion of the n-type semiconductor region 11 in the main portion 2. The first semiconductor region 121 is disposed for the purpose of reducing the resistance value of the path of the main current (current flowing between the source region and the drain region) in the first main current region. For example, the first semiconductor region 121 is set to an impurity density of 1 × 10 ¹⁶ atoms / cm ³ −3 × 10 ¹⁶ atoms / cm ³ .

The first main current control region of the first transistor T1 is a p-type body region and is configured by a p-type semiconductor region 131. The p-type semiconductor region 131 is set to an impurity density of, for example, 1 × 10 ¹⁷ atoms / cm ³ −3 × 10 ¹⁷ atoms / cm ³ . The region where the first main current control region is disposed, more specifically, the main current path portion between the first main current region and the second main current region of the first main current control region and the upper layer In the contact region portion (here, the contact region of the first main current control region) to which the electrode (18) is electrically connected, impurities of opposite conductivity type for forming the first semiconductor region 121 are present. Introduced (implanted or diffused). The main current path portion and the contact region portion of the first main current control region are set to be p-type by canceling the n-type of the first semiconductor region 121.

The second main current region is an n-type source region and is composed of an n-type semiconductor region 14. For example, the n-type semiconductor region 14 is set to an impurity density of 1 × 10 ²⁰ atoms / cm ³ −3 × 10 ²⁰ atoms / cm ³ .

  The gate insulating film 151 of the first transistor T1 is at least a first main current control, except for a contact region portion (here, a contact region of a first main current control region and a second main electrode region) described later. The region (p-type semiconductor region 131) is disposed on the surface between the first main current region and the second main current region (along the first main current control region). As the gate insulating film 151, for example, a single layer film of a silicon oxide film formed by using a thermal oxidation method can be practically used. As the gate insulating film 151, a single layer film of a silicon nitride film or a composite film in which a silicon oxide film and a silicon nitride film are combined can be used. For the gate electrode 161, for example, a silicon polycrystalline film formed by using the CVD method can be used practically. For example, an n-type impurity for reducing the resistance value is implanted or diffused into the silicon polycrystalline film. Has been introduced.

  In the main portion 2, the first transistor T1 does not show its planar structure, but the gate electrode 161 extends from the upper side to the lower side of the substrate 10 shown in FIG. It is arranged. The first main current control region and the second main current region of the first transistor T1 extend in the same direction as the extension direction of the gate electrode 161 between the adjacent gate electrodes 161, and the arrangement interval of the gate electrodes 161 Are arranged at regular intervals corresponding to Here, the first transistor T1 has a planar stripe shape. Note that the planar shape of the first transistor T1 is not necessarily limited to such a shape.

  An interlayer insulating film 17 is disposed on the first transistor T1 in the main portion 2. For example, a phosphorus silicate glass (PSG) film can be used practically for the interlayer insulating film 17. The interlayer insulating film 17 is formed on the second main current region of the first transistor T1 and on the region opposite to the main current path portion of the first main current control region with the second main current region interposed. Is provided with a contact opening 17H. An electrode 18 is disposed on the interlayer insulating film 17, and this electrode 18 is electrically connected to the first main current control region and the second main current region through a contact opening 17H disposed in the interlayer insulating film 17. Has been. The electrode 18 is a source electrode (or source wiring) in the first embodiment. For the electrode 18, for example, an Al alloy (for example, Al—Si, Al—Cu) in which at least one of silicon (Si) having alloy spike resistance and copper (Cu) having migration resistance is added to aluminum (Al). , Al-Cu-Si, etc.) can be used practically. The electrode 18 may be a composite film in which a barrier metal such as titanium (Ti) or titanium nitride (TiN) and aluminum are laminated.

  As shown on the right side in FIG. 1, the first transistor T2 of the sense unit 3 is disposed on the third main current region having the first conductivity type and the main surface portion of the third main current region. A second main current control region having a second conductivity type opposite to the first conductivity type; and a fourth main current control region disposed on a main surface portion of the second main current control region and having the first conductivity type. Main current region, and a first gate electrode 162 disposed via a second gate insulating film 152 along the second main current control region. Here, like the first transistor T1, the first conductivity type is n-type, and the second conductivity type is p-type.

The third main current region of the second transistor T2 is an n-type drain region, and is mainly composed of the n-type semiconductor region 11 in the same layer as the n-type semiconductor region 11 of the first transistor T1. That is, the n-type semiconductor region 11 is shared by the first transistor T1 and the second transistor T2. In the sense portion 3, in addition to the contact region portion 1322 of the second main current control region, the main surface portion of the main current path portion 1321 of the second main current control region and the n-type semiconductor region 11, that is, the third main current A second semiconductor region (surface n layer) 122 having the same conductivity type as that of the third main current region and having a higher impurity density than that of the third main current region is disposed on the main surface portion of the region. Has been. The second semiconductor region 122 is disposed for the purpose of reducing the resistance value of the path of the main current (current flowing between the source region and the drain region) in the third main current region. Similar to the first semiconductor region 121, the second semiconductor region 122 is set to an impurity density of, for example, 1 × 10 ¹⁶ atoms / cm ³ −3 × 10 ¹⁶ atoms / cm ³ , and in the first embodiment, The first semiconductor region 121 and the first semiconductor region 121 are manufactured at the same time and under the same manufacturing conditions. Here, the contact region portion 1322 is used to mean a connection portion with the electrode 18 in the second main current control region (p-type semiconductor region 132).

  In the first embodiment, the main current path portion (p-type semiconductor region) 1321 of the second main current control region and the fourth main current region (n-type semiconductor region 142) are provided. The second semiconductor region 122 is disposed in the same region as the region where is disposed. This is because the electrical characteristics of the second transistor T2 as a transistor are equal to the electrical characteristics of the first transistor T1.

The second main current control region of the second transistor T2 is a p-type body region, and is constituted by a p-type semiconductor region 132. The p-type semiconductor region 132 is set to an impurity density of, for example, 1 × 10 ¹⁷ atoms / cm ³ −3 × 10 ¹⁷ atoms / cm ³ , and in the first embodiment, the p-type semiconductor in the first main current control region The region 131 is manufactured simultaneously and under the same manufacturing conditions by the same manufacturing process.

The region where the second main current control region is disposed, specifically, the main current path portion 1321 between the third main current region and the fourth main current region of the second main current control region is the first The n-type of the second semiconductor region 122 is canceled and set to the p-type. That is, in the second transistor T2, the impurity density and the junction depth (x _j ) of the main current path portion 1321 of the second main current control region (p-type semiconductor region 132) are the same as those of the first transistor T1. It is set to be equal to the impurity density and junction depth of the main current path portion of the main current control region (p-type semiconductor region 131).

On the other hand, since the second semiconductor region 122 is not provided in the contact region portion 1322 of the second main current control region, it is not necessary to cancel the n-type of the second semiconductor region 122 and set it to p-type. The p-type impurity in contact region portion 1322 is deeply diffused in the depth direction from the main surface of the third main current region (n-type semiconductor region). That is, the junction depth (x _j ) of the contact region portion 1322 of the second main current control region, in other words, the junction depth immediately below the contact region of the second main current control region is the junction depth of the main current path 1321. The junction depth of the first main current control region is set deeper than the first main current control region.

The fourth main current region is an n-type source region and is composed of an n-type semiconductor region 142. The n-type semiconductor region 14 is set to an impurity density of 1 × 10 ²⁰ atoms / cm ³ −3 × 10 ²⁰ atoms / cm ³ , for example, and in the first embodiment, the n-type semiconductor region of the second main current region 141 are manufactured at the same time and under the same manufacturing conditions.

  The gate insulating film 152 of the second transistor T2 is at least a second main current control except for a contact region portion described later (here, a contact region of a second main current control region and a fourth main electrode region). The region (p-type semiconductor region 132) is disposed on the surface between the third main current region and the fourth main current region. The gate insulating film 152 is manufactured simultaneously and under the same manufacturing conditions by the same manufacturing process as the gate insulating film 151 of the first transistor T1. The gate electrode 162 is manufactured at the same time and under the same manufacturing conditions by the same manufacturing process as the gate electrode 161 of the first transistor T1.

  In the sense part 3, like the first transistor T1 of the main part 2, the second transistor T2 does not show its planar structure, but the gate electrode 162 from the upper side to the lower side of the substrate 10 shown in FIG. And a plurality of them are arranged at regular intervals. The second main current control region and the fourth main current region of the second transistor T2 extend in the same direction as the extending direction of the gate electrode 162 between the adjacent gate electrodes 162, and the arrangement interval of the gate electrodes 162 Are arranged at regular intervals corresponding to For example, like the first transistor T1, the second transistor T2 has a planar stripe shape. Note that the planar shape of the second transistor T2 is not necessarily limited to such a shape.

  An interlayer insulating film 17 is disposed on the second transistor T2 of the sense unit 3. This interlayer insulating film 17 is the same layer as the interlayer insulating film 17 on the main portion 2. On the fourth main current region of the second transistor T2 and on the region opposite to the main current path portion 1321 of the second main current control region with the fourth main current region interposed, the interlayer insulating film 17 is provided with a contact opening 17H. An electrode 18 is disposed on the interlayer insulating film 17, and the electrode 18 is electrically connected to the second main current control region and the fourth main current region through a contact opening 17H disposed in the interlayer insulating film 17. Has been. The electrode 18 is a source electrode (or source wiring) in the first embodiment, and is the same layer as the electrode 18 on the main unit 2.

  In FIG. 1, a separation region (separation buffer region) 4 is disposed at the center. The isolation region 4 is disposed on the main surface portion of the n-type semiconductor region 11 between the main portion 2 and the sense portion 3, and is constituted by a p-type semiconductor region 133. The p-type semiconductor region 133 includes a p-type semiconductor region 131 that is a first main current control region of the first transistor T1, and a p-type semiconductor region 132 that is a second main current control region of the second transistor T2. They are formed under the same manufacturing conditions by the same manufacturing process.

  A p-type semiconductor region 131 that is a first main current control region of the first transistor T1, and a p-type semiconductor region 131 that is a first main current control region of another first transistor T1 adjacent to the first transistor T1. When the separation distance between the second transistor T2 and the p-type semiconductor region 132 that is the second main current control region of the adjacent second transistor T2 is sufficiently large, the p-type semiconductor region 133 of the isolation region 4 is not necessarily Not necessary. The sufficiently large separation distance means that the contact region is formed between the second main current region of the first transistor T1 and the electrode 18 and between the fourth main current region of the second transistor T2 and the electrode 18. It has a width that can be formed.

[Features of semiconductor devices]
In the semiconductor device 1 according to the first embodiment configured as described above, the junction depth of the second main current control region of the second transistor T2 of the sense portion 3, specifically, the contact region portion 1322, is determined. This is deeper than the junction depth of the first main current control region of the first transistor T1 of the main portion 2. As shown by a one-dot chain line in FIG. 1, from the pn junction interface between the first main current control region (p-type semiconductor region 131) and the first main current region (n-type semiconductor region 11) of the first transistor T1. For the contour shape of the depletion layer 21 extending to the first main current region side, the second main current control region (p-type semiconductor region 132) and the third main current region (n-type semiconductor) of the second transistor T2. The contour shape of the depletion layer 22 extending from the pn junction interface with the region 11) toward the third main current region can be made gentle. As a result, avalanche breakdown at the pn junction between the third main current region and the second main current control region of the second transistor T2 of the sense unit 3 can be suppressed, and the withstand capability can be increased.

  For example, in the semiconductor device 1 according to the first embodiment, the withstand capability of the second transistor T2 of the sense unit 3 can be increased approximately twice. In addition, the breakdown voltage of the second transistor T2 was increased by about 20 V-30 V, and the breakdown voltage of the second transistor T2 was higher than the breakdown voltage of the first transistor T1.

  Furthermore, in the semiconductor device 1 according to the first embodiment, the first semiconductor region 121 is disposed in the main current path portion of the first main current control region of the first transistor T1 of the main portion 2. At the same time, the second semiconductor region 122 is disposed in the main current path portion 1321 of the second main current control region of the second transistor T2 of the sense portion 3 under the same manufacturing conditions. Therefore, the electrical characteristics of the first transistor T1 of the main section 2 and the electrical characteristics of the second transistor T2 of the sense section 3 can be set to be equal.

[Method for Manufacturing Semiconductor Device]
Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to FIGS.

  First, a substrate 10 made of an n-type silicon single crystal substrate is prepared (see FIG. 4). As shown in FIG. 4, an n-type semiconductor region 11 is formed on or on the main surface of the substrate 10. In the main part 2, the n-type semiconductor region 11 is used as a first main current region of the first transistor T1. In the sense unit 3, the n-type semiconductor region 11 is used as a third main current region of the second transistor T2.

  As shown in FIG. 5, the gate insulating film 151 is formed in the main portion 2 and the gate insulating film 152 is formed in the sense portion 3 on the main surface of the n-type semiconductor region 11. Here, each of the gate insulating films 151 and 152 is formed by the same manufacturing process under the same manufacturing conditions.

  Subsequently, a mask 30 is formed on the gate insulating film 152 in a region where the contact region portion (1322) of the second main current control region of the second transistor T2 of the sense portion 3 is formed (see FIG. 6). The mask 30 is formed in a region where the second semiconductor region (surface n layer) 122 is not formed in the sense portion 3. Here, the mask 30 is used as an ion-resistant implantation mask because n-type impurities are implanted using an ion implantation method. For the mask 30, for example, a photoresist film formed by using a photolithography technique can be practically used. When the n-type impurities forming the first semiconductor region (surface n layer) 121 and the second semiconductor region 122 are originally implanted using a mask, a manufacturing process is added only by changing the mask pattern. The mask 30 can be formed without doing so. If n-type impurities are not implanted using a mask, a mask 30 is formed by adding a manufacturing process.

  As shown in FIG. 6, n-type impurities are implanted into the main part 2, the sense part 3, and the isolation region 4. An ion implantation method is used for n-type impurity implantation. The n-type impurity is activated after the implantation or in a later step, and the first semiconductor region 121 is formed in the main portion 2 (and the isolation region 4), and the second semiconductor region 122 is formed in the sense portion 3. The The second semiconductor region 122 is not formed in the main surface portion of the n-type semiconductor region 11 immediately below the mask 30 because the n-type impurity is prevented from being implanted using the mask 30 when the n-type impurity is implanted. This non-injection region corresponds to the contact region portion (1322) of the second main current control region of the second transistor T2. Thereafter, the mask 30 is removed.

  As shown in FIG. 7, the gate electrode 161 is formed on the gate insulating film 151 in the main portion 2, and the gate electrode 162 is formed on the gate insulating film 152 in the sense portion 3. Each of the gate electrodes 161 and 162 is formed under the same manufacturing conditions by the same manufacturing process.

  As shown in FIG. 8, a p-type semiconductor region 131 is formed on the main surface portion of the n-type semiconductor region 11 in the main portion 2, and a p-type semiconductor region 132 is formed on the main surface portion of the n-type semiconductor region 11 in the sense portion 3. The Each of the p-type semiconductor regions 131 and 132 is formed under the same manufacturing conditions by the same manufacturing process. The p-type semiconductor region 131 uses the gate electrode 161 as an impurity-resistant implantation mask, the p-type semiconductor region 132 uses the gate electrode 162 as an impurity-resistant implantation mask, and p-type impurities are implanted by ion implantation. Semiconductor regions 131 and 132 can be formed.

  In the main part 2, the p-type semiconductor region 131 is used as a first main current control region of the first transistor T1. In the sense unit 3, the p-type semiconductor region 132 is used as a second main current control region of the second transistor T2. In the sense unit 3, the second main current control region is formed in a p-type by canceling the n-type of the second semiconductor region 122 in the region where the second semiconductor region 122 is formed. And a contact region 1322 formed in a p-type by canceling the n-type of the n-type semiconductor region 11 in a region where the second semiconductor region 122 is not formed. Since the contact region portion 1322 is formed in the n-type semiconductor region 11 having an impurity density lower than that of the second semiconductor region 122, the junction depth of the contact region portion 1322 is the junction depth of the main current path 1321. It is deeper than the depth and deeper than the junction depth of the first main current control region.

  As shown in FIG. 9, an n-type semiconductor region 141 is formed on the main surface portion of the first main current control region in the main portion 2, and an n-type semiconductor region is formed on the main surface portion of the second main current control region in the sense portion 3. 142 is formed. Each of n-type semiconductor regions 141 and 142 is formed under the same manufacturing conditions by the same manufacturing process. The n-type semiconductor region 141 uses the gate electrode 161 as an impurity-resistant implantation mask, the n-type semiconductor region 142 uses the gate electrode 162 as an impurity-resistant implantation mask, and further uses a mask formed by a photolithography technique (not shown). The n-type semiconductor regions 141 and 142 can be formed by implanting n-type impurities by ion implantation.

  Here, the n-type semiconductor regions 141 and 142 can be formed by a method other than a method using a mask formed by a photolithography technique. For example, after each of the gate electrodes 161 and 162 is formed, the n-type semiconductor region 141 is formed in the entire region between the gate electrodes 161 adjacent to the main surface portion of the p-type semiconductor region 131 using the gate electrode 161 as a mask, and the gate Using the electrode 162 as a mask, an n-type semiconductor region 142 is formed in the entire area between the gate electrodes 162 adjacent to the main surface portion of the p-type semiconductor region 132 (see FIGS. 8 and 9). Thereafter, an interlayer insulating film 17 is formed, and a contact opening 17H is formed in the interlayer insulating film 17 (see FIG. 1). Subsequently, in the main portion 2, the n-type semiconductor region 141 exposed from the contact opening 17H is removed by etching until the p-type semiconductor region 131 is exposed, and the n-type semiconductor region 141 is subdivided. Similarly, in the sense portion 3, the n-type semiconductor region 142 exposed from the contact opening 17H is removed by etching until the p-type semiconductor region 132 is exposed, so that the n-type semiconductor region 142 is subdivided. The contact opening 17H is used as a mask for patterning, and the n-type semiconductor region 141 is within a range deeper than the junction depth of the n-type semiconductor regions 141 and 142 and shallower than the junction depth of the p-type semiconductor regions 131 and 132. And 142 are patterned.

  In the main part 2, the n-type semiconductor region 141 is used as a second main current region of the first transistor T1. At the stage where the n-type semiconductor region 141 is formed, the first transistor T1 of the main portion 2 can be completed. In the sense unit 3, the n-type semiconductor region 142 is used as a fourth main current region of the second transistor T2. At the stage where the n-type semiconductor region 142 is formed, the second transistor T2 of the sense unit 3 can be completed.

  Next, an interlayer insulating film 17 covering at least the main portion 2 and the sense portion 3 is formed, and a contact opening 17H is formed in the interlayer insulating film 17 (see FIG. 1). Then, an electrode 18 that is electrically connected through the contact opening 17H is formed on the interlayer insulating film 17, and the semiconductor device 1 shown in FIG. 1 can be completed.

  As described above, in the semiconductor device 1 according to the first embodiment, the tolerance of the sense unit 2 can be increased and the tolerance can be improved as a whole device.

  Further, in the method of manufacturing the semiconductor device 1 according to the first embodiment, the main part 2 and the sense part 3 can be manufactured under the same manufacturing conditions by the same manufacturing process, so that the manufacturing becomes easy.

(Second Embodiment)
In the second embodiment of the present invention, an example in which the present invention is applied to a power semiconductor device equipped with an IGBT and equipped with a current sensing function will be described.

  The semiconductor device 1 according to the second embodiment is basically configured by the same cross-sectional structure as the semiconductor device 1 according to the first embodiment shown in FIG. In the semiconductor device 1 shown in FIG. 1, the first transistor T1 of the main unit 2 is configured by IGBT, and the second transistor T2 of the sense unit 3 is configured by IGBT.

  In the first transistor T1, the first main current region (n-type semiconductor region 11) is used as an n-type collector region, and the first main current control region (p-type semiconductor region 131) is a p-type body region ( p-type base region), and the second main current region (n-type semiconductor region 141) is used as an n-type emitter region. In the second transistor T2, the third main current region (n-type semiconductor region 11) is used as an n-type collector region, and the second main current control region (p-type semiconductor region 132) is a p-type body region ( The fourth main current region (n-type semiconductor region 142) is used as an n-type emitter region.

  In the semiconductor device 1 according to the second embodiment configured as described above, the tolerance of the sense unit 2 is increased and the entire device is obtained in the same manner as the effects obtained by the semiconductor device 1 according to the first embodiment. As a result, it is possible to achieve an effect that the withstand capability can be improved.

(Other embodiments)
As described above, the present invention has been described according to the first embodiment and the second embodiment. However, the description and the drawings constituting a part of this disclosure do not limit the present invention. The present invention can be applied to various alternative embodiments, examples, and operational technologies. For example, in the first embodiment described above, the example in which the vertical power transistor is mounted on the semiconductor device 1 and the vertical IGBT is mounted in the second embodiment has been described. It is not limited to the mold.

  In addition, the present invention provides a semiconductor in which a trench gate power transistor or a trench gate IGBT in which a gate insulating film and a gate electrode are embedded in a trench and a main current control region is disposed along the trench side wall through the gate insulating film is mounted. It can be applied to the device. In this case, as in the above-described embodiment, the junction depth of the contact region portion of the second main current control region in the second transistor of the sense portion is equal to the first main current of the first transistor of the main portion. It is set deeper than the junction depth of the control region.

  In the present invention, the planar shapes of the first transistor T1 of the main portion 2 and the second transistor T2 of the sense portion 3 of the semiconductor device according to the above-described embodiment are configured in a stripe shape. The shape is not limited, and a plurality of transistors may be arranged in a dot shape.

1 is an enlarged cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a circuit configuration diagram of the semiconductor device shown in FIG. 1. FIG. 2 is a schematic chip layout diagram of the semiconductor device shown in FIG. 1. FIG. 6 is a first process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. It is 2nd process sectional drawing. It is 3rd process sectional drawing. It is a 4th process sectional view. FIG. 10 is a fifth process cross-sectional view. It is 6th process sectional drawing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Main part 3 ... Sense part 4 ... Isolation area | region 10 ... Substrate 11 ... n-type semiconductor area (1st or 3rd main electric current area | region)
121 ... first semiconductor region 122 ... second semiconductor region 131, 132 ... p-type semiconductor region (first or second main current control region)
1321 ... Main current path portion 1322 ... Contact region portion 141, 142 ... n-type semiconductor region (second or fourth semiconductor region)
151, 152 ... gate insulating film 161, 162 ... gate electrode 17 ... interlayer insulating film 17H ... contact opening 18 ... electrode 21, 22 ... depletion layer 30 ... mask T1 ... first transistor T2 ... second transistor

Claims (7)

A first main current region having a first conductivity type;
A first main current control region disposed on a main surface portion of the first main current region and having a second conductivity type opposite to the first conductivity type;
A second main current region disposed on a main surface portion of the first main current control region and having the first conductivity type;
A first transistor having the first main current region, the first main current control region, and the second main current region;
A third main current region having the first conductivity type and having a planar area smaller than that of the first main current region;
A second main element disposed on a main surface portion of the third main current region, having the second conductivity type, and having a junction depth deeper than that of the first main current control region. A current control region;
A fourth main current region disposed on a main surface portion of the second main current control region and having the first conductivity type;
A second transistor having the third main current region, the second main current control region, and the fourth main current region;
A semiconductor device comprising: A first main current region having a first conductivity type, and a first main current control region having a second conductivity type opposite to the first conductivity type and disposed on the first main current region And a main portion having a first transistor which is disposed on the first main current control region and has a second main current region having the first conductivity type and which performs switching control of the main current;
A third main current region having the first conductivity type, and a junction depth of the first main current control region having the second conductivity type disposed on the third main current region. A second main current control region having a deep and deep junction depth, and a fourth main current region having the first conductivity type and disposed on the second main current control region, A sense unit having a second transistor for current detection of the transistor;
A semiconductor device comprising: A first gate electrode disposed via a first gate insulating film along the first main current control region of the first transistor;
A second gate electrode disposed via a second gate insulating film along the second main current control region of the second transistor,
The first main current region of the first transistor and the third main current region of the second transistor are electrically connected, and the first gate electrode and the second gate electrode are The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected. The second main current control region is a region different from the main current path portion through which a main current flows between the third main current region and the fourth main current region. A contact region portion to which the upper layer electrode is connected,
The junction depth of the contact region portion of the second main current control region is deeper than the junction depth of the first main current control region. 4. The semiconductor device according to any one of 3.   The semiconductor device according to claim 4, wherein a junction depth of the main current path portion in the second main current control region is equal to a junction depth of the first main current control region.   A first semiconductor region having the same conductivity type as that of the first main current region and having a higher impurity density than that of the first main current region is arranged over the entire main surface of the first main current region. The main surface portion of the third main current region has the same conductivity type as that of the third main current region except for the contact region portion between the second main current control region and the upper layer electrode. 6. The semiconductor device according to claim 4, wherein a second semiconductor region having a higher impurity density than that of the third main current region is provided.   7. The semiconductor device according to claim 1, wherein a resistor having a resistance of 800 ohms or less is electrically connected to the fourth main current region of the second transistor.

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