JP2009088006A - Insulation gate-type semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such problem that the reduction of resistance in a current route is limited in an insulation gate-type semiconductor device wherein two element regions are integrated while one substrate is being used as a common drain region, because current flowing between the two element regions detours deep to a semiconductor substrate with low resistance or to a metal layer provided on its backside. <P>SOLUTION: An embedded metal layer reaching an n<SP>+</SP>-type semiconductor substrate is provided in an n<SP>-</SP>-type semiconductor layer beneath a shield metal layer between two element regions. A part of current detouring around the bottom of the substrate flows shallow around the bottom of the n<SP>-</SP>-type semiconductor layer, so that the current route is partly made short and total resistance of the current route of a device can be reduced. Only an annular region is arranged in a border area between the two element regions to terminate a depletion layer. Thus, a low-resistance layer can be arranged under the annular region, contributing to the reduction of on-state resistance of the device. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an insulated gate semiconductor device, and more particularly to an insulated gate semiconductor device that realizes resistance reduction in a structure in which two element regions are arranged on one chip.

  As switching elements used in protection circuit devices that perform battery management for charging and discharging secondary batteries, two MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are arranged in one chip, and bidirectional current paths are created. An insulated gate semiconductor device that can be switched is known (for example, see Patent Document 1).

  FIG. 5 is a diagram showing a MOSFET in which two element regions are integrated on one chip as an example of a conventional insulated gate semiconductor device. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along the line cc of FIG. 5A.

  The MOSFET 150 is obtained by integrating the first element region 131 and the second element region 132 on one chip.

  The first element region 131 and the second element region 132 are provided on one substrate (semiconductor chip) 130 in which an n− type semiconductor layer 130b is stacked on an n + type semiconductor substrate 130a. That is, MOSFET cells constituting the respective element regions 131 and 132 are provided on the substrate 130, and the two element regions 131 and 132 share a drain region.

  The first element region 131 and the second element region 132 are arranged, for example, symmetrically with respect to the center line XX of the chip, and the first gate wiring electrode 133 and the second gate wiring electrode 134 are the first source electrode 135, The second source electrode 136 is provided so as to surround the outside. A high-concentration n-type impurity region 137 serving as a stopper region for a depletion layer extending in the substrate 30 is provided on the peripheral edge of the substrate 30 and at the boundary between the first element region 131 and the second element region 132, and on that, A shield metal layer 138 is disposed. The shield metal layer 138 is disposed around each of the first element region 131 and the second element region 132, and is shared by the two element regions at the boundary between the first element region 131 and the second element region 132.

The element regions 131 and 132 have the same configuration, and a trench 142 is provided in the p-type channel layer 141. The trench 142 has an inner wall covered with a gate insulating film 143, and a gate electrode 144 is embedded. An n-type source region 145 and a p-type body region 147 are provided between the trenches 142, and the gate electrode 144 is covered with an interlayer insulating film 146 to provide a first source electrode 135 (136). For example, in the case of a flip chip structure, a metal layer 140 for reducing the resistance of the current path is provided on the back surface of the substrate 130.
JP 2002-118258 A

  Referring to FIG. 6, the drain regions of the first element region 131 and the second element region 132 are common, and a current path is formed in the drain region from one element region to the other element region when conducting. .

  More specifically, current flows in a horizontal direction with respect to the main surface of the substrate 130 by using the low resistance n + -type semiconductor substrate 130a or the metal layer 140 on the back surface as a main path while avoiding the high-resistance n− type semiconductor layer 130b. .

  However, the thickness in the vertical direction of the n + type semiconductor substrate 130a is about 100 μm to 300 μm, and if the metal layer 140 or the n + type semiconductor substrate 130a in the vicinity thereof is used as the path, the current is deeply detoured, which limits the resistance reduction. was there.

  The present invention has been made in view of such a problem, and includes a one-conductivity-type semiconductor substrate, a one-conductivity-type semiconductor layer provided on the one-conductivity-type semiconductor substrate, and a first surface provided on one main surface of the one-conductivity-type semiconductor layer. 1 insulated gate type semiconductor element region, a second insulated gate type semiconductor element region provided on one main surface of the one conductivity type semiconductor layer, and the first and second insulated gate type semiconductor element regions And a metal layer embedded in the one-conductivity type semiconductor layer.

  According to the present invention, the metal layer embedded in the n − type semiconductor layer between the first insulated gate semiconductor device region and the second insulated gate semiconductor device region allows the bottom of the n − semiconductor layer (n + type semiconductor substrate). The low resistance region can be formed on the surface). As a result, a part of the current that is deeply detoured to the vicinity of the back surface of the substrate flows in a relatively shallow region below the n − type semiconductor layer, and a part of the current path is shortened. Therefore, the total resistance of the current path can be reduced, and the on-resistance of the insulated gate semiconductor device can be reduced.

  In particular, it is effective in reducing the resistance of the current path starting from a transistor cell existing near the boundary between the first insulated gate semiconductor element region and the second insulated gate semiconductor element region.

  Further, since it is only necessary to dispose the metal layer along the center line of the chip, it is possible to contribute to reduction of the on-resistance of the device with a desired width, that is, without changing the pattern of the element region.

  An embodiment of an insulated gate semiconductor device according to the present invention will be described with reference to FIGS. 1 to 4, taking an n-channel MOSFET as an example.

  The MOSFET 100 of the present invention includes a one-conductivity-type semiconductor substrate 1, a one-conductivity-type semiconductor layer 2, a first MOSFET element region 100a, a second MOSFET element region 100b, and a metal layer.

  FIG. 1 is a plan view showing the MOSFET 100.

  In the MOSFET 100 of this embodiment, a first MOSFET element region (hereinafter referred to as a first element region) 100a and a second MOSFET element region (hereinafter referred to as a second element region) 100b are formed on a substrate 10 constituting one semiconductor chip. It is an integrated one.

  The first element region 100 a and the second element region 100 b are arranged, for example, symmetrically with respect to the center line XX of the substrate (chip) 10.

  A first source electrode 17a connected to a source region (not shown) of the first element region 100a is provided on the surface of the first element region 100a, and a first gate wiring electrode 18a is provided on the outer periphery of the first source electrode 17a. It is done. A gate pad portion 18ap is provided in a part of the first gate wiring electrode 18a. A conductive layer (not shown) such as a polysilicon layer connected to the gate electrode (not shown) in the first element region 100a is provided below the first gate wiring electrode 18a.

  A second source electrode 17b connected to a source region (not shown) of the second element region 100b is provided on the surface of the second element region 100b, and a second gate wiring electrode 18b is provided on the outer periphery of the second source electrode 17b. It is done. A gate pad portion 18bp is provided in a part of the second gate wiring electrode 18b. A conductive layer (not shown) such as a polysilicon layer connected to the gate electrode (not shown) of the second element region 100b is provided below the second gate wiring electrode 18b.

  A shield metal layer 52 is provided over the entire periphery of the end portion of the substrate 10. The shield metal layer 52 is formed of, for example, the same metal layer (for example, an Al layer) as the first source electrode 17a and the first gate wiring electrode 18a (the same applies to the second element region 100b side). The shield metal layer 52 is in a floating state to which no potential is applied.

  The shield metal layer 52 is also disposed at the boundary between the first element region 100a and the second element region 100b, which is the center of the substrate 10, and is shared by the two element regions 100a and 100b.

  A metal layer 50 is buried in an n − type semiconductor layer (described later) below the shield metal layer 52 at the boundary, as indicated by a broken line.

  2 is a cross-sectional view taken along line aa in FIG.

  The first element region 100a and the second element region 100b are provided on the same semiconductor substrate 10 having the first main surface Sf1 and the second main surface Sf2. Accordingly, the first element region 100a and the second element region 100b have a common drain region.

  The configuration of the first element region 100a is as follows. Since the second element region 100b has the same configuration, the description thereof is omitted.

  The semiconductor substrate 10 is obtained by laminating an n− type semiconductor layer (for example, an n− type epitaxial layer) 2 on an n + type silicon semiconductor substrate 1. A channel layer 4 which is a p-type impurity region is provided on the surface of the n − type semiconductor layer 2 which becomes the first main surface Sf1.

  The trench 7 passes through the channel layer 4 and reaches the n − type semiconductor layer 2. The trench 7 is generally patterned in a lattice shape or a stripe shape in the plane pattern of the first main surface Sf1.

  A gate insulating film (for example, an oxide film) 11 is provided on the inner wall of the trench 7. The film thickness of the gate insulating film 11 is about several hundreds of squares depending on the MOSFET driving voltage. In addition, a conductive material is buried in the trench 7 to provide the gate electrode 13. The conductive material is, for example, polysilicon, and n-type impurities, for example, are introduced into the polysilicon in order to reduce the resistance.

  The source region 15 is an n + type impurity region in which an n type impurity is implanted into the surface of the channel layer 4 adjacent to the trench 7. Further, a body region 14 which is a diffusion region of a p + type impurity is provided on the surface of the channel layer 4 between the adjacent source regions 15 to stabilize the substrate potential. As a result, a portion surrounded by the adjacent trenches 7 becomes one cell of the MOSFET transistor, and a large number of these cells gather to constitute the first element region 100a of the MOSFET. A guard ring 21 that is a high-concentration p-type impurity region is provided on the outer periphery of the first element region 100a.

  In this embodiment, for the sake of convenience, the region up to the inside of the guard ring 21 will be described as the first element region 100a (second element region 100b).

  The gate electrode 13 is covered with an interlayer insulating film 16. The first source electrode 17a is provided on the first main surface Sf1 side of the semiconductor substrate 10 so as to cover the first element region 100a, and is connected to the source region 15 and the body region 14 through a contact hole between the interlayer insulating films 16. . The first source electrode 17a is a metal electrode that is patterned into a desired shape by sputtering aluminum (Al) or the like.

  The gate electrode 13 is drawn on the semiconductor substrate 10 by the conductive layer 13c, extends to the first gate wiring electrode 18a surrounding the semiconductor substrate 10, and is connected to the gate pad portion (see FIG. 1). A nitride film 23 is provided on the first source electrode 17a.

  A back metal layer 30 is provided on the second main surface Sf2 side of the semiconductor substrate 10. The back metal layer 30 contributes to reducing the resistance of the current flowing through the semiconductor substrate 10.

  Further, the metal layer 50 is embedded in the n − type semiconductor layer 2 between the first element region 100a and the second element region 100b. A metal layer (hereinafter referred to as a buried metal layer) 50 overlaps with the shield metal layer 52 disposed on the center line (XX line) of the chip, and is disposed below the shield metal layer 52. The bottom of the buried metal layer 50 reaches the n + type semiconductor substrate 1. The buried metal layer 52 is formed by embedding a metal layer such as aluminum in a trench formed in the n − type semiconductor layer 2.

  Further, an n-type impurity region (annular region) 51 in which high-concentration n-type impurities are diffused is provided on the surface of the n − type semiconductor layer 2 around the buried metal layer 52. The annular region 51 terminates a depletion layer extending from the first element region 100a and the second element region 100b.

  FIG. 3 is an equivalent circuit diagram showing an example when the MOSFET 100 is used as a switching element that switches a bidirectional current path.

  The MOSFET 100 has a configuration in which a first MOSFET 100a 'formed in the first element region 100a and a second MOSFET 100b' formed in the second element region 100b are connected in series with a common drain, and the drain terminal is not led out to the outside.

  That is, the first gate terminal G1 and the second gate terminal G2 connected to the first and second gate wiring electrodes, respectively, and the first source terminal S1 and the second source terminal S2 connected to the first and second source electrodes, respectively, are externally connected. 4 terminal element derived from

  The MOSFET 100 controls the MOSFETs 100a 'and 100b' by applying gate signals to the first gate terminal G1 and the second gate terminal G2, respectively. Then, the current path is switched according to the potential difference applied to the first source terminal S1 and the second source terminal S2.

  Each of the first MOSFET 100a 'and the second MOSFET 100b' has a parasitic diode. For example, the first MOSFET 100a 'is turned off and the second MOSFET 100b' is turned on by the control signal. Then, by setting the first source terminal S1 to a higher potential than the second source terminal S2, a current path in the d1 direction is formed by the parasitic diode of the first MOSFET 100a 'and the second MOSFET.

  On the other hand, the second MOSFET 100b 'is turned off by the control signal, and the first MOSFET 100a' is turned on. Then, by setting the first source terminal S1 to a potential lower than that of the second source terminal S2, a current path in the d2 direction is formed by the parasitic diode of the second MOSFET 100b 'and the first MOSFET.

  FIG. 4 is a cross-sectional view schematically showing a current path when the MOSFET 100 of the present embodiment is conductive. 4 is a cross-sectional view taken along line bb of FIG. Details of the first element region 100a and the second element region 100b are omitted.

  Referring to FIG. 4, shield metal layer 52 and annular region 51 are also provided at the end of semiconductor substrate 10 surrounding first element region 100a and second element region 100b. However, the buried metal layer 50 is provided only below the shield metal layer 52 between the first element region 100a and the second element region 100b.

  In the present embodiment, when the MOSFET 100 is conductive, the second element region 100b and the first element region 100b are connected from the first source electrode 17a and the first element region 100a via the n− type semiconductor layer 2, the n + type semiconductor substrate 1, and the back surface metal layer 30. A current path to the two source electrodes 17b is formed (the direction in which the current flows may be any).

  At this time, the resistance value of the current path can be reduced by the embedded metal layer 50. That is, the current mainly flows so as to make a deep detour along the second main surface Sf2 side (the back surface metal layer 30 and the n + type semiconductor substrate 1 in the vicinity thereof) of the semiconductor substrate 10 having a low resistance value. In the present embodiment, in addition to this, a current also flows in a region along the bottom of the n − type semiconductor layer 2 due to the buried metal layer 50. Accordingly, since some of the current that has been deeply bypassed is shallow and short, the resistance of the entire current path can be reduced.

  In particular, it is effective in reducing the resistance of the current path with the cell existing near the boundary between the first element region 100a and the second element region 100b as a base point.

  The boundary region between the first element region 100a and the second element region 100b only needs to be provided with the annular region 51 that terminates the depletion layer, and the low resistance buried layer 50 can be disposed within the boundary region 51.

  Further, since it is only necessary to dispose the buried metal layer 50 along the center line of the chip of the MOSFET 100, it is possible to contribute to the reduction of the on-resistance of the MOSFET 100 without changing the pattern of the element region.

  Further, the resistance can be further reduced as compared with the case where the low resistance layer for shortening the current path is formed in the impurity diffusion region.

  In this embodiment, the case of an n-channel MOSFET has been described as an example. However, a p-channel MOSFET having a reversed conductivity type can be implemented in the same manner and the same effect can be obtained.

It is a top view explaining the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the insulated gate semiconductor device of embodiment of this invention. It is an equivalent circuit diagram explaining the insulated gate semiconductor device of the embodiment of the present invention. It is sectional drawing explaining the insulated gate semiconductor device of embodiment of this invention. It is (A) top view and (B) sectional drawing explaining the conventional insulated gate semiconductor device. It is sectional drawing explaining the conventional insulated gate semiconductor device.

Explanation of symbols

1 n + type silicon semiconductor substrate 2 n− type semiconductor layer 4 channel layer 7 trench 10 semiconductor substrate (semiconductor chip)
DESCRIPTION OF SYMBOLS 11 Gate insulating film 13 Gate electrode 13c Conductive layer 14 Body region 15 Source region 16 Interlayer insulating film 17a First source electrode 17b Second source electrode 18a First gate wiring electrode 18b Second gate wiring electrode 18ap, 18bp Gate pad part 23 Nitride Film 30 (Back) Metal layer 50 (Embedded) Metal layer 51 Annular region 52 Shield metal layer 100 MOSFET
100a First (insulated gate type semiconductor) element region 100b Second (insulated gate type semiconductor) element region 100a ′ First MOSFET
100b 'second MOSFET
130 substrate 130a n + type silicon semiconductor substrate 130b n− type semiconductor layer 131 first element region 132 second element region 133 first gate line electrode 134 second gate line electrode 135 first source electrode 136 second source electrode 137 n type impurity Region 138 Shield metal layer 140 Metal layer 141 Channel layer 142 Trench 143 Gate insulating film 144 Gate electrode 145 Source region 146 Interlayer insulating film Sf1 First main surface Sf2 Second main surface S1, S2 Source terminal G1, G2 Gate terminal

Claims (5)

One conductivity type semiconductor substrate;
A one conductivity type semiconductor layer provided on the one conductivity type semiconductor substrate;
A first insulated gate semiconductor element region provided on one main surface of the one conductivity type semiconductor layer;
A second insulated gate semiconductor element region provided on one main surface of the one conductivity type semiconductor layer;
A metal layer embedded in the one conductivity type semiconductor layer between the first and second insulated gate semiconductor element regions;
An insulated gate semiconductor device comprising:   2. The insulated gate semiconductor device according to claim 1, wherein the metal layer reaches the one conductivity type semiconductor substrate.   2. The insulated gate semiconductor device according to claim 1, wherein another metal layer to which no potential is applied is provided on the surface of the metal layer.   4. The insulated gate semiconductor device according to claim 3, wherein the other metal layer extends around the one conductivity type semiconductor layer.   2. The insulated gate semiconductor device according to claim 1, wherein a high-concentration one-conductivity type impurity region is provided on a surface of the one-conduction type semiconductor layer around the metal layer.

Images