JP4961658B2 - Bidirectional element and semiconductor device - Google Patents

Description

The present invention relates to a bidirectional device and a semiconductor device such as a power integrated circuit (power IC) having the bidirectional device.

In a power supply device such as a battery, overcharging and overdischarging of the battery are prevented by controlling both when the battery is charged and when the battery is discharged (when a current is supplied to the load). Therefore, a bidirectional semiconductor switch that can turn on / off an AC signal and AC power is required, and a composite bidirectional element in which unidirectional semiconductor elements are connected in antiparallel is used as the bidirectional semiconductor switch. .
Further, the power supply device is downsized by using a power IC in which the composite bidirectional element and a control IC for controlling the composite bidirectional element are integrated on the same semiconductor substrate.
A single bidirectional element has also been developed. As an example, a bidirectional lateral insulated gate transistor (LIGBT) has been proposed (see Non-Patent Document 1, for example). Next, the structure and operation of the bidirectional LIGBT will be described.

FIG. 30 is a cross-sectional view of a main part of the bidirectional LIGBT. In the bidirectional LIGBT, two p ⁺ well regions 504 and 505 are formed on the surface side of the n semiconductor layer 503, and n ⁺ emitter regions 506 and 507 are formed in the p ⁺ well regions 504 and 505. The p ⁺ well regions 504 and 505 are formed so as to be exposed on the surface of the n semiconductor layer 503 and are separated by a predetermined distance (drift distance) so as to maintain a predetermined breakdown voltage. The n ⁺ emitter regions 506 and 507 are also formed so as to be exposed on the surface of the n semiconductor layer 503 (the surfaces of the p ⁺ well regions 504 and 505).
An insulated gate type gate electrode made of polysilicon or the like is disposed on a portion of the p ⁺ well regions 504 and 505 located between the two n ⁺ emitter regions 506 and 507 via the gate insulating films 508 and 509. 510, 511 are formed. Emitter electrodes 512 and 513 are formed so as to straddle the p ⁺ well regions 504 and 505 and the n ⁺ emitter regions 506 and 507. In this structure, when the voltage applied to the gate electrodes 510 and 511 is controlled, on / off of the main current flowing in both directions between the emitter electrodes 512 and 513 can be controlled.

FIG. 31 is a diagram showing output characteristics of the bidirectional LIGBT of FIG. Since the main current does not begin to flow unless the rising voltage (0.6 V) due to the built-in potential of the pn junction is exceeded, the on-voltage is high and the on-loss is large in a small current region.
In order to improve this, there is a single bidirectional MOSFET in which a bidirectional element is formed by a MOSFET whose voltage becomes zero V at the rising edge (see, for example, Patent Document 1). The contents will be described.
FIG. 32 is a cross-sectional view of a main part of a conventional bidirectional MOSFET. Here, a bidirectional LDMOSFET (Lateral Double-Diffused MOSFET) is illustrated. Similar to the above example, the semiconductor device has an SOI structure, and an n semiconductor layer 103 is formed on a semiconductor substrate 101 with an insulating layer 102 interposed therebetween. Two n ⁺⁺ drain regions 104 and 105 are formed on the surface side of the n semiconductor layer 103, and a p ⁺ well region 106 is formed between the n ⁺⁺ drain regions 104 and 105. The p ⁺ well region 106 is formed to a depth reaching the insulating layer 102 and divides the n semiconductor substrate 103 into two regions. Further, in the p ⁺ well region 106, two n ⁺⁺ source regions 107 and 108 are formed, and a p ⁺⁺ base contact 109 region is formed between the n ⁺⁺ source regions 107 and 108. . The n ⁺⁺ drain regions 104 and 105 and the p ⁺ well region 106 are exposed on the surface of the n semiconductor substrate 103, and the n ⁺⁺ source regions 107 and 108 and the p ⁺⁺ base contact region 109 are on the surface of the p ⁺ well region 106. Exposed to. Insulated gate type gate electrodes 112 and 113 are formed on the p ⁺ well region 106 via gate insulating films 110 and 111, and both gate electrodes 112 and 113 are connected in common. Drain electrodes 114 and 115 are connected to n ⁺⁺ drain regions 104 and 105, respectively. Further, the source electrode 117 is connected so as to straddle the n ⁺⁺ source regions 107 and 108 and the p ⁺⁺ base contact region 109.

In order to turn on the above-described bidirectional LDMOSFET, a voltage is applied between the gate electrodes 112 and 113 and the source electrode 117 so that the gate electrodes 112 and 113 have a positive potential. At this time, a channel is formed immediately below the gate insulating films 110 and 111 in the p ⁺ well region 106. Here, if a voltage is applied between the drain electrodes 114 and 115 so that the drain electrode 114 side has a high potential, the drain electrode 114 → n ⁺⁺ drain region 104 → n semiconductor layer 103 → gate electrode 112. Corresponding channel → n ⁺⁺ source region 107 → source electrode 117 → n ⁺⁺ source region 108 → channel corresponding to gate electrode 113 → n semiconductor layer 103 → n ⁺⁺ drain region 105 → electron current in the path of drain electrode 115 Flows. At this time, the current is dominated by the electron current (that is, monopolar), and no offset component is generated even at a low potential because there is no junction in the current path. That is, the linearity is good even in a minute current region. When the polarity of the voltage applied to the drain electrodes 114 and 115 is reversed, the direction of the current is reversed, but the same operation is performed. As a result, as shown in FIG. 33, an alternating current can be passed, and an operation with good linearity can be expected even in a minute current region.

On the other hand, in order to turn off the above-described bidirectional LDMOSFET, the gate electrodes 112 and 113 and the source electrode 117 are short-circuited. As a result, the channel formed immediately below the gate insulating films 110 and 111 in the p ⁺ well region 106 disappears, so that no electron current flows and the channel is turned off. In the off state, no current flows even if a positive or negative voltage is applied between the drain electrodes 114 and 115. That is, it is turned off with respect to the AC voltage. Here, the breakdown voltage is equal to the breakdown voltage of one side portion of the bidirectional LDMOSFET.
AC power can be turned on / off with a single chip using the above-described bidirectional LDMOSFET, and when conducting, the voltage / current characteristics have good linearity even in a very small current region, so that it can be used to turn on / off signal current. Is possible. Further, since the gate electrodes 112 and 113 are commonly connected and the number of the source electrodes 117 is one, only one drive circuit for supplying a control signal to the gate is sufficient and the control is easy.

As described above, since the main current flows through the channel without passing through the pn junction, it is basically the same as the current flowing through the resistor, and the current flows above zero voltage, and the on-voltage in a small current region. Becomes smaller and the on-loss can be reduced.
JP 11-224950 A ISPSD (International Symposium on Power Semiconductor Devices and ICs) 1997, pp 37-40)

However, since the withstand voltage of the bidirectional LDMOSFET of FIG. 32 is maintained at the withstand voltage of one of the bidirectional LDMOSFETs, both MOSFETs require a withstand voltage in order to maintain the forward / reverse withstand voltage, and the occupied area is doubled. As a result, the occupied area between the drain regions becomes large. In addition, because of the planar structure, it is difficult to miniaturize the cells constituting the bidirectional LDMOSFET, and therefore it is difficult to improve the on-voltage.
An object of the present invention is to solve the above-described problems and provide a high breakdown voltage bidirectional element that can increase the cell density of the bidirectional element and reduce the on-voltage, and a semiconductor device having the bidirectional element .

According to the present invention, the first and second divided semiconductor regions formed by dividing the surface layer of the well region by the trench formed from the surface of the well region in the well region of the first conductivity type. Prepared,
The first divided semiconductor region and the trench are provided in one direction parallel to the surface of the well region from the trench, and the second divided semiconductor region and the trench are provided in a direction opposite to the one direction. In the repeating region of the trench and the first and second divided semiconductor regions, and in the repeating region,
A drain region of a first conductivity type formed from the bottom of the trench to the side wall;
A first offset region of a second conductivity type formed on the surface layer of the first divided semiconductor region in contact with the sidewalls of the trench and the drain region on both sides of the first divided semiconductor region;
A first source region of a first conductivity type formed on a surface layer of the first offset region, in contact with a sidewall of the trench on both sides of the first divided semiconductor region, and in contact with the first offset region;
A first contact region of a second conductivity type formed on a surface layer of the first offset region in contact with the first offset region;
A first gate electrode formed on a sidewall of the trench on both sides of the first divided semiconductor region through the first insulating film from the drain region to the first source region. When,
A first source electrode in contact with the first source region and the first contact region;
A second conductivity type second offset region formed on the surface layer of the second divided semiconductor region in contact with the sidewalls of the trench and the drain region on both sides of the second divided semiconductor region;
A second source region of a first conductivity type formed on a surface layer of the second offset region, in contact with a sidewall of the trench on both sides of the second divided semiconductor region, and in contact with the second offset region;
A second contact region of a second conductivity type formed on the surface layer of the second offset region in contact with the second offset region;
A second gate electrode formed on a sidewall of the trench on both sides of the second divided semiconductor region of the second divided semiconductor region from the drain region to the second source region via a second insulating film; When,
A second source electrode in contact with the second source region and the second contact region,
The first gate electrode and the second gate electrode are electrically insulated;
The drain region is a drain, the first offset region is a channel, the first source region is a source, a first MOSFET, the drain region is a drain, the second offset region is a channel, and the second source region is a source. A second MOSFET and a bidirectional element connected in series;
The element is configured to allow a current to flow between the first source electrode and the second source electrode.

The well region may be a region selectively formed in the surface layer of the second conductivity type semiconductor substrate.
Further, it is preferable that a plurality of the first and second divided semiconductor regions are provided, and the trench width between adjacent divided semiconductor regions is wider than between the same regions.

The first conductivity type well region includes first and second divided semiconductor regions formed by dividing the surface layer of the well region by a trench formed from the surface of the well region.
The first divided semiconductor region and the trench are provided in one direction parallel to the surface of the well region from the trench, and the second divided semiconductor region and the trench are provided in a direction opposite to the one direction. In the repeating region of the trench and the first and second divided semiconductor regions, and in the repeating region,
A source region of a first conductivity type formed across the sidewall from the bottom of the trench selectively in a direction perpendicular to the one direction and parallel to the surface of the well region ;
A contact region of a second conductivity type formed across the sidewall from the bottom of the trench in a region that is selectively formed in the vertical direction and in which the source region is not formed;
A first conductivity type first offset region formed on a surface layer of the first divided semiconductor region in contact with the sidewalls of the trench, the source region and the contact region on both sides of the first divided semiconductor region; ,
A first drain region of a first conductivity type formed on a surface layer of the first offset region, in contact with a sidewall of the trench on both sides of the first divided semiconductor region, and in contact with the first offset region;
A first gate electrode formed on a sidewall of the trench on both sides of the first divided semiconductor region of the first divided semiconductor region through a first insulating film from the source region to the first drain region. When,
A first drain electrode in contact with the first drain region;
A second conductivity type second offset region formed on the surface layer of the second divided semiconductor region in contact with the sidewalls of the trench, the source region, and the contact region on both sides of the second divided semiconductor region; ,
A second drain region of a first conductivity type formed on a surface layer of the second offset region, in contact with a sidewall of the trench on both sides of the second divided semiconductor region, and in contact with the second offset region;
A second gate electrode formed on the sidewall of the trench on both sides of the second divided semiconductor region of the second divided semiconductor region from the source region to the second drain region via a second insulating film. When,
A second drain electrode in contact with the second drain region;
A conductor in contact with the source region and the contact region through an insulating film between the first gate electrode and the second gate electrode;
The first gate electrode and the second gate electrode are electrically insulated;
A first MOSFET having the source region as a source, the first offset region as a channel, and the first drain region as a drain, the source region as a source, the second offset region as a channel, and the second drain region as a drain. A second MOSFET and a bidirectional element connected in series;
The element is configured to allow a current to flow between the first drain electrode and the second drain electrode.

The bidirectional element and a control circuit for controlling the bidirectional element may be formed on the same semiconductor substrate .

According to the present invention, it is possible to achieve a high breakdown voltage and a low on-voltage of the bidirectional element .
Further, a safe operation region of the bidirectional element can be widened by forming a contact region and electrically contacting the offset region and the first and second source regions .

  In the following description, the first conductivity type is n-type and the second conductivity type is p-type, but this may be reversed.

FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention, in which FIG. 1 (a) is a plan view of the main part, FIG. 1 (b) is an enlarged view of part A of FIG. c) is a cross-sectional view of the main part taken along line XX of FIG. Here, a bidirectional LMOSFET (bidirectional lateral MOSFET) will be described as an example. The structure of this bidirectional LMOSFET is similar to a TLPM (trench lateral power MOSFET) structure.
An n well region 2 is formed in a p semiconductor substrate 1, a trench 3 is formed in the n well region 2, an n drain region 4 is formed below the bottom surface 3 a of the trench, and a p offset region is formed in a surface layer of the n well region 2. 5 is formed.
A gate insulating film 6 is formed on the inner wall of the trench 3, and a gate electrode 7 is formed on the trench side wall 3b via the gate insulating film. A first n source region 9 and a second n source region 10 are selectively formed on the surface of the p offset region 5 surrounded by the trench 3 so as to be in contact with the trench 3. The first n source region 9 and the second n source region 10 are alternately formed with the trench 3 interposed therebetween. The gate electrode 7 and the inside of the trench 3 are filled with an interlayer insulating film 8 and flattened. After the interlayer insulating film 8a is formed on the entire surface, contact holes are opened in the interlayer insulating film, and the first source electrode 11 and the second source electrode 12 are formed on the first n source region 9 and the second n source region 10, respectively. Form. The first source electrodes 11 and the second source electrodes 12 are connected by a first source line 13 and a second source line 14, respectively. The gate electrode 7 is connected to a gate pad (not shown) via a gate wiring.

As described above, by forming the n drain region 4 at the bottom of the trench, the electric field is relaxed and a high breakdown voltage of about 30 V can be secured.
In addition, as described above, the breakdown voltage is maintained along the trench 3 by forming the gate electrode 7 and the n drain region 4 at the bottom of the trench 3, and therefore, the first n source region 9 and the second n source The space on the surface of the region 10 can be narrowed, and the cells can be miniaturized. As a result, the on-voltage can be reduced.
Incidentally, by using the p semiconductor substrate 1 as described above, the substrate 1 can be set to the ground potential, and it becomes easy to form a CMOS circuit or the like (not shown) on the substrate 1. Further, although the n extended n drain region 4 formed at the bottom of the trench is formed apart, it may be formed so that the respective n drain regions 4 are in contact with each other.

Further, a configuration as shown in FIG. 2 may be used. FIG. 2A shows a configuration in which the n well region 2 also serves as the n drain region 4 in FIG. 2A and 2B show a configuration in the case where the semiconductor substrate is n-type, and in FIG. 2B, the semiconductor substrate 1 also serves as the n drain region 4 in FIG. 1C. In FIG. 8C, the n drain region 4 is further formed in FIG.
Further, in FIG. 1C, the gate electrode 7 is formed separately in the left and right in the trench 3, but may be one as shown in FIG.
FIG. 3 is an equivalent circuit diagram of the bidirectional LMOSFET of FIG. The operation of this bidirectional LDMOSFET 50 will be described. By applying a high voltage to the second source terminal S2 with respect to the first source terminal S1 and applying a voltage higher than the second source terminal S2 to the gate terminal G, the first and second n source regions 9 in FIG. A channel is formed on the side surface of the p offset region 5 sandwiched between 10 and the n drain region 4, and a current flows from the second source terminal S2 to the first source terminal S1. By applying a high voltage to the first source terminal S1 with respect to the second source terminal S2, and applying a voltage higher than the first source terminal S1 to the gate terminal G, the first and second n source regions 9, 10 and n A channel is formed on the side surface of the p offset region 5 sandwiched between the drain regions 4, and a current flows from the first source terminal S1 to the second source terminal S2. In this way, a bidirectional LMOSFET capable of flowing current bidirectionally is obtained.

  On the other hand, the channel formed in the p offset region 5 is extinguished by setting the gate terminal G to the potential of the low potential side of the first and second source terminals S1 and S2 or to the ground potential. The bidirectional LMOSFET can be blocked.

FIG. 4 is a block diagram of a semiconductor device according to a second embodiment of the present invention. FIG. 4 (a) is a plan view of the main part corresponding to FIG. 1 (b), and FIG. It is principal part sectional drawing cut | disconnected by the XX line. The difference from FIG. 1 is that p contact regions 15 and 16 surrounded by the first and second n source regions 9 and 10 are formed in the surface layer of the p offset region 5, and the first n source region 9 and the second n source region are formed. 10 and the respective p contacts 15 and 16 are formed. The operation is the same as described in FIG.
As described above, by forming the p contact regions 15 and 16, the potential of the p offset region 5 is stabilized, and the safe operation region of the bidirectional LMOSFET is widened. Others are the same as the first embodiment.
This bidirectional LMOSFET has p-contact regions 15 and 16 formed therein and has a built-in parasitic diode, and has an operation mode as a bidirectional IGBT. Therefore, the main current can flow between the first source electrode 11 and the second source electrode 12 even when the gate voltage (voltage of the gate electrode 7) is lower than the voltage of the source electrode on the high potential side.

FIG. 5 is a block diagram of a semiconductor device according to a third embodiment of the present invention. FIG. 5 (a) is a plan view of the main part, FIG. 5 (b) is an enlarged view of part B of FIG. (C) is principal part sectional drawing cut | disconnected by the XX line of the same figure (b). Here, a bidirectional LMOSFET will be described as an example.
An n well region 2 is formed in the p semiconductor substrate 1, a trench 33 is formed in the n well region 2, an n source region 34 is formed below the bottom surface 33 a of the trench, and a p offset region is formed in the surface layer of the n well region 2. 35 is formed.
A gate insulating film 36 is formed on the inner wall of the trench 33, and a gate electrode 37 is formed on the trench side wall 33 b via the gate insulating film 36. A first n drain region 39 and a second n drain region 40 are formed on the surface of the p offset region 35 surrounded by the trench 33 so as to be in contact with the trench 33. The first n drain region 39 and the second n drain region 40 are alternately formed with the trench 33 interposed therebetween. The gate electrode 37 and the trench 33 are filled with an interlayer insulating film 38 and planarized. Contact holes are opened in the interlayer insulating film 38 to form the first drain electrode 41 and the second drain electrode 42 on the first n drain region 39 and the second n drain region 40, respectively, and the surface of the n source region 34 And the pickup electrode 45 is filled. The pick-up electrode 45 has an effect of being equipotential when the n source region is divided into a plurality of parts, and can be made to have a predetermined potential by applying a control voltage. For example, a ground potential can be applied when the device is off so that no current flows between D1 and D2. The first drain electrodes 41 and the second drain electrodes 42 are connected to each other by a first drain wiring 43 and a second drain wiring 44, respectively. The gate electrode 37 is connected to a gate pad (not shown) via a gate wiring.

By forming the n source region 34 at the bottom of the trench and covering the interlayer insulating film 38 thereon, the electric field is relaxed and a high breakdown voltage of about 30 V can be secured.
Further, as described above, by forming the gate electrode 37 and the p offset region 35 in the trench, the breakdown voltage is maintained along the trench side wall 33b. Therefore, the first n drain region 39 and the second n drain The space on the surface of the region 40 can be narrowed, and the cell can be miniaturized. As a result, the on-voltage can be reduced.
Incidentally, by using the p semiconductor substrate 1 as described above, the substrate 1 can be set to the ground potential, and it becomes easy to form a CMOS circuit or the like (not shown) on the substrate 1. The n source regions 34 formed at the bottom of the trench are formed apart from each other, but may be formed so that the respective n drain regions 34 are in contact with each other.

  FIG. 6 is an equivalent circuit diagram of the bidirectional LMOSFET of FIG. The operation of the bidirectional LMOSFET 60 will be described. By applying a high voltage to the second drain terminal D2 with respect to the first drain terminal D1, and applying a voltage higher than the first drain terminal D1 to the gate terminal G, the first and second n drain regions 39 shown in FIG. , 40 and the n source region 34, a channel is formed on the side surface of the p offset region 35, and a current flows from the second drain terminal D 2 to the first drain terminal D 1. By applying a high voltage to the first drain terminal D1 relative to the second drain terminal D2, and applying a voltage higher than the second drain terminal D2 to the gate electrode G, the first and second n drain regions 39, 40 and n A channel is formed on the side surface of the p offset region 35 sandwiched between the source regions 34, and a current flows from the first drain terminal D1 to the second drain terminal D2. Thus, a bidirectional LMOSFET is obtained.

  On the other hand, by setting the gate terminal G to the same potential as the lower potential of the first and second drain terminals D1 and D2, the channel formed in the p offset region 35 is extinguished and the bidirectional LMOSFET is blocked. Can do.

FIG. 7 is a block diagram of a semiconductor device according to a fourth embodiment of the present invention. FIG. 7 (a) is a plan view of an essential part corresponding to FIG. 5 (b), and FIG. The principal part sectional drawing cut | disconnected by X1-X1 of this, The figure (c) is principal part sectional drawing cut | disconnected by X2-X2 of the figure (a). Here, a bidirectional LMOSFET will be described as an example.
The difference from FIG. 5 is that a p base pickup region 46 is formed next to the n source region 34 below the trench bottom surface 33a, and a pickup electrode 45 is formed in contact with the n source region 34 and the p base pickup region 36. It is. The operation is the same as that described in FIG.
Thus, by forming the p base pickup region 46 and shorting the p base pickup region 46 and the n source region 34 with the pickup electrode 45, the potential of the p offset region 35 is stabilized, and the bidirectional LMOSFET is operated safely. The area becomes wider. Others are the same as the third embodiment.

FIG. 8 is a main part layout diagram of the semiconductor device according to the fifth embodiment of the present invention. Here, a power IC mounted on the battery device is shown as an example.
This power IC forms a bidirectional LMOSFET 50, a drive / protection circuit unit 51, and a remaining amount circuit unit 52 on the same semiconductor substrate 91. The drive / protection circuit unit 51 and the remaining amount circuit unit 52 are provided with the voltage of the battery cell 92, the charging current flowing into the battery cell 92 from a charger (not shown), and the discharging current flowing out of the battery cell 92 into a load (such as a portable device). Is detected by the resistor 93, and the bidirectional LMOSFET 50 is normally controlled, and in the case of an abnormality such as overcharge or overdischarge, a signal for turning off the bidirectional LMOSFET 50 is transmitted to the bidirectional LMOSFET 50. Note that the drive / protection circuit unit 51 includes a charge pump circuit 53, which can apply a voltage higher than the voltages of the first and second source terminals S1 and S2 of the bidirectional LMOSFET 50 to the gate terminal G. ing. The control terminal is a terminal for designating the remaining charge of the battery cell 92 from the outside.

FIG. 9 shows a method of manufacturing a semiconductor device according to the sixth embodiment of the present invention. FIGS. 9A to 9C are cross-sectional views showing the main part manufacturing process shown in the order of processes. This is a method of manufacturing the bidirectional LMOSFET of FIG.
An n-well region 2 is formed on a p-semiconductor substrate 1, followed by formation of a p-offset region 5 having a surface concentration of 1 × 10 ¹⁷ cm ⁻³ and a diffusion depth of 1 μm, and using the oxide film as a mask, the n-well region 2 to form a trench 3 of width 1.5 [mu] m, the heat treatment from the window of the trench 3 bottom 3a on a surface concentration of 1 × 10 ¹⁸ cm ^-3 of the trench 3, the n drain region 4 of the diffusion depth 1μm and ion implantation (drive) (FIG. 2A). Here, the trench 3 is formed after the well region 2 and the p offset region 5 are formed, but may be formed after the trench 3 is formed.
Next, a threshold adjustment ion implantation (not shown) is performed at a channel forming position on the trench side wall 3b at a chilled angle of 45 degrees to form a diffusion layer having a surface concentration of 7 × 10 ¹⁶ cm ⁻³ and a diffusion depth of 0.3 μm. To do. Subsequently, the channel forming portion is cleaned, a gate insulating film 6 (for example, a gate oxide film) is formed on the inner wall of the trench, and doped polysilicon serving as the gate electrode 7 is formed on the gate insulating film 6 to a thickness of 0.3 μm. Then, a gate electrode 7 is formed by anisotropic etching ((b) in the figure).

  Next, first and second n source regions 9 and 10 are formed on the surface layer of the p offset region 5, and an oxide film is deposited as the interlayer insulating film 8. In this step, the trench is filled with the interlayer insulating film 8, and the surface of the interlayer insulating film 8 is flattened by etch back. Subsequently, ion implantation for reducing contact resistance is performed on the first and second n source regions 9 and 10, and the first and second source electrodes 11 and 11 are formed on the first and second n source regions 9 and 10 with aluminum or the like. 12 is formed. Subsequently, a first source wiring and a second source wiring (not shown) are formed (FIG. 3C).

FIG. 10 shows a method of manufacturing a semiconductor device according to a seventh embodiment of the present invention. FIGS. 10A to 10C are cross-sectional views showing the main part manufacturing process shown in the order of processes. This is a method of manufacturing the bidirectional LMOSFET of FIG.
The difference from FIG. 9 is that, in FIG. 10C, p contact regions 15 and 16 are formed, and the first and second source electrodes 11 and 12 and the p contact regions 15 and 16 are in contact with each other.

FIG. 11 shows a method of manufacturing a semiconductor device according to an eighth embodiment of the present invention. FIG. 11A to FIG. 11C are cross-sectional views showing a main part manufacturing process shown in the order of steps. This is a method of manufacturing the bidirectional LMOSFET of FIG.
An n-well region 2 is formed on a p-semiconductor substrate 1, a trench 33 having a width of 3 μm is formed in the n-well region 2 using an unillustrated oxide film as a mask, and a surface concentration of 1 × is applied from the window of the trench 33 to the bottom surface 33a of the trench. An n source region 34 having a density of 10 ¹⁸ cm ⁻³ and a diffusion depth of 1 μm is formed by ion implantation and heat treatment (drive). Subsequently, the mask oxide film is removed, and an isolation semiconductor region 61 divided by the trench 33 is formed so that the p offset region 35 having a surface concentration of 1 × 10 ¹⁷ cm ⁻³ and a diffusion depth of 1 μm is in contact with the n drain region 34. It forms (the figure (a)).
Next, ion implantation for threshold adjustment (not shown) is performed at a chilled angle of 45 degrees in the channel formation portion of the sidewall 33b of the trench, and a diffusion layer having a surface concentration of 7 × 10 ¹⁶ cm ⁻³ and a diffusion depth of 0.3 μm. Form. Subsequently, the channel forming portion is cleaned, a gate insulating film 36 is formed on the inner wall of the trench, and doped polysilicon serving as the gate electrode 37 is deposited on the gate insulating film 36 to a thickness of 0.3 μm, and anisotropic A gate electrode 37 is formed by etching (FIG. 5B).

  Next, first and second n drain regions 39 and 40 are formed in the surface layer of the p offset region 35, and an oxide film is deposited as the interlayer insulating film 38. In this step, the wide trench is not filled with the interlayer insulating film 38, and the interlayer insulating film 38 at the bottom of the trench is removed by etching and the surface of the n source region 34 is exposed. Subsequently, a barrier metal (not shown) is formed on the bottom surface 33 of the trench, and a pickup electrode 45 such as tungsten is buried and planarized. Subsequently, ion implantation for reducing contact resistance is performed on the first and second drain regions 39, 40, and the first and second drain electrodes 41, 41 are formed on the first and second n drain regions 39, 40 with aluminum or the like. 42 is formed. At this time, an aluminum film is also formed on the pickup electrode 45 at the same time. Subsequently, a first drain wiring and a second drain wiring (not shown) are formed ((c) in the figure).

FIG. 12 shows a method of manufacturing a semiconductor device according to a ninth embodiment of the present invention. FIGS. 12A and 12B are cross-sectional views of the main part manufacturing process corresponding to FIG. ), (D) are cross-sectional views of the main part manufacturing process corresponding to FIG. FIGS. 7A and 7C are cross-sectional views of the main part manufacturing process corresponding to X1-X1 in FIG. 7A, and FIGS. 7B and 7D are X2-X2 in FIG. 7A. It is principal part manufacturing process sectional drawing corresponded to. This is a method of manufacturing the bidirectional LMOSFET of FIG.
11 differs from FIG. 11 in that a p base pickup region 46 is formed at the bottom of the trench in FIG. 12A, and the pickup electrode 45 and this p base pickup region 46 are in contact with each other in FIG. .

FIG. 13 shows a method of manufacturing a semiconductor device according to the tenth embodiment of the present invention. FIG. 13A to FIG. This is a manufacturing method in which the bidirectional LMOSFET and the CMOS of FIG. 1 are formed on the same semiconductor substrate. The CMOS is a basic element for forming the drive / protection circuit and remaining amount circuit of FIG.
An n well region 72 is formed on a p semiconductor substrate 71, a trench 73 having a width of 1.5 μm is formed in the n well region 72 using an oxide film (not shown) as a mask, a p well region 76 is also formed, and a window of the trench 73 is formed. Then, an n drain region 74 having a surface concentration of 1 × 10 ¹⁷ cm ⁻³ and a diffusion depth of 1 μm is formed on the bottom surface 73a of the trench by ion implantation and heat treatment (drive). Subsequently, the mask oxide film is removed, and a p-offset region 75 having a surface concentration of 1 × 10 ¹⁷ cm ⁻³ and a diffusion depth of 1 μm is formed (FIG. 1A).

Next, element isolation on the surface is performed by a LOCOS process, and ion implantation for threshold adjustment (not shown) is performed at a chilled angle of 45 degrees in the channel formation portion of the CMOS portion and the channel formation portion of the trench side wall 73b to obtain a surface concentration of 7 ×. A diffusion layer having a density of 10 ¹⁶ cm ⁻³ and a diffusion depth of 0.3 μm is formed. Subsequently, the channel forming portion is cleaned, a gate insulating film 79 is formed on the inner wall of the trench, and doped polysilicon serving as the gate electrode 80 is deposited on the gate insulating film 79 to a thickness of 0.3 μm. The gate electrode 80 inside the CMOS portion and the trench is formed by reactive etching ((b) in the figure).
Next, first and second n source regions 81 and 82 are formed on the surface layer of the p offset region 75, source / drain regions 83 and 84 are formed in the CMOS portion, and an oxide film is deposited as an interlayer insulating film 87. In this step, the trench is filled with an interlayer insulating film 87, and the surface of the interlayer insulating film 87 is flattened by etch back. Subsequently, a contact hole is formed in the interlayer insulating film 87, plug ion implantation for reducing contact resistance is performed in the opening, and the first and second n-type source regions 81 and 82 are made of aluminum with the first and second layers. Source electrodes 85 and 86 are formed, and source / drain electrodes 88 and 89 are formed on the source / drain regions 83 and 84 in the CMOS portion (FIG. 5C).

  An embodiment including a gate wiring structure, which is a semiconductor device different from the semiconductor device of the present invention described above, will be described. The gate wiring and the source electrode are simultaneously formed of a metal film. Here, a source electrode connected to a contact hole and disposed immediately above a source region is a source electrode, and a gate wiring is a portion other than that.

FIGS. 14 to 17 show a semiconductor device according to an eleventh embodiment of the present invention, which is a configuration diagram of a main part including a gate wiring structure, FIG. 14 is a plan view, and FIG. 15 is a line XX in FIG. 16 is a cross-sectional view taken along the line YY of FIG. 14, and FIG. 17 is a cross-sectional view taken along the line ZZ of FIG. FIG. 14 is a plan view seen from the surface, and the portion hidden behind the shadow is indicated by a dotted line. Further, the interlayer insulating film 208a is not shown.
Only the differences from FIG. 1 will be described. In FIG. 1, one first n source region 9 and one second n source region 10 are alternately arranged. However, in this embodiment, the first n source region 209 is adjacent to each other. A plurality of second n source regions 210 are formed adjacent to each other. Further, the p offset region 205 is not in contact with the n drain region 204. Further, p contact regions 215 and 216 are formed in each source region as in FIG. FIG. 1 shows a gate wiring structure not shown.

When the p offset region 205 is not in contact with the n drain region 204, the breakdown voltage can be increased and the on-resistance can be reduced as compared with the case where the p offset region 205 is not in contact. However, since the width of the p offset (the width between the n-well region 202 and the source region 209) is narrow, high accuracy is required during manufacturing.
As shown in FIGS. 14 to 17, the first source electrode 211 connected to the first n source region 209 via the contact hole 217 formed in the interlayer insulating film 208 a and the first source connected to the first source electrode 211. The wiring 213 is formed of a metal film at the same time. The second source electrode 212 connected to the second n source region 210 via the contact hole 217 formed in the interlayer insulating film 208a and the second source wiring 214 connected to the second source electrode 212 are simultaneously formed of a metal film. It is formed. The adjacent first n source regions 209 and the second n source regions 210 are filled with a gate electrode 207 formed through a gate insulating film 206. The first n source region 209 group and the second n source region 210 group are opposed to each other with the interlayer insulating film 208 interposed therebetween. The current capacity can be increased by enlarging the trench outer periphery 203a and arranging the first n source region 209 group and the second n source region 210 group alternately in large numbers.

The polysilicon forming the gate electrode 207 forms an elongated trench 203b protruding like a cape from the trench outer periphery 203a in which the n source regions 209 and 210 are formed, and a gate insulating film formed on the inner wall of the trench 203b A polysilicon wiring 218 is formed via 206, and this polysilicon wiring 218 is also formed on the gate insulating film 206 formed on the p semiconductor substrate 201. The polysilicon wiring 218 and the metal film gate wiring 219 are connected through a contact hole 217 opened in the interlayer insulating film 208a.
Thus, in the semiconductor device of the present invention described above, the gate electrode 207 is one because it is connected by the polysilicon (gate electrode 207) formed over the entire side wall of the trench outer periphery 203a.
An example of an application apparatus using a semiconductor device having a single gate electrode is shown in FIG.

FIG. 18 is a diagram in which the bidirectional LMOSFET and the drive / protection circuit unit in FIG. 8 are extracted. FIGS. 18A to 18C show the time course when the battery cell is overcharged. FIG.
8A, when the battery cell 92 of FIG. 8 is charged with a portable device (not shown) connected thereto, an ON signal is given to the gate terminal G, and the left and right n-channel MOSFETs are turned on. The charging current I1 flows from the right to the left through the bidirectional LMOSFET 50 in the battery cell 92. At this time, the discharge current I2 is supplied from the battery cell 92 to the load. That is, the battery cell 92 is not charged but also discharged.
In FIG. 6B, when the battery cell 92 is overcharged, an off signal is given to the gate terminal G to turn off the left and right n-channel MOSFETs. When the left and right n-channel MOSFETs are turned off, the load and the battery cell 92 are disconnected in a circuit manner, the charging current I1 does not flow to the battery cell 92, and overcharging stops. At the same time, the discharge current I2 is not supplied from the battery cell 92 to the load. If the battery charger in FIG. 8 is unplugged during this overcharge period, no current is supplied to the load, and the load becomes inoperable.

In order to avoid this, as shown in FIG. 3C, an ON signal is again applied to the gate terminal G to turn on the bidirectional LMOSFET 50, and the discharge current I2 is supplied from the battery cell 92 to the load. However, since it detects that the voltage of the battery cell 92 has become a normal voltage and outputs an ON signal from the drive / protection circuit 51, a time delay occurs, and no current is supplied from the battery cell 92 to the load during that time. A state, that is, an instantaneous interruption occurs.
As a method of solving this, there is a method of using a bidirectional LMOSFET in which a gate electrode is provided for each of the left and right n-channel MOSFETs.
FIG. 19 is an equivalent circuit diagram of a bidirectional LMOSFET having two gate electrodes. This is a view corresponding to FIG.
The difference from FIG. 6 is that there are two gate electrodes, so that the gate terminal G in FIG. 6 is the two terminals of the first gate terminal G1 and the second gate terminal G2, and the n-channel MOSFETs 331 and 332 are respectively The point is that they can be operated individually, and the point that the parasitic diodes 333 and 334 of the n-channel MOSFET are used for the operation.

Next, an operation mode using the bidirectional LMOSFET 300 having the two gate electrodes will be described.
FIG. 20 is a diagram corresponding to FIG. 18, and FIGS. 20A to 20C are diagrams illustrating a time course when the battery cell is overcharged.
In FIG. 9A, an ON signal is given to the first and second gate terminals G1 and G2 from the drive / protection circuit 51, the left and right n-channel MOSFETs 331 and 332 are turned on, and the charging current I1 flows to the battery cell 92. . At this time, the discharge current I2 is supplied from the battery cell 92 to the load. That is, the battery cell 92 is not charged but also discharged.
In FIG. 5B, when the battery cell 92 is overcharged, an off signal is given to the first gate terminal G1, and the charging current I1 is stopped. At this time, the ON signal is left applied to the second gate terminal G2. Then, even if the charging current I1 is stopped, the discharge current I2 flows to the load through the parasitic diode 333 and the n-channel MOSFET 332, so that the instantaneous interruption does not occur.

In FIG. 5C, when the battery cell 92 returns to the normal voltage, the ON signal is again applied to the first gate terminal G1, and the left n-channel MOSFET 331 is turned ON. In this state, the discharge current I2 is supplied to the load via the left and right n-channel MOSFETs 331 and 332, and the normal operation is resumed.
In this way, by using the bidirectional LMOSFET 300 having two gate electrodes, the current to the load is supplied without interruption.
Next, the structure of a semiconductor device having two gate electrodes will be described.

  FIGS. 21 to 25 show a semiconductor device according to a twelfth embodiment of the present invention. FIG. 21 is a main part configuration diagram including a gate wiring, FIG. 21 is a plan view, and FIG. 22 is an AA line in FIG. 23 is a cross-sectional view taken along the line BB in FIG. 21, FIG. 24 is a cross-sectional view taken along the line CC in FIG. 21, and FIG. 25 is cut along the line DD in FIG. It is sectional drawing. FIG. 21 is a plan view seen from the surface, the portion hidden behind the shadow is indicated by a dotted line, and the interlayer insulating film 308a is not shown. In the trench, there are a plurality of islands 341 and 342 which are columnar trench remaining portions. In this figure, there are six islands 341 (device cells) operating as MOSFETs (islands where 309 and 310 in the figure are formed). There are two islands 342 forming the gate wiring. A p offset region 305, n source regions 309 and 310, and source electrodes 311 and 312 are formed on the island 341. The difference from FIGS. 14 to 17 is that the first gate electrode 307a and the second gate electrode 307b whose gate electrodes are surrounded by the interlayer insulating film 308 are independent, and these gate electrodes 307a and 307b The side wall 303a is separated from the polysilicon 307, and the gate electrodes 307a and 307b are connected to the metal first gate wiring 319 and the second gate wiring 320 via the polysilicon wiring 318, respectively. is there.

As described above, since the polysilicon 307 formed in the trench outer periphery 303a, the first gate electrode 307a and the second gate electrode 307b are separated by the interlayer insulating film 308, the island 341 in which the first n source region 309 is formed; The interval W1 between the islands 341 in which the second n source region 310 is formed is wide enough not to be filled with polysilicon for forming the gate electrode. On the other hand, the distance Wg1 between the islands 341 forming the first and second n source regions 309 and 310 is set to be completely filled with polysilicon forming the gate electrode. The gap Wg2 between the island 342 that forms the polysilicon wiring 318 for connecting the gate electrodes 307a and 307b to the metal gate wiring 319 and 320 and the island 341 that forms the n source regions 309 and 310 is also filled with polysilicon. Therefore, the same interval as Wg1 is used.
For example, when the thickness of the polysilicon forming the gate electrode is 0.3 μm, W1 is about 1 μm, and Wg1 and Wg2 are about 0.5 μm. In order to planarize the surface, W1 is preferably set to be equal to or smaller than the width of the island 341 forming the source region.

  In this manner, by forming the independent first gate electrode 307a and second gate electrode 307b, the effect described in FIG. 20 can be obtained.

26 to 29 are views showing a method of manufacturing a semiconductor device according to a thirteenth embodiment of the present invention, and are principal part process sectional views shown in the order of processes. In each figure, (a) is a cross-sectional view of a part corresponding to FIG. 22, (b) is a cross-sectional view of a part corresponding to FIG. 23, and (c) is a cross-sectional view of a part corresponding to FIG.
In FIG. 26, for example, an n-well region 302 having a surface concentration of 5 × 10 ¹⁶ cm ⁻² and a depth of about 4 μm is formed in the surface layer of the p semiconductor substrate 301, and a trench 303 reaching the n-well region 302 from the surface is formed in a mesh shape. Are formed to have a depth of about 2 μm, and trench-remaining portions, so-called islands 341 and 342 are formed in a columnar shape. The islands 341 and 342 are connected to the island 341 that forms the first and second p offset regions, the first and second n source regions, and the first and second gate electrodes and the first and second gate wirings in a later step. It becomes an island 342 that forms the polysilicon wiring 318.

The interval Wg1 between the islands 341 and the interval Wg2 between the islands 341 and 342 are equal to about 0.5 μm, so that the polysilicon is not separated even by polysilicon etchback (polysilicon patterning). Can be filled with. Further, by setting the interval W1 between the islands 341 and 342 and the sidewall of the trench outer periphery 303a and the interval W1 between the islands 341 forming the first source region 309 and the second source region 310 to 1 μm or more, the polysilicon is etched. At the back, the polysilicon can be completely separated.
In FIG. 27, a gate insulating film 306 is formed, and an n drain region 304 is formed at a high concentration of 1 × 10 ¹⁷ cm ⁻³ or more in the n well region 302 at the bottom of the trench in order to have a breakdown voltage of about 30 V to 50 V. Then, the p offset region 305 is formed apart from the n drain region 304 (sometimes connected). Thereafter, polysilicon to be the first and second gate electrodes 307a and 307b and the polysilicon wiring 318 is formed on the entire surface with a thickness of about 0.3 μm, and the polysilicon is formed between the islands 341 and between the islands 341 and 342. After completely filling with silicon, patterning is performed.

In FIG. 28, first and second n source regions 309 and 310 are formed at a high concentration of 1 × 10 ²⁰ cm ⁻³ or more using the first and second gate electrodes 307a and 307b as masks. A high-concentration p contact region 316 that penetrates the regions 309 and 310 and reaches the p offset region 305 is formed, and an interlayer insulating film 308a is formed on the surface.
In FIG. 29, a contact hole 317 is formed in the interlayer insulating film 308a, and the first and second source electrodes of the metal connected to the first and second n source regions 309 and 310 and the p contact regions 315 and 316 through the contact hole 317. 311 and 312, and first and second source lines 313 and 314 formed simultaneously with the first and second source electrodes 311 and 312, and a polysilicon line formed simultaneously with the first and second gate electrodes 307 a and 307 b Metal first and second gate wirings 319 and 320 connected to 318 are formed.

  When the thickness of polysilicon such as a gate electrode is about 0.3 μm, W1 is preferably 1 μm or more, and is preferably less than the width of the island in order to flatten the surface. Wg1 = Wg2 is preferably 0.5 μm or less.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the semiconductor device of 1st Example of this invention, (a) is a principal part top view, (b) is the A section enlarged view of (a), (c) is XX line of (b). Sectional view of the main part cut by 2A is a diagram of a configuration different from FIG. 1, in which FIG. 1A is a diagram in which an n-well region also serves as an n-drain region 4 in FIG. 1C, and FIG. The figure which also serves as an n drain region, (c) is a diagram in which an n drain region 4 is further formed in (b). 1 is an equivalent circuit diagram of the bidirectional LMOSFET of FIG. It is a block diagram of the semiconductor device of 2nd Example of this invention, (a) is a principal part top view equivalent to FIG.1 (b), (b) is the principal part cut | disconnected by the XX line of (a). Cross section It is a block diagram of the semiconductor device of 3rd Example of this invention, (a) is a principal part top view, (b) is the B section enlarged view of (a), (c) is XX line of (b). Sectional view of the main part cut by FIG. 5 is an equivalent circuit diagram of the bidirectional LMOSFET. It is a block diagram of the semiconductor device of 4th Example of this invention, (a) is a principal part top view equivalent to FIG.5 (b), (b) is the principal part cross section cut | disconnected by X1-X1 of (a). Figure, (c) is a cross-sectional view of the principal part cut at X2-X2 of (a) Principal part layout of a semiconductor device according to a fifth embodiment of the present invention FIG. 6 is a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention, wherein (a) to (c) are cross-sectional views of the main part manufacturing process shown in the order of processes; FIG. 7 is a manufacturing method of a semiconductor device according to a seventh embodiment of the present invention, wherein FIGS. FIG. 8 is a method for manufacturing a semiconductor device according to an eighth embodiment of the present invention, wherein FIGS. FIG. 11 shows a manufacturing method of a semiconductor device according to a ninth embodiment of the present invention, in which (a) and (b) are cross-sectional views of main part manufacturing steps corresponding to FIG. 11 (a), and (c) and (d) are FIG. c) Main part manufacturing process cross-sectional view corresponding to FIG. 10 is a manufacturing method of a semiconductor device according to a tenth embodiment of the present invention, and FIGS. Plan view of relevant part of a semiconductor device according to an eleventh embodiment of the present invention. Sectional drawing cut | disconnected by the XX line of FIG. Sectional drawing cut | disconnected by the YY line of FIG. Sectional drawing cut | disconnected by the ZZ line | wire of FIG. FIG. 9 is a diagram in which the bidirectional LMOSFET and the drive / protection circuit unit in FIG. 8 are extracted and (a) to (c) are diagrams illustrating a time course when the battery cell is overcharged. Equivalent circuit diagram of bidirectional LMOSFET having two gate electrodes FIG. 19 is a diagram corresponding to FIG. 18 in the case of using a bidirectional LMOSFET having two gate electrodes, and (a) to (c) are diagrams showing a time course when a battery cell is overcharged. The principal part top view of the semiconductor device of 12th Example of this invention Sectional drawing cut | disconnected by the AA line of FIG. Sectional drawing cut | disconnected by the BB line of FIG. Sectional drawing cut | disconnected by CC line of FIG. Sectional drawing cut | disconnected by the DD line | wire of FIG. It is principal part process sectional drawing of the manufacturing method of the semiconductor device of 13th Example of this invention, (a) is sectional drawing of the location corresponding to FIG. 22, (b) is sectional drawing of the location corresponding to FIG. (C) is a sectional view of a portion corresponding to FIG. 26 is a sectional view of the principal part of the method for fabricating the semiconductor device according to the thirteenth embodiment of the present invention continued from FIG. 26, (a) is a sectional view of a portion corresponding to FIG. 22, and (b) is equivalent to FIG. Sectional drawing of a location, (c) is a sectional view of a location corresponding to FIG. 27 is a sectional view of the principal part of the semiconductor device manufacturing method according to the thirteenth embodiment of the present invention continued from FIG. 27, (a) is a sectional view of a portion corresponding to FIG. 22, and (b) is equivalent to FIG. Sectional drawing of a location, (c) is a sectional view of a location corresponding to FIG. 28 is a sectional view of the principal part of the semiconductor device manufacturing method according to the thirteenth embodiment of the present invention continued from FIG. 28, (a) is a sectional view of a portion corresponding to FIG. 22, and (b) is equivalent to FIG. Sectional drawing of a location, (c) is a sectional view of a location corresponding to FIG. Sectional view of the main part of a conventional bidirectional LIGBT The figure which shows the output characteristic of bidirectional | two-way LIGBT of FIG. Sectional view of the main part of another conventional bidirectional MOSFET The figure which shows the output characteristic of bidirectional | two-way LIGBT of FIG.

Explanation of symbols

1, 71 201, 301 p semiconductor substrate
2, 72 202, 302 n-well region
3, 33, 73, 203, 303 trench
3a, 33a, 73a Bottom
3b, 33b, 73b Side
4, 74, 204, 304 n drain region
5, 35, 75, 205, 305 p offset region
6, 36, 79, 206, 306 Gate insulating film
7, 37, 80, 207 Gate electrode
8, 38, 87, 208, 208a, 308, 308a Interlayer insulating film
9, 81, 209, 309 First n source region 10, 82, 210, 310 Second n source region 11, 85, 211, 311 First source electrode 12, 86, 212, 312 Second source electrode 13, 213, 313 First 1 source wiring 14, 214, 314 2nd source wiring 15, 16, 215, 216, 315, 316 p contact region 34 n source region 39 1n drain region 40 2n drain region 41 1st drain electrode 42 2nd drain electrode 43 first drain wiring 44 second drain wiring 45 pickup electrode 46 p base pickup region 50, 60 bidirectional LMOSFET
51 drive / protection circuit unit 52 remaining amount circuit unit 53 charge pump circuit 61 divided semiconductor region 70, 90, 91 semiconductor substrate 83, 84 source / drain region 88, 89 source / drain electrode 92 battery device 203a, 303a outer periphery of trench 203b protruding Trench 307 Polysilicon 217, 317 Contact hole 218, 318 Polysilicon wiring 219 Gate wiring 300 Bidirectional LMOSFET
307a First gate electrode 307b Second gate electrode 319 First gate wiring 320 Second gate wiring 331, 332 n-channel MOSFET
333, 334 Parasitic diode 341, 342 Island
S1 First source terminal
S2 Second source terminal
G Gate terminal
G1 First gate terminal
G2 Second gate terminal
D1 first drain terminal
D2 Second drain terminal

Claims (5)

First and second divided semiconductor regions formed by dividing the surface layer of the well region by a trench formed from the surface of the well region in the well region of the first conductivity type,
The first divided semiconductor region and the trench are provided in one direction parallel to the surface of the well region from the trench, and the second divided semiconductor region and the trench are provided in a direction opposite to the one direction. In the repeating region of the trench and the first and second divided semiconductor regions, and in the repeating region,
A drain region of a first conductivity type formed from the bottom of the trench to the side wall;
A first offset region of a second conductivity type formed on the surface layer of the first divided semiconductor region in contact with the sidewalls of the trench and the drain region on both sides of the first divided semiconductor region;
A first source region of a first conductivity type formed on a surface layer of the first offset region, in contact with a sidewall of the trench on both sides of the first divided semiconductor region, and in contact with the first offset region;
A first contact region of a second conductivity type formed on a surface layer of the first offset region in contact with the first offset region;
A first gate electrode formed on a sidewall of the trench on both sides of the first divided semiconductor region through the first insulating film from the drain region to the first source region. When,
A first source electrode in contact with the first source region and the first contact region;
A second conductivity type second offset region formed on the surface layer of the second divided semiconductor region in contact with the sidewalls of the trench and the drain region on both sides of the second divided semiconductor region;
A second source region of a first conductivity type formed on a surface layer of the second offset region, in contact with a sidewall of the trench on both sides of the second divided semiconductor region, and in contact with the second offset region;
A second contact region of a second conductivity type formed on the surface layer of the second offset region in contact with the second offset region;
A second gate electrode formed on a sidewall of the trench on both sides of the second divided semiconductor region of the second divided semiconductor region from the drain region to the second source region via a second insulating film; When,
A second source electrode in contact with the second source region and the second contact region,
The first gate electrode and the second gate electrode are electrically insulated;
The drain region is a drain, the first offset region is a channel, the first source region is a source, a first MOSFET, the drain region is a drain, the second offset region is a channel, and the second source region is a source. A second MOSFET and a bidirectional element connected in series;
A bidirectional element, wherein the bidirectional element is an element for causing a current to flow between the first source electrode and the second source electrode. The bidirectional device according to claim 1 , wherein the well region is a region selectively formed in a surface layer of a second conductivity type semiconductor substrate. 3. Both according to claim 1 or 2 , wherein a plurality of the first and second divided semiconductor regions are provided, and the trench width between adjacent divided semiconductor regions is wider than between the same regions. Direction element. First and second divided semiconductor regions formed by dividing the surface layer of the well region by a trench formed from the surface of the well region in the well region of the first conductivity type,
The first divided semiconductor region and the trench are provided in one direction parallel to the surface of the well region from the trench, and the second divided semiconductor region and the trench are provided in a direction opposite to the one direction. In the repeating region of the trench and the first and second divided semiconductor regions, and in the repeating region,
A source region of a first conductivity type formed across the sidewall from the bottom of the trench selectively in a direction perpendicular to the one direction and parallel to the surface of the well region;
A contact region of a second conductivity type formed across the sidewall from the bottom of the trench in a region that is selectively formed in the vertical direction and in which the source region is not formed;
A first conductivity type first offset region formed on a surface layer of the first divided semiconductor region in contact with the sidewalls of the trench, the source region and the contact region on both sides of the first divided semiconductor region; ,
A first drain region of a first conductivity type formed on a surface layer of the first offset region, in contact with a sidewall of the trench on both sides of the first divided semiconductor region, and in contact with the first offset region;
A first gate electrode formed on a sidewall of the trench on both sides of the first divided semiconductor region of the first divided semiconductor region through a first insulating film from the source region to the first drain region. When,
A first drain electrode in contact with the first drain region;
A second conductivity type second offset region formed on the surface layer of the second divided semiconductor region in contact with the sidewalls of the trench, the source region, and the contact region on both sides of the second divided semiconductor region; ,
A second drain region of a first conductivity type formed on a surface layer of the second offset region, in contact with a sidewall of the trench on both sides of the second divided semiconductor region, and in contact with the second offset region;
A second gate electrode formed on the sidewall of the trench on both sides of the second divided semiconductor region of the second divided semiconductor region from the source region to the second drain region via a second insulating film. When,
A second drain electrode in contact with the second drain region;
A conductor in contact with the source region and the contact region through an insulating film between the first gate electrode and the second gate electrode;
The first gate electrode and the second gate electrode are electrically insulated;
A first MOSFET having the source region as a source, the first offset region as a channel, and the first drain region as a drain, the source region as a source, the second offset region as a channel, and the second drain region as a drain. A second MOSFET and a bidirectional element connected in series;
A bidirectional element, wherein the bidirectional element is an element for allowing a current to flow between the first drain electrode and the second drain electrode. The bi-directional device, a semiconductor device including a two-way element according to any one of claims 1 to 4 formed a control circuit for controlling the bidirectional elements on the same semiconductor substrate.

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