JP4887662B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device including a lateral MOSFET (hereinafter also abbreviated as TLPM) in which a MOS gate structure is formed in a trench on a silicon (Si) substrate, and a semiconductor diffusion resistance element, and a manufacturing method thereof.

A conventional semiconductor device in which a trench lateral MOSFET (TLPM) and a diffusion resistance element are integrated is shown in FIG. 17, and a plan view of the TLPM portion 200 and the diffusion resistance element region 201 is shown in FIG. A cross-sectional view taken along the line -B is shown in FIG. In FIG. 17 (a), for the sake of understanding, it is partially drawn in perspective. Hereinafter, a conventional semiconductor device in which an N-channel TLPM portion 200 in which the bottom of a trench is an N drain region and a P-type diffusion resistance element region 201 are integrated will be described with reference to FIG.
The semiconductor device includes a P well region 101 and an N well region 102 formed in a surface layer of a P-type silicon substrate 100, a P offset region 103 formed in each well region, and a P offset region from the surface of the P offset region 103. , Trenches 104 and 105 formed to a depth reaching P well region 101 and N well region 102, N drain region 106 formed on the bottom surface of trench 104 of TLPM portion 200, and sidewalls of trench 104 of TLPM portion 200, respectively. (The gate oxide film 107 is simultaneously formed on the bottom of the trench 104, the substrate surface, and the inner surface of the trench 105 in the diffusion resistance element region and the substrate surface), and the gates on the sidewalls of the trenches 104 and 105. Gate electrode formed in contact with oxide film 107 08 (region indicated by dotted dispersion), an N source region 109 formed on the substrate surface of the P offset region 103 in the TLPM portion 200 and having one end exposed on the sidewall of the trench, the inside of the trenches 104 and 105, and the silicon substrate surface The interlayer insulating film 110 (region indicated by the dotted line) formed above, the interlayer insulating film 110 and the gate oxide film 107 are opened from the surface of the interlayer insulating film 110, and the N drain region 106 and the N source of the TLPM portion are respectively formed. Contact holes 111, 112, and 113 (areas indicated by thick diagonal lines, reference numeral 113 is shown in FIG. 17A) reaching the area 109 and the gate electrode 108, and the surface of the interlayer insulating film 110 in the diffusion resistance element area 201 A P plug region 115 formed on the substrate surface at the bottom of the contact hole 114 reaching the substrate surface by opening from , 112, 113, 114, barrier metal 116 formed on the side walls and bottom surface of each of them (regions indicated by slanted thin lines), plug metal conductor 117 filling each of the contact holes, and Al electrode wiring in contact with plug metal conductor 117. (Source, drain, gate, and resistor electrode wirings) 118, 119, 120, and 121.

  18 to 23 are cross-sectional views of the semiconductor substrate showing the method of manufacturing the semiconductor device shown in FIG. 17, and are cross-sectional views arranged in the order of main steps. As shown in FIG. 18, a P-well region 101 and an N-well region 102 are selectively formed on a P-type silicon substrate 100, and then a channel region of the TLPM portion 200 and a resistance portion of the diffusion resistance element region 201 are selectively formed. A P offset region 103 is formed. Next, as shown in FIG. 19, trenches 104 and 105 are formed in a portion where the TLPM portion 200 and the diffusion resistance element region 201 are formed using an oxide film (thermal oxide film or deposited oxide film) as a mask. The trenches 104 and 105 are formed to a depth reaching the P well region 101 and the N well region 102 from the substrate surface, respectively. An insulating film (not shown) that covers the inside of the trench 105 is further formed on the oxide film, and an N drain region 106 is selectively formed only on the bottom surface of the trench 104 of the TLPM portion 200. After removing the oxide film and the insulating film, as shown in FIG. 20, a selective oxide film (LOCOS) 119 for element isolation between the TLPM portion 200 and the diffusion resistance element area 201 is formed in a P well region with a thickness of, for example, 600 nm. 101 and N well region 102 are formed only in the vicinity. Next, as shown in FIG. 21, a gate oxide film 107 is formed on the entire surface with a thickness of 17 nm, for example, and a doped polysilicon gate electrode 108 with a thickness of 300 nm is formed on the trench 104 by CVD (Chemical Vapor Deposition) and etch back, for example. , 105 are formed on the side wall and the gate electrode lead-out region 122 (region surrounded by a one-dot chain line in FIG. 17A). At this time, as shown in FIG. 17A, the gate electrode lead region 122 is provided in the TLPM portion, but is not provided in the diffusion resistance element region, so that the polysilicon electrode 108 in the trench 105 is connected to the outside. In other words, even if a voltage is applied, it shows a floating potential. Then, as shown in FIG. 22, after forming the source region 109 of the TLPM portion 200, a trench buried oxide film 110 to be the interlayer insulating film 110 is formed by CVD, and the surface is flattened using chemical mechanical polishing (CMP). Turn into. Then, as shown in FIG. 23, contact holes 111, 112, and 113 (shown in FIG. 17A) in the TLPM portion are formed by a photolithography process, and contacts 114 are formed in the diffusion resistance element region, respectively. A P plug region 115 is formed at the bottom of the contact hole 114 in the resistance element region. Thereafter, a barrier metal 116, a buried plug 117, and a metal electrode wiring 118 are formed to complete a conventional semiconductor device in which TLPM and diffusion resistance elements are integrated.

The following are known techniques related to the semiconductor device as described above. In a semiconductor device comprising a plurality of active element regions and resistor element regions formed independently of each other on a semiconductor substrate, wherein the resistor elements are insulated and separated via a dielectric layer formed by a trench. There is a disclosure of an invention related to a semiconductor device having a resistance element region that can be integrated at a high density without forming a MOS structure (Patent Document 1).
Japanese Patent Publication No.7-112005

However, when manufacturing the above-described semiconductor device, doped polysilicon is formed on the trench side wall of the diffusion resistance element region via a thin gate oxide film in the same manner as the TLPM portion when manufacturing the TLPM region. Since the electrodes are formed simultaneously (FIG. 21), they remain (FIGS. 22 and 23). Although the polysilicon electrode on the diffusion resistance element region side is in a floating state in terms of potential as described above, it is charged up, and thus affects the P offset region via the oxide film. As a result, there arises a problem that the resistance value of the diffusion resistance element using the resistance value in this region is not stable or may change.
In addition, since there is only an N well region at the bottom of the trench in the diffusion resistance element region, there is a problem that punch through may occur between adjacent P offset resistors.
As a means for avoiding the former problem, it is considered that the trench is pre-filled with an insulating film by CVD and etch back before forming the polysilicon electrode layer, but the trench in the TLPM portion is also buried at the same time. This method cannot be used. Further, if the TLPM portion and the diffusion resistance element region are formed by separate steps, the above problem can be solved, but the number of steps is greatly increased, which is not realistic.

  The present invention has been made in view of the above problems, and an object of the present invention is to simultaneously apply doped polysilicon electrodes to the trench sidewalls of both the TLPM portion and the diffusion resistance element region via a gate oxide film. Even in a semiconductor device having a process of forming, the resistance value of the resistance element does not become unstable even when the doped polysilicon electrode formed in the diffusion resistance element region is charged up, and the diffusion resistance It is an object of the present invention to provide a semiconductor device that does not punch through between elements and a manufacturing method thereof.

According to the present invention as set forth in claim 1, the object of the present invention is to provide a first conductive type semiconductor substrate with a plurality of first trenches and a plurality of second trenches, wherein the first trenches are gated inside. A MOS gate structure including a gate electrode is formed through an insulating film, and a lateral MOS transistor region including a second conductivity type source region on the surface of the semiconductor substrate and a second conductivity type drain region at the bottom of the first trench is formed. In the semiconductor device having a function of surrounding the diffusion resistance element region and isolating and separating the plurality of diffusion resistance element regions from each other, the gate insulating film formed on at least a side wall of the second trench equipped with 100nm or thicker oxide film thicker than, and a floating electrode of the gate electrode formed simultaneously formed on the inner wall of the oxide film With the semiconductor device is achieved.
According to the second aspect of the present invention, the first conductivity type semiconductor substrate includes a plurality of first trenches and a plurality of second trenches, and the first trenches are gated through a gate insulating film inside. Forming a MOS gate structure including an electrode, and forming a lateral MOS transistor region including a second conductivity type source region on the surface of the semiconductor substrate and a second conductivity type drain region at the bottom of the first trench; In a semiconductor device having a function of surrounding a diffusion resistance element region and isolating and separating the plurality of diffusion resistance element regions from each other, a second conductivity type formed simultaneously with the second conductivity type drain region at the bottom of the second trench The object can also be achieved by forming a semiconductor device having a high concentration region.

According to the third aspect of the present invention, in the semiconductor device according to the second aspect, the oxide film having a thickness of 100 nm or more is provided on at least the side wall of the second trench. It is preferable.
According to the present invention as set forth in claim 4, the thickness of the oxide film is made half or more of the width of the second trench, so that the semiconductor device according to claim 1 or 3 is formed. Is also preferable.
According to the present invention as set forth in claim 5, the thickness of the oxide film is 300 nm or more and the width of the second trench is 600 nm or less. It is desirable to do.
According to the present invention, the first conductivity type well region and the second conductivity type well region are respectively formed on the surface of the semiconductor substrate, and the first conductivity type offset region is formed in each of the two regions. Forming first and second trenches so as to reach the first conductivity type and second conductivity type well regions respectively from the surfaces of both of the first conductivity type offset regions, and to the bottom of the first trench The formation of the second conductivity type drain region and the formation of the second conductivity type source region on the surface of the first conductivity type offset region on the first trench side are respectively performed, and the first trench side is formed as a lateral MOS transistor. And the second trench is formed as a diffused resistance element region by surrounding the first conductivity type offset region, and then the lateral MOS transistor region and After an oxidation process for simultaneously forming an oxide film for isolating the diffusion resistance element region and an oxide film having a thickness of 100 nm or more on at least a side wall of the second trench, a gate electrode is formed on the side wall of the first trench. An interlayer insulating film is formed through an insulating film, filling the first and second trenches and covering the surface of the semiconductor substrate, and reaches the bottom of the first trench and the surface of the semiconductor substrate from the surface of the interlayer insulating film. The object is achieved by forming a lateral MOS transistor opening and a diffusion resistance element opening, and a method of manufacturing a semiconductor device including a step of embedding a conductor in each of the openings.

According to the seventh aspect of the present invention, the thickness of the oxide film can be equal to or greater than half the width of the second trench.
8. The semiconductor device according to claim 6, wherein a second conductivity type high concentration region is formed simultaneously with the second conductivity type drain region at the bottom of the second trench. It is preferable to use a method for manufacturing the device.
In short, in order to solve the problem, the present invention is configured to have a thick oxide film on the side wall of the second trench in the diffusion resistance element region or the entire inner surface thereof.
The oxide film is formed by simultaneously oxidizing the second trench in the diffusion resistance element region when forming an oxide film for element isolation.
In addition, by setting the width of the second trench in the diffusion resistance element region to 600 nm or less, when an oxide film having a thickness of 300 nm or more is formed, the polysilicon film is not left inside the second trench, and only the oxide film is buried. This is more preferable because the polysilicon electrode is not formed in the second trench in the diffusion resistance element region.

A diffusion region having the same conductivity type as the well region exposed on the bottom surface and having a higher concentration than the well region is formed on the bottom surface of the second trench in the diffusion resistance element region.
The formation of the high-concentration diffusion region on the bottom surface of the second trench is a semiconductor device manufacturing method performed in the same process as the formation of the drain region formed at the bottom of the first trench in the lateral MOS transistor region.

According to the present invention, even in a semiconductor device including a step of simultaneously forming a doped polysilicon electrode on the trench sidewalls of both the TLPM portion and the diffusion resistance element region via the gate oxide film, the doping of the diffusion resistance element region is performed. It is possible to provide a semiconductor device that does not cause the resistance value of the resistive element to become unstable due to the charge-up of the polysilicon electrode or punch-through between the diffused resistive elements, and a method for manufacturing the same.
According to the present invention, a thick oxide film is sandwiched between the trench sidewall of the diffusion resistance element region and the polysilicon electrode even after the process of forming the gate electrode of the TLPM portion, or the polysilicon electrode is not formed inside the trench. The silicon electrode is not charged up, and the resistance value is not stabilized or changed.
In addition, when forming an oxide film for element isolation, a technique for forming an oxide film at the same time in the trench portion of the diffused resistor element region can be manufactured without increasing the number of processes.

Further, since a diffusion region having a higher concentration than the well is formed on the bottom surface of the trench in the diffusion resistance element region, punch-through is not performed between adjacent diffusion resistance elements.
Further, in the manufacturing method in which the formation of the high concentration diffusion region is performed in the same process as the formation of the drain region of the TLPM part, the semiconductor device according to the present invention can be manufactured without increasing the number of processes.

  1A is a plan view of a semiconductor substrate according to the present invention, FIG. 1B is a plan view of the semiconductor substrate, FIG. 1B is a sectional view of the semiconductor substrate cut along AA, and FIGS. It is sectional drawing of the semiconductor substrate which shows the manufacturing process of this semiconductor device. FIG. 8 is a cross-sectional view of a semiconductor substrate showing a different semiconductor device according to the present invention, and FIGS. 9 to 13 are cross-sectional views of the semiconductor substrate showing a manufacturing process of the different semiconductor device according to the present invention. FIG. 14 is a cross-sectional view of a semiconductor substrate showing still another semiconductor device according to the present invention, and FIGS. 15 to 16 are cross-sectional views of the semiconductor substrate showing a manufacturing process of still another semiconductor device according to the present invention.

Hereinafter, embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
In the following description, the P conductivity type and the N conductivity type may be replaced with the opposite conductivity types. Further, the names of the source and drain of the TLPM section may be reversed in accordance with the replacement of the conductivity type. The TLPM section may be a bidirectional TLPM section in which two MOSFETs are connected in series without having a contact at the bottom of the trench.
FIG. 1A is a schematic plan view showing a semiconductor device according to Embodiment 1 of the present invention, and FIG. 1B is a schematic cross-sectional view taken along line AA, showing a TLPM portion 300 and a diffusion resistance element region. 301 is formed on the same semiconductor substrate.

  The TLPM portion 300 includes a P well region 1 formed in the surface layer of the silicon substrate 00, a P offset region 3 formed in the P well region 1, a first trench 4 formed in the P offset region 3, and a bottom surface of the first trench 4 An N drain region 6 formed on the first trench 4, a gate oxide film 7 formed on the sidewall of the first trench 4 (the gate oxide film 7 is also formed on the bottom of the first trench and the substrate surface), and the sidewall of the first trench 4. The doped polysilicon gate electrode 8 formed on the gate oxide film 7, the N source region 9 formed on the surface layer of the P offset region 3 and having one end exposed on the side wall of the first trench 4, and the first trench 4 And an interlayer insulating film 10 formed on the surface of the N source region 9, and the interlayer insulating film 10 and the gate oxide film 7 are opened to form an N drain region 6, an N source region 9, or a gate electrode 8. Contact holes 11, 12, 13 to be formed, barrier metal 16 formed on the side walls and bottom surfaces of the contact holes 11, 12, 13, plug metal conductor 17 filling the contact holes 11, 12, 13, and plug metal conductor 17 Al electrode wirings 18, 19, and 20 formed in the above. The Al electrode wirings 18, 19, and 20 are a source electrode wiring, a drain electrode wiring, and a gate electrode wiring in this order.

  The diffusion resistance element region 301 includes an N well region 2 formed in the surface layer of the silicon substrate 00, a P offset region 3 formed in the N well region 2, a second trench 5 formed in the P offset region 3, and a second trench. 5, a thick selective oxide film (LOCOS oxide film) 19a formed on at least the side wall, an interlayer insulating film 10 formed in the inside of the second trench 5 and on the substrate surface, and the interlayer insulating film 10 opened from the surface to form a substrate Contact hole 14 reaching the surface, P plug region 15 formed on the bottom surface of contact hole 14, barrier metal 16 formed on the side wall and bottom surface of contact hole 14, plug metal conductor 17 filling contact hole 14, and plug metal And an Al electrode wiring 21 formed on the conductor 17. The Al electrode wiring 21 uses the resistance value in the P offset region between the reference numerals 21a and 21b in the planar unit denoted by reference numeral 301 in FIG.

In the semiconductor device of the first embodiment described above, the selective oxide film 19a for element isolation in the first embodiment is different from the conventional semiconductor device described with reference to FIG. It can be seen that the region extends to the inside of the trench 5. Thus, in the first embodiment, even if the polysilicon electrode 8a is formed in the trench 5 simultaneously with the trench 4, the selective oxidation thicker than the conventional thin gate oxide film is formed between the side wall of the trench 5 and the polysilicon electrode 8a. Since the film is interposed, the above-described problem that the doped polysilicon electrode 8a in the diffusion resistance element region is charged up and the resistance value of the diffusion resistance element becomes unstable can be solved.
2 to 7 are main-portion cross-sectional views of the semiconductor substrate showing the manufacturing method of the semiconductor device of Example 1 in the order of steps. As shown in FIG. 2, a P-well region 1 and an N-well region 2 are selectively formed on a P-type silicon substrate 00, and then a P offset region that selectively becomes a channel formation region and a diffusion resistance region of the TLPM section 300. 3 is formed. Next, as shown in FIG. 3, a first trench having a width of 3 μm and a depth of 2 μm is formed by using an oxide film (thermal oxide film or deposited oxide film) as a mask in a portion where the TLPM portion 300 and the diffusion resistance element region 301 are formed. 4. A second trench 5 having a width of 1.5 μm and a depth of 2 μm is formed at the same time, and an insulating film (not shown) covering the inside of the trench 5 is further formed on the oxide film. An N drain region 6 is selectively formed only on the bottom surface of the trench 4. After removing the oxide film and the insulating film, as shown in FIG. 4, a selective oxide film 19a for element isolation is formed with a thickness of, for example, 600 nm by the LOCOS method. At this time, the LOCOS oxide film 19 is simultaneously formed in the second trench 5 portion of the diffusion resistance element. Next, as shown in FIG. 5, a gate oxide film 7 is formed with a thickness of, for example, 17 nm, and then doped polysilicon gate electrodes 8 and 8a with a thickness of 300 nm are formed by CVD and etch back methods. At this time, as shown in FIG. 1, in the TLPM portion 300, the lead region 22 of the gate electrode 8 is provided, but the diffusion resistance element region 301 is not provided with a corresponding region. As a result, the polysilicon electrode 8a in the trench 5 in the diffusion resistance element region 301 becomes a floating electrode that is not connected to the external electrode. Then, as shown in FIG. 6, after forming the source region 9 of the TLPM section 300, a buried oxide film is formed by CVD in the trenches 4 and 5 to be the interlayer insulating film 10, and chemical mechanical polishing (CMP) is used. Flatten the surface. Then, as shown in FIG. 7, contact holes 11, 12, 13, and 14 are formed at necessary portions by a photolithography process, and a P plug region 15 is formed at the bottom of the contact hole 14 of the diffusion resistance element 301. Thereafter, the barrier metal 16, the buried metal plug 17, and the metal electrode wirings 18, 19, 20, and 21 are formed.

  According to the manufacturing method of the first embodiment, the above-described problem can be solved only by enlarging the element isolation region in the region where the LOCOS oxide film is formed so as to include the diffusion resistance element region.

FIG. 8 is a schematic cross-sectional view showing a semiconductor device according to Example 2 of the present invention.
The TLPM section 300 has the same configuration as that of the first embodiment, and the diffusion resistance element region 301 includes an N well region 2 formed in the surface layer of the silicon substrate 00, a P offset region 3 formed in the N well region 2, and a P offset. Trench 5 formed in region 3, N drain region 6a having a higher impurity concentration than the N well region formed on the bottom of trench 5, interlayer insulating film 10 formed in the trench 5 and on the substrate surface, and interlayer insulating film 10 A contact hole 14 reaching the substrate surface by opening a hole, a P plug region 15 formed on the bottom surface of the contact hole 14, a barrier metal 16 formed on the side wall and bottom surface of the contact hole 14, and a plug metal conductor filling the contact hole 14 17 and electrode wiring 21 formed on the plug metal conductor.
In the semiconductor device of the second embodiment, since the N drain region 6a having a higher impurity concentration than the N well region is formed at the bottom of the trench 5 in the diffusion resistance element region 301, punch-through does not occur between adjacent diffusion resistance elements.

  9 to 13 are cross-sectional views of relevant parts of the semiconductor substrate showing the method of manufacturing the semiconductor device according to the second embodiment. The formation up to the P offset region 3 is the same as that in FIG. 2 of the first embodiment, and thereafter, as shown in FIG. 9, an oxide film (thermal oxide film or , A trench oxide 4 having a width of 3 μm and a depth of 2 μm and a trench 5 having a width of 1.5 μm and a depth of 2 μm are formed using the deposited oxide film) as a mask. N drain regions 6 and 6a are formed. After removing the mask oxide film, as shown in FIG. 10, a selective oxide film 19a for element isolation is formed only in the element isolation region with a thickness of, for example, 600 nm by the LOCOS method. Next, as shown in FIG. 11, a gate oxide film 7 is formed on the entire surface with a thickness of 17 nm, for example, and a doped polysilicon gate electrode with a thickness of 300 nm, for example, is formed in the trenches 4 and 5 by CVD and etch back methods. To do. At this time, the gate electrode lead-out region 22 (FIG. 1A) is provided in the TLPM section 300, but the diffusion resistance element region 301 is not provided and the polysilicon electrode 8a is in a floating state. Then, as shown in FIG. 12, after forming the source region 9 of the TLPM section 300, the trench 4 and the 5 buried oxide film to be the interlayer insulating film 10 are formed by CVD, and the surface is formed by chemical mechanical polishing (CMP). To flatten. Then, as shown in FIG. 13, contact holes 11, 12, 13, and 14 are formed in necessary portions by a photolithography process, and a P plug region 15 is formed at the bottom of the contact hole 14 in the diffusion resistance element region 301. Thereafter, barrier metal 16, buried plug 17, and Al metal electrode wirings 18, 19, 20, 21 are formed.

  According to the manufacturing method of the second embodiment, as described above, the formation of the N drain region 6a in the diffusion resistance element region 301 performed to prevent punch-through between adjacent diffusion resistance elements is the N drain region in the TLPM section 300. Since it is carried out simultaneously with the formation of the above, there is an effect that the above-mentioned problems can be efficiently solved without increasing a new process.

FIG. 14 is a schematic sectional view showing Embodiment 3 of the present invention. The feature of the third embodiment is a combination of the first embodiment and the second embodiment. With this configuration, even if the doped polysilicon electrode formed in the diffusion resistance element region 301 is charged up, the resistance is reduced. This is preferable in that the resistance value of the element does not become unstable, and a semiconductor device that does not punch through between the diffusion resistance elements can be obtained.
15 and 16 are cross-sectional views of the main part of the semiconductor substrate showing the method of manufacturing the semiconductor device described in the third embodiment of the present invention. This is a combination of the manufacturing methods of Example 1 and Example 2. Even if the doped polysilicon electrode formed in the diffusion resistance element region 301 is charged up, the resistance value of the resistance element does not become unstable even with the semiconductor device of this embodiment, which is a problem of the present invention. In addition, a semiconductor device that does not punch through between the diffusion resistance elements can be manufactured extremely efficiently without increasing the number of steps from the conventional method.

The principal part block diagram of the semiconductor device concerning this invention, (a) is a top view, (b) is sectional drawing cut | disconnected by AA Sectional drawing of the semiconductor substrate which shows the manufacturing process of the semiconductor device concerning this invention (the 1) Sectional drawing of the semiconductor substrate which shows the manufacturing process of the semiconductor device concerning this invention (the 2) Sectional drawing of the semiconductor substrate which shows the manufacturing process of the semiconductor device concerning this invention (the 3) Sectional drawing of the semiconductor substrate which shows the manufacturing process of the semiconductor device concerning this invention (the 4) Sectional drawing of the semiconductor substrate which shows the manufacturing process of the semiconductor device concerning this invention (the 5) Sectional drawing of the semiconductor substrate which shows the manufacturing process of the semiconductor device concerning this invention (the 6) Sectional drawing of the semiconductor substrate which shows a different semiconductor device concerning this invention Sectional drawing of the semiconductor substrate which shows the manufacturing process of this semiconductor device concerning the present invention (the 1) Sectional drawing of the semiconductor substrate which shows the manufacturing process of a different semiconductor device concerning the present invention (the 2) Sectional drawing of the semiconductor substrate which shows the manufacturing process of a different semiconductor device concerning the present invention (the 3) Sectional drawing of the semiconductor substrate which shows the manufacturing process of a different semiconductor device concerning the present invention (the 4) Sectional drawing of the semiconductor substrate which shows the manufacturing process of a different semiconductor device concerning the present invention (the 5) Sectional drawing of the semiconductor substrate which shows the further different semiconductor device concerning this invention Sectional drawing of the semiconductor substrate which shows the manufacturing process of the further different semiconductor device concerning this invention (the 1) Sectional drawing of the semiconductor substrate which shows the manufacturing process of the further different semiconductor device concerning the present invention (the 2) FIG. 2 is a main part configuration diagram of a conventional semiconductor device, FIG. Sectional drawing of the semiconductor substrate which shows the manufacturing process of the conventional semiconductor device (the 1) Sectional drawing of the semiconductor substrate which shows the manufacturing process of the conventional semiconductor device (the 1) Sectional drawing of the semiconductor substrate which shows the manufacturing process of the conventional semiconductor device (the 2) Sectional drawing of the semiconductor substrate which shows the manufacturing process of the conventional semiconductor device (the 3) Sectional drawing of the semiconductor substrate which shows the manufacturing process of the conventional semiconductor device (the 4) Sectional drawing of the semiconductor substrate which shows the manufacturing process of the conventional semiconductor device (the 5)

Explanation of symbols

00 ... Silicon substrate 1 ... P well region 2 ... N well region 3 ... P offset region 4 ... First trench 5 ... Second trench 6 ... N drain region 7 ... Gate oxide film 8 ... Doped polysilicon gate electrode 8a ... Floating Electrode 9 ... N source region 10 ... Interlayer insulating film 11, 12, 13, 14 ... Opening 15 ... P plug region 16 ... Metal barrier 17 ... Embedded metal plug 18, 19, 20, 21 ... Al metal electrode wiring 22 ... Gate Electrode extraction region 300... TLPM portion 301... Diffusion resistance element region.

Claims (8)

The first conductivity type semiconductor substrate includes a plurality of first trenches and a plurality of second trenches, and the first trench forms a MOS gate structure including a gate electrode through a gate insulating film, and is formed on the surface of the semiconductor substrate. A second conductivity type source region, a lateral MOS transistor region having a second conductivity type drain region at the bottom of the first trench is configured, and the second trench surrounds the diffusion resistance element region and includes a plurality of the diffusion resistance element regions. In a semiconductor device having a function of insulating and isolating from each other, an oxide film having a thickness of 100 nm or more thicker than the gate insulating film formed at least on the side wall of the second trench and an inner wall of the oxide film A semiconductor device comprising: a floating electrode formed simultaneously with the gate electrode . The first conductivity type semiconductor substrate includes a plurality of first trenches and a plurality of second trenches, and the first trench forms a MOS gate structure including a gate electrode through a gate insulating film, and is formed on the surface of the semiconductor substrate. A second conductivity type source region, a lateral MOS transistor region having a second conductivity type drain region at the bottom of the first trench is configured, and the second trench surrounds the diffusion resistance element region and includes a plurality of the diffusion resistance element regions. A semiconductor device having a function of insulating and isolating from each other, wherein the second trench has a second conductivity type high concentration region formed simultaneously with the second conductivity type drain region at the bottom of the second trench. The semiconductor device according to claim 2, wherein an oxide film having a thickness of 100 nm or more is provided on at least a side wall of the second trench. 4. The semiconductor device according to claim 1, wherein the thickness of the oxide film is set to be not less than half of the width of the second trench. 5. The semiconductor device according to claim 4, wherein the thickness of the oxide film is 300 nm or more and the width of the second trench is 600 nm or less. A first conductivity type well region and a second conductivity type well region are respectively formed on the surface of the semiconductor substrate, and a first conductivity type offset region is formed in each of the two regions, and from both surfaces of the first conductivity type offset region, Forming first and second trenches to reach the first conductivity type and second conductivity type well regions, respectively, forming a second conductivity type drain region at the bottom of the first trench, A source region of a second conductivity type is formed on the surface of the first conductivity type offset region, and the first trench side is used as a lateral MOS transistor region, and the second trench is the first conductivity type offset region. After forming the diffused resistive element region by forming a shape surrounding the gate electrode, the lateral MOS transistor region and the diffused resistive element region are oxidized for element isolation. And an oxidation step of simultaneously forming an oxide film having a thickness of 100 nm or more on at least the side wall of the second trench, a gate electrode is formed on the side wall of the first trench through a gate insulating film, and the first, second, An interlayer insulating film that fills the trench and covers the surface of the semiconductor substrate is formed, and a lateral MOS transistor opening and a diffusion resistance element opening that reach the bottom of the first trench and the surface of the semiconductor substrate from the surface of the interlayer insulating film. Forming a hole and embedding a conductor in each of the openings. A method for manufacturing a semiconductor device, comprising: 7. The method of manufacturing a semiconductor device according to claim 6, wherein the thickness of the oxide film is not less than half of the width of the second trench. 8. The method of manufacturing a semiconductor device according to claim 6, wherein a second conductivity type high concentration region is formed simultaneously with the second conductivity type drain region at the bottom of the second trench.

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