JP5788678B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a polysilicon layer inside and outside a trench formed in a semiconductor layer, and a method for manufacturing the same.

  2. Description of the Related Art Conventionally, a semiconductor device having a structure in which a trench is formed in a semiconductor layer and embedded in a polysilicon layer in the trench has been used. An example of such a semiconductor device is a trench gate type MISFET (Metal-Insulator-Semiconductor Field-Effect-Transistor). Another example is a micro electro mechanical systems (MEMS) device. The trench gate type MISFET has a structure in which a conductive polysilicon layer embedded in a trench formed in a semiconductor layer is used as a gate electrode as disclosed in Patent Document 1, for example. A gate insulating film is formed on the inner wall of the trench, and the gate electrode faces the semiconductor layer through the gate insulating film. A MEMS device is an apparatus in which a certain structure is formed by processing a semiconductor substrate such as silicon. Even in such a MEMS device, a conductive polysilicon layer may be embedded in a trench formed in a semiconductor substrate.

JP 2010-27796 A

The inventor of the present application is examining a structure using a conductive polysilicon film not only in the trench but also outside the trench in the semiconductor device as described above. Such a conductive polysilicon film can be used as a wiring film or as an electrode of a capacitor.
When manufacturing a semiconductor device having such a structure, a step of embedding a conductive polysilicon layer in the trench and a step of separately forming a conductive polysilicon film outside the trench are necessary. The step of embedding conductive polysilicon in the trench includes, for example, a step of forming a polysilicon film on the entire surface of the semiconductor substrate, and a step of etching back and removing the polysilicon outside the trench. The step of forming the conductive polysilicon film outside the trench includes, for example, a step of forming a polysilicon film over the entire surface of the semiconductor substrate and a step of patterning the polysilicon film by photolithography. Thus, since there are many processes, productivity is bad and there exists a fault which becomes expensive according to it.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device manufacturing method capable of reducing the number of processes and improving productivity. Another object of the present invention is to provide a semiconductor device having a structure capable of reducing the number of processes and improving productivity.

According to a first aspect of the present invention for achieving the above object, a step of forming a well for element isolation in a power element region of a semiconductor layer on a semiconductor substrate, and a region surrounded by the well of the semiconductor layer Forming a trench on the semiconductor layer, forming an insulating film on the semiconductor layer so as to cover an inner wall of the trench and a surface outside the trench, filling the trench, and forming the trench on the insulating film outside the trench. is deposited, further wherein the step of forming the power element so that also formed in the capacitor region provided outside the region of the conductive polysilicon film on a semiconductor substrate, in the trench, and the insulating outside the trench upper predetermined region of the well on the film, as well as the polysilicon layer in the capacitor region remains, to selectively remove the polysilicon film Capacitor including a polysilicon etch process, and a capacitor film stacked so as to be in contact with the polysilicon film of the capacitor area, forming a stacked conductive films in contact with the capacitor film, the polysilicon film Forming a structure in the capacitor region .

The invention according to claim 2 is a method of manufacturing a semiconductor device according to claim 1, further comprising an insulating film etching step of etching the insulating film so that the insulating film remains on the inner wall of the trench and the predetermined region. There is .

According to a third aspect of the present invention , a logic region is provided outside the power element region on the semiconductor substrate, the insulating film is also formed on a surface of the semiconductor layer in the logic region, and in the insulating film etching step, The insulating film on the semiconductor layer in the logic region is etched, and further includes a step of forming a thermal oxide film on the exposed surface of the semiconductor layer in the logic region after the insulating film etching step. Or a method of manufacturing a semiconductor device according to 2 ;

4. The semiconductor device according to claim 1, further comprising a film thickness reducing step for reducing the film thickness of the polysilicon film before the polysilicon etching step. It is a manufacturing method .

As described in claim 5, the film thickness reduction process includes any one of a chemical mechanical polishing process, an etch back process, and a combination process of thermal oxide film formation and etching thereof. Is preferred.
According to a sixth aspect of the present invention, the trench has a side wall along the depth direction of the trench, and the semiconductor layer has a source region, a channel region, and a drain region so as to be adjacent to the side wall. The method of manufacturing a semiconductor device according to claim 1, wherein the polysilicon film in the trench is a gate electrode facing the channel region through the insulating film .

The invention according to claim 7 is the method for manufacturing a semiconductor device according to any one of claims 1 to 6 , further comprising a step of forming an interlayer insulating film on the capacitor structure and the trench .

According to an eighth aspect of the present invention , a power element region and a capacitor region provided outside the power element region are formed on a semiconductor substrate, and the power element region is formed with a trench and a well for element isolation. A first insulating film that covers the inner wall of the trench, a second insulating film that covers the surface of the semiconductor layer in a predetermined region outside the trench, and has a thickness equal to the first insulating film; embedded in the trench, a first conductive polysilicon layer opposite the inner wall surface of the trench through the first insulating film, over the Oite the wells on the second insulating layer outside the trench is formed, said saw including a second conductive polysilicon layer having the same composition as the first conductive polysilicon layer, the capacitor region, a third conductive policy having the same composition as the first conductive polysilicon layer A capacitor layer laminated to be in contact with the third conductive polysilicon layer, and a conductive film laminated to be in contact with the capacitive film, the third conductive polysilicon layer, the capacitance In the semiconductor device, a capacitor structure including a film and the conductive film is provided in the capacitor region .

The invention according to claim 9 is the semiconductor device according to claim 8 , further comprising a thermal oxide film formed on a surface of the semiconductor layer exposed from the second insulating film .
A tenth aspect of the present invention is the semiconductor device according to the ninth aspect , wherein a film thickness of the first insulating film is different from a film thickness of the thermal oxide film .

According to an eleventh aspect of the present invention, the trench has a sidewall along the depth direction of the trench, and the semiconductor layer has a source region, a channel region, and a drain region so as to be adjacent to the sidewall. and is a polysilicon film in said trench, said first a gate electrode facing the channel region via an insulating film, a semiconductor device according to any one of claims 8-10.

A twelfth aspect of the present invention is the semiconductor device according to any one of the eighth to eleventh aspects, wherein a film thickness of the third conductive polysilicon layer of the capacitor structure is 1 μm or less .

1A to 1E are cross-sectional views for explaining a method of manufacturing a semiconductor device according to one reference embodiment. 2A to 2F are cross-sectional views for explaining a method of manufacturing a semiconductor device according to another reference embodiment. Figure 3 is a schematic plan view for explaining the structure of a semiconductor device according to an embodiment of the present invention. Figure 4 is a sectional view showing a configuration of a main portion before the semiconductor device according to you facilities embodiment. Figure 5A is a cross-sectional view showing the manufacturing process before the semiconductor device according to you facilities embodiment. FIG. 5B is a cross-sectional view showing a step subsequent to FIG. 5A. FIG. 5C is a cross-sectional view showing a step subsequent to FIG. 5B. FIG. 5D is a cross-sectional view showing a step subsequent to FIG. 5C. FIG. 5E is a cross-sectional view showing a step subsequent to FIG. 5D. FIG. 5F is a cross-sectional view showing a step subsequent to FIG. 5E. FIG. 5G is a cross-sectional view showing a step subsequent to FIG. 5F. FIG. 5H is a cross-sectional view showing a step subsequent to FIG. 5G. FIG. 5I is a cross-sectional view showing a step subsequent to FIG. 5H. FIG. 5J is a cross-sectional view showing a step subsequent to FIG. 5I. FIG. 5K is a cross-sectional view showing a step subsequent to FIG. 5J. FIG. 5L is a cross-sectional view showing a step subsequent to FIG. 5K. FIG. 5M is a cross-sectional view showing a step subsequent to FIG. 5L. FIG. 5N is a cross-sectional view showing a step subsequent to FIG. 5M. FIG. 5O is a cross-sectional view showing a step subsequent to FIG. 5N. FIG. 5P is a cross-sectional view showing a step subsequent to FIG. 5O. FIG. 5Q is a cross-sectional view showing a step subsequent to FIG. 5P. FIG. 5R is a cross-sectional view showing a step subsequent to FIG. 5Q. FIG. 5S is a cross-sectional view showing a step subsequent to FIG. 5R. FIG. 5T is a cross-sectional view showing a step subsequent to FIG. 5S. FIG. 5U is a cross-sectional view showing a step subsequent to FIG. 5T. FIG. 5V is a cross-sectional view showing a step subsequent to FIG. 5U. FIG. 5W is a cross-sectional view showing a step subsequent to FIG. 5V. FIG. 5X is a cross-sectional view showing a step subsequent to FIG. 5W.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1A to 1E are cross-sectional views for explaining a method of manufacturing a semiconductor device according to one reference embodiment. As shown in FIG. 1A, a trench 2 is formed on the surface of the semiconductor layer 1. Next, as illustrated in FIG. 1B, an insulating film 3 (for example, an oxide film) is formed on the semiconductor layer 1 so as to cover the inner wall of the trench 2 and the surface of the semiconductor layer 1 outside the trench 2. Thereafter, as shown in FIG. 1C, the conductive polysilicon film 4 is formed so as to fill the trench 2 and to be deposited also on the insulating film 3 outside the trench 2. Then, as shown in FIG. 1D, a resist 5 is selectively formed in a predetermined region on the insulating film 3 outside the trench 2. Using this resist 5 as a mask, the polysilicon film 4 is etched. This etching is performed until there is no polysilicon film 4 in the region not covered with the resist 5 outside the trench 2. Thereafter, the resist 5 is removed to leave the conductive polysilicon film 4 in the predetermined region, as shown in FIG. 1E. That is, the first conductive polysilicon layer 41 is formed in the trench 2, and the second conductive polysilicon layer 42 is formed in the predetermined region outside the trench 2.

  Since the first and second conductive polysilicon layers 41 and 42 are both part of the polysilicon film 4, they have the same composition. The insulating film 3 includes a first insulating film 31 formed on the inner wall of the trench 2 and a second insulating film 32 formed between the second conductive polysilicon layer 42 and the semiconductor layer 1. These first and second insulating films 31 and 32 are both part of the insulating film 3 and are covered with first and second conductive polysilicon layers 41 and 42 formed in the same process. Therefore, they are made of the same material and have the same film thickness.

Thus, according to this reference embodiment, since the first and second polysilicon layers 41 and 42 can be simultaneously formed, can reduce the number of processes can be improved and cost reduction of the productivity accordingly .
2A to 2F are cross-sectional views for explaining a method of manufacturing a semiconductor device according to another reference embodiment. 2A to 2F, parts corresponding to those in FIGS. 1A to 1E are denoted by the same reference numerals.

  First, as shown in FIG. 2A, a trench 2 is formed on the surface of the semiconductor layer 1. Next, as shown in FIG. 2B, an insulating film 3 (for example, an oxide film) is formed on the semiconductor layer 1 so as to cover the inner wall of the trench 2 and the surface of the semiconductor layer 1 outside the trench 2. Thereafter, as shown in FIG. 2C, the conductive polysilicon film 4 is formed so as to fill the trench 2 and to be deposited also on the insulating film 3 outside the trench 2.

  Next, as shown in FIG. 2D, a film thickness reduction process for reducing the film thickness of the polysilicon film 4 is performed. Thereby, the thickness of the polysilicon film 4 on the semiconductor layer 1 outside the trench 2 is reduced to a required thickness. Therefore, for example, in order to fill the trench 2 with the polysilicon film 4, even if the thickness of the polysilicon film 4 outside the trench 2 is larger than the required thickness, the trench 2 The film thickness of the outer polysilicon film 4 can be adjusted.

  Next, as shown in FIG. 2E, a resist 5 is selectively formed in a predetermined region on the insulating film 3 outside the trench 2. Using this resist 5 as a mask, the polysilicon film 4 is etched. This etching is performed until there is no polysilicon film 4 in the region not covered with the resist 5 outside the trench 2. Thereafter, the resist 5 is removed to leave the conductive polysilicon film 4 in the predetermined region, as shown in FIG. 2F. That is, the first conductive polysilicon layer 41 is formed in the trench 2, and the second conductive polysilicon layer 42 is formed in the predetermined region outside the trench 2.

  Since the first and second conductive polysilicon layers 41 and 42 are both part of the polysilicon film 4, they have the same composition. The insulating film 3 includes a first insulating film 31 formed on the inner wall of the trench 2 and a second insulating film 32 formed between the second conductive polysilicon layer 42 and the semiconductor layer 1. These first and second insulating films 31 and 32 are both part of the insulating film 3 and are covered with first and second conductive polysilicon layers 41 and 42 formed in the same process. Therefore, they are made of the same material and have the same film thickness.

Thus, according to this reference embodiment, since the first and second polysilicon layers 41 and 42 can be simultaneously formed, can reduce the number of processes can be improved and cost reduction of the productivity accordingly . Since the second polysilicon layer 42 is formed by patterning the polysilicon film 4 having a reduced thickness, the second polysilicon layer 42 can be formed to a necessary and sufficient thickness. For example, depending on the depth and width of the trench 2, the thickness of the polysilicon film 4 may have to be formed larger than that required for the second polysilicon layer 42. Even in such a case, the second polysilicon layer 42 can be formed with the minimum necessary film thickness.

  Further, by forming the polysilicon film 4 thick, a recess (a depression) 4 a generated on the surface of the polysilicon film 4 immediately above the trench 2 can be reduced. That is, when the polysilicon film 4 is thin, a clear recess 4 a is formed on the surface of the polysilicon film 4 immediately above the trench 2. On the other hand, if the polysilicon film 4 is formed thick, the profile of the recess 4a can be blunted, and the recess amount is reduced accordingly. Therefore, when the polysilicon film 4 is subsequently etched to expose the insulating film 3, the recess 41a of the first conductive polysilicon layer 41 in the trench 2 is also reduced. As a result, the facing area between the conductive polysilicon layer 41 and the sidewall of the trench 2 can be accurately controlled, so that the characteristics of the device can be stabilized. In particular, when a large number of trenches 2 are formed in the semiconductor layer 1, it is possible to improve the uniformity of the amount of depression of the first conductive polysilicon layer 41 in the large number of trenches 2. Thereby, the characteristic variation of the semiconductor device can be reduced.

Figure 3 is a schematic plan view for explaining the structure of a semiconductor device according to an embodiment of the present invention. The semiconductor device 10 is configured by forming a plurality of element regions 12, 13, and 14 on a semiconductor substrate 11. For example, the element region 12 may be a power element region in which a large number of power device cells are formed. The element region 13 may be a capacitor region in which one or more capacitors 15 are formed. Further, the element region 14 may be a logic region in which logic elements constituting a logic circuit are formed. Hereinafter, the element regions 12, 13, and 14 are referred to as “power element region 12”, “capacitor region 13”, and “logic region 14”, respectively.

  As shown in the partial enlarged plan view, the power element region 12 includes a plurality of linear trenches 20 formed in a stripe shape. Each end of the trench 20 is commonly connected to an interconnect trench 21 formed so as to be orthogonal to the longitudinal direction of the trench 20. Furthermore, a plurality of extraction trenches 22 having a T-shaped connection end in a plan view are connected to the interconnection trench 21. A conductive polysilicon layer is embedded in the trenches 20, 21, and 22. A contact portion 23 made of a conductive polysilicon layer is formed outside the trench 22 at the connection end of the lead trench 22. The conductive polysilicon layer constituting the contact portion 23 is continuous with the conductive polysilicon layer in the extraction trench 22 and is therefore electrically connected to each other.

FIG. 4 is a cross-sectional view showing the configuration of the main part of the semiconductor device 10. The semiconductor substrate 11 includes an n ⁺ type silicon substrate 16 and an n type epitaxial layer 17 grown on the n ⁺ type silicon substrate 16. In the n ⁺ -type silicon substrate 16, an electrode film 18 is formed on the surface (back surface) opposite to the n-type epitaxial layer 17. Functional elements having different structures are formed in the power element region 12, the capacitor region 13, and the logic region 14 in the n-type epitaxial layer 17 and on the surface thereof. A trench VDMOS (Vertical Double diffused MOS) type transistor 19 is formed in the power element region 12. A capacitor 15 is formed in the capacitor region 13. The logic region 14 includes a low breakdown voltage n-channel MOSFET 52, a low breakdown voltage p-channel MOSFET 53, a low breakdown voltage depletion n-channel MOSFET 54, a high breakdown voltage n-channel MOSFET 55, a field p-channel MOSFET 56, and a polysilicon resistor 57. And are formed.

  As described above, the trench VDMOS transistor 19 has a plurality of trenches 20 formed in a stripe shape. FIG. 4 shows only two trenches 20 for the sake of simplicity. A polysilicon gate 45 that is a first conductive polysilicon layer is buried in the trench 20. A gate oxide film 46 as an insulating film is formed between the polysilicon gate 45 and the inner wall surface of the trench 20. That is, the gate oxide film 46 is formed so as to cover the inner wall surface of the trench 20. The polysilicon gate 45 is opposed to the n-type epitaxial layer 17 that forms the inner wall surface of the trench 20 with the gate oxide film 46 interposed therebetween.

A p-type well 61 for element isolation is formed in the n-type epitaxial layer 17. For example, the p-type well 61 is formed in an annular shape surrounding the trenches 20, 21, and 22 (see FIG. 3) formed in the power element region 12 in plan view. A field oxide film 161 is formed on the surface of the n-type epitaxial layer 17 so as to surround the p-type well 61 in plan view. A p-type base layer 71 is formed in the surface layer portion of the n-type epitaxial layer 17 in a region exposed from the field oxide film 161. The trench 20 is formed so as to penetrate from the front surface to the back surface of the p-type base layer 71 and further reach the n-type epitaxial layer 17 immediately below the p-type base layer 71. An n ⁺ type source layer 81 is formed on the p type base layer 71 so as to be in contact with the trench 20. A p ⁺ type contact layer 91 is formed on the p type base layer 71. Between a pair of adjacent trenches 20, a pair of n ⁺ -type source layers 81 are formed to extend in stripes in the longitudinal direction of trench 20 (direction perpendicular to the paper surface of FIG. 4) so as to be in contact with each trench 20. A p ⁺ -type contact layer 91 extending linearly in the longitudinal direction of the trench 20 is formed between them. Further, an interlayer insulating film 101 is formed so as to cover the surface of the p-type base layer 71. A contact hole 111 is formed in the interlayer insulating film 101. A source electrode 121 electrically connected to the n ⁺ type source layer 81 and the p ⁺ type contact layer 91 through the contact hole 111 is formed on the interlayer insulating film 101. Above the p-type well 61, a polysilicon wiring 47, which is an example of a second conductive polysilicon layer, is formed in the interlayer insulating film 101. The polysilicon wiring 47 is connected to the metal layer 48 on the interlayer insulating film 101. The contact portion 23 shown in FIG. 3 is made of the same conductive polysilicon layer as the polysilicon wiring 47 and is formed simultaneously with the polysilicon wiring 47.

  The metal layer 48 and the source electrode 121 are covered with another interlayer insulating film 131. A contact hole 132 is formed in the interlayer insulating film 131. A metal wiring layer 133 is formed on the interlayer insulating film 131. The metal wiring layer 133 is connected to the source electrode 121 through the contact hole 132. The metal wiring layer 133 is covered with a passivation film 134. A pad opening 135 is formed in the passivation film 134 at a predetermined position on the metal wiring layer 133. The metal wiring layer 133 in the region exposed from the pad opening 135 is used as a pad 136 for external connection. In this embodiment, the passivation film 134 is composed of a laminated film of a lower layer 134A and an upper layer 134B laminated on the lower layer 134A. For example, the lower layer 134A may be made of silicon nitride, and the upper layer 134B may be made of polyimide.

The n ⁺ -type source layer 81 is a source region, the region facing the trench 20 in the p-type base layer 71 is a channel region, and the n-type epitaxial layer 17 and the n ⁺ -type silicon substrate 16 below the p-type base layer 71 are This is the drain region. The polysilicon gate 45 embedded in the trench 20 faces the channel region (p-type base layer 71) with the gate oxide film 46 interposed therebetween. Therefore, by applying a control voltage higher than a predetermined threshold voltage to the polysilicon gate 45, an inversion layer is formed in the channel region (near the inner wall surface of the trench 20). Thereby, conduction between the source and the drain is established.

The low breakdown voltage n-channel MOSFET 52 includes a p-type well 62 formed in the n-type epitaxial layer 17 and another p-type well 142 formed in a shallow region of the surface layer portion of the p-type well 62. A channel stop layer 152 is formed on the periphery of the p-type well 142, and a field oxide film 162 is formed on the channel stop layer 152. In a region surrounded by the field oxide film 162, a pair of n ⁺ -type source / drain layers 82 are formed on the surface layer portion of the p-type well 142. A gate insulating film 172 is formed on the surface of the p-type well 142. A polysilicon gate 182 is disposed on the gate insulating film 172 so as to face the region between the n ⁺ -type source / drain layers 82. A contact hole 192 that penetrates the field oxide film 162 is formed, and a p ⁺ -type contact layer 92 is formed in a surface layer portion of the p-type well 142 in a region immediately below the contact hole 192. Further, an interlayer insulating film 102 is formed so as to cover the field oxide film 162, the polysilicon gate 182, the n ⁺ -type source / drain layer 82 and the like. A plurality of contact holes 112 are formed in the interlayer insulating film 102. On the interlayer insulating film 102, electrodes 122 are formed that are electrically connected to the n ⁺ -type source / drain layer 82 and the p ⁺ -type contact layer 92 through the contact holes 112, respectively. The electrode 122 is covered with the interlayer insulating film 131 described above.

The low breakdown voltage p-channel MOSFET 53 includes a p-type well 63 formed in the n-type epitaxial layer 17 and an n-type well 203 formed in a shallow region of the surface layer portion of the p-type well 63. A field oxide film 163 is formed above the peripheral edge of the n-type well 203. In a region surrounded by the field oxide film 163, a pair of p ⁺ -type source / drain layers 93 are formed on the surface layer portion of the n-type well 203. A gate insulating film 173 is formed on the surface of the n-type well 203. A polysilicon gate 183 is arranged on the gate insulating film 173 so as to face the region between the p ⁺ type source / drain layers 93. A contact hole 193 penetrating the field oxide film 163 is formed, and an n ⁺ -type contact layer 83 is formed in a surface layer portion of the n-type well 203 in a region immediately below the contact hole 193. Further, an interlayer insulating film 103 is formed so as to cover the field oxide film 163, the polysilicon gate 183, the p ⁺ type source / drain layer 93, and the like. A plurality of contact holes 113 are formed in the interlayer insulating film 103. On the interlayer insulating film 103, electrodes 123 electrically connected to the p ⁺ type source / drain layer 93 and the n ⁺ type contact layer 83 through the contact holes 113 are formed. The electrode 123 is covered with the interlayer insulating film 131 described above.

The low breakdown voltage depletion n-channel MOSFET 54 includes a p-type well 64 formed in the n-type epitaxial layer 17 and another p-type well 144 formed in a shallow region of the surface layer portion of the p-type well 64. A channel stop layer 154 is formed on the peripheral edge of the p-type well 144, and a field oxide film 164 is formed on the channel stop layer 154. In a region surrounded by the field oxide film 164, a pair of n ⁺ -type source / drain layers 84 are formed on the surface layer portion of the p-type well 144. Further, between the pair of n ⁺ -type source-drain layer 84, n ⁺ -type than the source-drain layer 84 of low n-type impurity concentration n ^- -type layer 224 is formed. A gate insulating film 174 is formed on the surface of the pair of n ⁺ -type source / drain layers 84 and n ⁻ -type layer 224. On the gate insulating film 174, a polysilicon gate 184 is disposed so as to face a region (n ⁻ type layer 224) between the n ⁺ type source / drain layers 84. A contact hole 194 that penetrates the field oxide film 164 is formed, and a p ⁺ -type contact layer 94 is formed in a surface layer portion of the p-type well 144 in a region immediately below the contact hole 194. Further, an interlayer insulating film 104 is formed so as to cover the field oxide film 164, the polysilicon gate 184, the n ⁺ type source / drain layer 84, and the like. A plurality of contact holes 114 are formed in the interlayer insulating film 104. On the interlayer insulating film 104, electrodes 124 electrically connected to the n ⁺ type source / drain layer 84 and the p ⁺ type contact layer 94 via the contact holes 114 are formed. The electrode 124 is covered with the interlayer insulating film 131 described above.

The high breakdown voltage n-channel MOSFET 55 includes a p-type well 65 formed in the n-type epitaxial layer 17 and a shallow p-type well 145 formed in the peripheral region of the surface layer portion of the p-type well 65. A channel stop layer 155 is formed on the p-type well 145, and a field oxide film 165 is formed on the channel stop layer 155. In a region surrounded by the channel stop layer 155, a pair of n ⁺ -type source / drain layers 85 are formed on the surface layer portion of the p-type well 65. One (drain layer) of the pair of n ⁺ -type source / drain layers 85 is formed in an n-type well 205 formed in a shallow region of the p-type well 145. This n-type well 205 is formed under the field oxide film 165. The field oxide film 165 has an opening 165 a that exposes the surface of the p-type well 65 in a region between the n-type well 205 and the other (source layer) of the pair of n ⁺ -type source / drain layers 85. Is formed. A gate insulating film 175 is formed on the surface of the p-type well 145 in the opening 165a. A polysilicon gate 185 is disposed on the gate insulating film 175. Polysilicon gate 185 extends to the surface of field oxide film 165 outside opening 165a and is formed to reach a region above n-type well 205.

A pair of contact holes 195 penetrating the field oxide film 165 is also formed. A p ⁺ -type contact layer 95 is formed in the surface layer portion of the p-type well 145 in a region immediately below one contact hole 195. Another contact hole 195 is formed immediately above the n ⁺ type source / drain layer 85 in the n type well 205. Further, an interlayer insulating film 105 is formed so as to cover the field oxide film 165, the polysilicon gate 185, the n ⁺ type source / drain layer 85, and the like. A plurality of contact holes 115 are formed in the interlayer insulating film 105. On the interlayer insulating film 105, electrodes 125 electrically connected to the n ⁺ -type source / drain layer 85 and the p ⁺ -type contact layer 95 through contact holes 114 and 195 are formed. The electrode 125 is covered with the interlayer insulating film 131 described above.

The field p-channel MOSFET 56 includes a pair of p-type wells 146 formed in the shallow region of the surface layer portion of the n-type epitaxial layer 17 with a space therebetween, and a pair formed in the surface layer region in the p-type well 146. P ⁺ -type source / drain layer 96. The surface of n-type epitaxial layer 17 is covered with field oxide film 166. A polysilicon gate 186 is arranged on the field oxide film 166 so as to face the region between the pair of p-type wells 146. Further, a pair of contact holes 196 penetrating the field oxide film 166 is formed immediately above the pair of p ⁺ type source / drain layers 96. Further, an interlayer insulating film 106 is formed so as to cover the field oxide film 166, the polysilicon gate 186, and the like. In the interlayer insulating film 106, a pair of contact holes 116 is formed immediately above the pair of p ⁺ -type source / drain layers 96. On the interlayer insulating film 103, electrodes 126 electrically connected to the p ⁺ type source / drain layers 96 through contact holes 196 and 116 are formed. The electrode 126 is covered with the interlayer insulating film 131 described above.

The polysilicon resistor 57 includes a polysilicon layer 187 whose resistivity is adjusted by adding impurities. A p-type well 67 is formed in the n-type epitaxial layer 17 in a region where the polysilicon resistor 57 is formed. The surface of the n-type epitaxial layer 17 including the surface region of the p-type well 67 is covered with a field oxide film 167. A polysilicon layer 187 is formed on field oxide film 167. In the polysilicon layer 187, a pair of p ⁺ -type contact regions 97 are formed with a gap therebetween. Further, an interlayer insulating film 107 is formed so as to cover field oxide film 167 and polysilicon layer 187. A pair of contact holes 117 are formed in the interlayer insulating film 107 at positions corresponding to the pair of p ⁺ -type contact regions 97, respectively. On the interlayer insulating film 107, a pair of electrodes 127 that are electrically connected to the pair of p ⁺ -type contact regions 97 via the pair of contact holes 117 are formed. The electrode 127 is covered with the interlayer insulating film 131 described above.

  The capacitor 15 includes a lower polysilicon electrode film 44 that is an example of a second conductive polysilicon layer, an upper polysilicon electrode film 188, and an insulating film 43 serving as a capacitor film sandwiched between the upper and lower electrodes. A p-type well 68 is formed in the n-type epitaxial layer 17 in a region where the capacitor 15 is formed. The surface of the p-type well 68 is covered with a thermal oxide film 49 which is an example of an insulating film. A lower polysilicon electrode film 44 is formed on the thermal oxide film 49. The lower polysilicon electrode film 44 is made of a conductive polysilicon layer, and in this embodiment, has the same composition as the polysilicon gate 45 of the trench VDMOS transistor 19. Further, an insulating film 43 as a capacitive film is formed so as to cover the lower polysilicon electrode film 44. The insulating film 43 may be made of a nitride film. An upper polysilicon electrode film 188 is formed on the insulating film 43 and faces the lower polysilicon electrode film 44 with the insulating film 43 interposed therebetween. Thereby, a capacitor structure is formed.

In this embodiment, the upper polysilicon electrode film 188 is made of a conductive polysilicon layer, and is formed in a region surrounded by the lower polysilicon electrode film 44 in plan view (see FIG. 3). The lower polysilicon electrode film 44 has a protruding region 44a that protrudes from the upper polysilicon electrode film 188 in plan view.
The protruding region 44 a of the lower polysilicon electrode film 44 and the upper polysilicon electrode film 188 are covered with the interlayer insulating film 108. A plurality of contact holes 118 are formed in the interlayer insulating film 108 at positions corresponding to the upper polysilicon electrode film 188 and positions corresponding to the protruding regions 44 a of the lower polysilicon electrode film 44. A plurality of electrodes 128 electrically connected to the protruding regions 44a of the upper polysilicon electrode film 188 and the lower polysilicon electrode film 44 are formed on the interlayer insulating film 108 through the contact holes 118. Yes. The electrode 128 is covered with the interlayer insulating film 131 described above.

5A to 5X are cross-sectional views showing the manufacturing process of the semiconductor device 10 in the order of steps.
In the step shown in FIG. 5A, the n-type epitaxial layer 17 is grown on the n ⁺ -type silicon substrate 16 by silicon epitaxial growth performed while adding an n-type impurity (for example, As: arsenic). Then, a thick (for example, about 4500 mm) thermal oxide film 250 is formed on the surface of n-type epitaxial layer 17.

In the step shown in FIG. 5B, openings 251-255 and 257-258 corresponding to the p-type wells 61-65 and 67-68 are formed in the thick thermal oxide film 250 by photolithography and etching. Then, a thin (for example, about 500 mm) pad thermal oxide film 259 is formed on the surface of n-type epitaxial layer 17 exposed in openings 251-255 and 257-258. Thereafter, p-type impurity ions (for example, B ⁺ : boron ions) are implanted using thick oxide film 250 as a mask.

In the step shown in FIG. 5C, drive diffusion for activating the implanted p-type impurity ions is performed. Thereby, p-type wells 61-65 and 67-68 are formed in each region. Thereafter, thick oxide film 250 and pad thermal oxide film 259 are removed by etching, and pad oxide film 260 covering the entire surface of n-type epitaxial layer 17 is formed.
In the step shown in FIG. 5D, a resist mask 261 (indicated by a two-dot chain line) having openings 263 and 265 corresponding to the n-type wells 203 and 205 is formed on the pad oxide film 260 by photolithography. Using this resist mask 261 as a mask, n-type impurity ions (for example, P ⁺ : phosphorus ions) are implanted. Thereafter, the resist mask 261 is peeled off, an annealing process (heat treatment) is performed, and the implanted n-type impurity ions are activated, whereby n-type wells 203 and 205 are formed in each region. Then, etching for removing the pad oxide film 260 is performed.

  In the step shown in FIG. 5E, a thin pad thermal oxide film 267 that covers the entire surface of the n-type epitaxial layer 17 is formed. Further, a nitride film 268 as an oxidation resistant film is formed over the entire surface of the pad thermal oxide film 267 by, for example, low pressure CVD (chemical vapor deposition). Openings corresponding to the field oxide films 161-167 are formed in the nitride film 268 by etching using a resist formed by photolithography as a mask. In other words, the nitride film 268 is left in the region to be exposed from the field oxide films 161-167. Thereafter, the resist mask is peeled off.

In the step shown in FIG. 5F, a resist mask 270 (indicated by a two-dot chain line) having openings 272, 274-276 corresponding to the p-type wells 142, 144-146 is formed by photolithography. Using this resist mask 270 as a mask, p-type impurity ions (for example, B ⁺ : boron ions) are implanted. At this time, the implantation energy is about 50 keV and the amount of implantation is about 1 × 10 ¹³ cm ⁻² . Since the implantation energy is relatively high, the p-type impurity ions pass through the nitride film 268 exposed from the resist mask 270 and are implanted to a relatively deep position in the n-type epitaxial layer 17. Next, using the resist mask 270 and the nitride film 268 as a mask, p-type impurity ions (for example, B ⁺ : boron ions) are implanted with relatively low energy. At this time, the implantation energy is about 15 keV, and the amount of implantation is about 5 × 10 ¹³ cm ⁻² . Since the implantation energy is relatively low, the p-type impurity ions are implanted to a relatively shallow position in the n-type epitaxial layer 17 in a region that does not pass through the nitride film 268 and is not covered with the nitride film 268. Thereafter, the resist mask 270 is peeled off.

In the step shown in FIG. 5G, LOCOS (Local Oxidation of Silicon) oxidation treatment is performed. Thus, a thick thermal oxide film grows on the surface of n-type epitaxial layer 17 in the region exposed from nitride film 268, and field oxide films 161-167 are formed in the respective regions. At this time, the p-type impurity ions implanted in the process of FIG. 5F are activated by the heat applied to the n-type epitaxial layer 17. As a result, p-type wells 142 and 144-146 and p ⁺ -type channel stop layers 152 and 154 to 155 are formed in the respective regions. Thereafter, nitride film 268 is peeled off by etching, and pad thermal oxide film 267 is peeled off by etching.

In the step shown in FIG. 5H, pad thermal oxide film 277 is formed on the surface of n-type epitaxial layer 17 exposed from field oxide films 161-167. Further, a nitride film 278 and a USG (Undoped Silicate Glass) film 279 laminated thereon are formed so as to cover the entire surface of the substrate.
In the step shown in FIG. 5I, an opening 280 corresponding to the trench 20 is formed in the nitride film 278 and the USG film 279 by etching using a resist formed by photolithography as a mask. Then, after removing the resist, trench 20 is formed in n-type epitaxial layer 17 by etching using the laminated film of nitride film 278 and USG film 279 as an etching mask. For example, the trench 20 may be formed to a depth of about 1.8 μm.

In the step shown in FIG. 5J, the nitride film 278 and the USG film 279 are removed by etching. Before the nitride film 278 is peeled off, a step of forming a sacrificial oxide film and removing it by etching may be performed once or a plurality of times. Thereby, the surface roughness of the trench 20 can be improved before the gate oxide film 46 is formed.
In the step shown in FIG. 5K, a thermal oxide film 50 is formed on the entire surface. The thermal oxide film 50 is formed so as to cover the entire inner wall of the trench 20 and to cover the entire substrate surface including the surface of the n-type epitaxial layer 17 outside the trench 20. The thickness of the thermal oxide film 50 may be about 250 mm, for example. Further, a conductive polysilicon film 40 is formed on the entire surface of the substrate by being laminated on the thermal oxide film 50. The formation of the conductive polysilicon film 40 may be performed by depositing polysilicon by low pressure CVD and impurity diffusion (for example, phosphorus diffusion) for imparting conductivity to the deposited polysilicon film. . The thickness of the deposited polysilicon film may be about 1 μm, for example. This film thickness is preferably determined so that, for example, the inside of the trench 20 is filled with polysilicon. Further, the thickness of the polysilicon film 40 is such that a depression (a recess similar to the recess 4a in FIGS. 1 and 2) generated in the upper portion of the trench 20 does not significantly affect the uniformity in the subsequent etching. It is preferable to set it sufficiently large.

  In the process shown in FIG. 5L, the conductive polysilicon film 40 outside the trench 20 is thinned to a necessary and sufficient thickness for the polysilicon wiring 47 and the lower polysilicon electrode film 44 (film thickness reduction process). This film thickness reduction step may be performed by etch back or by chemical mechanical polishing (CMP). The thickness of the polysilicon film 40 can also be reduced by repeating the formation of the thermal oxide film and the etching of the thermal oxide film. By such a film thickness reduction process, for example, the conductive polysilicon film 40 may be thinned by about 1000 to 2000 mm. The thickness of the conductive polysilicon film 40 after being thinned may be about 4000 mm to 5000 mm. Thereafter, a nitride film 285 is formed on the surface of the thinned conductive polysilicon film 40 by, for example, low pressure CVD. A part of the nitride film 285 becomes the insulating film 43 (capacitance film) of the capacitor 15. The thickness of the nitride film 285 may be about 1000 mm.

  In the step shown in FIG. 5M, a resist mask 286 that covers the regions of the polysilicon wiring 47 and the lower polysilicon electrode film 44 is formed by photolithography. By etching using resist mask 286 as a mask, nitride film 285 and conductive polysilicon film 40 are etched. Thereby, the polysilicon wiring 47 and the lower polysilicon electrode film 44 are formed. Further, the nitride film 285 is left on the polysilicon wiring 47 and the lower polysilicon electrode film 44. The nitride film 285 left on the lower polysilicon electrode film 44 becomes an insulating film 43 as a capacitive film. Thereafter, the resist mask 286 is peeled off.

In the step shown in FIG. 5N, a pad thermal oxide film 287 is formed on the entire surface. Further, a resist mask 288 having an opening 289 corresponding to the p-type base layer 71 is formed by photolithography. Using this resist mask 288 as a mask, p-type ions (for example, B ⁺ : boron ions) are implanted. Then, after the resist mask 288 is removed, the implanted ions are activated by annealing (heat treatment). Thereby, the p-type base layer 71 is formed.

In the step shown in FIG. 5O, a p-type impurity (for example, BF ₂ ⁺ : boron fluoride ion) for threshold adjustment is implanted into the entire surface of the substrate, and then the n ⁻ type layer of the low breakdown voltage depletion n-channel MOSFET 54. A resist mask 291 having an opening 292 corresponding to 224 is formed. Using this resist mask 291 as a mask, n-type impurity ions (for example, P ⁺ : phosphorus ions) are implanted. Thereafter, the resist mask 291 is peeled off. The implanted n-type impurity ions are activated by heat in a post process shown in FIG. Thereby, the n ⁻ -type layer 224 is formed.

  In the step shown in FIG. 5P, gate insulating films 172 to 175 made of a thermal oxide film are formed by thermal oxidation of the surface of the n-type epitaxial layer 17. Thereafter, a polysilicon film 180 is formed on the entire surface by, for example, low pressure CVD. If necessary, the polysilicon film 180 may be planarized. For example, the flatness of the surface of the polysilicon film 180 can be increased by etching back after forming a TEOS (tetraethoxysilane) film over the entire surface.

In the step shown in FIG. 5Q, phosphorus as an impurity for imparting conductivity is diffused into the polysilicon film 180. Further, p-type impurity ions (for example, B ⁺ : boron ions) are implanted into the entire surface, and n-type impurity ions (for example, P ⁺ : phosphorous ions) are further implanted into the entire surface. Thus, the conductive polysilicon film 180 is obtained.
In the step shown in FIG. 5R, a resist mask 295 that covers regions corresponding to the polysilicon gates 182-186, the polysilicon layer 187, and the upper polysilicon electrode film 188 is formed by photolithography. Etching is performed using the resist mask 295 as a mask to form polysilicon gates 182-186, a polysilicon layer 187, and an upper polysilicon electrode film 188. This etching stops at the gate insulating film 172-175, the field oxide film 161-167, and the nitride film 285 (insulating film 43) on the polysilicon wiring 47 and the lower polysilicon electrode film 44. Next, the resist mask 295 is peeled off, and the surface is etched to remove the exposed thermal oxide film (the exposed part of the gate insulating film 172 to 175 and the surface layer part of the field oxide film 161 to 167). The

In the step shown in FIG. 5S, a pad oxide film 296 is formed on the surface, and a resist mask 298 is formed by photolithography. The resist mask 298 is formed in a pattern having openings corresponding to the n ⁺ type source layer 81, the n + type source / drain layers 82, 84 and 85, and the n ⁺ type contact layer 83. Using this resist mask 298 as a mask, n-type impurity ions are implanted. For example, P ⁺ (phosphorus ion) and As ⁺ (arsenic ion) may be implanted sequentially. Thereafter, the resist mask 298 is peeled off.

In the step shown in FIG. 5T, a new resist mask 299 is formed by photolithography. The resist mask 299 is formed in a pattern having openings corresponding to the p ⁺ type contact layers 91, 92, 94 and 95, the p ⁺ type source / drain layers 93 and 96, and the p ⁺ type contact region 97. Using this resist mask 299 as a mask, p-type impurity ions (for example, B ⁺ : boron ions) are implanted. Thereafter, the resist mask 299 is peeled off.

In the step shown in FIG. 5U, a TEOS film 99 as a buried insulating film is formed by CVD, for example, and a depression inside field oxide film 161 in the region of trench VDMOS transistor 19 is filled. The thickness of the TEOS film 99 may be equal to or greater than the thickness of the polysilicon wiring 47. Thereafter, an interlayer insulating film 100 made of, for example, BPSG (Boron-phosphorous Silicate Glass) is formed on the entire surface. This interlayer insulating film 100 becomes interlayer insulating films 101 to 108 in each region. Next, annealing (heat treatment) for causing the interlayer insulating film 100 to flow is performed. Simultaneously with this heat treatment, the impurity ions implanted in the steps of FIGS. 5S and 5T are activated to form n ⁺ -type layers 81-85 and p ⁺ -type layers (or regions) 91-97. Thereafter, a resist mask 301 having openings corresponding to the contact holes 111 to 118 is formed by photolithography. Contact holes 111-118 are formed in the interlayer insulating film 100 (101-108) by etching using the resist mask 301 as a mask. Thereafter, the resist mask 301 is peeled off.

  In the step shown in FIG. 5V, the electrode film 120 is formed on the entire surface. The electrode film 120 may be, for example, a laminated film in which Ti / TiN / AlSiCu / Ti / TiN are laminated in this order from the lower side. Such an electrode film 120 can be formed by sputtering. Thereafter, a resist mask 302 having a pattern corresponding to the electrodes 121-128 is formed by photolithography. Electrodes 121-128 (see FIG. 5W) are formed by etching using the resist mask 302 as a mask. Thereafter, the resist mask 302 is peeled off.

  In the step shown in FIG. 5W, an interlayer insulating film 131 is formed, and a resist mask 303 having an opening corresponding to the contact hole 132 is formed by photolithography. A contact hole 132 exposing the source electrode 121 is formed by etching using the resist mask 303 as a mask. Thereafter, the resist mask 303 is peeled off. The interlayer insulating film 131 may be, for example, a laminated film of a TEOS film and an SOG (Spin on Glass) film (for example, a laminated film in which the SOG film is sandwiched between two TEOS films).

  In the step shown in FIG. 5X, the metal wiring layer 133 is formed. That is, after the metal wiring layer 133 is formed on the entire surface, unnecessary portions are removed by etching using the resist mask 304 formed by photolithography as a mask. As a result, a metal wiring layer 133 is formed which is buried in the contact hole 132 of the interlayer insulating film 131 and extends on the interlayer insulating film 131 at the periphery of the contact hole 132. The metal wiring layer 133 may be, for example, a laminated film in which Ti / TiN / AlSiCu are laminated in this order from the lower side. Such a metal wiring layer 133 can be formed by sputtering.

Thereafter, as shown in FIG. 4, a passivation film 134 is formed on the interlayer insulating film 131, and a pad opening 135 exposing a part of the metal wiring layer 133 is formed by photolithography and etching. As described above, the passivation film 134 may be a laminated film including a lower layer 134A made of a nitride film and an upper layer 134B made of a polyimide film laminated thereon. Thereafter, a thinning process is performed by grinding from the back surface of the n ⁺ -type silicon substrate 16 as necessary. Then, an electrode film 18 is formed on the back surface of the n ⁺ type silicon substrate 16.

  As described above, according to this embodiment, after forming the trench 20 in the n-type epitaxial layer 17, the thermal oxide film 50 covering the inner wall of the trench 20 and the surface of the epitaxial layer 17 outside the trench 20 is formed. Then, conductive polysilicon film 40 is formed on thermal oxide film 50 so as to fill trench 20 and to be deposited on thermal oxide film 50 outside trench 20. Thereafter, the polysilicon film 40 other than the predetermined region inside the trench 20 and outside the trench 20 is selectively removed. Thus, the polysilicon gate 45 made of the conductive polysilicon layer in the trench 20 and the polysilicon wiring 47 and the lower polysilicon electrode film 44 made of the conductive polysilicon layer in a predetermined region outside the trench 20 are simultaneously formed. Can do. Thereby, since the number of processes can be reduced, the productivity of the semiconductor device 10 can be improved.

  The exposed portion of thermal oxide film 50 is then removed by etching, and another thermal oxide film (gate insulating film 172-175 and field oxide film 161-167) is formed on the surface of n-type epitaxial layer 17. . Since this thermal oxide film is formed in a separate process from the thermal oxide film 50, it has a film thickness different from that of the thermal oxide film 50. That is, since the gate oxide film 46 in the trench 20 and the thermal oxide film 49 immediately below the lower polysilicon electrode film 44 are part of the thermal oxide film 50, they have the same film thickness. Gate insulating film 172-175 and field oxide film 161-167 have a film thickness different from that of gate oxide film 46 and thermal oxide film 49.

  Furthermore, in this embodiment, after the thickness of the conductive polysilicon film 40 is reduced, the patterning is performed. Thereby, the polysilicon film 40 having a film thickness sufficient to fill the trench 20 can be formed, and the film thicknesses of the polysilicon wiring 47 and the lower polysilicon electrode film 44 can be optimized. As a result, the difference in height between the surfaces of the interlayer insulating films 101 and 108 in the vicinity of the trench 20 and particularly in the capacitor region 13 can be reduced (for example, 1 μm or less, more preferably 6000 mm or less). Thus, a mask pattern can be precisely formed at the time of opening fine contact holes 111-118 or photolithography when patterning fine electrodes 121-128. More specifically, since an exposure process margin can be ensured in the photolithography exposure process, a precise mask pattern can be formed. Thereby, since an abnormality such as a short circuit between wirings can be avoided, the yield can be improved.

Further, by forming the conductive polysilicon film 40 thick in advance, a recess (dent) generated on the surface of the polysilicon film 40 immediately above the trench 20 can be reduced. Thereby, when the polysilicon film 40 is etched to remove the polysilicon film 40 outside the trench 20, the depression of the polysilicon layer in the trench 20 is reduced. Thereby, the uniformity of the amount of depression of the polysilicon layer (polysilicon gate 45) in the numerous trenches 20 formed in the epitaxial layer 17 can be improved. That is, in each trench 20, the facing area between the polysilicon gate 45 and the inner wall surface of the trench 20 (particularly the n ⁺ -type source layer 81) can be accurately controlled. Thereby, stable device characteristics can be realized.

In this embodiment, since the polysilicon gate 45 and the polysilicon electrode film 44 under the capacitor 15 can be formed by a common process, the manufacturing process of the semiconductor device 10 having the trench VDMOS transistor 19 and the capacitor 15 is performed. It can be simplified. Thereby, productivity can be improved.
Further, in this embodiment, the upper polysilicon electrode film 188 of the capacitor 15 is formed in the same process as the polysilicon gate 182-186 of the MOSFET 52-56 and the polysilicon layer 187 of the polysilicon resistor 57. This can also reduce the number of steps, thereby further improving productivity.

As mentioned above, although one Embodiment of this invention was described, this invention can also be implemented with another form. For example, the film thickness, film material, and the like described in the above-described embodiments are merely examples, and the design can be changed as necessary. The invention is also applicable to the formation of MEMS devices having trenches and conductive polysilicon layers embedded therein. In addition, various design changes can be made within the scope of the matters described in the claims.
Features that can be extracted from the description of this specification and the accompanying drawings are described below.
1. Forming a trench in the semiconductor layer;
Forming an insulating film on the semiconductor layer so as to cover an inner wall of the trench and a surface outside the trench;
Filling the trench and forming a conductive polysilicon film to be deposited on the insulating film outside the trench;
And a polysilicon etching step of selectively removing the polysilicon film so that the polysilicon film remains in a predetermined region on the insulating film outside the trench and outside the trench.
According to this method, after forming the trench in the semiconductor layer, the insulating film covering the inner wall of the trench and the surface of the semiconductor layer outside the trench is formed. Then, a conductive polysilicon film is formed on the insulating film so as to fill the trench and to be deposited on the insulating film outside the trench. Then, the polysilicon film other than the predetermined region inside and outside the trench is selectively removed. Thus, the conductive polysilicon layer in the trench and the conductive polysilicon layer in a predetermined region outside the trench can be formed simultaneously. Thereby, since the number of processes can be reduced, the productivity of the semiconductor device can be improved. In this case, the conductive polysilicon layer in the trench and the conductive polysilicon layer in the predetermined region have the same composition.
The insulating film may be an oxide film. More specifically, the oxide film may be a thermal oxide film formed by thermally oxidizing the surface of the semiconductor layer.
2. The semiconductor device according to claim 1, further comprising an insulating film etching step of etching the insulating film so that the insulating film remains on an inner wall of the trench and the predetermined region.
By this method, a structure in which a conductive polysilicon layer is stacked on an insulating film can be formed outside the trench simultaneously with the formation of the structure near the trench. As a result, the number of steps can be reduced, and the productivity of the semiconductor device can be improved. Since the insulating film covering the inner wall of the trench and the insulating film in the predetermined region are formed in the same process, they can be formed to have the same film thickness.
3. Item 3. The method of manufacturing a semiconductor device according to Item 1 or 2, further comprising a step of forming a thermal oxide film on the exposed surface of the semiconductor layer after the insulating film etching step.
By this method, the surface of the semiconductor layer can be protected with a thermal oxide film. Since this thermal oxide film is formed in a separate process from the insulating film under the conductive polysilicon layer, it has a different thickness from that of the insulating film.
4). Item 4. The method for manufacturing a semiconductor device according to any one of Items 1 to 3, further including a film thickness reduction step of reducing the thickness of the polysilicon film before the polysilicon etching step.
If a conductive polysilicon film is formed so as to fill the trench, the polysilicon film outside the trench may become thicker than necessary. Therefore, if the film thickness reduction process is performed, the film thickness of the polysilicon film outside the trench can be optimized. As a result, the height difference between the vicinity of the trench and the predetermined region can be reduced, so that the subsequent steps can be performed precisely. More specifically, the mask pattern can be precisely formed during photolithography. More specifically, in the photolithography exposure process, if a large height difference occurs on the surface to be exposed, the exposure process margin is lowered. This may cause various abnormalities such as a short circuit between the wirings. The film thickness reduction process provides a solution to this problem.
Further, by forming the polysilicon film thick, a recess (dent) generated on the surface of the polysilicon film immediately above the trench can be reduced. That is, when the polysilicon film is thin, a clear recess can be formed on the surface of the polysilicon film immediately above the trench. In contrast, when the polysilicon film is formed thick, the recess profile can be blunted, and the recess amount is reduced accordingly. Therefore, when the polysilicon film is subsequently etched to expose the insulating film, the depression of the polysilicon layer in the trench is also reduced. Therefore, when a large number of trenches are formed in the semiconductor layer, the uniformity of the amount of depression of the polysilicon layer in the large number of trenches can be improved. The thickness of the polysilicon film remaining on the surface of the semiconductor layer outside the trench can be optimized by the thickness reduction process.
5. Item 5. The method of manufacturing a semiconductor device according to Item 4, wherein the film thickness reduction step includes any one of a chemical mechanical polishing step, an etch back step, and a combination step of thermal oxide film formation and etching.
6). The trench has a sidewall along the depth direction of the trench, and the semiconductor layer has a source region, a channel region, and a drain region so as to be adjacent to the sidewall. Item 6. The semiconductor device according to any one of Items 1 to 5, wherein the polysilicon film is a gate electrode facing the channel region through the insulating film.
By this method, a semiconductor device having a trench gate type MISFET can be manufactured. Since the gate electrode and the conductive polysilicon layer outside the trench can be formed at the same time, the number of processes is reduced, and the productivity can be improved.
7). A capacitor structure including the polysilicon film by forming a capacitor film laminated to be in contact with the polysilicon film formed in the semiconductor layer outside the trench and a conductive film laminated to be in contact with the capacitor film Item 7. The method for manufacturing a semiconductor device according to any one of Items 1 to 6, further comprising:
By this method, the capacitor structure can be formed using the conductive polysilicon layer outside the trench formed simultaneously with the formation of the conductive polysilicon layer in the trench. Accordingly, the number of processes can be reduced, so that productivity can be improved.
8). Item 8. The method for manufacturing a semiconductor device according to Item 7, further comprising a step of forming an interlayer insulating film on the capacitor structure and the trench.
This feature is particularly preferably combined with the feature described in Item 4. This reduces the difference in height of the interlayer insulating film on the trench and capacitor structure, so that fine contact holes can be precisely formed in the interlayer insulating film, and fine patterns can be precisely formed on the interlayer insulating film. can do.
9. A semiconductor layer in which a trench is formed;
A first insulating film covering an inner wall of the trench;
A second insulating film covering the surface of the semiconductor layer in a predetermined region outside the trench and having a film thickness equal to the first insulating film;
A first conductive polysilicon layer embedded in the trench and facing the inner wall surface of the trench through the first insulating film;
A second conductive polysilicon layer formed on the second insulating film outside the trench and having the same composition as the first conductive polysilicon layer;
Including a semiconductor device.
The semiconductor device having this configuration can be manufactured by the method of Item 1 or 2. Therefore, a semiconductor device having a structure having the first conductive polysilicon layer embedded in the trench and the second conductive polysilicon layer on the insulating film outside the trench can be manufactured with a small number of steps.
10. Item 10. The semiconductor device according to Item 9, further including a thermal oxide film formed on a surface of the semiconductor layer exposed from the second insulating film.
The semiconductor device having this configuration can be manufactured by the method of Item 3.
11. Item 11. The semiconductor device according to Item 10, wherein the film thickness of the first insulating film is different from the film thickness of the thermal oxide film.
The semiconductor device having this configuration can be manufactured by the method of Item 3. That is, since the first and second insulating films and the thermal oxide film are formed in separate steps, they have different film thicknesses.
12 The trench has side walls along the depth direction of the trench,
The semiconductor layer has a source region, a channel region, and a drain region so as to be adjacent to the sidewall,
Item 12. The semiconductor device according to any one of Items 9 to 11, wherein the polysilicon film in the trench is a gate electrode facing the channel region through the first insulating film.
The semiconductor device having this configuration can be manufactured by the method of Item 6.
13. A capacitance film laminated to be in contact with the second conductive polysilicon layer; and a conductive film laminated to be in contact with the capacitance film, the second conductive polysilicon layer, the capacitance film, and the Item 13. The semiconductor device according to any one of Items 9 to 12, wherein a capacitor structure including a conductive film is provided.
The semiconductor device having this configuration can be manufactured by the method described in Item 7. Therefore, a semiconductor device having the first conductive polysilicon layer embedded in the trench and the capacitor structure formed outside the trench can be manufactured with a small number of steps.
14 Item 14. The semiconductor device according to Item 13, wherein the film thickness of the second conductive polysilicon layer of the capacitor structure is 1 μm or less.
The semiconductor device may further include an interlayer insulating film that covers the capacitor structure and the first conductive polysilicon layer. According to the configuration of Item 14, since the difference in height of the interlayer insulating film is small, a fine contact hole can be precisely formed in the interlayer insulating film, or a fine pattern on the interlayer insulating film can be formed with high precision. it can. Such a structure can be produced, for example, by applying the method of Item 4 or 5 and the method of Item 8 in combination.

DESCRIPTION OF SYMBOLS 1 Semiconductor layer 2 Trench 3 Insulating film 4 Polysilicon film 4a Recess 5 Resist 10 Semiconductor device 11 Semiconductor substrate 12 Power element area 13 Capacitor area 14 Logic area 15 Capacitor 16 n ⁺ type silicon substrate 17 N-type epitaxial layer 18 Electrode film 19 Trench VDMOS transistor 20 Trench 21 Interconnect trench 22 Lead trench 23 Contact portion 31 First insulating film 32 Second insulating film 40 Conductive polysilicon film 41 First conductive polysilicon layer 41a Depression 42 Second conductive polysilicon layer 43 Insulating film (capacitive film)
44 Lower polysilicon electrode film 44a Overhang region 45 Polysilicon gate 46 Gate oxide film 47 Polysilicon wiring 48 Metal layer 49 Thermal oxide film 50 Thermal oxide film 52 Low breakdown voltage n-channel MOSFET
53 Low voltage p-channel MOSFET
54 Low breakdown voltage depletion n-channel MOSFET
55 High breakdown voltage n-channel MOSFET
56 Field p-channel MOSFET
57 polysilicon resistor 61-65, 67-68 p-type well 71 p-type base layer 81 n ⁺ type source layer 82-85 n ⁺ type source / drain layer 91-92, 94-95 p ⁺ type contact layer 93.96 p ⁺ type source / drain layer 97 p ⁺ type contact region 99 TEOS film 100-108 Interlayer insulating film 111-118 Contact hole 120 Electrode film 121 Source electrode 122-128 Electrode 131 Interlayer insulating film 132 Contact hole 133 Metal wiring layer 134 Passivation Film 134A lower layer 134B upper layer 135 pad opening 136 pad 142, 144-146 p-type well 152, 154-155 channel stop layer 161-167 field oxide film 165a opening 172-175 gate insulating film 180 polysilicon film 182-186 polysilicon Ngeto 187 polysilicon layer 188 above the polysilicon electrode film 192-196 contact hole 203 and 205 n-type well 224 n ^- -type layer 250 thick oxide film 268 the nitride film 278 the nitride film 279 USG film 285 nitride film

Claims (12)

Forming a well for element isolation in a power element region of a semiconductor layer on a semiconductor substrate;
Forming a trench in a region surrounded by the well of the semiconductor layer,
Forming an insulating film on the semiconductor layer so as to cover an inner wall of the trench and a surface outside the trench;
Fill said trench, said trench outside of said deposited on the insulating film, further forming said power element outside the area is also formed in the capacitor region provided is so that the conductive polysilicon film on said semiconductor substrate And a process of
A polysilicon etching process for selectively removing the polysilicon film so that the polysilicon film remains in the predetermined region above the well and the capacitor region in the trench and on the insulating film outside the trench. and,
A capacitor film stacked to be in contact with the polysilicon film in the capacitor region and a conductive film stacked to be in contact with the capacitor film are formed, and a capacitor structure including the polysilicon film is formed in the capacitor region. Forming the semiconductor device, comprising: forming the semiconductor device.   The method of manufacturing a semiconductor device according to claim 1, further comprising an insulating film etching step of etching the insulating film so that the insulating film remains on an inner wall of the trench and the predetermined region. A logic region is provided outside the power element region on the semiconductor substrate,
The insulating film is also formed on the surface of the semiconductor layer in the logic region,
In the insulating film etching step, the insulating film on the semiconductor layer in the logic region is etched,
The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a thermal oxide film on the exposed surface of the semiconductor layer in the logic region after the insulating film etching step.   4. The method of manufacturing a semiconductor device according to claim 1, further comprising a film thickness reduction process for reducing a film thickness of the polysilicon film before the polysilicon etching process. 5.   The method of manufacturing a semiconductor device according to claim 4, wherein the film thickness reduction step includes any one of a chemical mechanical polishing step, an etch back step, and a combination step of thermal oxide film formation and etching thereof. . The trench has side walls along the depth direction of the trench,
The semiconductor layer has a source region, a channel region, and a drain region so as to be adjacent to the sidewall,
The method for manufacturing a semiconductor device according to claim 1, wherein the polysilicon film in the trench is a gate electrode facing the channel region through the insulating film. The capacitor structure and further comprising the step of forming an interlayer insulating film on the trench method of manufacturing a semiconductor device according to any one of claims 1 to 6. On the semiconductor substrate, having a power element region and a capacitor region provided outside the power element region,
The power element region is
A semiconductor layer in which a trench and a well for element isolation are formed;
A first insulating film covering an inner wall of the trench;
A second insulating film covering the surface of the semiconductor layer in a predetermined region outside the trench and having a film thickness equal to the first insulating film;
A first conductive polysilicon layer embedded in the trench and facing the inner wall surface of the trench through the first insulating film;
The formed above Oite the wells on the second insulating film outside the trench, seen including a second conductive polysilicon layer having the same composition as the first conductive polysilicon layer,
The capacitor region is
A third conductive polysilicon layer having the same composition as the first conductive polysilicon layer;
A capacitive film laminated to be in contact with the third conductive polysilicon layer; and a conductive film laminated to be in contact with the capacitive film;
A semiconductor device, wherein a capacitor structure including the third conductive polysilicon layer, the capacitor film, and the conductive film is provided in the capacitor region . A logic region formed outside the power element region on the semiconductor substrate;
The semiconductor layer extends to the logic region;
The semiconductor device according to claim 8 , further comprising a thermal oxide film formed on a surface of the semiconductor layer exposed from the second insulating film in the logic region . The semiconductor device according to claim 9 , wherein a film thickness of the first insulating film is different from a film thickness of the thermal oxide film. The trench has side walls along the depth direction of the trench,
The semiconductor layer has a source region, a channel region, and a drain region so as to be adjacent to the sidewall,
Polysilicon film in said trench, said first a gate electrode facing the channel region via an insulating film, a semiconductor device according to any one of claims 8-10. The semiconductor device according to claim 8 , wherein a film thickness of the third conductive polysilicon layer of the capacitor structure is 1 μm or less.

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