JP5385567B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a trench gate type VDMOSFET and a method for manufacturing the semiconductor device.

As a structure effective for miniaturization of a VDMOSFET (Vertical Double diffused Metal Oxide Semiconductor Field Effect Transistor), a trench gate structure is generally known.
FIG. 5 is a schematic cross-sectional view of a semiconductor device having a conventional trench gate type VDMOSFET.

The semiconductor device 100 includes an N ⁺ type substrate 101. An N ⁻ type epitaxial layer 102 is stacked on the N ⁺ type substrate 101. The base layer portion of the N ⁻ -type epitaxial layer 102 is an N ⁻ -type region 103, and the P-type body region 104 is formed adjacent to the N ⁻ -type region 103 in the surface layer portion of the N ⁻ -type epitaxial layer 102. ing.
A trench 105 is dug down from the surface of the N ⁻ type epitaxial layer 102. Trench 105 penetrates P-type body region 104, and the deepest part reaches N ⁻ -type region 103. A gate electrode 107 made of polysilicon doped with N-type impurities at a high concentration is buried in the trench 105 via a gate insulating film 106 made of SiO ₂ (silicon oxide).

An N ⁺ type source region 108 is formed along the trench 105 in the surface layer portion of the P type body region 104. In the N ⁺ -type source region 108, a P ⁺ -type contact region 109 is formed through the N ⁺ -type source region 108 in the center portion in plan view.
An interlayer insulating film 110 is stacked on the N ⁻ type epitaxial layer 102. A source wiring 111 is formed on the interlayer insulating film 110. The source wiring 111 is grounded. The source wiring 111 is in contact (electrically connected) to the N ⁺ type source region 108 and the P ⁺ type contact region 109 through a contact hole 112 formed in the interlayer insulating film 110. Further, the gate wiring 113 is electrically connected to the gate electrode 107 through a contact hole (not shown) formed in the interlayer insulating film 110.

A drain electrode 114 is formed on the back surface of the N ⁺ type substrate 101.
While applying a positive voltage of appropriate magnitude to the drain electrode 114, by controlling the potential of the gate electrode 107, a channel is formed near the interface between the gate insulating film 106 in the P-type body region 104, N ⁺ -type A current flows between the source region 108 and the drain electrode 114. Thereby, the switching operation of the VDMOSFET is achieved.
JP 11-274484 A

As an index representing the switching performance of the VDMOSFET, for example, the product _R on · _{Q g} the resistance _{R on} the gate charge _{Q g} is used.
The on-resistance R _on is a resistance between the source and the drain. In the semiconductor device 100 illustrated in FIG. 5, the on-resistance R _on is a resistance between the N ⁺ type source region 108 and the N ⁺ type substrate 101 (between the source wiring 111 and the drain electrode 114).

Gate charge Q _g is the gate - drain capacitance C _gd, the gate - a charge amount accumulated in the combined capacitance of the source capacitance C _gs. In the semiconductor device 100 shown in FIG. 5, the gate-drain capacitance C _gd includes the capacitance of the portion sandwiched between the gate electrode 107 and the bottom surface of the trench 105 in the gate insulating film 106, the N ⁻ type region 103, and the P type. This is a combined capacity with the capacity of the depletion layer 115 extending from the interface with the body region 104. In the semiconductor device 100 illustrated in FIG. 5, the gate-source capacitance C _gs is the capacitance of the gate insulating film 106 in a portion sandwiched between the gate electrode 107 and the N ⁺ type source 108.

More product _R on · _{Q g} the resistance _{R on} the gate charge _{Q g} is small, it is possible to achieve faster switching operation. However, as shown in FIG. 6, R _on and Q _g are in a so-called trade-off relationship in which when one is reduced, the other increases. Therefore, in order to reduce R _on · Q _g , it is necessary to reduce one of R _on and Q _g and prevent the other from increasing.

An object of the present invention, without causing an increase in on-resistance R _on, is to provide a semiconductor device and a manufacturing method thereof capable of reducing gate charge quantity Q _g.

In order to achieve the above object, according to the first aspect of the present invention, there is provided a step of forming a trench in a semiconductor layer of a first conductivity type, an oxide film material is deposited on the semiconductor layer, and an oxide film material deposition layer is formed. Forming the semiconductor layer, etching back the oxide film material deposition layer to partially leave the oxide film material deposition layer on a peripheral edge of the bottom surface of the trench, and the semiconductor including the bottom surface and side surface of the trench A thick film portion having a relatively large thickness on the periphery of the bottom surface of the trench by oxidizing the oxide material deposition layer left on the periphery of the bottom surface of the trench and the bottom surface of the trench; Forming an oxide film including a thin film portion having a relatively small thickness on a central portion surrounded by a peripheral edge portion; and forming a gate electrode so as to fill the trench on the oxide film; The half Introducing a second conductivity type impurity from the surface of the body layer to form the second conductivity type body region; and introducing the first conductivity type impurity from the surface of the semiconductor layer to the periphery of the trench. Forming the source region of the first conductivity type in contact with the body region, removing a portion outside the trench in the oxide film, and forming the thick film portion and the thick film portion on the bottom and side surfaces of the trench. Forming a gate insulating film including the thin film portion.
In this method, an oxide film material deposition layer is partially left on the peripheral edge of the bottom surface of the trench. The remaining oxide material deposition layer is oxidized simultaneously with the surface of the semiconductor layer including the bottom and side surfaces of the trench. By this oxidation, the remaining oxide film material deposition layer becomes a thick film portion having a relatively large thickness. On the other hand, the portion formed by oxidizing the bottom surface of the trench becomes a thin film portion having a relatively small thickness. The thick film portion and the thin film portion become the thick film portion and the thin film portion of the gate insulating film, respectively.
Thus, the thick film portion and the thin film portion of the gate insulating film can be formed simultaneously. Therefore, a gate insulating film having a thick film portion and a thin film portion can be easily formed without going through a complicated process.
The manufacturing method according to claim 1 , wherein a semiconductor layer, a first conductivity type region of a first conductivity type formed in a base layer portion of the semiconductor layer, and a semiconductor layer formed on the first conductivity type region are formed in the first conductivity type region. A body region of a second conductivity type in contact, a trench formed in the semiconductor layer, penetrating through the body region and having a deepest portion reaching the first conductivity type region, and around the trench in a surface layer portion of the semiconductor layer A source region of the first conductivity type formed and in contact with the body region; a gate insulating film formed on a bottom surface and a side surface of the trench; and a gate electrode embedded in the trench through the gate insulating film; hints, the gate insulating film, on the periphery of the bottom surface of the trench, and a thick film portion having a relatively large thickness (thickness in the depth direction of the trench), among which are surrounded by the peripheral portion On the parts, and a thin film portion having a relatively small thickness, it is possible to obtain a semiconductor device.

According to this configuration, the first conductivity type region is formed in the base layer portion of the semiconductor layer. Further, a second conductivity type body region is formed in contact with the first conductivity type region in the semiconductor layer. Furthermore, a trench in which a gate electrode is embedded via a gate insulating film is formed in the semiconductor layer. The trench penetrates the body region, and the deepest portion reaches the first conductivity type region. In the surface layer portion of the semiconductor layer, a source region of the first conductivity type is formed around the trench. The gate insulating film includes a thick film portion having a relatively large thickness on the peripheral portion of the bottom surface of the trench, and a thin film portion having a relatively small thickness on the central portion surrounded by the peripheral portion. And .

In the trench gate type transistor, a channel is formed in a region (channel formation region) in the vicinity of the interface with the gate insulating film in the body region.
For example, it is conceivable to increase the gap between the gate electrode and the bottom surface of the trench by uniformly increasing the thickness of the gate insulating film, thereby reducing the capacitance between them. However, when the thickness of the portion of the gate insulating film facing the channel formation region is increased, not only the gate threshold voltage is increased, but also the current capability is decreased, so that the channel resistance is increased. As a result, the on-resistance R _on increases.

On the other hand, in the configuration in which the gate insulating film has the thick film portion on the bottom surface of the trench, the thickness of the gate insulating film on the side surface of the trench is set to an appropriate thickness considering the gate threshold voltage and channel resistance. An interval between the gate electrode and the bottom surface of the trench facing each other with the portion interposed therebetween can be increased. Thus, without increasing the gate threshold voltage and on-resistance R _on, it is possible to reduce the capacitance between the gate electrode and the bottom surface of the trench (first conductivity type region). Therefore, the gate-drain capacitance C _gd can be reduced without increasing the on-resistance R _on , and thus the gate charge amount Q _g can be reduced. As a result, high speed switching operation of the transistor can be achieved.

  By forming the gate insulating film thickly on the peripheral edge of the bottom surface of the trench, the distance between the gate electrode and the bottom surface of the trench can be increased at the peripheral edge, thereby reducing the capacitance between them. be able to. Further, the thickness of the thin film portion is set so that the upper surface of the thin film portion is at the same position as or lower than the interface between the first conductivity type region and the body region. (Overall channel length). As a result, good operation of the transistor can be ensured.

Therefore, a favorable operation of the transistor can be ensured while the gate-drain capacitance C _gd can be reduced .

As described in 請 Motomeko 2, in the step of forming the oxide film, the oxide film may be formed in a uniform thickness on a side surface of the trench.

In this case, as described in claim 3, in the step of forming the oxide film, the oxide film, the thickness of the thick portion is larger than the thickness of the portion on the side surface of the trench Kunar so It is preferable to be formed .
According to the manufacturing method of the third aspect, the thick film portion having a thickness larger than the thickness of the gate insulating film on the side surface of the trench is formed. By relatively small thickness of the gate insulating film on the side surface of the trench, it is possible to reduce the on-resistance R _on, on the other hand, by increasing relative thickness of the thick portion, The gate-drain capacitance C _gd can be reduced.

Further, as described in claim 4, in the step of forming the oxide film, the oxide film, the thickness of the portion where the thickness of the portion in contact with the front Symbol source region on a side surface of the trench is in contact with the body region it may be formed to a size Kunar so than is.
According to the manufacturing method of the fourth aspect, on the side surface of the trench, the gate insulating film in which the thickness of the portion in contact with the source region is larger than the thickness of the portion in contact with the body region is formed. By increasing the thickness of the portion of the gate insulating film in contact with the source region while making the thickness of the portion in contact with the body region of the gate insulating film an appropriate film thickness considering the gate threshold voltage and channel resistance, The capacitance between the source region, that is, the gate-source capacitance _Cgs can be reduced. Therefore, the gate-source capacitance C _gs can be reduced without increasing the on-resistance R _on , and thus the gate charge amount Q _g can be further reduced. As a result, further speeding up of the switching operation of the transistor can be achieved.

In addition, since the thickness of the portion of the gate insulating film that is in contact with the source region is large, a large interval between the gate electrode and the source region can be ensured. As a result, the gate-source breakdown voltage can be improved.
In this case, as described in claim 5, in the step of forming the oxide film, the oxide film, the thickness of the thick film portion is the portion in contact with the body region thickness larger than Kunar so on Preferably it is formed .
According to the manufacturing method of the fifth aspect, the gate insulating film in which the thickness of the portion in contact with the body region is relatively small is formed.

By relatively small thickness of the portion in contact with the body region of the gate insulating film, it is possible to reduce the on-resistance R _on, on the other hand, by increasing relative thickness of the thick portion The gate-drain capacitance C _gd can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention. The semiconductor device 1 has an array structure in which unit cells having trench gate type VDMOSFETs are arranged in a matrix.
An N ⁻ type epitaxial layer made of silicon doped with an N type impurity at a lower concentration (for example, 10 ¹⁵ / cm ³ ) than the N ⁺ type substrate 2 is formed on the N ⁺ type substrate 2 that forms the base of the semiconductor device 1. Layer 3 is laminated. The base layer portion of the epitaxial layer 3 is an N ⁻ type region 4 as a first conductivity type region in a state as it is after epitaxial growth. Further, in the epitaxial layer 3, N ^- on type region 4, the body region 5 of the P type the N ^- formed in contact with the mold region 4.

A trench 6 is dug from the surface of the epitaxial layer 3. Trench 6 penetrates body region 5, and the deepest part reaches N ⁻ type region 4. Further, a plurality of trenches 6 are formed at regular intervals in the left-right direction in FIG. 1, and each extend in a direction (direction along the gate width) perpendicular to the paper surface of FIG. Each trench 6 has a width W ₁ in the horizontal direction in FIG. 1 (a direction orthogonal to the gate width), for example, formed by 0.5 [mu] m. A gate insulating film 7 made of SiO ₂ (silicon oxide) is formed in the trench 6 so as to cover the entire inner surface.

The gate insulating film 7 has a thick film portion 71 having a relatively large thickness (thickness in the depth direction of the trench 6) and a thin film portion 72 that obtains a relatively small thickness on the bottom surface of the trench 6. And.
The thick film portion 71 is formed on the peripheral edge portion of the bottom surface of the trench 6. The thick film portion 71 is formed in a cross-sectional shape that increases in thickness as it approaches the side surface of the trench 6. The maximum thickness of the thick portion 71 _{T ox2} (e.g., 150 nm) is the bottom surface of the trench 6 and the N ^- top type region 4 ^- distance _{H 1} between the (N type region 4 and the interface between the body region 5) (e.g. , 50 nm). On the other hand, the minimum thickness T _ox1 (for example, 50 nm) of the thick film portion 71 is equal to the interval H ₁ . Further, the thick portion 71, the bottom surface of the trench 6, for example, in contact with the width _{W 3} of 0.1 [mu] m.

The thin film portion 72 is formed on the central portion of the bottom surface of the trench 6. The upper surface of the thin film portion 72 is located on the same plane as the upper surface of the N ⁻ -type region 4. In other words, the thickness _{T ox1} thin section 72, the bottom surface and the N of the trench 6 ^- equal to the spacing _{H 1} between the upper surface of the mold region 4. Further, the thin film portion 72 is in contact with the bottom surface of the trench 6 with a width W ₂ of 0.3 μm, for example.
A gate electrode 8 is embedded in the trench 6 by filling the inside of the gate insulating film 7 in the trench 6 with polysilicon doped with N-type impurities at a high concentration.

Further, in the surface layer portion of the epitaxial layer 3, an N-type impurity concentration higher than the N-type impurity concentration of the N ⁻ -type region 4 on both sides of the trench 6 in the direction orthogonal to the gate width (left-right direction in FIG. 1). An N ⁺ type source region 9 having (for example, 10 ¹⁹ / cm ³ ) is formed. The source region 9 extends in the direction along the gate width along the trench 6, and the bottom thereof is in contact with the body region 5. A P ⁺ -type contact region 10 is formed through the source region 9 at the center of the source region 9 in the direction orthogonal to the gate width.

  That is, the trenches 6 and the source regions 9 are alternately provided in a direction orthogonal to the gate width, and extend in a direction along the gate width. A boundary between adjacent unit cells is set on the source region 9 along the source region 9 in a direction orthogonal to the gate width. At least one contact region 10 is provided across two unit cells adjacent in the direction orthogonal to the gate width. The boundary between unit cells adjacent in the direction along the gate width is set so that the gate electrode 8 included in each unit cell has a constant gate width.

An interlayer insulating film 13 is stacked on the epitaxial layer 3.
A source line 14 and a gate line 16 are formed on the interlayer insulating film 13. The source wiring 14 is grounded.
A contact hole 15 is formed through the interlayer insulating film 13 at a position where the source wiring 14 and the source region 9 including the contact region 10 face each other. A source plug 18 is embedded in the contact hole 15. The source wiring 14 is in contact (electrically connected) to the source region 9 and the contact region 10 via the source plug 18.

Further, a contact hole 11 is formed through the interlayer insulating film 13 at a position where the gate wiring 16 and the gate electrode 8 face each other. A gate plug 12 is embedded in the contact hole 11. The gate wiring 16 is contacted (electrically connected) to the gate electrode 8 through the gate plug 12.
A drain electrode 27 is formed on the back surface of the N ⁺ type substrate 2.

A channel is formed in the vicinity of the interface with the gate insulating film 7 in the body region 5 (channel formation region 29) by controlling the potential of the gate electrode 8 while applying an appropriate positive voltage to the drain electrode 27. A current flows between the source region 9 and the drain electrode 27.
In the semiconductor device 1, the thickness of the gate insulating film 7 is not uniformly increased, but the gate insulating film 7 is locally thickly formed on the peripheral edge of the bottom surface of the trench 6. Thus, the gate insulating film 7 includes a thick film portion 71 having a thickness larger than that of other portions on the peripheral edge portion of the bottom surface of the trench 6. Therefore, the thickness of the gate insulating film 7 on the side surface of the trench 6 is set to an appropriate thickness considering the gate threshold voltage and channel resistance, and the gate electrode 8 and the bottom surface of the trench 6 facing each other with the thick film portion 71 interposed therebetween. The interval between them can be increased. Therefore, the capacitance C _ox1 between the gate electrode 8 and the bottom surface of the trench 6 (N ⁻ type region 4) sandwiching the gate insulating film 7 is reduced without increasing the gate threshold voltage and the on-resistance R _on. be able to. Therefore, the gate-drain capacitance C _gd can be reduced without increasing the on-resistance R _on , and thus the gate charge amount Q _g can be reduced. As a result, the switching operation speed of the VDMOSFET can be increased.

In the semiconductor device 100 shown in FIG. 5, the same width and the gate width of the trench 105 to the width W ₁ and the gate width W _g of each trench 6. The thickness of the gate insulating film 106 is _assumed to be equal to the thickness T _ox1 of the thin film portion 72 of the gate insulating film 7. In this case, in the semiconductor device 100, the capacitance C _ox2 between the gate electrode 107 and the bottom surface (N ⁻ -type region 103) of the trench 105 facing each other with the gate insulating film 106 interposed therebetween is
C _ox2 = ε _ox · W ₁ · W _g / T _ox1
However, it becomes a relative dielectric constant of ε _ox : SiO ₂ .

On the other hand, in the semiconductor device 1, when the thickness of the thick film portion 71 in the depth direction of the trench 6 is _{Tox (t)} , the gate electrode 8 and the bottom surface of the trench 6 facing each other with the gate insulating film 7 interposed therebetween ( The capacitance C _ox1 between the N ⁻ type region 4) is
_{C ox1 = ε ox · W 2} · W g / T ox1 + 2∫ 0 W3 ε ox · dt / T ox (t)
It becomes.

Here, it is assumed that _{０ 0} ^W3 ε _ox · dt / T _{ox (t) ≈W 3} / 2T _ox1 . Then, by substituting W ₁ = 0.5 μm, W ₂ = 0.3 μm, W ₃ = 0.1 μm, and T _ox1 = 50 nm into the above equations for _obtaining the capacitances C _ox1 and C _ox2 , C _ox1 and C _{ox1 When comparing} with _ox2 ,
C _ox1 = 0.8C _ox2
It becomes.

Therefore, the capacitance _{C ox1} in the structure of the semiconductor device 1, to be reduced is understood than the capacitance _{C ox2} in the structure of the semiconductor device 100.
The gate insulating film 7 includes a thin film portion 72 on the center of the bottom surface of the trench 6, and the upper surface of the thin film portion 72 is located on the same plane as the upper surface of the N ⁻ -type region 4. Therefore, the gate electrode 8 can be opposed over the entire length (total channel length) of the channel formation region 29. As a result, good operation of the VDMOSFET can be ensured.

Therefore, it is possible to secure a good operation of the VDMOSFET while reducing the gate-drain capacitance C _gd (.
2A to 2N are schematic cross-sectional views for explaining a method of manufacturing the semiconductor device shown in FIG.
First, as shown in FIG. 2A, an epitaxial layer 3 is formed on an N ⁺ type substrate 2 by an epitaxial growth method.

Next, as shown in FIG. 2B, a sacrificial oxide film 21 made of SiO ₂ is formed on the surface of the epitaxial layer 3 by thermal oxidation. Thereafter, a SiN (silicon nitride) layer is formed on the sacrificial oxide film 21 by P-CVD (Plasma Chemical Vapor Deposition), and the trench 6 is formed by patterning the SiN layer. A hard mask 22 having an opening in a portion facing the portion to be formed is formed. Then, the sacrificial oxide film 21 and the epitaxial layer 3 are etched using the hard mask 22 to form the trench 6 (step of forming a trench). After the trench 6 is formed, the sacrificial oxide film 21 and the hard mask 22 are removed.

Next, as shown in FIG. 2C, an oxide film 23 made of SiO ₂ is formed over the entire surface of the epitaxial layer 3 including the inner surface of the trench 6 by performing a thermal oxidation process.
After the oxide film 23 is formed, as shown in FIG. 2D, a polysilicon deposition layer 24 doped with N-type impurities at a high concentration is formed on the oxide film 23 by the CVD method (oxide film). A step of forming a material deposition layer). The deposited layer 24 is formed to a thickness that does not fill the trench 6.

Then, as shown in FIG. 2E, the deposited layer 24 is etched back. By this etch back, a part of the deposited layer 24 remains as a deposited piece 30 on the peripheral edge of the bottom surface of the trench 6 (step of partially leaving the oxide film material deposited layer).
Next, as shown in FIG. 2F, the oxide film 23 is removed by etching, leaving a portion sandwiched between the deposited piece 30 and the inner surface of the trench 6. Thereby, the central part and the side surface of the bottom surface of the trench 6 are exposed.

  Next, as shown in FIG. 2G, the surface of the epitaxial layer 3 and the deposited piece 30 are oxidized by thermal oxidation, and an oxide film 31 is formed. The deposited piece 30 made of polysilicon doped with N-type impurities at a high concentration is oxidized at an oxidation rate three times that of the epitaxial layer 3 made of Si, for example. Therefore, by simultaneously oxidizing the surface of the epitaxial layer 3 and the deposited piece 30, a thick film portion 32 having a relatively large thickness in the depth direction of the trench 6 is formed on the peripheral edge portion of the bottom surface of the trench 6. A thin film portion 33 having a relatively small thickness is formed on the central portion surrounded by the peripheral edge portion.

  Next, a polysilicon deposition layer doped with N-type impurities at a high concentration is formed on the oxide film 31 by CVD. The trench 6 is filled with a polysilicon deposition layer. Etching removes a portion of the polysilicon deposition layer existing outside the trench 6. Thereby, as shown in FIG. 2H, the gate electrode 8 embedded in the trench 6 is obtained (step of forming the gate electrode).

Thereafter, ions of P-type impurities are implanted from the surface of the oxide film 31 toward the inside of the epitaxial layer 3. Next, drive-in diffusion processing is performed. By this drive-in diffusion treatment, ions of P-type impurities implanted into the epitaxial layer 3 are diffused, and as shown in FIG. 2I, a body region 5 is formed in the epitaxial layer 3 (a step of forming a body region). . Further, the portion other than the body region 5 in the epitaxial layer 3 becomes the N ⁻ type region 4 as it is after the epitaxial growth.

After the drive-in diffusion process, as shown in FIG. 2J, a mask 25 having an opening in a portion facing the portion where the source region 9 is to be formed is formed on the oxide film 31. Then, ions of N-type impurities are implanted into the surface layer portion of the epitaxial layer 3 through the opening of the mask 25. After this ion implantation, the mask 25 is removed.
Further, as shown in FIG. 2K, a mask 26 having an opening at a portion facing the portion where the contact region 10 is to be formed is formed on the oxide film 31. Then, ions of P-type impurities are implanted into the surface layer portion of the epitaxial layer 3 through the opening of the mask 26. After this ion implantation, the mask 26 is removed.

Thereafter, an annealing process is performed. By this annealing treatment, ions of N-type impurities and P-type impurities implanted in the surface layer portion of the epitaxial layer 3 are activated, and the source region 9 and the contact region are formed in the surface layer portion of the epitaxial layer 3 as shown in FIG. 2L. 10 is formed (step of forming a source region).
After passing through the above steps, a portion of the oxide film 31 existing outside the trench 6 is removed, and the oxide film 31 is left only on the inner surface of the trench 6, whereby the gate insulating film 7 is obtained. The thick film portion 32 and the thin film portion 33 of the oxide film 31 become the thick film portion 71 and the thin film portion 72 of the gate insulating film 7, respectively.

Thereafter, SiO ₂ is deposited on the epitaxial layer 3 by the CVD method. Next, on the deposited SiO ₂ , a mask 20 having an opening in a portion facing the portion where the contact hole 11 and the contact hole 15 are to be formed is formed, and the SiO ₂ is dry etched using the mask 20. . Thereby, as shown in FIG. 2M, the interlayer insulating film 13 having the contact hole 11 and the contact hole 15 is formed.

Then, as shown in FIG. 2N, the gate plug 12, the gate wiring 16, the source plug 18, the source wiring 14, and the drain electrode 27 are formed. Thereby, the semiconductor device 1 shown in FIG. 1 is obtained.
In this manufacturing method, a portion of the deposited layer 24 is left as a deposited piece 30 on the peripheral portion of the bottom surface of the trench 6 by the etch back of the deposited layer 24. The deposited piece 30 is oxidized simultaneously with the surface of the epitaxial layer 3 by a thermal oxidation process. By this oxidation, the deposited piece 30 becomes a thick film portion 32 having a relatively large thickness. On the other hand, a portion formed by oxidizing the bottom surface of the trench 6 becomes a thin film portion 33 having a relatively small thickness. The thick film portion 32 and the thin film portion 33 become the thick film portion 71 and the thin film portion 72 of the gate insulating film 7, respectively.

Thus, the thick film portion 71 and the thin film portion 72 of the gate insulating film 7 can be formed simultaneously. That is, the gate insulating film 7 including the thick film portion 71 and the thin film portion 72 can be easily formed without going through a complicated process.
FIG. 3 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention.
3, parts corresponding to the parts shown in FIG. 1 are denoted by the same reference numerals as in FIG. In the following description, only differences from the structure shown in FIG. 1 will be described, and description of each part given the same reference numeral will be omitted.

In the semiconductor device 201 shown in FIG. 3, the gate insulating film 7 is formed on the side surface of the trench 6 such that the thickness of the portion 202 in contact with the source region 9 is larger than the thickness of the portion 203 in contact with the body region 5. Yes. More specifically, the thickness of the portion 203 in contact with the body region 5 of the gate insulating film 7 is set to an appropriate thickness considering the gate threshold voltage and channel resistance, and the portion of the gate insulating film 7 in contact with the source region 9 is The thickness is increased. Thus, without increasing the on-resistance R _on, the capacitance between the gate electrode 8 and the source region 9, i.e. the gate - it is possible to reduce the source capacitance C _gs, further reducing the turn gate charge Q _g can do. As a result, further speeding up of the switching operation of the transistor can be achieved.

In addition, since the thickness of the portion 202 in contact with the source region 9 of the gate insulating film 7 is large, a large interval between the gate electrode 8 and the source region 9 can be secured. As a result, the gate-source breakdown voltage can be improved.
4A to 4G are schematic cross-sectional views for explaining a method of manufacturing the semiconductor device shown in FIG.

The semiconductor device 201 illustrated in FIG. 3 is obtained by performing the processes illustrated in FIGS. 4A to 4G in place of the processes illustrated in FIGS. 2H to 2M after the processes illustrated in FIGS. 4A to 4G, parts corresponding to those shown in FIGS. 2I to 2M are denoted by the same reference numerals as in FIGS. 2I to 2M.
After the step shown in FIG. 2G, a polysilicon deposition layer doped with N-type impurities at a high concentration is formed on the oxide film 31 by CVD. The trench 6 is filled with a polysilicon deposition layer. Etching removes a portion of the deposited layer of polysilicon and oxide film 31 that exists outside the trench 6. As a result, the gate electrode 8 embedded in the trench 6 is obtained as shown in FIG. 4A.

Thereafter, ions of P-type impurities are implanted from the surface of the oxide film 31 toward the inside of the epitaxial layer 3. Next, drive-in diffusion processing is performed. By this drive-in diffusion treatment, ions of P-type impurities implanted into the epitaxial layer 3 are diffused, and a body region 5 is formed in the epitaxial layer 3. Further, the portion other than the body region 5 in the epitaxial layer 3 becomes the N ⁻ type region 4 as it is after the epitaxial growth.

After the drive-in diffusion process, as shown in FIG. 4B, a mask 25 having an opening in a portion facing the portion where the source region 9 is to be formed is formed on the oxide film 31. Then, ions of N-type impurities are implanted into the surface layer portion of the epitaxial layer 3 through the opening of the mask 25. After this ion implantation, the mask 25 is removed.
Further, as shown in FIG. 4C, a mask 26 having an opening in a portion facing the portion where the contact region 10 is to be formed is formed on the oxide film 31. Then, ions of P-type impurities are implanted into the surface layer portion of the epitaxial layer 3 through the opening of the mask 26. After this ion implantation, the mask 26 is removed.

Thereafter, an annealing process is performed. By this annealing treatment, ions of N-type impurities and P-type impurities implanted in the surface layer portion of the epitaxial layer 3 are activated, and the source region 9 and the contact region are formed in the surface layer portion of the epitaxial layer 3 as shown in FIG. 4D. 10 is formed.
Next, HF (hydrofluoric acid) is supplied to the surface of the epitaxial layer 3. Due to the action of HF, as shown in FIG. 4E, the portion of the oxide film 31 in contact with the source region 9 is removed.

Thereafter, as shown in FIG. 4F, an oxide film 204 is formed by thermal oxidation treatment between the surface of the epitaxial layer 3, the surface of the gate electrode 8, and between the source region 9 and the gate electrode 8. Since the portion where the N-type impurity is implanted at a high concentration has a high growth rate of the oxide film by the thermal oxidation treatment, the oxide film 204 grows to a thickness larger than that of the oxide film 31 in a short time.
After the above steps, as shown in FIG. 4G, a portion of the oxide film 204 existing outside the trench 6 is removed, and the oxide film 204 is left only in the trench 6. The remaining oxide film 204 constitutes the gate insulating film 7 together with the oxide film 31 and becomes a portion 202 in contact with the source region 9 of the gate insulating film 7. Next, SiO ₂ is deposited on the epitaxial layer 3 by the CVD method. Next, on the deposited SiO ₂ , a mask 20 having an opening in a portion facing the portion where the contact hole 11 and the contact hole 15 are to be formed is formed, and the SiO ₂ is dry etched using the mask 20. . Thereby, the interlayer insulating film 13 having the contact hole 11 and the contact hole 15 is formed.

Then, the gate plug 12, the gate wiring 16, the source plug 18, the source wiring 14, and the drain electrode 27 are formed. Thereby, the semiconductor device 201 shown in FIG. 3 is obtained.
A configuration in which the conductivity type of each semiconductor portion of the semiconductor devices 1 and 201 is reversed may be employed. That is, in the semiconductor devices 1 and 201, the P-type portion may be N-type and the N-type portion may be P-type.

  In addition, various design changes can be made within the scope of matters described in the claims.

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention. FIG. 2A is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device shown in FIG. FIG. 2B is a schematic cross-sectional view showing a step subsequent to FIG. 2A. FIG. 2C is a schematic cross-sectional view showing a step subsequent to FIG. 2B. FIG. 2D is a schematic cross-sectional view showing a step subsequent to FIG. 2C. FIG. 2E is a schematic cross-sectional view showing a step subsequent to FIG. 2D. FIG. 2F is a schematic cross-sectional view showing a step subsequent to FIG. 2E. FIG. 2G is a schematic cross-sectional view showing a step subsequent to FIG. 2F. FIG. 2H is a schematic cross-sectional view showing a step subsequent to FIG. 2G. FIG. 2I is a schematic cross-sectional view showing a step subsequent to FIG. 2H. FIG. 2J is a schematic cross-sectional view showing a step subsequent to FIG. 2I. FIG. 2K is a schematic cross-sectional view showing a step subsequent to FIG. 2J. FIG. 2L is a schematic cross-sectional view showing a step subsequent to FIG. 2K. FIG. 2M is a schematic cross-sectional view showing a step subsequent to FIG. 2L. FIG. 2N is a schematic cross-sectional view showing a step subsequent to FIG. 2M. FIG. 3 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention. FIG. 4A is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. FIG. 4B is a schematic cross-sectional view showing a step subsequent to FIG. 4A. FIG. 4C is a schematic cross-sectional view showing a step subsequent to FIG. 4B. FIG. 4D is a schematic cross-sectional view showing a step subsequent to FIG. 4C. FIG. 4E is a schematic cross-sectional view showing a step subsequent to FIG. 4D. FIG. 4F is a schematic cross-sectional view showing a step subsequent to FIG. 4E. FIG. 4G is a schematic cross-sectional view showing a step subsequent to FIG. 4F. FIG. 5 is a schematic cross-sectional view of a semiconductor device having a conventional trench gate type VDMOSFET. Figure 6 is a graph showing the relationship between the resistance _{R on} the gate charge quantity _{Q g} of VDMOSFET shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 3 Epitaxial layer 4 N ^- type area | region 5 Body area | region 6 Trench 7 Gate insulating film 8 Gate electrode 9 Source area 10 Contact area 24 Deposition layer 30 Deposition piece 31 Oxide film 32 Thick film part 33 Thin film part 71 Thick film part 72 Thin film portion 201 Semiconductor device

Claims (5)

Forming a trench in the semiconductor layer of the first conductivity type;
Depositing an oxide film material on the semiconductor layer to form an oxide film material deposition layer;
Etching back the oxide material deposition layer to partially leave the oxide material deposition layer on the peripheral edge of the bottom surface of the trench;
The surface of the semiconductor layer including the bottom and side surfaces of the trench and the oxide film material deposition layer left on the peripheral portion of the bottom surface of the trench are oxidized to be relatively large on the peripheral portion of the bottom surface of the trench. Forming an oxide film including a thick film portion having a thickness and a thin film portion having a relatively small thickness on a central portion surrounded by the peripheral edge portion ;
Forming a gate electrode so as to fill the trench on the oxide film;
Introducing a second conductivity type impurity from the surface of the semiconductor layer to form the second conductivity type body region;
Introducing the first conductivity type impurity from the surface of the semiconductor layer to the periphery of the trench to form the first conductivity type source region in contact with the body region;
Removing the portion outside the trench in the oxide film, and forming a gate insulating film including the thick film portion and the thin film portion on a bottom surface and a side surface of the trench.   The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the oxide film, the oxide film is formed with a uniform thickness on a side surface of the trench.   3. The semiconductor device according to claim 2, wherein in the step of forming the oxide film, the oxide film is formed such that a thickness of the thick film portion is larger than a thickness of a portion on a side surface of the trench. Manufacturing method.   The step of forming the oxide film, wherein the oxide film is formed on a side surface of the trench so that a thickness of a portion in contact with the source region is larger than a thickness of a portion in contact with the body region. 2. A method for manufacturing a semiconductor device according to 1.   5. The semiconductor device according to claim 4, wherein in the step of forming the oxide film, the oxide film is formed such that a thickness of the thick film portion is larger than a thickness of a portion in contact with the body region. Production method.

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