JP2010147299A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing a gate electrode from being deepened too much in forming a contact hole (first contact hole) for contact with the gate electrode: and to provide a method for manufacturing the same. <P>SOLUTION: A hard mask 26 having an opening 27 is formed on an epitaxial layer 3, and a gate trench 6 is formed using the hard mask 26. After that, the material of a gate electrode is embedded in the gate trench 6 and the opening 27. Then, the hard mask 26 is removed. Then, a body region 5, a drain region 4, a source region 9 and a body contact region 10 are formed, and an interlayer dielectric 11 is stacked on the epitaxial layer 3. Finally, a gate contact hole 13 and a source contact hole 15 used for contact with the gate electrode 8 and the body contact layer 10 are simultaneously formed by etching, respectively. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  For example, a trench gate type VDMOSFET (Vertical Double diffused Metal Oxide Semiconductor Field Effect Transistor) is known as a power MOSFET having a low on-resistance characteristic.

  FIG. 5 is a schematic cross-sectional view of a semiconductor device including a conventional trench gate type VDMOSFET.

The semiconductor device 101 includes a substrate 102 made of N ⁺ type silicon. An epitaxial layer 103 made of silicon is stacked on the substrate 102. The epitaxial layer 103 forms an N ⁻ type drain region 104 in the base layer portion. In the epitaxial layer 103, a P-type body region 105 is formed in contact with the drain region 104 above the drain region 104.

  A plurality of gate trenches 106 are dug from the surface of the epitaxial layer 103. The plurality of gate trenches 106 extend in the same direction so as to be parallel to each other at regular intervals. The gate trench 106 penetrates the body region 105, and the deepest part reaches the drain region 104. A gate electrode 108 made of polysilicon doped with an N-type impurity at a high concentration is buried in the gate trench 106 via a gate insulating film 107.

An N ⁺ type source region 109 is formed in the surface layer portion of the body region 105. In the surface layer portion of the body region 105, a P ⁺ -type body contact region 110 is formed penetrating the source region 109 in the layer thickness direction at a position spaced from the gate trench 106.

  An interlayer insulating film 111 is laminated on the epitaxial layer 103. In the interlayer insulating film 111, a gate contact hole 114 penetrating the interlayer insulating film 111 is formed at a portion facing the gate electrode 108. In the interlayer insulating film 111, a source contact hole 112 penetrating the interlayer insulating film 111 is formed at a portion facing the body contact region 110. The gate contact hole 114 and the source contact hole 112 are formed simultaneously by supplying the same etching gas.

  A gate contact plug 116 is embedded in the gate contact hole 114. The gate contact plug 116 is connected to the gate electrode 108 at the bottom and side surfaces thereof.

  On the other hand, a source contact plug 113 is embedded in the source contact hole 112. The source contact plug 113 is connected to the body contact region 110 on the bottom surface and connected to the source region 109 on the side surface.

  A gate wiring 117 and a source wiring 118 are formed on the interlayer insulating film 111. The gate wiring 117 and the source wiring 118 are connected to the gate contact plug 116 and the source contact plug 113, respectively.

A drain electrode 115 is formed on the back surface of the substrate 102.
JP 2006-135038 A

  In the step of forming the source contact hole 112 and the gate contact hole 114, a mask having openings facing the regions where the source contact hole 112 and the gate contact hole 114 are to be formed is formed on the interlayer insulating film 111. Then, an etching gas is supplied to the interlayer insulating film 111 through this mask. This supply of the etching gas is continued until the source contact hole 112 penetrates the interlayer insulating film 111, the source contact hole 112 is dug from the surface of the epitaxial layer 103, and the source region 109 is exposed on the side surface of the source contact hole 112. It is done. Therefore, the gate contact hole 114 is formed through the interlayer insulating film 111 and further dug down from the surface of the gate electrode 108.

  Therefore, when the etching rate of polysilicon, which is the material of the gate electrode 108, is larger than that of silicon, which is the material of the epitaxial layer 103, the gate contact hole 114 digs deep into the gate electrode 108. Therefore, the distance between the gate contact plug 116 embedded in the gate contact hole 114 and the drain region 104 is shortened. As the distance between the gate contact plug 116 and the drain region 104 is shorter, a leak current is likely to occur between the gate and the drain.

  An object of the present invention is to provide a semiconductor device capable of preventing the gate electrode from being deeply dug when a contact hole (first contact hole) for contact with the gate electrode is formed, and a method for manufacturing the same.

  In order to achieve the above object, according to the first aspect of the present invention, there is provided a step of forming a hard mask having an opening for selectively exposing a surface of a semiconductor layer of the first conductivity type, Forming a gate trench by digging from the exposed surface, embedding a gate electrode material in the gate trench and the opening, and depositing on the hard mask; and the electrode material on the surface Etch back until the surface of the hard mask is lowered to substantially the same height as the surface of the hard mask, removing the hard mask after removing the electrode material, and introducing a second conductivity type impurity into the semiconductor layer. Accordingly, the drain region of the first conductivity type contacting the body region from the second conductivity type body region and the back surface side opposite to the surface side of the semiconductor layer. Forming a region; and introducing a first conductivity type impurity into a surface layer portion of the semiconductor layer to form a first conductivity type source region in contact with the body region from the surface side of the semiconductor layer; Forming a second conductivity type body contact region connected to the body region through the source region by introducing a second conductivity type impurity into the source region in plan view; After forming the body contact region, a step of laminating an insulating film on the semiconductor layer and etching are performed to form a portion of the insulating film facing the gate trench and a portion of the insulating film facing the body contact region. A step of digging down from the surface of the semiconductor device and simultaneously forming the first contact hole and the second contact hole It is the law.

  According to this method, prior to forming the gate trench, a hard mask having an opening at a position where the gate trench is to be formed is formed on the semiconductor layer. Then, a portion of the semiconductor layer exposed from the hard mask opening is dug down to form a gate trench in the semiconductor layer. Next, with the hard mask left on the semiconductor layer, a gate electrode material (electrode material) is deposited in the gate trench and the hard mask opening and on the hard mask. Thereafter, the deposited layer of electrode material is etched back until its surface is lowered to approximately the same position as the surface of the hard mask. As a result, the electrode material remains in the openings of the gate trench and the hard mask, and a gate electrode having a shape protruding from the surface of the semiconductor layer is obtained.

  After the formation of the gate electrode, the hard mask is removed. Then, after forming the body region, the drain region, the source region, and the body contact region on the semiconductor layer, an insulating film is stacked on the semiconductor layer. Thereafter, a first contact hole and a second contact hole are simultaneously formed in a portion of the insulating film facing the gate trench and a portion of the insulating film facing the body contact region by etching.

  At this time, if through holes are formed in a portion of the insulating film facing the gate trench and a portion facing the body contact region, the gate electrode and the semiconductor layer (body contact region) are exposed through the through holes. To do. Since the gate electrode protrudes from the surface of the semiconductor layer, the etching rate of the material of the gate electrode (electrode material) is the etching rate of the semiconductor layer when the etching further proceeds after the gate electrode and the semiconductor layer are exposed. Even if it is larger than this, it is possible to prevent the gate electrode from being dug down to a deep position in the gate trench. Therefore, in a semiconductor device in which a conductive plug is embedded in the first contact hole, a long distance between the plug and the drain region can be ensured. As a result, the generation of leakage current between the gate and the drain can be suppressed.

  According to a second aspect of the present invention, a step of forming a hard mask having an opening for selectively exposing the surface of the first conductive type semiconductor layer, and a surface of the semiconductor layer exposed from the opening. Forming a gate trench, burying a gate electrode material in the gate trench and the opening and depositing it on the hard mask, and a surface of the electrode material on the semiconductor layer Etching back until it is lowered to a position approximately the same height as the surface of the electrode, and after removing the electrode material, burying a conductive material made of the same material as the electrode material so as to fill the opening; and After forming the material, a step of removing the hard mask, and introducing a second conductivity type impurity into the semiconductor layer, the second conductivity type body region and Forming a first conductivity type drain region in contact with the body region from the back side opposite to the surface side of the semiconductor layer, and introducing a first conductivity type impurity into a surface layer portion of the semiconductor layer; Forming a source region of a first conductivity type in contact with the body region from the surface side of the semiconductor layer, and introducing a second conductivity type impurity into the source region in a plan view. A step of forming a body contact region of a second conductivity type penetrating through and connected to the body region; a step of forming an insulating film on the semiconductor layer after the formation of the body contact region; and A portion of the insulating film facing the gate trench and a portion of the insulating film facing the body contact region are dug down from their surfaces to form a first contour. And a step of simultaneously forming a Tohoru and second contact holes, a method of manufacturing a semiconductor device.

  According to this method, prior to forming the gate trench, a hard mask having an opening at a position where the gate trench is to be formed is formed on the semiconductor layer. Then, a portion of the semiconductor layer exposed from the hard mask opening is dug down to form a gate trench in the semiconductor layer. Next, with the hard mask left on the semiconductor layer, a gate electrode material (electrode material) is deposited in the gate trench and the hard mask opening and on the hard mask. Thereafter, the deposited layer of electrode material is etched back until its surface is lowered to approximately the same position as the surface of the semiconductor layer. Next, a conductive material made of the same material as the electrode material is embedded in the opening of the hard mask so as to fill the opening. As a result, the electrode material in the gate trench and the conductive material in the opening of the hard mask are integrated, and a gate electrode having a shape protruding from the surface of the semiconductor layer is obtained.

  After the formation of the gate electrode, the hard mask is removed. Then, after forming the body region, the drain region, the source region, and the body contact region on the semiconductor layer, an insulating film is stacked on the semiconductor layer. Thereafter, a first contact hole and a second contact hole are simultaneously formed in a portion of the insulating film facing the gate trench and a portion of the insulating film facing the body contact region by etching.

  At this time, if through holes are formed in a portion of the insulating film facing the gate trench and a portion facing the body contact region, the gate electrode and the semiconductor layer (body contact region) are exposed through the through holes. To do. Since the gate electrode protrudes from the surface of the semiconductor layer, the etching rate of the material of the gate electrode (electrode material) is the etching rate of the semiconductor layer when the etching further proceeds after the gate electrode and the semiconductor layer are exposed. Even if it is larger than this, it is possible to prevent the gate electrode from being dug down to a deep position in the gate trench. Therefore, in a semiconductor device in which a conductive plug is embedded in the first contact hole, a long distance between the plug and the drain region can be ensured. As a result, the generation of leakage current between the gate and the drain can be suppressed.

  According to a third aspect of the present invention, there is provided a semiconductor layer, a gate trench dug down from the surface of the semiconductor layer, and a body of a first conductivity type formed on a side of the gate trench in the semiconductor layer. A source region of a second conductivity type formed in a surface layer portion of the semiconductor layer and in contact with the body region from the surface side of the semiconductor layer; and through the source region from the surface of the semiconductor layer, A second-conductivity-type body contact region connected to the region and a first-conductivity-type drain formed in the base layer portion of the semiconductor layer and in contact with the body region from the back surface side opposite to the front surface side of the semiconductor layer A gate electrode which is provided on the gate trench and fills the gate trench and protrudes from the surface of the semiconductor layer; an insulating film stacked on the semiconductor layer; A first contact hole formed in a portion of the insulating film facing the gate electrode and penetrating the insulating film, and a second contact hole formed in a portion of the insulating film facing the body contact region and penetrating the insulating film. A contact hole, a first conductive plug connected to the gate electrode through the first contact hole, and a second conductive connected to the source region and the body contact region through the second contact hole. The semiconductor device includes a plug, wherein the gate electrode has a recess having an inner surface continuous with a side surface of the first contact hole, and the first conductive plug enters the recess.

  This semiconductor device can be obtained, for example, by the method for manufacturing a semiconductor device according to claims 1 and 2.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention.

  The semiconductor device 1 has a structure in which unit cells of trench gate type VDMOSFETs are arranged in a matrix. In FIG. 1, some of the plurality of unit cells are shown.

On an N ⁺ type substrate 2 that forms the base of the semiconductor device 1, an N ⁻ type epitaxial layer 3 made of silicon doped with an N type impurity at a lower concentration than the substrate 2 is laminated. The base layer portion of the epitaxial layer 3 as a semiconductor layer forms an N ⁻ -type drain region 4 that is maintained as it is after epitaxial growth. In the epitaxial layer 3, a P-type body region 5 is formed on the drain region 4 in contact with the drain region 4.

  A gate trench 6 is dug from the surface 31 of the epitaxial layer 3. Although not shown in FIG. 1, a plurality of gate trenches 6 are formed at regular intervals, and they extend in the same direction (perpendicular to the plane of FIG. 1) in parallel with each other. The gate trench 6 is integrally formed with a pair of planar side surfaces 61 facing each other and a curved bottom surface 62 connecting them at the lower ends of the pair of side surfaces 61. Thereby, the gate trench 6 is formed in a substantially U shape in a sectional view. The gate trench 6 penetrates the body region 5 in the layer thickness direction, and the deepest portion (bottom surface 62) reaches the drain region 4.

  A gate insulating film 7 made of silicon oxide is formed in the gate trench 6 so as to cover the entire region of the side surface 61 and the bottom surface 62.

  On the gate trench 6, the gate electrode 8 is integrally formed having a buried portion 81 buried inside the gate insulating film 7 and a protruding portion 82 protruding from the surface 31 of the epitaxial layer 3. ing. The gate electrode 8 is made of, for example, polysilicon doped with an N-type impurity at a high concentration.

In the surface layer portion of the epitaxial layer 3, source regions 9 are formed on both sides of the gate trench 6 in the direction orthogonal to the gate width (left and right direction in FIG. 1). Source region 9 has an N-type impurity concentration (for example, 10 ¹⁹ / cm ³ ) that is higher than the N-type impurity concentration of drain region 4. The source region 9 extends along the gate trench 6 in the direction along the gate width (direction perpendicular to the paper surface of FIG. 1), and the bottom thereof is in contact with the body region 5 from the surface side of the epitaxial layer 3.

Further, in the epitaxial layer 3, a P ⁺ -type body contact region 10 that penetrates from the surface 31 of the source region 9 in the direction orthogonal to the gate width and is connected to the body region 5 is formed. .

  That is, the gate trenches 6 and the source regions 9 are alternately provided in a direction orthogonal to the gate width, and each extend in a direction along the gate width. A boundary between adjacent unit cells is set on the source region 9 along the source region 9 in a direction orthogonal to the gate width. At least one body contact region 10 is provided across two unit cells adjacent in a direction orthogonal to the gate width. The boundary between unit cells adjacent in the direction along the gate width is set so that the gate electrode 8 included in each unit cell has a constant gate width.

  On the epitaxial layer 3, an interlayer insulating film 11 made of silicon oxide is laminated. The interlayer insulating film 11 is formed in a substantially hat shape in sectional view protruding in the same direction as the protruding direction of the gate electrode 8 so as to bypass the protruding portion 82 of the gate electrode 8 along the surface 31 of the epitaxial layer 3. Yes.

  A gate contact hole 13 is formed in a portion of the interlayer insulating film 11 facing the gate electrode 8 so as to penetrate the interlayer insulating film 11 from the surface 12 and reach the middle part of the gate electrode 8. The bottom surface of the gate contact hole 13 is shallower than the bottom surface of the source contact hole 15 described later with respect to the surface 31 of the epitaxial layer 3. By forming the gate contact hole 13 so as to reach the middle part of the gate electrode 8, the gate electrode 8 is formed with a recess 14 having an inner surface continuous with the side surface of the gate contact hole 13 in the interlayer insulating film 11. Yes. The side surface and bottom surface of the recess 14 form part of the side surface and bottom surface of the gate contact hole 13, respectively.

  A source contact hole 15 is formed in a portion of the interlayer insulating film 11 facing the body contact region 10. The source contact hole 15 penetrates the interlayer insulating film 11 and is formed by digging down the surface layer portion of the body contact region 10. As a result, the source region 9 is exposed on the side surface of the source contact hole 15 and the body contact region 10 is exposed on the bottom surface.

  A gate contact plug 16 made of a conductive material is embedded in the gate contact hole 13. The gate contact plug 16 as the first conductive plug is electrically connected to the gate electrode 8 in the recess 14.

  A source contact plug 17 made of a conductive material is embedded in the source contact hole 15. The source contact plug 17 as the second conductive plug is electrically connected to the body contact region 10 and the source region 9.

  On the interlayer insulating film 11, a gate wiring 18 integrated with the gate contact plug 16 and a source wiring 19 integrated with the source contact plug 17 are formed to be insulated from each other.

  The source wiring 19 is grounded. When the source wiring 19 is grounded, the potentials of the source region 9 and the body region 5 that are electrically connected to the source wiring 19 through the source contact plug 17 are set to the ground potential.

  A drain electrode 22 is formed on the back surface of the substrate 2. A drain wiring 23 is connected to the drain electrode 22.

  By controlling the potential of the gate electrode 8 while applying an appropriate positive voltage to the drain electrode 22, a channel is formed in the vicinity of the interface with the gate insulating film 7 in the body region 5. A current can flow between the drain wiring 23.

  2A to 2J are schematic cross-sectional views showing the method of manufacturing the semiconductor device shown in FIG. 1 in the order of steps.

  First, the epitaxial layer 3 is formed on the substrate 2 by the epitaxial growth method.

  Next, a sacrificial oxide film 24 made of silicon oxide is formed on the surface 31 of the epitaxial layer 3 by thermal oxidation. Thereafter, a sacrificial nitride film 25 made of silicon nitride is formed on the sacrificial oxide film 24 by a method such as P-CVD (Plasma Chemical Vapor Deposition) or LP-CVD (Low Pressure Chemical Vapor Deposition). It is formed. Then, by patterning the sacrificial oxide film 24 and the sacrificial nitride film 25, as shown in FIG. 2A, a hard mask 26 having an opening 27 is formed in a portion facing the portion where the gate trench 6 is to be formed.

  Next, the gate trench 6 having the bottom surface 62 and the pair of side surfaces 61 is formed in the epitaxial layer 3 by etching from the surface 31 exposed through the opening 27 using the hard mask 26, as shown in FIG. 2B. Is done.

  Next, as shown in FIG. 2C, the gate insulating film 7 is formed on the inner surface (the bottom surface 62 and the side surface 61) of the gate trench 6 by thermal oxidation.

  Subsequently, as shown in FIG. 2D, a polysilicon deposition layer 28 as a gate electrode material is formed on the epitaxial layer 3 by CVD (Chemical Vapor Deposition) while the hard mask 26 is left. . The gate trench 6 and the opening 27 of the hard mask 26 are filled with the deposited layer 28, and the surface of the hard mask 26 is covered with the deposited layer 28.

  Then, as shown in FIG. 2E, the deposited layer 28 is etched back until the surface of the deposited layer 28 is lowered to a position substantially the same as the surface of the hard mask 26 (the surface of the sacrificial nitride film 25). As a result, the portion of the deposited layer 28 that is outside the gate trench 6 and the opening 27 (that is, the portion on the hard mask 26) is removed, and the deposited layer 28 remaining in the opening 27 is used as the protruding portion 82 to form the gate. The gate electrode 8 having the deposited layer 28 remaining in the trench 6 as the buried portion 81 is obtained.

  Thereafter, as shown in FIG. 2F, the hard mask 26 is removed. Thereby, the surface 31 of the epitaxial layer 3 is exposed.

  Next, P-type impurities (for example, boron ions) are introduced from the surface 31 into the epitaxial layer 3 by ion implantation. Then, by performing a heat treatment for diffusing the P-type impurity, as shown in FIG. 2G, a body region 5 extending from the upper end to the bottom of the gate trench 6 is formed on the side of the gate trench 6. Also, a drain region 4 is formed in the base layer portion of the epitaxial layer 3 extending from the bottom of the gate trench 6 to the substrate 2 and is maintained in the state after the epitaxial growth, separated from the body region 5.

  Next, N-type impurities (for example, arsenic ions) are introduced from the surface 31 into the epitaxial layer 3 by ion implantation. Then, by performing a heat treatment for diffusing the N-type impurity, the source region 9 is formed in the surface layer portion of the epitaxial layer 3 as shown in FIG. 2G. Further, P-type impurities (for example, boron ions) are introduced from the surface 31 into the epitaxial layer 3 by ion implantation. Then, by performing heat treatment for diffusing the P-type impurity, a body contact region 10 that penetrates the source region 9 and contacts the body region 5 is formed as shown in FIG. 2G.

  Thereafter, an interlayer insulating film 11 is laminated on the epitaxial layer 3 by CVD, as shown in FIG. 2H.

  Next, a mask (not shown) is formed on the interlayer insulating film 11 by photolithography. The mask is formed with openings that expose portions of the interlayer insulating film 11 that face the gate trench 6 and portions that face the body contact region 10.

The same etching gas is simultaneously supplied to a plurality of portions of the interlayer insulating film 11 exposed from the opening of the mask. As the etching gas, a gas capable of etching the interlayer insulating film 11 (silicon oxide) and the epitaxial layer 3 (silicon), for example, CF ₄ gas is used.

  In this etching process, first, the interlayer insulating film 11 is etched, and then the body contact region 10 and the gate electrode 8 are simultaneously etched. Then, on the body contact region 10 side, after the etching gas is supplied until the source region 9 is exposed, the supply of the etching gas is stopped. Thereby, as shown in FIG. 2I, the source contact hole 15 exposing the body contact region 10 and the source region 9 and the gate contact hole 13 exposing the gate electrode 8 as the recess 14 are formed simultaneously.

Note that the etching rate of silicon forming the epitaxial layer 3 with respect to CF ₄ gas is, for example, 200 to 300 nm / min, and the etching rate of polysilicon forming the gate electrode 8 is larger than that of the epitaxial layer 3. 350 to 450 nm / min.

  Thereafter, a conductive material is formed on the epitaxial layer 3 by sputtering. The conductive material is deposited (deposited) so as to fill the gate contact hole 13 and the source contact hole 15 and form a thin film on the interlayer insulating film 11. Then, the conductive material on the interlayer insulating film 11 is patterned by photolithography and etching. As a result, as shown in FIG. 2J, the gate contact plug 16 and the gate wiring 18, and the source contact plug 17 and the source wiring 19 are formed at the same time. Further, the drain electrode 22 is formed on the back surface of the substrate 2 by sputtering.

  Through the above steps, the semiconductor device 1 shown in FIG. 1 is obtained.

  According to the above manufacturing method, prior to the formation of the gate trench 6, the hard mask 26 having the opening 27 is formed in a portion facing the portion where the gate trench 6 is to be formed. Then, the portion exposed from the opening 27 in the epitaxial layer 3 is dug down, whereby the gate trench 6 is formed in the epitaxial layer 3. Next, with the hard mask 26 left on the epitaxial layer 3, the material of the gate electrode 8 (electrode material) is deposited in the gate trench 6 and the opening 27 of the hard mask 26 and on the hard mask 26. Is done. Thereafter, the deposited layer 28 of the electrode material is etched back until the surface thereof is lowered to substantially the same position as the surface of the hard mask 26 (sacrificial nitride film 25). As a result, the electrode material remains in the opening 27 of the gate trench 6 and the hard mask 26, and the gate electrode 8 having a shape protruding from the surface 31 of the epitaxial layer 3 is obtained.

  After the formation of the gate electrode 8, the hard mask 26 is removed. Then, after formation of body region 5, drain region 4, source region 9 and body contact region 10 on epitaxial layer 3, interlayer insulating film 11 is laminated on epitaxial layer 3.

  Thereafter, the gate contact hole 13 and the source contact hole 15 are respectively formed in a portion facing the gate trench 6 in the interlayer insulating film 11 and a portion facing the body contact region 10 in the interlayer insulating film 11 by etching using the same etching gas. Formed simultaneously.

  At this time, if through holes are formed in the portion of the interlayer insulating film 11 facing the gate trench 6 and the portion facing the body contact region 10, the gate electrode 8 and the epitaxial layer 3 ( The body contact region 10) is exposed. Since the gate electrode 8 has a protruding portion 82 that protrudes from the surface 31 of the epitaxial layer 3, the material of the gate electrode 8 (electrode material) is used when etching is further performed after the gate electrode 8 and the epitaxial layer 3 are exposed. ) Is higher than the etching rate of the epitaxial layer 3 (silicon), the gate electrode 8 can be prevented from being dug down to a deep position in the gate trench 6. Therefore, in the semiconductor device 1, it is possible to ensure a long distance between the gate contact plug 16 embedded in the gate contact hole 13 and the drain region 4. As a result, the generation of leakage current between the gate and the drain can be suppressed.

  Further, since the protrusion 82 is formed in the process of forming the gate electrode 8, it is not necessary to provide a separate process. Therefore, an increase in the number of processes in the semiconductor device manufacturing process can be suppressed. As a result, an increase in manufacturing cost can be suppressed.

  FIG. 3 is a schematic cross-sectional view of a semiconductor device according to the second embodiment of the present invention. In FIG. 3, portions corresponding to the respective portions shown in FIG. 1 are denoted by the same reference numerals as those respective portions. Further, in the following, detailed description of the parts denoted by the same reference numerals is omitted.

  In the semiconductor device 41 of FIG. 3, the gate electrode 8 includes a buried portion 42 buried in the gate trench 6 and a protruding portion 43 protruding from the surface 31 of the epitaxial layer 3 as described later. Formed with.

  Other configurations are the same as those of the first embodiment described above, and the operation is also the same.

  4A to 4K are schematic cross-sectional views showing the method of manufacturing the semiconductor device shown in FIG. 1 in the order of steps.

  First, the epitaxial layer 3 is formed on the substrate 2 by the epitaxial growth method.

  Next, a sacrificial oxide film 24 made of silicon oxide is formed on the surface 31 of the epitaxial layer 3 by thermal oxidation. Thereafter, a sacrificial nitride film 25 made of silicon nitride is formed on the sacrificial oxide film 24 by a method such as P-CVD (Plasma Chemical Vapor Deposition) or LP-CVD (Low Pressure Chemical Vapor Deposition). It is formed. Then, by patterning the sacrificial oxide film 24 and the sacrificial nitride film 25, as shown in FIG. 4A, a hard mask 26 having an opening 27 is formed at a portion facing the portion where the gate trench 6 is to be formed.

  Next, the gate trench 6 having the bottom surface 62 and the pair of side surfaces 61 is formed in the epitaxial layer 3 by etching from the surface 31 exposed from the opening 27 using the hard mask 26, as shown in FIG. 4B. .

  Next, the gate insulating film 7 is formed on the inner surface (the bottom surface 62 and the side surface 61) of the gate trench 6 by thermal oxidation as shown in FIG. 4C.

  Subsequently, as shown in FIG. 4D, a polysilicon deposition layer 28 as a material for the gate electrode is formed on the epitaxial layer 3 by a CVD (Chemical Vapor Deposition) method. The gate trench 6 and the opening 27 of the hard mask 26 are filled with the deposited layer 28, and the surface of the hard mask 26 is covered with the deposited layer 28.

  Then, as shown in FIG. 4E, the deposited layer 28 is etched back until the surface of the deposited layer 28 is lowered to a position that is substantially the same height as the surface 31 of the epitaxial layer 3. As a result, a portion of the deposited layer 28 that exists outside the gate trench 6 (that is, a portion on the hard mask 26 and a portion in the opening 27) is removed, and a buried portion 42 buried in the gate trench 6 is obtained. .

  Next, a polysilicon deposition layer (not shown) as a material (electrode material) of the gate electrode 8 is formed on the epitaxial layer 3 by the CVD (Chemical Vapor Deposition) method with the hard mask 26 remaining. The The opening 27 of the hard mask 26 is filled with the deposited layer, and the surface of the hard mask 26 is covered with the deposited layer. Then, as shown in FIG. 4F, the deposited layer is etched back until the surface of the deposited layer (not shown) is lowered to a position substantially the same as the surface of the hard mask 26 (the surface of the sacrificial nitride film 25). The As a result, the protruding portion 43 existing in the opening 27 in the deposited layer is obtained, and the gate electrode 8 in which the protruding portion 43 and the embedded portion 42 obtained in the previous step are integrated is obtained.

  Thereafter, as shown in FIG. 4G, the hard mask 26 is removed. Thereby, the surface 31 of the epitaxial layer 3 is exposed.

  Next, P-type impurities (for example, boron ions) are introduced from the surface 31 into the epitaxial layer 3 by ion implantation. Then, by performing a heat treatment for diffusing the P-type impurity, as shown in FIG. 4H, a body region 5 extending from the upper end to the bottom of the gate trench 6 is formed on the side of the gate trench 6. Also, a drain region 4 is formed in the base layer portion of the epitaxial layer 3 extending from the bottom of the gate trench 6 to the substrate 2 and is maintained in the state after the epitaxial growth, separated from the body region 5.

  Next, N-type impurities (for example, arsenic ions) are introduced from the surface 31 into the epitaxial layer 3 by ion implantation. Then, by performing heat treatment for diffusing the N-type impurity, the source region 9 is formed in the surface layer portion of the epitaxial layer 3 as shown in FIG. 4H. Further, P-type impurities (for example, boron ions) are introduced from the surface 31 into the epitaxial layer 3 by ion implantation. Then, by performing heat treatment for diffusing the P-type impurity, as shown in FIG. 4H, a body contact region 10 penetrating the source region 9 and in contact with the body region 5 is formed.

  Thereafter, an interlayer insulating film 11 is laminated on the epitaxial layer 3 by CVD, as shown in FIG. 4I.

  Next, a mask (not shown) is formed on the interlayer insulating film 11 by photolithography. The mask is formed with openings that expose portions of the interlayer insulating film 11 that face the gate trench 6 and portions that face the body contact region 10.

  The same etching gas is simultaneously supplied to a plurality of portions of the interlayer insulating film 11 exposed from the opening of the mask. The etching gas described above is used as the etching gas.

  In this etching process, first, the interlayer insulating film 11 is etched, and then the body contact region 10 and the protrusion 43 are simultaneously etched. Then, on the body contact region 10 side, after the etching gas is supplied until the source region 9 is exposed, the supply of the etching gas is stopped. Thereby, as shown in FIG. 4J, the source contact hole 15 exposing the body contact region 10 and the source region 9 and the gate contact hole 13 exposing the gate electrode 8 as the recess 14 are formed simultaneously.

  Thereafter, a conductive material is formed on the epitaxial layer 3 by sputtering. The conductive material is deposited (deposited) so as to fill the gate contact hole 13 and the source contact hole 15 and form a thin film on the interlayer insulating film 11. Then, the conductive material on the interlayer insulating film 11 is patterned by photolithography and etching. As a result, as shown in FIG. 4K, the gate contact plug 16 and the gate wiring 18, and the source contact plug 17 and the source wiring 19 which are integrated with each other are formed at the same time. Further, the drain electrode 22 is formed on the back surface of the substrate 2 by sputtering.

  Through the above steps, the semiconductor device 41 shown in FIG. 3 is obtained.

  According to the above manufacturing method, in the etching process for forming the gate contact hole 13 and the source contact hole 15, the interlayer insulating film 11 penetrates through the portion facing the gate trench 6 and the portion facing the body contact region 10, respectively. When the holes are formed, the gate electrode 8 and the epitaxial layer 3 (body contact region 10) are exposed through the through holes. Since the gate electrode 8 has the protrusion 43 that protrudes from the surface 31 of the epitaxial layer 3, the material of the gate electrode 8 (electrode material) when the etching further proceeds after the gate electrode 8 and the epitaxial layer 3 are exposed. ) Is higher than the etching rate of the epitaxial layer 3 (silicon), the gate electrode 8 can be prevented from being dug down to a deep position in the gate trench 6. Therefore, in the semiconductor device 41, a long distance between the gate contact plug 16 embedded in the gate contact hole 13 and the drain region 4 can be secured. As a result, the generation of leakage current between the gate and the drain can be suppressed.

  Although a plurality of embodiments of the present invention have been described above, the present invention can be implemented in other forms.

  For example, the conductivity type of each semiconductor portion of the semiconductor device 1 may be reversed. That is, in the semiconductor device 1 and the semiconductor device 41, the P-type portion may be N-type and the N-type portion may be P-type.

  In addition, various design changes can be made within the scope of matters described in the claims.

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 7 is a schematic cross-sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 1. It is typical sectional drawing which shows the next process of FIG. 2A. It is typical sectional drawing which shows the next process of FIG. 2B. It is typical sectional drawing which shows the next process of FIG. 2C. It is typical sectional drawing which shows the next process of FIG. 2D. It is typical sectional drawing which shows the next process of FIG. 2E. It is typical sectional drawing which shows the next process of FIG. 2F. It is typical sectional drawing which shows the next process of FIG. 2G. It is typical sectional drawing which shows the next process of FIG. 2H. FIG. 2D is a schematic cross-sectional view showing a step subsequent to FIG. 2I. It is typical sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 4 is a schematic cross sectional view for illustrating the method for manufacturing the semiconductor device shown in FIG. 3. FIG. 4B is a schematic cross-sectional view showing the next step of FIG. 4A. It is typical sectional drawing which shows the next process of FIG. 4B. FIG. 4D is a schematic sectional view showing a step subsequent to FIG. 4C. FIG. 4D is a schematic cross-sectional view showing a step subsequent to FIG. 4D. It is typical sectional drawing which shows the next process of FIG. 4E. It is typical sectional drawing which shows the next process of FIG. 4F. It is typical sectional drawing which shows the next process of FIG. 4G. It is typical sectional drawing which shows the process of FIG. 4H. FIG. 4D is a schematic sectional view showing a step subsequent to FIG. 4I. FIG. 4D is a schematic cross-sectional view showing a step subsequent to FIG. 4J. It is typical sectional drawing of a semiconductor device provided with the conventional trench gate type VDMOSFET.

Explanation of symbols

1 Semiconductor Device 3 Epitaxial Layer (Semiconductor Layer)
4 Drain region 5 Body region 6 Gate trench 8 Gate electrode 9 Source region 10 Body contact region 11 Interlayer insulating film (insulating film)
12 Surface (insulating film surface)
13 Gate contact hole (first contact hole)
14 Recess (Recess of gate electrode)
15 Source contact hole (second contact hole)
16 Gate contact plug (first conductive plug)
17 Source contact plug (second conductive plug)
26 Hard mask 27 Opening (hard mask opening)
31 Surface (Surface of semiconductor layer)
41 Semiconductor device

Claims (3)

Forming a hard mask having an opening for selectively exposing the surface of the semiconductor layer on the first conductivity type;
Forming a gate trench by digging down the semiconductor layer from the surface exposed from the opening;
Burying a material of a gate electrode in the gate trench and the opening and depositing on the hard mask;
Etching back the electrode material until the surface of the electrode material is lowered to approximately the same height as the surface of the hard mask;
Removing the hard mask after removing the electrode material;
By introducing a second conductivity type impurity into the semiconductor layer, a second conductivity type body region and a first conductivity type drain region in contact with the body region from the back side opposite to the surface side of the semiconductor layer Forming a step;
Forming a first conductivity type source region in contact with the body region from the surface side of the semiconductor layer by introducing a first conductivity type impurity into a surface layer portion of the semiconductor layer;
Forming a second contact type body contact region connected to the body region through the source region by introducing a second conductivity type impurity into the source region in plan view;
After forming the body contact region, laminating an insulating film on the semiconductor layer;
Forming a first contact hole and a second contact hole simultaneously by etching down a portion of the insulating film facing the gate trench and a portion of the insulating film facing the body contact region by etching; A method for manufacturing a semiconductor device. Forming a hard mask having an opening for selectively exposing the surface of the semiconductor layer on the first conductivity type;
Forming a gate trench by digging down the semiconductor layer from the surface exposed from the opening;
Burying a material of a gate electrode in the gate trench and the opening and depositing on the hard mask;
Etching back the electrode material until the surface of the electrode material is lowered to a position substantially the same as the surface of the semiconductor layer;
After removing the electrode material, burying a conductive material made of the same material as the electrode material so as to fill the opening;
Removing the hard mask after forming the conductive material;
By introducing a second conductivity type impurity into the semiconductor layer, a second conductivity type body region and a first conductivity type drain region in contact with the body region from the back side opposite to the surface side of the semiconductor layer Forming a step;
Forming a first conductivity type source region in contact with the body region from the surface side of the semiconductor layer by introducing a first conductivity type impurity into a surface layer portion of the semiconductor layer;
Forming a second contact type body contact region connected to the body region through the source region by introducing a second conductivity type impurity into the source region in plan view;
After forming the body contact region, laminating an insulating film on the semiconductor layer;
Forming a first contact hole and a second contact hole simultaneously by etching down a portion of the insulating film facing the gate trench and a portion of the insulating film facing the body contact region by etching; A method for manufacturing a semiconductor device. A semiconductor layer;
A gate trench dug from the surface of the semiconductor layer;
A body region of a first conductivity type formed on a side of the gate trench in the semiconductor layer;
A source region of a second conductivity type formed in a surface layer portion of the semiconductor layer and in contact with the body region from the surface side of the semiconductor layer;
A body contact region of a second conductivity type penetrating the source region from the surface of the semiconductor layer and connected to the body region;
A drain region of a first conductivity type formed in a base layer portion of the semiconductor layer and in contact with the body region from the back surface side opposite to the front surface side of the semiconductor layer;
A gate electrode provided on the gate trench, filling the gate trench and projecting from a surface of the semiconductor layer;
An insulating film laminated on the semiconductor layer;
A first contact hole formed in a portion of the insulating film facing the gate electrode and penetrating the insulating film;
A second contact hole formed in a portion of the insulating film facing the body contact region and penetrating the insulating film;
A first conductive plug connected to the gate electrode through the first contact hole;
A second conductive plug connected to the source region and the body contact region via the second contact hole;
The gate electrode is formed with a recess having an inner surface continuous with a side surface of the first contact hole,
The semiconductor device, wherein the first conductive plug enters the recess.

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