JP2009049315A - Semiconductor device, and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing a gate-drain charge amount without increasing on-resistance. <P>SOLUTION: In this semiconductor device 1, a base layer part of an epitaxial layer 3 forms an N<SP>-</SP>type region 4, and a P-type body region 5 in contact with the N<SP>-</SP>type region 4 is formed in the epitaxial layer 3. A trench 6 penetrates a body region 5 from a surface of the epitaxial layer 3, and its deepest part reaches the N<SP>-</SP>type region 4. A gate insulation film 7 is formed in the trench 6. A source region 9 is formed in a surface layer part of the epitaxial layer 3. Electrodes 81 and 82 constituting an gate electrode 8 are formed along a part of the gate insulation film 7 covering a side surface of the trench 6. In a part surrounded by the gate electrode 8 in a bottom part in the trench 6, an insulator 17 is embedded, and contacts a part of the gate insulation film 7 covering the bottom surface of the trench 6. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a trench gate type VDMOSFET and a method for manufacturing the semiconductor device.

As a structure effective for miniaturization of a VDMOSFET (Vertical Double diffused Metal Oxide Semiconductor Field Effect Transistor), a trench gate structure is generally known.
FIG. 3 is a cross-sectional view schematically showing a semiconductor device having a conventional trench gate type VDMOSFET.

The semiconductor device 100 includes an N ⁺ type substrate 101. An N ⁻ type epitaxial layer 102 is laminated on the N ⁺ type substrate 101. The base layer portion of the N ⁻ -type epitaxial layer 102 is an N ⁻ -type region 103, and the P-type body region 104 is formed adjacent to the N ⁻ -type region 103 in the upper and lower portions on the surface layer portion of the N ⁻ -type epitaxial layer 102. ing.
A trench 105 is dug down from the surface of the N ⁻ type epitaxial layer 102. Trench 105 penetrates P-type body region 104, and its deepest portion reaches N ⁻ -type region 103. A gate electrode 107 made of polysilicon doped with an N-type impurity at a high concentration is buried in the trench 105 via a gate insulating film 106 made of SiO ₂ (silicon oxide).

An N ⁺ type source region 108 is formed along the trench 105 in the surface layer portion of the P type body region 104. In the N ⁺ -type source region 108, a P ⁺ -type source contact region 109 is formed through the N ⁺ -type source region 108 in the center portion in plan view.
An interlayer insulating film 110 is stacked on the N ⁻ type epitaxial layer 102. A source wiring 111 is formed on the interlayer insulating film 110. The source wiring 111 is grounded. The source wiring 111 is in contact (electrically connected) to the N ⁺ type source region 108 and the P ⁺ type source contact region 109 through a contact hole 112 formed in the interlayer insulating film 110. Further, the gate wiring 113 is electrically connected to the gate electrode 107 through a contact hole (not shown) formed in the interlayer insulating film 110.

A drain electrode 114 is formed on the back surface of the N ⁺ type substrate 101.
By controlling the potential of the gate electrode 107 while applying an appropriate positive voltage to the drain electrode 114, a channel is formed in the vicinity of the interface with the gate insulating film 106 in the P-type body region 104, and N ⁺ A current can flow between the type source region 108 and the drain electrode 114. Thereby, the switching operation of the VDMOSFET is achieved.
JP 11-274484 A

As an index representing the switching performance of the VDMOSFET, for example, on-resistance R _on and the gate of the VDMOSFET - product R _on · Q _gd between the drain charge amount Q _gd is used, the more the product is small, achieving a faster switching operation can do.
In the semiconductor device 100 of FIG. 3, the on-resistance R _on2 the VDMOSFET has a source region composed of N ⁺ -type source region 108 and the P ⁺ -type source contact region 109, is the resistance between the N ⁺ -type substrate 101 . On the other hand, the gate-drain charge amount Q _gd2 of the _VDMOSFET is a gate-drain capacitance C _gd2 formed parasitically between the gate and the drain (the gate insulating film 106 sandwiched between the gate electrode 107 and the bottom surface of the trench 105). and the capacitance C _ox2, N ^- is the charge amount accumulated in the combined capacitance) of the capacitor C _dep2 the depletion layer 115 spreading from the interface with the mold region 103 and the P-type body region 104. In the semiconductor device 100, if it is possible to reduce R _on2 · Q _gd2, it is possible to achieve high-speed switching operation of the VDMOSFET.

However, as shown in FIG. 4, and R _on2 and Q _gd2, when reducing one, the other increases, in a so-called trade-off relationship. Therefore, to reduce the R _on2 · Q _gd2 serves to reduce one of R _on2 and Q _gd2, it is necessary to prevent the other increases.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of reducing the gate-drain charge amount without increasing the on-resistance.

  In order to achieve the above object, the invention according to claim 1 is formed in a semiconductor layer, a first conductivity type region of a first conductivity type formed in a base layer portion of the semiconductor layer, the semiconductor layer, A second conductivity type body region in contact with the first conductivity type region; a trench formed in the semiconductor layer, penetrating through the body region and having a deepest portion reaching the first conductivity type region; and a surface layer portion of the semiconductor layer A first conductivity type source region formed around the trench and in contact with the body region; a gate insulating film formed on a bottom surface and a side surface of the trench; and a portion covering the side surface of the trench in the gate insulating film Formed in a portion surrounded by the gate electrode at the bottom of the trench and in contact with a portion of the gate insulating film covering the bottom of the trench Comprising a rim member, a is a semiconductor device.

According to this configuration, the gate electrode is formed along the portion of the gate insulating film that covers the side surface of the trench. The insulator is in contact with the portion of the gate insulating film that covers the bottom surface of the trench at the bottom of the trench surrounded by the gate electrode.
A gate electrode is not formed at a portion of the gate insulating film that contacts the insulator. Therefore, compared to the conventional configuration in which the gate electrode is in contact with the entire upper surface of the portion covering the bottom surface of the trench in the gate insulating film (see FIG. 3), the first conductivity type is sandwiched between the portions covering the bottom surface of the trench in the gate insulating film. The area of the gate electrode facing the region can be reduced. Therefore, the parasitic capacitance generated between the gate electrode and the bottom surface (first conductivity type region) of the trench can be reduced. As a result, the gate-drain capacitance can be reduced, and the gate-drain charge amount can be reduced. Further, the on-resistance of the semiconductor device is not increased by the structure in which the insulator is in contact with the portion of the gate insulating film that covers the bottom surface of the trench. That is, according to the above configuration, the gate-drain charge amount can be reduced without increasing the on-resistance.

  A semiconductor device having such a structure can be obtained by the manufacturing method according to claim 2. A step of forming a trench in the first conductivity type semiconductor layer; a step of oxidizing the surface of the semiconductor layer including a bottom surface and a side surface of the trench to form an oxide film; and a gate electrode on the oxide film. Forming an electrode material deposition layer; and etching back the electrode material deposition layer to partially cover the electrode material deposition layer along a portion of the oxide film covering a side surface of the trench. Forming a gate electrode, depositing an insulating material on the oxide film so as to fill the trench, and forming an insulating material deposition layer, and the insulating material deposition layer. Etching back the oxide film removes a portion outside the trench in the insulating material deposition layer and surrounds the gate electrode at the bottom in the trench. Forming an insulator in contact with a portion of the oxide film covering the bottom surface of the trench, removing a portion outside the trench in the oxide film, and forming a gate insulating film on the bottom surface and side surface of the trench; Forming a second conductivity type body region by introducing a second conductivity type impurity from the surface of the semiconductor layer; and forming the first conductivity type from the surface of the semiconductor layer to the periphery of the trench. And introducing a conductivity type impurity to form the first conductivity type source region in contact with the body region.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a sectional view schematically showing the structure of a semiconductor device according to an embodiment of the present invention.
The semiconductor device 1 has an array structure in which unit cells having trench gate type VDMOSFETs are arranged in a matrix.
On the N ⁺ type substrate 2 that forms the base of the semiconductor device 1, silicon doped with an N type impurity at a lower concentration (for example, 1 × 10 ¹⁵ to 4 × 10 ¹⁵ / cm ³ ) than the N ⁺ type substrate 2. An N ⁻ type epitaxial layer 3 is stacked. The base layer portion of the epitaxial layer 3 is the N ⁻ type region 4 as the first conductivity type region in a state as it is after the epitaxial growth. Further, in the epitaxial layer 3, N ^- on type region 4, the body region 5 of the P type the N ^- formed in contact with the mold region 4.

A trench 6 is dug from the surface of the epitaxial layer 3. Trench 6 penetrates body region 5, and the deepest portion reaches N ⁻ type region 4. A plurality of trenches 6 are formed at regular intervals in the left-right direction in FIG. 1, and each extend in a direction (direction along the gate width) orthogonal to the plane of FIG. Each trench 6 has a width W ₁ in the horizontal direction in FIG. 1 (a direction orthogonal to the gate width), for example, formed by 0.5 [mu] m. A gate insulating film 7 made of SiO ₂ (silicon oxide) is formed in the trench 6 so as to cover the entire inner surface. The gate insulating film 7 is formed with a thickness _Tox of, for example, 50 nm.

A gate electrode 8 is formed inside the gate insulating film 7 in the trench 6.
The gate electrode 8 is made of polysilicon doped with an N-type impurity at a high concentration, and includes an electrode 81 and an electrode 82 having the same shape and facing each other in a direction perpendicular to the gate width. The electrodes 81 and 82 are formed along the portion of the gate insulating film 7 that covers the side surface of the trench 6, and are formed in a substantially triangular cross section in which the thickness of the trench 6 extends in a reverse taper direction in the depth direction of the trench 6. Yes. The insulator 17 is buried at the bottom of the trench 6 by filling the portion surrounded by the electrode 81 and the electrode 82 in the trench 6 with SiO ₂ halfway in the depth direction of the trench 6. . The insulator 17 is in contact with the portion of the gate insulating film 7 covering the bottom surface of the trench 6 with a width W ₂ of 0.3 μm, for example.

Further, in the surface layer portion of the epitaxial layer 3, an N-type impurity concentration higher than the N-type impurity concentration of the N ⁻ -type region 4 on both sides of the trench 6 in the direction orthogonal to the gate width (left-right direction in FIG. 1). An N ⁺ type source region 9 having (for example, 10 ¹⁹ / cm ³ ) is formed. The source region 9 extends in the direction along the gate width along the trench 6, and the bottom thereof is in contact with the body region 5. A P ⁺ -type source contact region 10 is formed through the source region 9 at the center of the source region 9 in the direction orthogonal to the gate width.

  That is, the trenches 6 and the source regions 9 are alternately provided in a direction orthogonal to the gate width, and extend in a direction along the gate width. A boundary between adjacent unit cells is set on the source region 9 along the source region 9 in a direction orthogonal to the gate width. At least one source contact region 10 is provided across two unit cells adjacent in a direction orthogonal to the gate width. The boundary between unit cells adjacent in the direction along the gate width is set so that the gate electrode 8 included in each unit cell has a constant gate width.

  An interlayer insulating film 13 is stacked on the epitaxial layer 3. A source wiring 14 is formed on the interlayer insulating film 13. The source wiring 14 is grounded. The source wiring 14 is in contact (electrically connected) to the source region 9 and the source contact region 10 through a source plug 18 embedded in a contact hole 15 formed in the interlayer insulating film 13. A gate wiring 16 is formed on the interlayer insulating film 13. The gate wiring 16 is in contact (electrically connected) with the electrodes 81 and 82 via the gate plug 12 embedded in the contact hole 11 formed in the trench 6 and the interlayer insulating film 13.

A drain electrode 27 is formed on the back surface of the N ⁺ type substrate 2.
By controlling the potential of the gate electrode 8 while applying an appropriate positive voltage to the drain electrode 27, a channel is formed in the vicinity of the interface with the gate insulating film 7 in the body region 5. A current can flow between the drain electrode 27.
In this semiconductor device 1, an electrode 81 and an electrode 82 having a substantially triangular cross-section forming the gate electrode 8 are arranged opposite to each other in a direction perpendicular to the gate width. The electrode 81 and the electrode 82 are respectively formed in the gate insulating film 7. It is formed along a portion covering the side surface of the trench 6. Then, the portion surrounded by the gate electrode 8 (the electrode 81 and electrode 82) at the bottom of the trench 6, the insulator 17 in a portion covering the bottom of the trench 6 in the gate insulating film 7 is in contact with the width W ₂ .

The gate electrode 8 is not formed on the portion of the gate insulating film 7 where the insulator 17 is in contact. Therefore, for example, as in the semiconductor device 100 shown in FIG. 3, the trench in the gate insulating film 7 is compared with the conventional configuration in which the gate electrode 107 is in contact with the entire upper surface of the portion covering the bottom surface of the trench 105 in the gate insulating film 106. 6, the area of the gate electrode 8 facing the N ⁻ -type region 4 can be reduced with the portion covering the bottom surface of 6 being sandwiched. As a result, the gate-drain capacitance C _gd1 in the semiconductor device 1 can be reduced.

For example, in the semiconductor device 100 of FIG. 3, the parasitic capacitance C _ox2 generated between the gate electrode 107 and the bottom surface (N ⁻ -type region 103) facing each other with the gate insulating film 106 interposed therebetween, and the semiconductor of the present embodiment. In the device 1, the parasitic capacitance C _ox1 generated between the gate electrode 8 and the bottom surface (N ⁻ type region 4) of the trench 6 facing each other with the gate insulating film 7 interposed therebetween is compared. In this comparison, the width of the trench 105, the thickness of the gate insulating film 106, and the gate width in the semiconductor device 100 are the width W ₁ of the trench 6, the thickness _Tox of the gate insulating film 7, and the gate width in the semiconductor device 1. Same as W _g .

In the semiconductor device 100 of FIG. 3, the parasitic capacitance C _ox2 is C _ox2 = ε _ox · W ₁ · W _g / T _ox (ε _ox : relative permittivity of SiO ₂ W _g : gate width T _ox : gate insulating film 7 Thickness).
In contrast, in the semiconductor device 1 of the present embodiment, when the difference between the width W ₂ of width W ₁ and the insulator 17 of the trench 6 and 2W _3, the parasitic capacitance C _{ox1 is, C ox1 = ε ox · 2W} 3 W _g / T _ox (ε _ox : relative dielectric constant of SiO ₂ W _g : gate width T _ox : thickness of the gate insulating film 7)

Substituting, for example, W ₁ = 0.5 μm, W ₂ = 0.3 μm, W ₃ = 0.1 μm and _Tox = 50 nm into the above _formula , and comparing C _ox1 and C _ox2 , C _ox1 = 0.4C _ox2 , it can be seen that C _ox1 in the semiconductor device 1 is reduced compared to C _ox2 in the semiconductor device 100.
The gate of the semiconductor device 1 - drain capacitance C _gd1 is, for example, a C _ox1, N ^- -type region 4 and the depletion layer 28 expanding from the interface between the body region 5 is represented by the combined capacitance of the capacitance C _dep1 with. Therefore, C _gd1 can be reduced by reducing C _ox1, and as a result, the gate-drain charge amount Q _gd1 can be reduced.

Further, the on-resistance of the semiconductor device 1 is not increased by the configuration in which the insulator 17 is in contact with the portion of the gate insulating film 7 covering the bottom surface of the trench 6. Therefore, according to the structure of the semiconductor device 1, the gate-drain charge amount Q _gd1 can be reduced without increasing the on-resistance.
2A to 2M are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device 1 in the order of steps.

First, as shown in FIG. 2A, an epitaxial layer 3 is formed on an N ⁺ type substrate 2 by an epitaxial growth method. Next, as shown in FIG. 2B, a sacrificial oxide film 21 made of SiO ₂ is formed on the surface of the epitaxial layer 3 by thermal oxidation. Thereafter, a SiN (silicon nitride) layer is formed on the sacrificial oxide film 21 by P-CVD (Plasma Chemical Vapor Deposition), and the trench 6 is formed by patterning the SiN layer. A hard mask 22 having an opening in a portion facing the portion to be formed is formed. Then, the sacrificial oxide film 21 and the epitaxial layer 3 are etched using the hard mask 22 to form the trench 6 (step of forming a trench). After the trench 6 is formed, the sacrificial oxide film 21 and the hard mask 22 are removed.

Next, as shown in FIG. 2C, by performing a thermal oxidation process, an oxide film 23 made of SiO ₂ is formed over the entire surface of the epitaxial layer 3 including the inner surface of the trench 6 (an oxide film is formed). Process).
After the oxide film 23 is formed, as shown in FIG. 2D, a polysilicon deposition layer 24 doped with N-type impurities at a high concentration is formed on the oxide film 23 by the CVD method (electrode material). A step of forming a deposited layer). The deposited layer 24 is formed with a thickness at which the portion on the side surface of the trench 6 facing in the direction orthogonal to the gate width does not contact. That is, the trench 6 is not filled with the deposited layer 24.

  Then, as shown in FIG. 2E, the portion covering the bottom surface of the trench 6 of the deposition layer 24 is partially removed by etch back. Thereby, the deposited layer 24 partially left along the side surface of the trench 6 in the oxide film 23 becomes the gate electrode 8 (electrode 81 and electrode 82) (step of forming the gate electrode), and the oxide film 23 A portion covering the bottom surface of the trench 6 is partially exposed.

Next, as shown in FIG. 2F, SiO ₂ is deposited on the epitaxial layer 3 by HDP-CVD (High Density Plasma Chemical Vapor Deposition). SiO ₂ is deposited until the trench 6 is filled and the epitaxial layer 3 is covered. Thereby, the deposition layer 19 is formed in the trench 6 and on the epitaxial layer 3 (step of forming an insulating material deposition layer).

  Then, as shown in FIG. 2G, a part of the deposited layer 19 existing outside the trench 6 and a part of the trench 6 existing in the trench 6 are removed by etch back. Thereby, the insulator 17 in contact with the portion covering the bottom surface of the trench 6 in the oxide film 23 is formed in the portion surrounded by the electrode 81 and the electrode 82 at the bottom in the trench 6 (step of forming an insulator). Further, a portion of the oxide film 23 existing outside the trench 6 is removed, and the oxide film 23 is left only on the inner surface of the trench 6, whereby the gate insulating film 7 is obtained (step of forming a gate insulating film).

Thereafter, ions of P-type impurities are implanted toward the inside of the epitaxial layer 3.
Next, drive-in diffusion processing is performed. By this drive-in diffusion treatment, ions of P-type impurities implanted into the epitaxial layer 3 are diffused, and as shown in FIG. 2H, a body region 5 is formed in the epitaxial layer 3 (a step of forming a body region). . Further, the portion other than the body region 5 in the epitaxial layer 3 becomes the N ⁻ -type region 4 as it is after the epitaxial growth.

After the drive-in diffusion process, as shown in FIG. 2I, a mask 25 having an opening in a portion facing the portion where the source region 9 is to be formed is formed on the epitaxial layer 3. Then, ions of N-type impurities are implanted into the surface layer portion of the epitaxial layer 3 through the opening of the mask 25. After this ion implantation, the mask 25 is removed.
Further, as shown in FIG. 2J, a mask 26 having an opening in a portion facing the portion where the source contact region 10 is to be formed is formed on the epitaxial layer 3. Then, ions of P-type impurities are implanted into the surface layer portion of the epitaxial layer 3 through the opening of the mask 26. After this ion implantation, the mask 26 is removed.

Thereafter, an annealing process is performed. By this annealing treatment, ions of N-type impurities and P-type impurities implanted into the surface layer portion of the epitaxial layer 3 are activated, and the source region 9 and the source contact are formed on the surface layer portion of the epitaxial layer 3 as shown in FIG. Region 10 is formed (step of forming a source region).
Thereafter, SiO ₂ is deposited on the epitaxial layer 3 by the CVD method. SiO ₂ is deposited until the trench 6 is filled and the epitaxial layer 3 is covered. Next, on the deposited SiO ₂ , a mask 20 having an opening in a portion facing the portion where the contact hole 11 and the contact hole 15 are to be formed is formed, and the SiO ₂ is dry etched using the mask 20. . In this dry etching, the etching time is controlled so that the electrode 81 and the electrode 82 can be exposed. Thereby, as shown in FIG. 2L, the interlayer insulating film 13 in which the contact hole 11 and the contact hole 15 are formed is formed.

As shown in FIG. 2M, a gate plug 12 is embedded in the contact hole 11, a gate wiring 16 is formed on the gate plug 12, and a source plug 18 is embedded in the contact hole 15. A source wiring 14 is formed thereon. A drain electrode 27 is formed on the back surface of the N ⁺ type substrate 2. Thereby, the semiconductor device 1 shown in FIG. 1 is obtained.

Although one embodiment of the present invention has been described above, the present invention can be implemented in other forms. For example, a configuration in which the conductivity type of each semiconductor portion of the semiconductor device 1 is inverted may be employed. That is, in the semiconductor device 1, the P-type portion may be N-type and the N-type portion may be P-type.
In addition, various design changes can be made within the scope of matters described in the claims.

It is sectional drawing which shows typically the structure of the semiconductor device which concerns on one Embodiment of this invention. FIG. 2 is a cross-sectional view schematically showing a method for manufacturing the semiconductor device of FIG. 1. It is sectional drawing which shows the process next of FIG. 2A typically. It is sectional drawing which shows the process next of FIG. 2B typically. FIG. 2D is a cross-sectional view schematically showing a step subsequent to FIG. 2C. It is sectional drawing which shows the next process of FIG. 2D typically. It is sectional drawing which shows the process next of FIG. 2E typically. It is sectional drawing which shows the next process of FIG. 2F typically. It is sectional drawing which shows the process next to FIG. 2G typically. It is sectional drawing which shows the next process of FIG. 2H typically. FIG. 2D is a cross-sectional view schematically showing a step subsequent to FIG. 2I. FIG. 2D is a cross-sectional view schematically showing a step subsequent to FIG. 2J. FIG. 2D is a cross-sectional view schematically showing a step subsequent to FIG. 2K. FIG. 2D is a cross-sectional view schematically showing the next step of FIG. 2L. It is sectional drawing which shows typically the semiconductor device which has the conventional trench gate type VDMOSFET. The ON resistance R _on2 and the gate of the VDMOSFET shown in FIG. 3 - it is a graph showing the relationship between the drain charge amount Q _gd2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 N ⁺ type board | substrate 3 Epitaxial layer 4 N ^- type area | region 5 Body area | region 6 Trench 7 Gate insulating film 8 Gate electrode 9 Source area 10 Source contact area 17 Insulator 19 Deposition layer 23 Oxide film 24 Deposition layer

Claims (2)

A semiconductor layer;
A first conductivity type region of a first conductivity type formed in a base layer portion of the semiconductor layer;
A second conductivity type body region formed in the semiconductor layer and in contact with the first conductivity type region;
A trench formed in the semiconductor layer, penetrating the body region, and having a deepest portion reaching the first conductivity type region;
A source region of a first conductivity type formed around the trench in the surface layer portion of the semiconductor layer and in contact with the body region;
A gate insulating film formed on the bottom and side surfaces of the trench;
A gate electrode formed along a portion of the gate insulating film covering a side surface of the trench;
And an insulator formed in a portion surrounded by the gate electrode at a bottom portion in the trench and in contact with a portion covering the bottom surface of the trench in the gate insulating film. Forming a trench in the semiconductor layer of the first conductivity type;
Oxidizing the surface of the semiconductor layer including the bottom and side surfaces of the trench to form an oxide film;
Depositing a gate electrode material on the oxide film to form an electrode material deposition layer;
Etching back the electrode material deposition layer to leave the electrode material deposition layer partially along the portion of the oxide film that covers the side surface of the trench; and forming a gate electrode;
Depositing an insulating material on the oxide film so as to fill the trench to form an insulating material deposition layer;
Etching back the insulating material deposition layer and the oxide film removes a portion outside the trench in the insulating material deposition layer, and at a portion surrounded by the gate electrode at the bottom in the trench, Forming an insulator in contact with a portion of the oxide film covering the bottom surface of the trench, removing a portion outside the trench in the oxide film, and forming a gate insulating film on the bottom surface and side surface of the trench; ,
Introducing a second conductivity type impurity from the surface of the semiconductor layer to form the second conductivity type body region;
Introducing a first conductivity type impurity from the surface of the semiconductor layer to the periphery of the trench to form the first conductivity type source region in contact with the body region. .

Images