JP3999225B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a MIS transistor having a trench gate structure (hereinafter referred to as a trench gate type MISFET) and a manufacturing method thereof.

  A so-called trench gate structure in which a trench is formed in a semiconductor substrate and then a gate electrode is formed in the trench (groove) is applied to a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) or MISFET. This is an advantageous structure for use in (see, for example, Patent Document 1).

FIG. 12 is a sectional view showing a semiconductor device having a conventional trench gate type MISFET. In the trench gate type MISFET shown in FIG. 12, an N ⁻ type drain layer 112 made of an N type epitaxial layer and a P type body region 113 are sequentially formed on an N ⁺ type silicon substrate 111. Further, a trench 116 is formed in the P-type body region 113 so as to penetrate the P-type body region 113 and reach the bottom to the N ⁻ type drain layer 112. A pair of N ⁺ type source regions 114 that are in contact with each trench 116 are formed at the top of the P type body region 113 sandwiched between the two trenches 116, and the top of the P type body region 113 is A P ⁺ type diffusion region 115 is formed in a portion sandwiched between the pair of N ⁺ type source regions 114. The N ⁺ type source region 114 and the P ⁺ type diffusion region 115 are formed so as not to reach the N ⁻ type drain layer 112.

The trench 116 is filled with a gate electrode 118 made of polysilicon via a gate insulating film 117, and an insulating film made of a cap oxide film 119 and a PSG (Phospho Silicate Glass) film is formed on the gate electrode 118. A film 120 is formed. A source electrode film 121 is formed on the N ⁺ type source region 114, the P ⁺ type diffusion region 115 and the insulating film 120.

In the power MISFET having such a structure, a high voltage is applied between the source electrode film 121 and the N ⁻ -type drain layer 112, and a threshold voltage or higher is applied between the gate electrode 118 and the N ⁺ -type source region 114. When a voltage is applied, an inversion layer is formed at the interface between the gate insulating film 117 and the P-type body region 113, and current flows from the N ⁻ -type drain layer 112 to the N ⁺ -type source region 114 through the inversion layer.
JP 2001-85685 A

  However, the conventional power MISFET as described above has the following problems.

As shown in FIG. 12, the bottom surface (lower end) of the N ⁺ -type source region 114 is formed to be lower than the upper surface (upper end) of the gate electrode 118 embedded in the trench 116. When ion implantation is performed deeply to form such an N ⁺ type source region 114, a portion of the N ⁺ type source region 114 that is in contact with the source electrode film 121 on the upper side surface of the trench 116. Thus, it is difficult to form an ohmic junction between the source electrode film 121 and the N ⁺ type source region 114. Therefore, it is impossible to make a source contact with a sufficiently low resistance.

  Therefore, the present invention realizes a good ohmic junction between a source electrode film and a source region, and thereby a semiconductor device including a trench gate type MISFET capable of making a sufficiently low resistance source contact, and its manufacture It aims to provide a method.

  In order to achieve the above object, a first semiconductor device according to the present invention is provided on a semiconductor region, a drain region of a first conductivity type provided below the semiconductor region, and a drain region in the semiconductor region. A second conductivity type body region, a first conductivity type first source region provided on the body region in the semiconductor region, and a first source region in the semiconductor region. A second source region of the first conductivity type reaching, a trench provided in the semiconductor region and reaching the drain region, a gate insulating film provided on at least a side surface in the trench, and provided on the gate insulating film in the trench And an insulating film covering the gate electrode in the trench.

  According to the first semiconductor device, since the first source region can be provided deeply, the first source region and the gate electrode can easily overlap with each other, and the gate-source offset can be avoided. it can. Then, when the source electrode is formed on the upper surface of the semiconductor region by providing the second source region so that the impurity concentration in the vicinity of the upper surface of the semiconductor region is high, the source electrode and the second source region A good ohmic junction can be formed therebetween. Due to these two synergistic effects, the resistance of the semiconductor device can be reduced as compared with the prior art.

  In the first semiconductor device, the drain region may include a first conductivity type high concentration drain region and a first conductivity type low concentration drain region provided on the high concentration drain region.

  The first semiconductor device may further include a source electrode provided above the second source region.

  In this case, the source electrode is provided from above the second source region to above the portion of the side surface in the trench where the second source region is exposed, and the peak position of the impurity concentration in the second source region. Is preferably within the range of the height of the source electrode provided on the side surface in the trench. In this case, since the impurity concentration of the second source region in contact with the source electrode is high, the ohmic junction at the interface between the two becomes better.

  In this case, a silicide film may be provided between the second source region and the source electrode. In this case, the resistance between the source region and the source electrode is further reduced by the silicide film.

  In the first semiconductor device, it is preferable that the upper end of the portion of the gate electrode that is in contact with the gate insulating film is provided above the boundary between the first source region and the body region. In this case, the overlap amount between the portion of the gate electrode that is in contact with the gate insulating film and the first source region is increased, so that the resistance can be further reduced.

  In the first semiconductor device, the upper end of the insulating film is preferably provided below the peak position of the impurity concentration of the second source region. In this way, when the semiconductor region exposed on the side surface of the trench is silicided in the subsequent manufacturing process, the silicide film can be reliably formed up to the height of the peak position.

  In the first semiconductor device, a second conductivity type impurity region in contact with the body region is provided in a region located on each side of the first source region and the second source region in the semiconductor region, Each side surface of the first source region and the second source region may be surrounded by a trench and an impurity region.

A second semiconductor device according to the present invention includes a semiconductor region, a first conductivity type drain region provided below the semiconductor region, and a second conductivity type body region provided on the drain region in the semiconductor region. A source region of a first conductivity type provided on the body region in the semiconductor region and reaching the upper surface of the semiconductor region; a trench provided in the semiconductor region and reaching the drain region; and a gate provided on at least a side surface in the trench An insulating film, a gate electrode provided on the gate insulating film in the trench, and an insulating film covering the gate electrode in the trench, the upper end of the insulating film being provided below the upper surface of the semiconductor region In the source region, the impurity concentration in the portion from the upper end of the insulating film to the upper surface of the semiconductor region is 1 × 10 ²⁰ atoms / cm ³ or more.

  That is, according to the second semiconductor device, when the source region is provided on the upper surface of the semiconductor region by providing the source region so that the impurity concentration in the vicinity of the upper surface of the semiconductor region is increased, A good ohmic junction can be formed between the two. Therefore, it is possible to provide a semiconductor device including a trench gate type MISFET that can have a sufficiently low resistance source contact.

  In the second semiconductor device, the drain region may include a first conductivity type high concentration drain region and a first conductivity type low concentration drain region provided on the high concentration drain region.

  The second semiconductor device may further include a source electrode provided above the source region.

  In this case, the source electrode is provided from above the source region to above the portion of the side surface in the trench where the source region is exposed, and the peak position of the impurity concentration in the source region is provided on the side surface in the trench. Preferably, it is within the range of the height of the source electrode. In this case, since the impurity concentration of the source region in contact with the source electrode is high, the ohmic junction at the interface between the two becomes better.

  In this case, a silicide film may be provided between the source region and the source electrode. In this case, the resistance between the source region and the source electrode is further reduced by the silicide film.

  In the second semiconductor device, the upper end of the portion of the gate electrode that is in contact with the gate insulating film is preferably provided above the boundary between the source region and the body region. In this case, the overlap amount between the portion of the gate electrode that is in contact with the gate insulating film and the source region is increased, so that the resistance can be further reduced.

  In the second semiconductor device, the upper end of the insulating film is preferably provided below the peak position of the impurity concentration of the source region. In this way, when the semiconductor region exposed on the side surface of the trench is silicided in the subsequent manufacturing process, the silicide film can be reliably formed up to the height of the peak position.

  In the second semiconductor device, a region of the semiconductor region located on the side of the source region is provided with a second conductivity type impurity region in contact with the body region, and a side surface of the source region is formed by the trench and the impurity region. It may be surrounded.

  The first semiconductor device manufacturing method according to the present invention includes a step (a) of preparing a semiconductor region having a drain region and a second conductivity type body region provided on the drain region; A step (b) of forming a trench reaching the drain region, a step (c) of forming a gate insulating film on at least a side surface of the semiconductor region exposed in the trench after the step (b), and a step (c) After step (d), a step (d) of forming a gate electrode on the gate insulating film in the trench, a step (e) of forming an insulating film on the gate electrode in the trench after the step (d), and a step (b) After the step (f) of forming the first source region of the first conductivity type on the body region by ion-implanting the first conductivity type impurity into the semiconductor region, and after the step (b) The first conductivity type in the semiconductor region By ion-implanting an impurity, it is provided on the first source region, and the step (g) forming a second source region of the first conductivity type to reach the upper surface of the semiconductor region.

  According to the manufacturing method of the first semiconductor device, the second source region is formed shallower than the first source region. As a result, the first source region can diffuse the impurity to a region away from the upper surface of the semiconductor region, and the second source region can increase the impurity concentration near the upper surface of the semiconductor region. Therefore, the first source region and the gate electrode can be reliably overlapped, thereby preventing an offset between the gate and the source. In addition, a semiconductor device having a good ohmic junction between the source electrode provided on the second source region and the second source region can be obtained. By these two synergistic effects, a lower resistance semiconductor device can be obtained.

  The first semiconductor device manufacturing method may further include a step (h) of forming a source electrode above the second source region after the step (e), the step (f), and the step (g). Good.

  In this case, in the step (h), the source electrode is also formed on the portion of the side surface in the trench where the second source region is exposed, and the peak position of the impurity concentration in the second source region is defined in the trench. It is preferable to set within the range of the height of the source electrode provided on the inner side surface. In this case, since the impurity concentration of the second source region in contact with the source electrode can be increased, the ohmic junction at the interface between the two can be improved.

  In this case, the method further includes a step of forming a silicide film on the second source region after the step (e), the step (f), and the step (g) and before the step (h). In the step (h), it is preferable to form a source electrode on the silicide film. In this way, by providing the silicide film, the resistance between the source region and the source electrode can be further reduced.

  In the first method for manufacturing a semiconductor device, in step (a), as the drain region, a first conductivity type high-concentration drain region provided in a lower portion of the semiconductor region and a first concentration provided on the high-concentration drain region. A conductive type low-concentration drain region may be prepared.

  In the first method for manufacturing a semiconductor device, in step (f), the boundary between the first source region and the body region is lower than the upper end of the portion of the gate electrode that is in contact with the gate insulating film. It is preferable to perform ion implantation. Thus, the overlap amount between the portion of the gate electrode that is in contact with the gate insulating film and the first source region can be increased.

  In the first method for manufacturing a semiconductor device, in the step (g), it is preferable to perform ion implantation so that the peak position of the impurity concentration of the second source region is higher than the upper end of the insulating film. This is due to the following reason. That is, the silicide film is formed on the trench side surface (the semiconductor region is exposed) above the insulating film. At this time, if the peak concentration is located above the upper end of the insulating film, the silicide film can be reliably formed up to the height where the peak concentration is located.

  In the first method for manufacturing a semiconductor device, after the step (a), a body is formed from the upper surface of the semiconductor region to a region located on each side of the first source region and the second source region in the semiconductor region. The method may further include a step (i) of forming a second conductivity type impurity region reaching the region, and the side surfaces of the first source region and the second source region may be surrounded by the trench and the impurity region.

The second method for manufacturing a semiconductor device according to the present invention includes a step (a) of preparing a semiconductor region having a drain region and a body region of a second conductivity type provided on the drain region; A step (b) of forming a trench reaching the drain region, a step (c) of forming a gate insulating film on at least a side surface of the semiconductor region exposed in the trench after the step (b), and a step (c) After step (d), a step (d) of forming a gate electrode on the gate insulating film in the trench, a step (e) of forming an insulating film on the gate electrode in the trench after the step (d), and a step (b) ), A step (j) of forming a first conductivity type source region on the body region by ion-implanting the first conductivity type impurity into the semiconductor region at least three times or more, The top edge of the insulation film Than the upper surface of the semiconductor region is provided below, the impurity concentration of the portion from the upper end of the insulating film of the source region to the upper surface of the semiconductor region is 1 × 10 ²⁰ atoms / cm ³ or more.

  According to the second method for manufacturing a semiconductor device, since the source region is formed by ion implantation three or more times, impurities can be diffused from the upper surface of the semiconductor region to a region spaced downward, and the vicinity of the upper surface of the semiconductor region. The impurity concentration of can be increased. Accordingly, the source region and the gate electrode can be reliably overlapped, thereby preventing an offset between the gate and the source. In addition, a semiconductor device having a good ohmic junction between the source electrode provided on the source region and the source region can be obtained. By these two synergistic effects, a lower resistance semiconductor device can be obtained.

  The second semiconductor device manufacturing method may further include a step (k) of forming a source electrode above the source region after the step (e) and the step (j).

  In this case, in the step (k), the source electrode is formed also on the portion of the side surface in the trench where the source region is exposed, and the peak position of the impurity concentration in the source region is provided on the side surface in the trench. It is preferable to set within the range of the height of the source electrode. In this way, since the impurity concentration of the source region in contact with the source electrode can be increased, the ohmic junction at the interface between the two can be made in a better state.

  In this case, the method further includes a step of forming a silicide film on the source region after the step (e) and the step (j) and before the step (k). A source electrode is preferably formed thereon. In this way, by providing the silicide film, the resistance between the source region and the source electrode can be further reduced.

  In the second method for manufacturing a semiconductor device, in step (a), as the drain region, a first conductivity type high concentration drain region provided below the semiconductor region and a first concentration provided on the high concentration drain region. A conductive type low-concentration drain region may be prepared.

  In the second method for fabricating a semiconductor device, in step (j), ion implantation is performed so that the boundary between the source region and the body region is lower than the upper end of the portion of the gate electrode that is in contact with the gate insulating film. It is preferable to carry out. Thus, the overlap amount between the source region and the portion of the gate electrode that is in contact with the gate insulating film can be increased.

  In the second method for manufacturing a semiconductor device, in step (j), it is preferable to perform ion implantation so that the peak position of the impurity concentration of the source region is higher than the upper end of the insulating film. This is due to the following reason. That is, the silicide film is formed on the trench side surface (the semiconductor region is exposed) above the insulating film. At this time, if the peak concentration is located above the upper end of the insulating film, the silicide film can be reliably formed up to the height where the peak concentration is located.

  In the second method for manufacturing a semiconductor device, after the step (a), a second conductivity type impurity region reaching the body region from the upper surface of the semiconductor region is formed in a region located lateral to the source region in the semiconductor region. A step (l) of forming may further be provided, and the side surface of the source region may be surrounded by the trench and the impurity region.

  According to the semiconductor device and the manufacturing method thereof of the present invention, it is possible to satisfactorily make an ohmic junction between the source region and the silicide film that becomes a part of the source electrode while avoiding the offset between the gate and the source. Thus, a low resistance trench gate type MISFET can be obtained.

(First embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings.

  First, the trench gate type MISFET according to the present embodiment will be described. FIG. 1A is a schematic plan view showing the semiconductor device according to the present embodiment. Moreover, FIG.1 (b) is the typical perspective view which looked at the cross section in the AA 'line of Fig.1 (a) in the BB' direction. In FIG. 1A, the silicide film 10 and the source electrode film 12 on the surface of the semiconductor region 14 in FIG. 1B are omitted for easy understanding.

  In the semiconductor device of the present embodiment, as shown in FIG. 1A, a plurality of trenches 13 are provided at a certain interval along a direction parallel to the BB ′ direction on the semiconductor region 14. Yes. The upper portion of each trench 13 is filled with a source electrode film 12, and in the plane shown in FIG. 1A, the source electrode film 12 and the semiconductor region 14 (the high concentration N-type diffusion region 9, the second high concentration). A silicide film 10 is formed between the P-type source region 8). Further, high-concentration N-type diffusion regions 9 are formed on both sides of the second high-concentration P-type source region 8. That is, the second high-concentration P-type source region 8 has two sides that are in contact with the two trenches 13 provided opposite to each other, and the other two sides that are provided with two high levels provided opposite to each other. Each of the N-type diffusion regions 9 is in contact with each other. Here, the configuration shown in FIG. 1A may be repeatedly provided in the AA ′ direction and / or the BB ′ direction.

As shown in FIG. 1B, the semiconductor region 14 includes a high concentration P-type drain region 1 and a low concentration P-type drain region 2 provided on the high concentration P-type drain region 1 and made of an epitaxial layer. , An N-type body region 3 provided on the low-concentration P-type drain region 2, a first high-concentration P-type source region 6 provided on the source formation region of the N-type body region 3, and a first A second high-concentration P-type source region 8 provided on the high-concentration P-type source region 6 and a high-concentration N-type diffusion region 9 provided in the body contact formation region on the N-type body region 3 are provided. is doing. The second high concentration P-type source region 8 is formed so as to be in contact with the entire upper surface of the first high concentration P-type source region 6. Here, the semiconductor region 14 may be a silicon substrate, for example, or may be composed of a silicon substrate and an epitaxial layer formed thereon. In the present application, the high concentration P-type drain region means a region having an impurity concentration of about 1 × 10 ¹⁹ atoms / cm ³ or more, and the low concentration P-type drain region means an impurity concentration of 5 × 10 ¹⁶ atoms / cm ^3. It shall mean a region that is about cm ³ or less.

  Then, the trench 13 penetrates through the second high concentration P-type source region 8, the first high concentration P-type source region 6 and the N-type body region 3 in the semiconductor region 14, and the low-concentration P-type drain region 2. Of these, it is provided to reach a predetermined depth. This trench 13 extends in the BB ′ line direction, penetrates through the high-concentration N-type diffusion region 9 and the N-type body region 3 in the body contact formation region, and is predetermined in the low-concentration P-type drain region 2. It is provided to reach the depth of. The trenches 13 are provided at regular intervals, and at least the N-type body region 3, the first high-concentration P-type source region 6, and the second high-concentration P-type source region are located between the two trenches 13. 8 and a high-concentration N-type diffusion region 9 are formed.

  In the trench 13, a gate electrode 5 made of polysilicon is provided via a gate insulating film 4. The gate electrode 5 extends from the side surface of the N-type body region 3 in the trench 13 to a part of the low-concentration P-type drain region 2 and a part of the first high-concentration P-type source region 6 located above and below it. It is provided to straddle.

  A buried insulating film 7 is provided in the trench 13 above the gate electrode 5 so as to cover the gate electrode 5. The end of the bottom surface of the buried insulating film 7, that is, the portion in contact with the gate insulating film 4 is provided above the interface between the first high-concentration P-type source region 6 and the N-type body region 3. .

  Then, on the upper surface of the second high-concentration P-type source region 8 and the high-concentration N-type diffusion region 9 and on the portion of the side surface of the trench 13 that is located above the buried insulating film 7 in the semiconductor region 14. Further, a silicide film 10 is provided. A source electrode film 12 is formed on the silicide film 10 so as to fill the buried insulating film 7 in the trench 13.

  In this structure, the first high concentration P-type source region 6 and the second high concentration P-type source region 8 have concentration peak positions at different depths. Specifically, the lower end (bottom surface) of the first high-concentration P-type source region 6 is located below the upper end of the gate electrode 5. The second high-concentration P-type source region 8 is provided so that the impurity concentration peak is located above the upper end (upper surface) of the buried insulating film 7 formed on the gate electrode 5.

  According to the semiconductor device of the present embodiment, the first high-concentration P-type source region 6 is deeply provided, whereby the first high-concentration P-type source region 6 and the gate electrode 5 are easily overlapped. It is possible to avoid an offset between the gates. Then, by increasing the impurity concentration in the vicinity of the upper surface of the semiconductor region 14 by the second high concentration P-type source region 8, the source electrode film 12 electrically connected to the silicide film 10 and the second high concentration A good ohmic junction can be formed with the P-type source region 8. With these two synergistic effects, it is possible to form a semiconductor device having a lower resistance than before.

  FIG. 2A is a diagram showing the impurity distribution along the line mm ′ shown in FIG. 1B, and FIG. 2B is the vicinity of the line mm ′ shown in FIG. It is sectional drawing which expands and shows this structure. In FIG. 2, Chemical conc. (Solid line) is the concentration of the actually implanted P-type impurity (boron), and Active conc. (Thick broken line) is the impurity concentration of the implanted impurity that is activated by annealing. Yes, Phos (dashed line) is the concentration of the N-type impurity (phosphorus) implanted before boron implantation.

  As shown in FIG. 2A, in the present embodiment, the first high-concentration P-type source region 6 is formed in order to avoid a high resistance due to an offset between the gate and the source. The junction position between the first high-concentration P-type source region 6 and the N-type body region 3 is controlled by the first implantation condition, and the second high-concentration P-type source region 8 is formed to form the second high-concentration P-type source region 8. The impurity distribution is controlled so that the concentration peak is located at the depth at which the silicide film 10 is formed on the inner side surface of the trench 13 according to the implantation condition 2. Thereby, a low-resistance source contact can be formed. Even if the order of the first injection and the second injection is reversed, the effect is not affected. In the present embodiment, the silicide film 10 is provided between the source electrode film 12 that is a wiring electrode film and the semiconductor region 14, but the silicide film may be omitted in the present invention.

Further, it is preferable to set the impurity concentration of the surface portion of the semiconductor region 14 including the second high-concentration P-type source region 8 to about 1 × 10 ²⁰ atoms / cm ³ or more. In this way, a good ohmic junction can be realized between the source electrode film 12 and the source region.

  Next, a method for manufacturing the semiconductor device of this embodiment will be described. 3A to 3C and FIGS. 4A to 4C are cross-sectional views illustrating the manufacturing process of the semiconductor device according to the present embodiment.

First, in the step shown in FIG. 3A, after a high concentration P-type drain region 1 is formed on a semiconductor substrate (not shown), a P-type epitaxial having a thickness of 5 μm is formed on the high concentration P-type drain region 1 by epitaxial growth. A layer (not shown) is formed. Thereafter, P, which is an N-type impurity, is ion-implanted into the P-type epitaxial layer under the conditions of an implantation energy of 500 KeV and a dose of 1 × 10 ¹³ ions / cm ² , so that a diffusion depth (drain) is formed above the P-type epitaxial layer. -Body junction position) An N-type body region 3 of 1.1 μm is formed. As a result, a semiconductor region 14 is formed between the high-concentration P-type drain region 1 and the N-type body region 3 in which the low-concentration P-type drain region 2 made of a P-type epitaxial layer is formed. Thereafter, a mask material 11 having an opening in a trench formation region is formed on the substrate using photolithography and dry etching. As the mask material 11, an oxide film, a laminated film made of a lower oxide film and an upper nitride film, or a laminated film made of a lower oxide film, an intermediate silicon film, and an upper nitride film may be used. Thereafter, by performing dry etching using the mask material 11 as a mask, a trench having a depth of 1.3 to 1.5 nm that penetrates the N-type body region 3 and reaches a predetermined depth of the low-concentration P-type drain region 2 is obtained. 13 is formed. At this time, the bottom surface of the trench 13 is formed between the upper surface and the lower surface of the low concentration P-type drain region 2 so as not to reach the upper surface of the high concentration P-type drain region 1.

  Next, in the step shown in FIG. 3B, a gate insulating film 4 having a thickness of 20 to 30 nm made of, for example, a silicon oxide film is formed on the surface in the trench 13. Before forming the gate insulating film 4, a sacrificial oxide film may be formed in order to remove surface roughness in the trench 13, and then the sacrificial oxide film may be removed by wet etching.

  Next, in the step shown in FIG. 3C, a polysilicon film (not shown) having a thickness of 400 nm serving as a gate electrode is deposited on the substrate so as to fill the trench 13. At this time, in order to reduce the resistance of the polysilicon film, a doped polysilicon film is deposited in advance, or an impurity is diffused after depositing a non-doped polysilicon film. Thereafter, etch back is performed on the polysilicon film to remove a portion of the polysilicon film located on the upper surface of the semiconductor region 14 and an upper portion of the portion located in the trench 13 to thereby form a trench. A gate electrode 5 is formed in 13. At this time, it is desirable that the retreat amount from the surface of the semiconductor region 14 to the upper surface of the gate electrode 5 is about 200 to 500 nm.

  Next, in the step shown in FIG. 4A, a silicon oxide film (NSG (Non Silicate Glass) film / not shown) containing no impurities is formed on the entire surface of the substrate by, for example, CVD (chemical vapor deposition). It is formed with a thickness of about. Thereafter, the silicon oxide film is etched for a predetermined time to form a buried insulating film 7 made of a silicon oxide film in the trench 13. At this time, it is desirable that the retraction amount from the upper surface of the semiconductor region 14 to the upper surface of the buried insulating film 7 is about 0 to 120 nm. In this etching, the portion of the gate insulating film 4 exposed above the trench 13 is also removed, so that the upper end of the gate insulating film 4 is at the same height as the upper surface of the buried insulating film 7. Further, the mask material 11 (shown in FIG. 3C) remaining on the upper surface of the semiconductor region 14 is also removed. As a result, the N-type body region 3 is exposed on the upper surface thereof and on the side surfaces of the upper portion of the trench 13. The mask material 11 may be selectively removed after removing the silicon oxide film and the gate insulating film 4.

Next, in the step shown in FIG. 4B, after forming a resist (not shown) having an opening in the source formation region on the substrate, B, which is a P-type impurity, is implanted into the N-type body region 3 at an energy of 80 KeV. Then, ions are implanted under the condition of a dose amount of 4 × 10 ¹⁵ ions / cm ² to form a first high-concentration P-type source region 6 having a diffusion depth of 1.1 μm, for example. Subsequently, B, which is a P-type impurity, is ion-implanted under the conditions of an implantation energy of 60 KeV and a dose of 4 × 10 ¹⁵ ions / cm ² , thereby forming a second high-concentration P-type source region 8 having a diffusion depth of 150 nm, for example. To do. At this time, the second high-concentration P-type source region 8 is formed so that the peak position of the impurity concentration of the second high-concentration P-type source region 8 is higher than the upper surface of the buried insulating film 7. Note that either the first high concentration P-type source region 6 or the second high concentration P-type source region 8 may be formed first. Thereafter, although not shown in FIG. 4B, after forming a resist having an opening on the body contact formation region on the substrate, N as an N-type impurity is implanted with an implantation energy of 120 KeV and a dose of 5 × 10. Ions are implanted under the condition of ¹⁵ ions / cm ² to form a high concentration N-type diffusion region 9 as shown in FIG.

  Next, in the step shown in FIG. 4C, the silicide film 10 is formed on the entire exposed surface of the semiconductor region 14 (including the portion exposed on the side surface in the trench 13) using the salicide technique. Selectively form. Thereby, a silicide film 10 is formed on the second high concentration P-type source region 8 and the high concentration N-type diffusion region 9 (see FIG. 1). Thereafter, after forming a metal film (not shown) on the substrate, the metal film is patterned to form the source electrode film 12 on the silicide film 10 and the buried insulating film 7.

  According to the above configuration, the source region is provided using two types of acceleration voltages. Specifically, the junction depth between the source region and the body region is controlled by the first implantation for forming the first high-concentration P-type source region 6, thereby offsetting the source-gate. You can avoid that. Further, by the second implantation for forming the second high-concentration P-type source region 8, the impurity concentration in the vicinity of the upper surface of the semiconductor region 14 is increased, thereby the silicide film 10 and the second high-concentration P-type source region. A good ohmic junction can be realized. With these two synergistic effects, it is possible to form a semiconductor device having a lower resistance than the conventional one.

(Second Embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to the drawings.

  This embodiment differs from the first embodiment in the impurity distribution of the source region and the method for forming the impurity distribution. That is, the planar configuration and the cross-sectional configuration of the semiconductor device of this embodiment are basically the same as those of the first embodiment shown in FIGS.

  FIG. 5A is a diagram showing the impurity distribution of the present embodiment along the line mm ′ shown in FIG. 1B. FIG. 5B is a diagram showing the m distribution shown in FIG. It is sectional drawing which expands and shows the structure of the vicinity of -m 'line. In the first embodiment, the first high-concentration P-type source region 6 and the second high-concentration P-type source region 8 correspond to respective impurity distributions formed by two ion implantations. However, in this embodiment, the distinction between the first high-concentration P-type source region 6 and the second high-concentration P-type source region 8 does not correspond to a specific impurity distribution. Specifically, in this embodiment, the source region is formed by ion implantation three or more times, and a portion of the formed source region that is located below the upper end (upper surface) of the buried insulating film 7 is the first. One high concentration P-type source region 6 is formed, and a portion of the formed source region located above the upper end (upper surface) of the buried insulating film 7 is defined as a second high concentration P-type source region 8. Also in this embodiment, the end portion of the bottom surface of the buried insulating film 7, that is, the portion in contact with the gate insulating film 4 is from the interface between the first high-concentration P-type source region 6 and the N-type body region 3. Is also provided on the upper side.

As shown in FIG. 5A, the feature of the present embodiment is that the impurity concentration of the second high-concentration P-type source region 8, that is, the range from the upper end of the buried insulating film 7 to the upper surface of the semiconductor region 14. The impurity concentration of the located source region is 1 × 10 ²⁰ atoms / cm ³ or more. Here, the peak position of the impurity concentration in the source region composed of the first high-concentration P-type source region 6 and the second high-concentration P-type source region 8 is above the upper end of the buried insulating film 7, that is, in the trench 13. It exists in the range of the height of the source electrode film 12 provided in an inner side surface.

In this embodiment, in order to form the impurity distribution as shown in FIG. 5A, in the step shown in FIG. 4B of the first embodiment, for example, ion implantation is performed as follows. That is, first, B, which is a P-type impurity, is ion-implanted (implanted (A)) under conditions of an implantation energy of 4 KeV and a dose of 4 × 10 ¹⁵ ions / cm ² , and then B is implanted with an energy of 20 KeV and a dose of 4 ×. Ion implantation (implantation (B)) is performed under the condition of 10 ¹⁵ ions / cm ² , and then B is implanted (implantation (C)) under the conditions of an implantation energy of 60 KeV and a dose of 4 × 10 ¹⁵ ions / cm ^2. . The semiconductor device manufacturing method of this embodiment is the same as that of the first embodiment except for the process shown in FIG. 4B, that is, the source region forming process. The impurity concentration shown in FIG. 5A is the impurity concentration activated by annealing among the implanted impurities. In FIG. 5A, Phos (dashed line) is the concentration of the N-type impurity (phosphorus) implanted before boron implantation. Moreover, in this embodiment, the implementation order of injection | pouring (A)-(C) is not specifically limited. Further, the junction shown in FIG. 5A is formed by the implantation (C).

  Hereinafter, the effects of the present embodiment will be described with reference to FIGS. 6 and 7. FIG. 6 schematically shows details of the resistance Rs generated in the source region. FIG. 7 shows the influence of the above-described ion implantation (A) to (C) on the drain current with reference to the case where a complete ohmic junction is formed between the source electrode film and the source region. .

  As shown in FIG. 7, excellent characteristics equivalent to those of ohmic junction can be obtained by forming the source region by three injections (A) to (C). In contrast, the characteristics deteriorate as the number of injections decreases. This is presumably because the trench sidewall contact resistance shown in FIG. 6 is reduced by implantation (B), and the Si surface contact resistance shown in FIG. 6 is reduced by implantation (A).

  That is, according to the present embodiment, since the source region is formed by ion implantation three or more times, impurities can be diffused from the upper surface of the semiconductor region 14 to a region away from the upper surface, and the vicinity of the upper surface of the semiconductor region 14 can be diffused. Impurity concentration can be increased. Therefore, the source region and the gate electrode 5 can be reliably overlapped, thereby preventing an offset between the gate and the source. In addition, a semiconductor device having a good ohmic junction between the source electrode film 12 provided on the source region and the source region can be obtained. By these two synergistic effects, a lower resistance semiconductor device can be obtained.

  In the first and second embodiments, the P-channel type MIS transistor has been described as an example. However, the present invention can also be applied to an N-channel type MIS transistor, and in this case, the same effect can be obtained. Can be obtained.

  In the first and second embodiments, the drain region has the high concentration P-type drain region 1 and the low concentration P-type drain region 2 provided on the high concentration P-type drain region 1. . However, instead of this, for example, as shown in FIG. 8, the low concentration P-type drain region 2 may not be provided.

  In the first and second embodiments, the trench 13 penetrates the second high-concentration P-type source region 8, the first high-concentration P-type source region 6 and the N-type body region 3 in the semiconductor region 14. However, the low-concentration P-type drain region 2 is provided so as to reach a predetermined depth. However, instead of this, for example, as shown in FIG. 9, the trench 13 includes a second high concentration P-type source region 8, a first high concentration P-type source region 6, and an N-type body region in the semiconductor region 14. 3 and the low-concentration P-type drain region 2 may be provided so as to reach a predetermined depth in the high-concentration P-type drain region 1. Also in this case, for example, as shown in FIG. 10, the low concentration P-type drain region 2 may not be provided.

FIGS. 11A and 11B are diagrams for explaining the effects obtained by the configurations shown in FIGS. 9 and 10. That is, as shown in FIGS. 11A and 11B, when the trench 13 is formed deeply, thereby increasing the overlap amount Lov between the gate electrode and the drain region, the on-current _ION also increases. On the contrary, when the trench 13 is shallow and the overlap amount Lov between the gate electrode and the drain region is small, or when an offset (offset amount: Loff) is generated between the gate electrode and the drain region, the on-state is turned on. The current _ION decreases.

  As described above, the present invention relates to a semiconductor device and a method for manufacturing the same, and when applied to a trench gate type MISFET, a silicide which becomes a part of a source region and a source electrode while avoiding a gate-source offset. The effect of being able to satisfactorily make ohmic contact with the film is obtained, which is very useful.

(A) is a typical top view which shows the semiconductor device which concerns on the 1st and 2nd embodiment of this invention, (b) is a cross section in the AA 'line of Fig.1 (a) B It is the typical perspective view seen in -B 'direction. (A) is a figure which shows the impurity distribution (1st Embodiment) in the mm 'direction shown in FIG.1 (b), (b) is the mm' location shown in FIG.1 (b). It is sectional drawing which expands and shows the structure of the vicinity. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(c) is sectional drawing which shows each process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A) is a figure which shows the impurity distribution (2nd Embodiment) in the mm 'direction shown in FIG.1 (b), (b) is the mm' location shown in FIG.1 (b). It is sectional drawing which expands and shows the structure of the vicinity. It is a figure for demonstrating the effect acquired by the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a figure for demonstrating the effect acquired by the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a typical perspective view which shows the variation of the semiconductor device which concerns on the 1st and 2nd embodiment of this invention. It is a typical perspective view which shows the variation of the semiconductor device which concerns on the 1st and 2nd embodiment of this invention. It is a typical perspective view which shows the variation of the semiconductor device which concerns on the 1st and 2nd embodiment of this invention. (A) And (b) is a figure for demonstrating the effect acquired by the structure shown in FIG.9 and FIG.10. It is sectional drawing which shows the semiconductor device which has the conventional trench gate type MISFET.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 High concentration P type drain region 2 Low concentration P type drain region 3 N type body region 4 Gate insulating film 5 Gate electrode 6 First high concentration P type source region 7 Buried insulating film 8 Second high concentration P type source region 9 High-concentration N-type diffusion region 10 Silicide film 11 Mask material 12 Source electrode film 13 Trench 14 Semiconductor region

Claims (28)

A semiconductor region;
A drain region of a first conductivity type provided under the semiconductor region;
A body region of a second conductivity type provided on the drain region in the semiconductor region;
A first source region of a first conductivity type provided on the body region in the semiconductor region;
A second source region of a first conductivity type provided on the first source region in the semiconductor region and reaching the upper surface of the semiconductor region;
A trench provided in the semiconductor region and reaching the drain region from an upper surface of the semiconductor region ;
A gate insulating film provided on at least a side surface in the trench;
A gate electrode provided on the gate insulating film in the trench;
Bei example an insulating film overlying the gate electrode in said trench,
An upper end of a portion of the gate electrode that is in contact with the gate insulating film is provided above a boundary between the first source region and the body region .   2. The semiconductor according to claim 1, wherein the drain region includes a first conductivity type high concentration drain region and a first conductivity type low concentration drain region provided on the high concentration drain region. apparatus.   The semiconductor device according to claim 1, further comprising a source electrode provided above the second source region. The source electrode is provided from above the second source region to above the portion of the side surface in the trench where the second source region is exposed,
4. The semiconductor device according to claim 3, wherein a peak position of the impurity concentration in the second source region is within a height range of the source electrode provided on a side surface in the trench.   The semiconductor device according to claim 3, wherein a silicide film is provided between the second source region and the source electrode. The upper end of the insulating film, the semiconductor device according to any one of claims 1 to 5, characterized in that provided below the peak position of the impurity concentration of the second source region. Of the semiconductor regions, the body contact formation region located on the side of each of the first source region and the second source region has a second conductivity type that reaches the body region from the upper surface of the semiconductor region . the semiconductor device according to any one of claims 1 to 6, characterized in that the impurity region is provided. A semiconductor region;
A drain region of a first conductivity type provided under the semiconductor region;
A body region of a second conductivity type provided on the drain region in the semiconductor region;
A source region of a first conductivity type provided on the body region in the semiconductor region and reaching an upper surface of the semiconductor region;
A trench provided in the semiconductor region and reaching the drain region from an upper surface of the semiconductor region ;
A gate insulating film provided on at least a side surface in the trench;
A gate electrode provided on the gate insulating film in the trench;
An insulating film covering the gate electrode in the trench ;
A source electrode provided above the source region ,
The upper end of the insulating film is provided below the upper surface of the semiconductor region,
The semiconductor device according to claim 1, wherein an impurity concentration in a portion from the upper end of the insulating film to the upper surface of the semiconductor region in the source region is 1 × 10 ²⁰ atoms / cm ³ or more. 9. The semiconductor according to claim 8 , wherein the drain region includes a first conductivity type high concentration drain region and a first conductivity type low concentration drain region provided on the high concentration drain region. apparatus. The source electrode is provided from above the source region to above the portion of the side surface in the trench where the source region is exposed,
10. The semiconductor device according to claim 8 , wherein a peak position of the impurity concentration in the source region is within a height range of the source electrode provided on a side surface in the trench. The semiconductor device according to claim 8, wherein a silicide film is provided between the source region and the source electrode. The upper end of the portion in contact with the gate insulating film of said gate electrode is any one of claims 8-11, characterized in that provided above the boundary between the source region and the body region 2. A semiconductor device according to item 1. 13. The semiconductor device according to claim 8 , wherein an upper end of the insulating film is provided below a peak position of an impurity concentration of the source region. Of the semiconductor region, a body contact formation region located on the side of the source region is provided with a second conductivity type impurity region reaching the body region from the upper surface of the semiconductor region. The semiconductor device of any one of Claims 8-13 . Preparing a semiconductor region having a drain region and a second conductivity type body region provided on the drain region;
Forming a trench reaching the drain region from an upper surface of the semiconductor region in the semiconductor region (b);
(C) forming a gate insulating film on at least a side surface of the semiconductor region exposed in the trench after the step (b);
A step (d) of forming a gate electrode on the gate insulating film in the trench after the step (c);
A step (e) of forming an insulating film on the gate electrode in the trench after the step (d);
After the step (b), a step (f) of forming a first source region of the first conductivity type on the body region by ion implantation of a first conductivity type impurity into the semiconductor region;
After the step (b), a first conductivity type second ion reaching the upper surface of the semiconductor region is formed on the first source region by ion implantation of a first conductivity type impurity into the semiconductor region. e Bei and step (g) forming a source region,
In the step (f), the ion implantation is performed so that a boundary between the first source region and the body region is lower than an upper end of a portion of the gate electrode that is in contact with the gate insulating film. A method for manufacturing a semiconductor device, comprising: The method further comprises a step (h) of forming a source electrode above the second source region after the step (e), the step (f), and the step (g). 15. A method for manufacturing a semiconductor device according to 15 . In the step (h), the source electrode is formed also on a portion of the side surface in the trench where the second source region is exposed, and the peak position of the impurity concentration in the second source region is set. The method of manufacturing a semiconductor device according to claim 16 , wherein the semiconductor device is set within a range of a height of the source electrode provided on a side surface in the trench. A step of forming a silicide film on the second source region after the step (e), the step (f) and the step (g) and before the step (h);
18. The method of manufacturing a semiconductor device according to claim 16 , wherein the source electrode is formed on the silicide film in the step (h). In the step (a), as the drain region, a first conductivity type high concentration drain region provided below the semiconductor region and a first conductivity type low concentration drain provided on the high concentration drain region. The method for manufacturing a semiconductor device according to claim 15 , wherein a region is prepared. 20. The ion implantation is performed in the step (g) so that a peak position of the impurity concentration of the second source region is higher than an upper end of the insulating film. A method for manufacturing a semiconductor device according to claim 1. After the step (a), the body region is formed from the upper surface of the semiconductor region to the body contact formation region located on each side of the first source region and the second source region of the semiconductor region. the method of manufacturing a semiconductor device according to any one of claims 15 to 20, characterized in that it further comprises a step (i) of forming an impurity region of the second conductivity type to reach. Preparing a semiconductor region having a drain region and a second conductivity type body region provided on the drain region;
Forming a trench reaching the drain region from an upper surface of the semiconductor region in the semiconductor region (b);
(C) forming a gate insulating film on at least a side surface of the semiconductor region exposed in the trench after the step (b);
A step (d) of forming a gate electrode on the gate insulating film in the trench after the step (c);
A step (e) of forming an insulating film on the gate electrode in the trench after the step (d);
After the step (b), a first conductivity type source region is formed on the body region by ion implantation of a first conductivity type impurity into the semiconductor region at least three times or more ( j) and
A step (k) of forming a source electrode above the source region after the step (e) and the step (j) ,
The upper end of the insulating film is provided below the upper surface of the semiconductor region,
A method of manufacturing a semiconductor device, wherein an impurity concentration in a portion from the upper end of the insulating film to an upper surface of the semiconductor region in the source region is 1 × 10 ²⁰ atoms / cm ³ or more. In the step (k), the source electrode is formed also on a portion of the side surface in the trench where the source region is exposed, and a peak position of the impurity concentration in the source region is defined on the side surface in the trench. 23. The method of manufacturing a semiconductor device according to claim 22 , wherein the method is set within a range of a height of the source electrode provided in the semiconductor device. A step of forming a silicide film on the source region after the step (e) and the step (j) and before the step (k);
24. The method of manufacturing a semiconductor device according to claim 22 , wherein the source electrode is formed on the silicide film in the step (k). In the step (a), as the drain region, a first conductivity type high concentration drain region provided below the semiconductor region and a first conductivity type low concentration drain provided on the high concentration drain region. The method for manufacturing a semiconductor device according to claim 22 , wherein a region is prepared. In the step (j), the ion implantation is performed so that a boundary between the source region and the body region is lower than an upper end of a portion of the gate electrode that is in contact with the gate insulating film. The method for manufacturing a semiconductor device according to claim 22 , wherein the method is a semiconductor device manufacturing method. 27. The ion implantation is performed according to any one of claims 22 to 26 , wherein in the step (j), the ion implantation is performed such that a peak position of the impurity concentration of the source region is higher than an upper end of the insulating film. The manufacturing method of the semiconductor device as described in 2. After the step (a), a second conductivity type impurity region reaching the body region from the upper surface of the semiconductor region is formed in a body contact formation region located on the side of the source region in the semiconductor region. the method of manufacturing a semiconductor device according to any one of claims 22 to 27, characterized by further comprising a step (l).

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