JP2007158139A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing an element forming region and raising driving ability, while raising electric separation between semiconductor elements, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device includes the element forming region 10A which is electrically separated from a semiconductor substrate 11 and divided into a plurality of island regions 10a arrayed in a gate widthwise direction, gate electrodes 15a, 15b formed over the plurality of island regions 10a, a p-type body region 17 formed in the upper part of the island region 10a, source regions 18s and a body draw-up region 19 formed in the upper part of the p-type body region 17, drain regions 18d formed in the upper part of the island region 10a, and in-contact wiring 22 and metal wiring 23 which are electrically connected to the drain regions 18d or source regions 18s and the body draw-up region 19. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a semiconductor element electrically isolated from a semiconductor substrate and a manufacturing method thereof.

  A general LDMOS (Laterally Diffused Metal-Oxide Semiconductor) according to the prior art is disclosed, for example, in Non-Patent Document 1 shown below. Such an LDMOS is widely used as an integrated circuit for power control that can be formed on the same chip together with other semiconductor elements by forming a diffusion layer in the lateral direction.

  Further, a conventional technique for reducing the chip area by reducing the element area of the LDMOS is disclosed in, for example, Patent Document 1 shown below. This prior art has a configuration in which a trench is formed in a bulk substrate, a gate insulating film is formed on the surface inside the trench, and then a gate electrode is embedded in the trench. In such a configuration, the channel is formed along the side surface of the gate electrode during operation. That is, a channel is formed in the vertical direction with respect to the bulk substrate surface. Therefore, the element area on the upper surface of the bulk substrate can be reduced, and as a result, the chip area can be reduced.

  Further, in recent semiconductor devices, a semiconductor substrate having an SOI (Silicon On Insulator) structure (hereinafter referred to as an SOI substrate) is used instead of a bulk substrate for the purpose of downsizing and speeding up of operation. It was.

  An SOI substrate generally comprises a lowermost support substrate, an insulating film on the support substrate, and a silicon thin film on the insulating film. A semiconductor element such as a transistor is formed on a silicon thin film in an SOI substrate. For this reason, a semiconductor device using an SOI substrate is in a state in which the semiconductor element is surrounded by an insulating film that does not need to consider electrical interference, thereby reducing leakage current and electrical interference between semiconductor elements. Etc. are reduced.

  For reference, for example, Patent Document 2 or 3 shown below discloses a technique for improving electrical isolation between semiconductor elements by widening the bottom of a substantial element isolation insulating film. . In the technique disclosed in Patent Document 2, when forming an element isolation insulating film by STI (Shallow Trench Isolation) method, the bottom of the formed trench is expanded by dry etching, and this is filled with the insulating film. The bottom of the element isolation insulating film to be formed is widened. In the technique disclosed in Patent Document 3, when forming an element isolation insulating film by the STI method, the bottom of the formed element isolation insulating film is expanded by thermally oxidizing the bottom of the formed trench. Yes.

For reference, for example, Patent Document 4 shown below discloses a technique for expanding the bottom of a trench formed in a bulk substrate by CDE (Chemical Dry-Etching).
JP 2005-136150 A Japanese Patent Laid-Open No. 7-130952 JP 2004-186557 A JP-A-6-37275 S. Whiston, et al., “Complementary LDMOS transistor for a CMOS / BiCMOS process”, ISPSD'2000, pp. 51-54, May 2000.

  By the way, in the semiconductor device according to Patent Document 1 described above, a gate electrode is formed in a trench formed so as to divide the source and drain. For this reason, the driving capability of the semiconductor element is determined by the depth of the trench in which the gate electrode is formed. However, as described above, the SOI substrate has an insulating layer under the silicon thin film. Therefore, when the semiconductor device according to Patent Document 1 is formed on an SOI substrate, the drive capability that can be realized is limited by the thickness of the silicon thin film.

  Patent Documents 2 to 4 described above disclose a technique for improving electrical isolation between semiconductor elements by widening the bottom of the element isolation insulating film formed on the bulk substrate by the STI method. A configuration for improving the driving capability of the semiconductor element is not disclosed.

  Accordingly, the present invention has been made in view of the above problems, and provides a semiconductor device and a manufacturing method thereof capable of reducing the element formation region and improving the driving capability while improving the electrical isolation between the semiconductor elements. The purpose is to provide.

  In order to achieve such an object, a semiconductor device according to the present invention includes a plurality of island-like regions having first to third regions arranged in a first direction and arranged in order in a second direction perpendicular to the first direction. A semiconductor substrate having a first well region of the first conductivity type including the first well region is formed on the entire side surface and lower surface of the first well region, and the first well region is insulated by insulating the first well region from the semiconductor substrate. A plurality of islands formed between a first insulating film electrically isolated from the semiconductor substrate and adjacent island regions, and arranging the first well regions in the first direction by insulating the adjacent island regions. A second insulating film electrically divided into regions, a first conductor film formed on the second region of the island region, and a second insulating film between the second regions facing each other in the adjacent island region Formed in the formed trench and electrically connected to the first conductor film. A series of gate electrodes formed so as to straddle a plurality of island-shaped regions along the first direction, and a part thereof extends to a part below the gate electrode. In addition, the second conductivity type second well region formed from the upper part of the first region to the upper part of the second region in the island-like region, and a part of the upper surface of the second well region are left under the gate electrode, and a part of the gate region is formed. A first conductivity type source region formed above the second well region and a second portion formed in a region adjacent to the source region and part of the second well region so as to extend under the electrode. A first conductivity type first high concentration region, a drain region of the first conductivity type formed in a part of the island region above the third region and not adjacent to the region under the gate electrode, and a plurality of island shapes A first electrically connected to a plurality of drain regions formed in each region; Configured to have a line, and a plurality of island regions second wiring connected plurality of source regions and a first heavily doped region and electrically formed respectively.

  Insulating first insulation between a part of the semiconductor substrate and the entire side surface and bottom surface of a first well region (also referred to as an element formation region) in which a semiconductor element such as an LDMOS transistor is formed and the semiconductor substrate. By forming the film, the first well region can be isolated from the semiconductor substrate. In this way, by adopting a configuration in which the first well region is electrically separated from the semiconductor substrate, the semiconductor element formed in the first well region is electrically interfered with in the same manner as the semiconductor device manufactured using the SOI substrate. It is possible to obtain a structure that does not need to be considered. Thereby, it is possible to reduce leakage current and electrical interference between semiconductor elements. Further, not only in the upper surface of the first well region, but also in a trench formed between the individual first well regions divided into a plurality of island-like regions, that is, in the second direction (gate length direction) in each island-like region. By forming the gate electrode also on the side surface parallel to the gate electrode, it is possible to drive the side part in addition to the upper part of the island-like region when a predetermined bias voltage is applied to the gate electrode. Become. As a result, the drive region can be enlarged regardless of the chip mounting area, and as a result, the first well region can be reduced and the drive capability can be improved. Furthermore, in the present invention, for example, a bulk substrate or the like can be used as the semiconductor substrate. Therefore, for example, the second direction of each island-shaped region (gate is not limited to the thickness of the silicon thin film in the SOI substrate). It is possible to set the width in the vertical direction (depth direction) of the gate electrode formed on the side surface parallel to the (long direction).

  The semiconductor device according to the present invention includes a first conductivity type including a plurality of island-shaped regions having first to third regions arranged in a first direction and arranged in order in a second direction perpendicular to the first direction. A semiconductor substrate having a first well region is formed on the entire side surface of the first well region, and the side surface of the first well region is electrically isolated from the semiconductor substrate by insulating between the side surface of the first well region and the semiconductor substrate. A first insulating film to be separated and an entire lower surface of the first well region surrounded by the first insulating film, and the lower surface of the first well region is formed by bonding and separating the lower surface of the first well region and the semiconductor substrate. The first well region is formed between the first high-concentration region of the second conductivity type electrically isolated from the semiconductor substrate and the adjacent island-shaped regions, and the adjacent island-shaped regions are insulated from each other in the first direction. Electrically divided into a plurality of arrayed island regions Formed in a trench formed in the second insulating film between the edge film, the first conductor film formed on the second region of the island region, and the second region facing each other in the adjacent island region; A series of gate electrodes formed so as to straddle a plurality of island-shaped regions along the first direction by including the first conductive film and the second conductive film electrically continuous, and a part of the gate electrode A second well region of a second conductivity type formed from the upper portion of the first region to the upper portion of the second region in the island-like region so as to extend to a part under the electrode; and an upper surface of the second well region under the gate electrode. A source region of the first conductivity type formed in the upper part of the second well region and a part of the source region in the upper part of the second well region so that a part extends below the gate electrode while leaving a part. A second high concentration region of the second conductivity type formed in a region adjacent to the third region, and a third region in the island region A first conductivity type drain region formed in a part of the upper portion and not adjacent to the region under the gate electrode and electrically connected to the plurality of drain regions formed in each of the plurality of island-shaped regions The first wiring and a plurality of source regions formed in each of the plurality of island-shaped regions and a second wiring electrically connected to the second high concentration region are configured.

  An insulating first insulating film is formed between a side surface of a first well region (also referred to as an element forming region) in which a semiconductor element such as an LDMOS transistor is formed and a part of the semiconductor substrate. As a result, the side surface of the first well region can be isolated from the semiconductor substrate. In addition, a first high concentration region having a conductivity type (second conductivity type) opposite to the conductivity type of the first well region (first conductivity type) is formed on the entire bottom surface of the first well region. The entire bottom surface can be bonded and separated from the semiconductor substrate. Therefore, according to the present invention, the first well region can be electrically isolated from the semiconductor substrate by the first insulating film and the first high concentration region. In this way, by adopting a configuration in which the first well region is electrically separated from the semiconductor substrate, the semiconductor element formed in the first well region is electrically interfered with in the same manner as the semiconductor device manufactured using the SOI substrate. It is possible to obtain a structure that does not need to be considered. Thereby, it is possible to reduce leakage current and electrical interference between semiconductor elements. Further, not only in the upper surface of the first well region, but also in a trench formed between the individual first well regions divided into a plurality of island-like regions, that is, in the second direction (gate length direction) in each island-like region. By forming the gate electrode also on the side surface parallel to the gate electrode, it is possible to drive the side part in addition to the upper part of the island-like region when a predetermined bias voltage is applied to the gate electrode. Become. As a result, the drive region can be enlarged regardless of the chip mounting area, and as a result, the first well region can be reduced and the drive capability can be improved. Furthermore, in the present invention, for example, a bulk substrate or the like can be used as the semiconductor substrate. Therefore, for example, the second direction of each island-shaped region (gate is not limited to the thickness of the silicon thin film in the SOI substrate). It is possible to set the width in the vertical direction (depth direction) of the gate electrode formed on the side surface parallel to the (long direction).

  A semiconductor device according to the present invention includes a semiconductor substrate having a first conductivity type element formation region including a first region and a plurality of second regions protruding in a comb shape from the first region as viewed from above. An insulating film formed on the entire side surface of the element forming region, and electrically insulating the side surface of the element forming region from the semiconductor substrate by insulating between the side surface of the element forming region and the semiconductor substrate; and an element surrounded by the insulating film A drain region of a second conductivity type formed on the entire lower surface of the formation region and electrically separating the lower surface of the element formation region from the semiconductor substrate by bonding and separating the lower surface of the element formation region and the semiconductor substrate; A series of two regions are formed on a part of the first region, on the second region, between adjacent second regions, and at the tip so as to wrap from the three sides and the upper surface that are not continuous with the first region. Gate electrode and the upper portion of the first region A source region of the second conductivity type formed from the upper portion to the upper portion of the second region, and a region adjacent to the source region in the upper portion of the first region, the first conductivity type high region formed in a region other than under the gate electrode It has a concentration region and a first conductivity type well region formed between a source region and a drain region in the element formation region.

  By forming an insulating insulating film between the side surface of the element formation region which is a partial region of the semiconductor substrate and the semiconductor substrate, the side surface of the element formation region can be insulated and separated from the semiconductor substrate. Further, by forming a drain region having the conductivity type of the element formation region (conductivity type opposite to the first conductivity type (second conductivity type) of the element formation region on the entire bottom surface of the element formation region, the entire bottom surface of the element formation region is bonded from the semiconductor substrate. Therefore, according to the present invention, the element formation region can be electrically isolated from the semiconductor substrate by the insulating film and the drain region, and thus the element formation region can be electrically isolated from the semiconductor substrate. With the separated structure, the semiconductor element formed in the element formation region can be made into a structure that does not need to consider electrical interference, as in the semiconductor device manufactured using the SOI substrate. It is possible to reduce leakage current, electrical interference between semiconductor elements, etc. In addition to not only the upper surface of the comb-shaped protruding portion in this element formation region. When a predetermined bias voltage is applied to the gate electrode by forming the gate electrode between the portions protruding in a comb shape and also in the trench formed earlier, that is, the side surface of the portion protruding in a comb shape. In addition to the upper portion of the element formation region, the side portion can be driven, so that the drive region can be enlarged regardless of the chip mounting area. In the present invention, for example, a bulk substrate can be used as the semiconductor substrate, and therefore, the thickness is limited to, for example, the thickness of the silicon thin film on the SOI substrate. The width in the vertical direction (depth direction) of the gate electrode formed on the side surface parallel to the gate length direction of the element formation region can be set without any change. A semiconductor in which a channel is formed in a vertical direction because an impurity buried layer for electrically isolating the lower surface of the element formation region from the semiconductor substrate is used as a drain region and a source region is formed above the element formation region. An apparatus can be realized.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the step of preparing a semiconductor substrate including a first well region of a first conductivity type, the step of forming a first trench on the entire side surface of the first well region, Forming a second trench that divides the well region into a plurality of island-shaped regions having first to third regions arranged in a first direction and sequentially arranged in a second direction perpendicular to the first direction; By thermally oxidizing the bottoms of the first and second trenches, a first insulating film that insulates between the entire lower surface of each of the plurality of island-shaped regions and the semiconductor substrate is formed on the entire lower surface of each of the plurality of island-shaped regions. A step of filling the first trench with the second insulating film and filling the second trench with the third insulating film; and a third trench in the third insulating film located between the opposing second regions in the adjacent island regions Forming multiple islands Forming a series of first gate electrodes across a plurality of island-shaped regions along the first direction by forming a series of conductor films on the second region and in the third trench in the region; A step of forming a second well region extending from an upper portion of the first region to a portion under the first gate electrode by injecting and diffusing impurities of a second conductivity type from the upper surface of the first region in the region; By implanting and diffusing impurities of the first conductivity type from the upper surface of the first region in the shaped region, a part of the upper surface of the second well region under the first gate electrode remains, and a part thereof extends to the lower portion of the first gate electrode. A step of forming an extended source region in the upper portion of the second well region, and an impurity of the first conductivity type are implanted and diffused from the upper surface of the third region in the island-shaped region, so that the upper portion of the third region in the island-shaped region is Partial and adjacent to the region under the first gate electrode A region adjacent to the source region in the upper portion of the second well region by forming a drain region in a non-existing region and injecting and diffusing impurities of the second conductivity type from the upper surface of the first region in the island-like region; Forming a first high concentration region in a region other than under the first gate electrode, forming a first wiring electrically connected to a plurality of drain regions formed in each of the plurality of island regions, Forming a plurality of source regions formed in each of the island-like regions and a second wiring electrically connected to the first high-concentration region.

  An insulating first insulating film is formed between the entire bottom surface of a first well region (also referred to as an element forming region) in which a semiconductor element such as an LDMOS transistor is formed and a part of the semiconductor substrate. By forming, the entire bottom surface of the first well region can be isolated from the semiconductor substrate. Further, by forming the second insulating film in the first trench surrounding the entire side surface of the first well region, the entire side surface of the first well region can be insulated and separated from the semiconductor substrate. Therefore, according to the present invention, the first well region can be electrically isolated from the semiconductor substrate by the first and second insulating films. In this way, by electrically separating the first well region from the semiconductor substrate, the semiconductor element formed in the first well region is considered for electrical interference as in the case of the semiconductor device manufactured using the SOI substrate. The structure can be made unnecessary. Thereby, it is possible to reduce leakage current and electrical interference between semiconductor elements. In the present invention, not only the upper surface of the first well region but also the third direction formed in the third trench formed between the first well regions divided into a plurality of island-like regions, that is, the first direction (gates) in the individual island-like regions. In order to form the first gate electrode also on the side surface perpendicular to the width direction), that is, the side surface parallel to the second direction (gate length direction), when a predetermined bias voltage is applied to the gate electrode, In addition to the upper part, the side part can be driven. As a result, it becomes possible to manufacture a semiconductor device in which the drive region is enlarged regardless of the chip mounting area, and as a result, it is possible to reduce the first well region and improve the drive capability. In the present invention, since a bulk substrate or the like can be used as the semiconductor substrate, for example, the second direction of each island-like region (gate is not limited to the thickness of the silicon thin film in the SOI substrate). It is possible to set the width in the vertical direction (depth direction) of the first gate electrode formed on the side surface parallel to the long direction.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the step of preparing a semiconductor substrate having a first well type first well region, the step of forming a first trench on the entire side surface of the first well region, Forming a second trench that divides one well region into a plurality of island-like regions having first to third regions arranged in a first direction and sequentially arranged in a second direction perpendicular to the first direction; Etching the lower portion of the first and second trenches to widen the lower portion of the first and second trenches, and thermally oxidizing the lower portion of the first and second trenches that have been widened, Forming a first insulating film that insulates between the entire lower surface and the semiconductor substrate on the entire lower surface of each of the plurality of island-like regions, filling the first trench with the second insulating film, and forming the second trench with the third insulating film; Next to the process of filling with Forming a third trench in a third insulating film located between the second regions facing each other in the island-like region, and forming a series of conductor films on the second region and in the third trench in the plurality of island-like regions. By forming, a step of forming a series of first gate electrodes straddling a plurality of island regions along the first direction, and injecting and diffusing impurities of the second conductivity type from the upper surface of the first region in the island regions As a result, a step of forming a second well region extending from the upper portion of the first region to a portion under the first gate electrode, and an impurity of the first conductivity type are implanted from the upper surface of the first region in the island region. Forming a source region in the upper part of the second well region by diffusing, leaving a part of the upper surface of the second well region below the first gate electrode while partially extending to the lower part of the first gate electrode; Of the first conductivity type from the upper surface of the third region in the region Forming a drain region in a region that is a part of the upper portion of the third region in the island region and not adjacent to the region under the first gate electrode, and the first region in the island region A step of forming a first high-concentration region in a region adjacent to the source region above the second well region and other than under the first gate electrode by injecting and diffusing impurities of the second conductivity type from the upper surface Forming a first wiring electrically connected to the plurality of drain regions formed in each of the plurality of island-shaped regions, and a plurality of source regions and first high-concentration regions formed in each of the plurality of island-shaped regions And a step of forming a second wiring electrically connected.

  An insulating first insulating film is formed between the entire bottom surface of a first well region (also referred to as an element forming region) in which a semiconductor element such as an LDMOS transistor is formed and a part of the semiconductor substrate. By forming, the entire bottom surface of the first well region can be isolated from the semiconductor substrate. Further, by forming the second insulating film in the first trench surrounding the entire side surface of the first well region, the entire side surface of the first well region can be insulated and separated from the semiconductor substrate. Therefore, according to the present invention, the first well region can be electrically isolated from the semiconductor substrate by the first and second insulating films. In this way, by electrically separating the first well region from the semiconductor substrate, the semiconductor element formed in the first well region is considered for electrical interference as in the case of the semiconductor device manufactured using the SOI substrate. The structure can be made unnecessary. Thereby, it is possible to reduce leakage current and electrical interference between semiconductor elements. In the present invention, not only the upper surface of the first well region but also the third direction formed in the third trench formed between the first well regions divided into a plurality of island-like regions, that is, the first direction (gates) in the individual island-like regions. In order to form the first gate electrode also on the side surface perpendicular to the width direction), that is, the side surface parallel to the second direction (gate length direction), when a predetermined bias voltage is applied to the gate electrode, In addition to the upper part, the side part can be driven. As a result, it becomes possible to manufacture a semiconductor device in which the drive region is enlarged regardless of the chip mounting area, and as a result, it is possible to reduce the first well region and improve the drive capability. In the present invention, since a bulk substrate or the like can be used as the semiconductor substrate, for example, the second direction of each island-like region (gate is not limited to the thickness of the silicon thin film in the SOI substrate). It is possible to set the width in the vertical direction (depth direction) of the first gate electrode formed on the side surface parallel to the long direction.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: preparing a semiconductor substrate having a first well region of a first conductivity type; and forming a first trench in a side surface perpendicular to the first direction in the first well region. And a second trench that divides the first well region into a plurality of island regions having first to third regions arranged in a first direction and arranged in order in a second direction perpendicular to the first direction. Forming a gap under each of the plurality of island-like regions by etching the lower portions of the first and second trenches, filling at least part of the gap with the first insulating film, and Filling the trench with the second insulating film and filling the second trench with the third insulating film; forming the third trench on a side surface parallel to the first direction in the first well region; and A process of filling with an insulating film; Forming a fourth trench in a third insulating film positioned between opposing second regions in adjacent island regions, and a series of conductor films on the second region and in the fourth trench in the plurality of island regions Forming a series of first gate electrodes across the plurality of island regions along the first direction, and implanting a second conductivity type impurity from the upper surface of the first region in the island regions. By diffusing, a step of forming a second well region extending from the upper portion of the first region to a portion under the first gate electrode, and an impurity of the first conductivity type are implanted from the upper surface of the first region in the island region. Forming a source region in the upper part of the second well region, while leaving a part of the upper surface of the second well region under the first gate electrode, while partly extending under the first gate electrode; First conductivity type from the upper surface of the third region in the island region A step of forming a drain region in a region which is a part of the upper portion of the third region in the island region and not adjacent to the region under the first gate electrode by injecting and diffusing the impurity; By implanting and diffusing impurities of the second conductivity type from the upper surface of the region, a first high concentration region is formed in a region adjacent to the source region above the second well region and other than under the first gate electrode. Forming a first wiring electrically connected to a plurality of drain regions formed in each of the plurality of island regions, a plurality of source regions and a first high concentration formed in each of the plurality of island regions And a step of forming a second wiring electrically connected to the region.

  An insulating first insulating film (a part of the semiconductor substrate) between the entire bottom surface of a first well region (also referred to as an element formation region) where a semiconductor element such as an LDMOS transistor is formed and the semiconductor substrate. The whole bottom surface of the first well region can be insulated and separated from the semiconductor substrate. In addition, by forming the second and fourth insulating films in the first and fourth trenches that surround the entire side surface of the first well region, respectively, the entire side surface of the first well region can be isolated from the semiconductor substrate. Therefore, according to the present invention, the first well region can be electrically separated from the semiconductor substrate by the first, second and fourth insulating films. In this way, by electrically separating the first well region from the semiconductor substrate, the semiconductor element formed in the first well region is considered for electrical interference as in the case of the semiconductor device manufactured using the SOI substrate. The structure can be made unnecessary. Thereby, it is possible to reduce leakage current and electrical interference between semiconductor elements. In the present invention, not only the upper surface of the first well region but also the third direction formed in the third trench formed between the first well regions divided into a plurality of island-like regions, that is, the first direction (gates) in the individual island-like regions. In order to form the first gate electrode also on the side surface perpendicular to the width direction), that is, the side surface parallel to the second direction (gate length direction), when a predetermined bias voltage is applied to the gate electrode, In addition to the upper part, the side part can be driven. As a result, it becomes possible to manufacture a semiconductor device in which the drive region is enlarged regardless of the chip mounting area, and as a result, it is possible to reduce the first well region and improve the drive capability. In the present invention, since a bulk substrate or the like can be used as the semiconductor substrate, for example, the second direction of each island-like region (gate is not limited to the thickness of the silicon thin film in the SOI substrate). It is possible to set the width in the vertical direction (depth direction) of the first gate electrode formed on the side surface parallel to the long direction.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: preparing a semiconductor substrate having a first well region of a first conductivity type; forming a first trench on the entire side surface of the first well region; Forming a second trench that divides one well region into a plurality of island regions having first to third regions arranged in the first direction and arranged in order in the second direction; By implanting and diffusing impurities of the second conductivity type into the bottom surfaces of the first and second trenches so that the impurity concentration becomes higher, the entire bottom surface of each of the plurality of island-like regions and the semiconductor substrate are separated from each other. A step of forming the first high-concentration region on the entire lower surface of each of the plurality of island-like regions, a step of filling the first trench with the first insulating film and the second trench with the second insulating film, and an adjacent island-like region 2nd territory opposite in Forming a third trench in the second insulating film positioned therebetween, and forming a series of conductor films on the second region and in the third trench in the plurality of island-shaped regions; Forming a series of first gate electrodes extending along the first direction and injecting and diffusing impurities of the second conductivity type from the upper surface of the first region in the island region, Forming a second well region extending to a part under one gate electrode, and implanting and diffusing impurities of the first conductivity type from the upper surface of the first region in the island-like region; Forming a source region over the second well region while leaving a part of the upper surface of the second well region, and extending from the upper surface of the third region in the island region to the first By injecting and diffusing conductivity type impurities, Forming a drain region in a part of the upper part of the third region in the region not adjacent to the region under the first gate electrode, and implanting a second conductivity type impurity from the upper surface of the first region in the island-like region. By diffusing, a step of forming a second high concentration region in a region adjacent to the source region above the second well region and other than under the first gate electrode, and a plurality of regions formed in each of the plurality of island regions Forming a first wiring electrically connected to the drain region, and forming a second wiring electrically connected to the plurality of source regions and the second high concentration region formed in each of the plurality of island-shaped regions And a step of performing.

  An insulating first insulating film is formed in a first trench that surrounds the entire side surface of a first well region (also referred to as an element forming region) in which a semiconductor element such as an LDMOS transistor is formed, which is a partial region of the semiconductor substrate. As a result, the entire side surface of the first well region can be insulated and separated from the semiconductor substrate. In addition, a first high concentration region having a conductivity type (second conductivity type) opposite to the conductivity type of the first well region (first conductivity type) is formed on the entire bottom surface of the first well region. The entire bottom surface can be bonded and separated from the semiconductor substrate. Therefore, according to the present invention, the first well region can be electrically isolated from the semiconductor substrate by the first insulating film and the first high concentration region. In this way, by electrically separating the first well region from the semiconductor substrate, the semiconductor element formed in the first well region is considered for electrical interference as in the case of the semiconductor device manufactured using the SOI substrate. The structure can be made unnecessary. Thereby, it is possible to reduce leakage current and electrical interference between semiconductor elements. In the present invention, not only the upper surface of the first well region but also the third direction formed in the third trench formed between the first well regions divided into a plurality of island-like regions, that is, the first direction (gates) in the individual island-like regions. In order to form the first gate electrode also on the side surface perpendicular to the width direction), that is, the side surface parallel to the second direction (gate length direction), when a predetermined bias voltage is applied to the gate electrode, In addition to the upper part, the side part can be driven. As a result, it becomes possible to manufacture a semiconductor device in which the drive region is enlarged regardless of the chip mounting area, and as a result, it is possible to reduce the first well region and improve the drive capability. In the present invention, since a bulk substrate or the like can be used as the semiconductor substrate, for example, the second direction of each island-like region (gate is not limited to the thickness of the silicon thin film in the SOI substrate). It is possible to set the width in the vertical direction (depth direction) of the first gate electrode formed on the side surface parallel to the long direction.

  In addition, a method of manufacturing a semiconductor device according to the present invention includes a first conductivity type element formation region including a first region and a plurality of second regions protruding in a comb shape from the first region when viewed from above. A step of preparing a semiconductor substrate, a step of forming a first trench on the entire side surface of the element formation region, and an impurity of a second conductivity type are implanted into the bottom surface of the first trench so as to have an impurity concentration higher than that of the element formation region. And forming a drain region for bonding and separating the lower surface of the element formation region and the semiconductor substrate under the element formation region, a step of filling the first trench with an insulating film, and an upper portion of the first region A step of forming a source region by injecting and diffusing a first conductivity type impurity into a part of the first region and an upper portion of the second region, and a second conductivity type in a region above the one region and adjacent to the source region By injecting and diffusing impurities A step of forming a concentration region, a step of forming a series of second trenches between adjacent second regions and at the tip thereof, and a plurality of second regions respectively from three side surfaces and an upper surface that are not continuous with the first region. And a step of forming a series of gate electrodes on a part of the first region, on the second region, and in the second trench.

  By forming an insulating insulating film in the first trench formed on the entire side surface of the element formation region, which is a partial region in the semiconductor substrate, the entire side surface of the element formation region can be isolated from the semiconductor substrate. Further, a drain region having a conductivity type (second conductivity type) opposite to the conductivity type of the element formation region (first conductivity type) is formed on the entire element formation region bottom surface, so that the entire element formation region bottom surface is removed from the semiconductor substrate. Can be separated. Therefore, according to the present invention, the element formation region can be electrically separated from the semiconductor substrate by the insulating film and the drain region. As described above, by electrically separating the element formation region from the semiconductor substrate, it is necessary to consider the electrical interference in the semiconductor element formed in the element formation region in the same manner as the semiconductor device formed using the SOI substrate. It can be set as a structure without. Thereby, it is possible to reduce leakage current and electrical interference between semiconductor elements. Further, in the present invention, not only the upper surface of the portion protruding in a comb-teeth shape in the element forming region, but also between the portions protruding in a comb-teeth shape and in the second trench formed earlier, that is, the portion protruding in a comb-teeth shape Since the gate electrode is also formed on the side surface of the element, it is possible to drive the side part in addition to the upper part of the element formation region when a predetermined bias voltage is applied to the gate electrode. As a result, it becomes possible to manufacture a semiconductor device in which the drive region is enlarged regardless of the chip mounting area, and as a result, it is possible to reduce the element formation region and improve the drive capability. Further, in the present invention, for example, a bulk substrate can be used as the semiconductor substrate. Therefore, for example, the side surface parallel to the gate length direction of the element formation region is not limited by the thickness of the silicon thin film in the SOI substrate. It is possible to set the width of the gate electrode formed in the vertical direction (depth direction). Furthermore, in the present invention, the impurity buried layer for electrically isolating the lower surface of the element formation region from the semiconductor substrate is used as the drain region, and the source region is formed above the element formation region. A semiconductor device formed in the direction can be realized.

  According to the present invention, it is possible to realize a semiconductor device and a manufacturing method thereof that can reduce the element formation region and improve the driving capability while improving the electrical isolation between the semiconductor elements.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. In the following description, each drawing only schematically shows the shape, size, and positional relationship to the extent that the contents of the present invention can be understood. Therefore, the present invention is illustrated in each drawing. It is not limited to only the shape, size, and positional relationship. Moreover, in each figure, a part of hatching in a cross section is abbreviate | omitted for clarity of a structure. Furthermore, the numerical values exemplified below are merely preferred examples of the present invention, and therefore the present invention is not limited to the illustrated numerical values.

  First, Embodiment 1 according to the present invention will be described in detail with reference to the drawings. In this embodiment, as an example of the semiconductor device 100 according to the present invention, an LDMOS field effect transistor (FET) that forms an n-type channel is manufactured.

Overall Configuration FIG. 1 is a top view showing the configuration of the semiconductor device 100 according to this embodiment. 2 is a cross-sectional view along AA ′ in FIG. 1, FIG. 3 is a cross-sectional view along BB ′ in FIG. 1, and FIG. 4 is a cross-sectional view along CC ′ in FIG.

  First, the schematic configuration of the semiconductor device 100 according to the present embodiment will be described with reference to FIGS. As shown in FIG. 1, the semiconductor device 100 has a configuration in which an element isolation insulating film 12a is formed on a side surface of an element formation region (also referred to as an active region) 10A in which a semiconductor element such as a transistor is formed. With this configuration, in this embodiment, the side surface of the element formation region 10 </ b> A is electrically separated from the semiconductor substrate 11. 2 to 4, the semiconductor device 100 has a configuration in which an insulating film (hereinafter referred to as a buried insulating film 12c) is formed under the element formation region 10A. With this configuration, in this embodiment, the lower surface of the element formation region 10 </ b> A is electrically separated from the semiconductor substrate 11.

  As described above, in this embodiment, the element formation region 10A is electrically completely separated from the semiconductor substrate 11 by the element isolation insulating film 12a and the buried insulating film 12c. In other words, the semiconductor substrate 11 according to the present example has a configuration partially similar to that of the SOI substrate. As a result, the semiconductor device 100 according to the present embodiment has a structure in which the semiconductor element formed in the element formation region 10A does not need to consider electrical interference, similar to the semiconductor device manufactured using, for example, an SOI substrate. . Hereinafter, a structure in which the element formation region 10A is surrounded by the element isolation insulating film 12a and the buried insulating film 12c is referred to as a partial SOI structure 10B.

  Further, in this embodiment, the element formation region 10A includes a plurality of regions (hereinafter referred to as island-shaped regions) by an insulating film (hereinafter referred to as an isolation insulating film 12b) formed so as to hang over the element isolation insulating film 12a. 10a) is electrically separated. In other words, in this embodiment, the element formation region 10A for forming one LDMOS is electrically divided into a plurality of island regions 10a arranged in the gate width direction (first direction) by the isolation insulating film 12b. Have a configuration.

  Each island-like region 10a has a shape protruding in a strip shape elongated in the gate length direction (second direction). Therefore, the shape obtained by combining the element isolation insulating film 12a and the isolation insulating film 12b according to this embodiment has a shape in which strip-shaped insulating films are combined in a lattice shape (in this example, a “mesh” shape). The components of the semiconductor device 100 according to the present embodiment are respectively formed in the plurality of island-like regions 10a that are electrically divided so as to be arranged along the gate width direction as described above. In other words, the semiconductor device 100 according to the present embodiment is formed in the element formation region 10A divided into a plurality of island regions 10a so as to be arranged along the gate width direction.

  Next, the configuration of the semiconductor device 100 according to the present embodiment will be described in detail with reference to FIGS. As shown in FIGS. 1 to 4, the semiconductor device 100 includes an element formation region 10A having a plurality of island regions 10a electrically isolated from the semiconductor substrate 11, and individual island regions 10a in the element formation region 10A. The n-well region 17w, the p-type body region 17, the drain region 18d, the source region 18s, and the body pulling region 19 formed on the gate insulating film 14a and a plurality of gate insulating films 14a formed on a part of each island-shaped region 10a. It has a gate electrode 15a formed over the island-shaped region 10a, and a gate insulating film 14b and a gate electrode 15b formed in part between the adjacent island-shaped regions 10a. Here, for convenience of explanation, as shown in FIG. 2, each island-like region 10a is divided into first to third regions 10-1, 10-2 and 10-3 which are arranged in order in the gate length direction. According to this, the gate insulating film 14a is formed on the second region 10-2 in each island-like region 10a, and the gate insulating film 14b is formed on the side surface of the second region 10-2 in each island-like region 10a. Is done. The gate electrode 15b is formed in a region between the second regions 10-2 in the adjacent island regions 10a and sandwiched between the respective gate insulating films 14b, and the gate electrode 15a is formed in each of the island regions 10a. It is formed so as to connect the gate insulating film 14a on the second region 10-2 and the gate electrode 15b.

  In the above configuration, the semiconductor substrate 11 is, for example, a silicon bulk substrate having n-type conductivity. Hereinafter, this is referred to as an n-type silicon substrate. The substrate resistance can be about 8 to 22 Ω (ohms), for example. Therefore, the element formation region 10A (island region 10a) has n-type conductivity. The n-well region 17w that uses a part of the element formation region 10A also has n-type conductivity.

  The element isolation insulating film 12a formed so as to electrically isolate the side surface of the element formation region 10A from the semiconductor substrate 11 can be, for example, a silicon oxide film. The isolation insulating film 12b that divides the element formation region 10A into a plurality of island-like regions 10a arranged in the gate width direction can be formed of, for example, a silicon oxide film. The element isolation insulating film 12a and the isolation insulating film 12b can be formed using, for example, an STI (Shallow Trench Isolation) method. That is, an enclosing trench formed by combining strip-like trenches in a lattice pattern so as to surround the element forming region 10A and to divide the element forming region 10A into a plurality of island regions 10a (trenches 102a and 102b described later). Can be formed by embedding a silicon oxide film or the like in the semiconductor substrate 11. In addition, the dimension of the trench formed by combining strip-shaped trenches in a lattice shape is, for example, the length of the short side (hereinafter referred to as the width) on the upper surface, for example, 1 μm when combined in a “mesh” shape as in this embodiment. The length of the long side on the upper surface (hereinafter referred to as length) is, for example, about 9 to 11 μm, and the length from the upper surface to the bottom surface (hereinafter referred to as thickness) is, for example, about 4 to 6 μm. can do.

  The buried insulating film 12c formed so as to electrically isolate the bottom surface of the element formation region 10A, specifically, the bottom surface of each island-shaped region 10a from the semiconductor substrate 11 is, for example, a silicon oxide film. it can. The buried insulating film 12c is divided into, for example, a trench (corresponding to a trench 102a described later) formed so as to surround the side surface of the element formation region 10A and a plurality of island regions 10a arranged in the gate width direction. The lower part of each of the trenches (corresponding to a trench 102b to be described later) formed so as to be formed can be formed, for example, by thermally oxidizing and expanding the bottom. At this time, the lower portions of the trenches 102a and 102b are widened from these side surfaces by at least 0.5 μm or more in the horizontal direction when, for example, the dimension in the gate width direction of the island region 10a is about 1 μm as described above. For example, in this embodiment, the buried insulating film 12c is formed over the entire element formation region 10A by extending the lower part of the trenches 102a and 102b (corresponding to a cavity 105 described later) by about 1 μm in the horizontal direction by thermal oxidation. . Thus, the trenches located in parallel, that is, the bottom of the island-like region 10a can be closed by the silicon oxide film (embedded insulating film 12c) formed by thermal oxidation. Note that the structure formed thereby is the partial SOI structure 10B described above.

  By forming the element isolation insulating film 12a, the isolation insulating film 12b, and the buried insulating film 12c as described above, the element formation region 10A has a width of, for example, about 1 μm, a length of, for example, about 7 μm, and a thickness. Is electrically divided into a plurality of island-like regions 10a having a length of, for example, about 2 to 3 μm.

  A gate insulating film 14a is formed on the second region 10-2 in each island-like region 10a. Similarly, a gate insulating film 14b is formed on the side surface of the second region 10-2 in each island-like region 10a. In other words, the isolation insulating film 12b gate insulating film 14a located between the second regions 10-2 in the adjacent island regions 10a thermally oxidizes the upper surface of the second region 10-2 in each island region 10a, for example. This is a silicon oxide film formed in (1). The film thickness can be, for example, about 20 nm (nanometers). Further, the gate insulating film 14b is formed by removing the isolation insulating film 12b positioned between the second regions 10-2 in the adjacent island regions 10a, for example, and then exposing the island regions 10a (second regions 10-2). It is a silicon oxide film formed by thermally oxidizing the side surface. The film thickness (however, the thickness in the gate length direction) can be about 20 nm, for example.

  As described above, the gate electrode 15b is formed in a trench formed in the isolation insulating film 12b located between the second regions 10-2 in the adjacent island regions 10a. The gate electrode 15b is also formed in a trench formed in the element isolation insulating film 12a located on the side surface of the second region 10-2 of the two island-like regions 10a located on the outermost side in the gate width direction. On the other hand, the gate electrode 15a is formed in a series from the gate insulating film 14a on the second region 10-2 to the gate electrode 15b in each island-like region 10a. In other words, the gate electrode 15a is formed so as to straddle the plurality of island regions 10a. However, the gate electrode 15a and the gate electrode 15b are continuous conductor films. Therefore, in this embodiment, a series of gate electrodes 15a and 15b are formed so as to straddle the plurality of island-like regions 10a. The gate electrodes 15a and 15b are polysilicon films having conductivity by containing an n-type impurity such as phosphorus. The film thickness of the gate electrode 15a can be set to about 3 μm, for example. Further, the width of the gate electrode 15b in the gate width direction is a value obtained by subtracting the thickness of the two gate insulating films 14b from the adjacent interval between the island regions 10a. Therefore, in this example, it can be set to about 0.96 μm (about 1 μm).

  As described above, in this embodiment, the gate electrode is formed on the upper surface and the side surface of each island-like region 10a. Therefore, in addition to the upper surface of the island-shaped region 10a, a driving region during operation is also formed on this side surface. In other words, the drive region is formed in the vertical direction (perpendicular to the substrate) in the semiconductor substrate 11. For this reason, it becomes possible to improve the drive capability per unit area in the semiconductor chip in which the semiconductor device 100 is formed. Note that the driving surface in this description refers to a region where a channel for flowing current during operation is formed. The driving capability refers to the capability of the semiconductor element determined based on the current flowing with respect to the applied bias voltage.

  For example, as shown in FIG. 3, a silicide film 15c is formed on a portion of the gate electrode 15a that is electrically connected to the in-contact wiring 22 formed on the interlayer insulating film 21 described later. The resistance may be reduced.

Further, as shown in FIG. 2, an impurity having p-type conductivity is implanted into the upper portion of each island-like region 10a and diffused in a direction parallel to the surface of the semiconductor substrate 11, that is, in a lateral direction. , P-type body region 17 is formed. The p-type body region 17 is formed from the first region 10-1 to a part of the second region 10-2 in the island-shaped region 10a. At this time, the upper surface of the p-type body region 17 is located at a part of the upper surface of the second region 10-2 below the gate electrode 15a. Further, for example, arsenic ions or boron ions can be applied to the p-type conductivity impurity used when forming the p-type body region 17. Further, the dose amount and the acceleration energy when forming the p-type body region 17 can be set to, for example, about 1 × 10 ¹⁴ / cm ^{2 and} about 10 KeV (kiloelectron volts), respectively. The p-type body region 17 is a region where a channel is formed by applying a predetermined bias voltage to the gate electrode 15a.

As shown in FIG. 2, an impurity having n-type conductivity is implanted into a part of the upper part of the p-type body region 17, and the source region 18s is formed by diffusing the impurity in the lateral direction. The source region 18s is formed from the first region 10-1 to a part of the second region 10-2 in the island region 10a. At this time, the upper surface of the source region 18s is located on a part of the upper surface of the second region 10-2 below the gate electrode 15a. However, the upper surface of the p-type body region 17 remains under the gate electrode 15a. Further, for example, phosphorus ions can be applied to the n-type conductivity impurity used when forming the source region 18s. Further, the dose amount and the acceleration energy at the time of forming the source region 18s can be set to, for example, about 1 × 10 ¹⁷ / cm ^{2 and} about 10 KeV, respectively.

  Further, as shown in FIG. 2, a predetermined region of the p-type body region 17 is implanted with a predetermined impurity to form a body pulling region 19. The body pulling region 19 is a diffusion region for controlling the potential of the p-type body region 17. Therefore, an impurity having the same conductivity type (p-type) as that of the p-type body region 17 is used as an impurity used when forming the body pulling region 19. The dose amount and acceleration energy when forming the body pulling region 19 can be set to about 1 × 10 17 / cm 2 and about 10 KeV, respectively.

Further, an impurity having n-type conductivity is implanted into the upper part of each island-like region 10a and diffused in the lateral direction, thereby forming a drain region 18d. The drain region 18d is formed in the third region 10-3 in the island-like region 10a and not in contact with the second region 10-2. In other words, the drain region 18d is formed in a region other than the p-type body region 17 and not adjacent to the region under the gate electrode 15a. Further, for example, phosphorus ions can be applied to the n-type conductivity impurity used when forming the drain region 18d, as in the source region 18s. Further, the dose amount and acceleration energy when forming the drain region can be set to, for example, about 1 × 10 ¹⁷ / cm ^{3 and} about 10 KeV, respectively.

  A silicide film 18a is formed on the source region 18s and the drain region 18d, respectively, on the portions electrically connected to the contact wirings 22 formed in the interlayer insulating film 21 described later. Low resistance.

  The element formation region 10A other than the region where the p-type body region 17, the drain region 18d, the source region 18s, and the body pulling region 19 are formed becomes an n-well region 17w.

  As shown in FIGS. 1 to 4, the semiconductor element having the above configuration is electrically isolated from other layers by being covered with an interlayer insulating film 21 deposited on the entire upper surface of the semiconductor substrate 11. . The interlayer insulating film 21 is, for example, a silicon oxide film. The film thickness can be about 1 μm, for example.

  In-contact wirings 22 are respectively formed on the interlayer insulating film 21 on the drain region 18d and on the source region 18s and the body pulling region 19 in the semiconductor element. The in-contact wiring 22 is formed by filling a contact hole opened in the interlayer insulating film 21 so as to expose the upper surface of the drain region 18d and the upper surface of the source region 18s and the body pulling region 19 with a conductor such as titanium. can do. At this time, as described above, the silicide film 18a made of titanium silicide is formed on the surface of the drain region 18d, the source region 18s, and the body pulling region 19 exposed by the contact holes, respectively. Ohmic contacts with the source region 18s, the drain region 18d, and the body pulling region 19 can be formed.

  Similarly, in-contact wiring 22 is formed in the interlayer insulating film 21 on the gate electrode 15a in the semiconductor element. The in-contact wiring 22 can be formed by filling a contact hole formed in the interlayer insulating film 21 so as to expose a part of the upper surface of the gate electrode 15a with a conductor such as titanium. At this time, as described above, the silicide film 15c made of titanium silicide is formed on the surface of the gate electrode 15a exposed by the contact hole, thereby forming an ohmic contact between the contact wiring 22 and the gate electrode 15a. it can.

  On the interlayer insulating film 21, metal wirings 23 and 24 electrically connected to the respective contact wirings 22 formed as described above are formed. As a result, the gate electrodes 15 a and 15 b, the drain region 18 d, the source region 18 s and the p-type body region 17 in the semiconductor element are electrically drawn up to the interlayer insulating film 21.

  In addition, the semiconductor device 100 having the above configuration can be switched in the same manner as a normal n-type MOSFET. Specifically, by applying a positive potential or a ground potential to the gate electrode while applying a positive potential to the drain region 18d while grounding the source region 18s, the p-type bodies below the gate electrodes 15a and 15b are applied. The region 17 is inverted, depleted or accumulated. Thereby, the amount of current flowing from the drain region 18d to the source region 18s can be controlled.

Manufacturing Method Next, a manufacturing method of the semiconductor device 100 according to the present embodiment will be described in detail with reference to the drawings. 5 to 13 are process diagrams showing a method for manufacturing the semiconductor device 100. FIG. In addition, below, each process is demonstrated suitably based on the AA 'cross section in FIG. 1, a BB' cross section, and CC 'cross section.

In this manufacturing method, first, a bulk n-type silicon substrate is prepared as the semiconductor substrate 11. Next, the surface of the semiconductor substrate 11 is thermally oxidized to form a silicon oxide film 101a having a thickness of about 20 nm, for example. Subsequently, a silicon nitride film 101b having a film thickness of, for example, about 500 nm is formed on the silicon oxide film 101a by, for example, a CVD (Chemical Vapor Deposition) method. Thereby, as shown in FIG. 5A, a laminated film of the silicon oxide film 101a and the silicon nitride film 101b is formed on the semiconductor substrate 11. The silicon nitride film 101b functions as a protective film for protecting the surface of the semiconductor substrate 11 from thermal oxidation (see FIG. 7B) in a later process. The silicon oxide film 101 a is a pad oxide film for bringing the silicon nitride film 101 b into close contact with the semiconductor substrate 11. In the thermal oxidation when forming the silicon oxide film 101a, the heating temperature is set to 500 ° C., for example, and the heating time is set to 2 hours, for example. For example, a mixed gas of NH ₃ and SiH ₂ Cl ₂ is used for forming the silicon nitride film 101b. The gas flow ratio at this time can be NH ₃ : SiH ₂ Cl ₂ = 10: 1. The film forming conditions can be set such that the pressure in the chamber is 0.2 Torr and the stage temperature is 780 ° C.

  Next, a predetermined resist solution is spin-coated on the silicon nitride film 101b, and this is subjected to existing exposure processing and development processing, thereby forming a resist pattern R1 having a grid-like opening shape. In this example, the opening shape of the resist pattern R1 has a “eye” shape (“day” shape in Example 2 described later). In this shape, four rectangles (three in Example 2) arranged in parallel in the drawing have a width of, for example, about 1 μm and a length of, for example, about 7 μm. The adjacent interval is, for example, about 1 μm. In addition, two rectangles arranged in parallel in the horizontal direction in the drawing have a width of, for example, about 1 μm and a length of, for example, about 7 μm. According to this dimension, in the drawing, the vertical length of the outer periphery is about 7 μm, and the horizontal length is about 9 μm.

Next, using the resist pattern R1 as a mask, the silicon nitride film 101b, the silicon oxide film 101a, and the semiconductor substrate 11 are sequentially etched using, for example, an existing etching technique, as shown in FIG. Trenches 102 a and 102 b having the same opening shape as that of the resist pattern R 1 described above are formed in the semiconductor substrate 11. The trench 102a is a groove in which an element isolation insulating film 12a for electrically isolating the side surface of the element formation region 10A from the semiconductor substrate 11 is formed, and the trench 102b arranges the element formation region 10A in the gate width direction. This is a groove in which an isolation insulating film 12b for electrically dividing into a plurality of island-like regions 10a is formed. The depth of the trenches 102a and 102b from the surface of the semiconductor substrate 11 is, for example, 5 μm. As a result, a strip-shaped island region 10a having a width of about 1 μm, a length of about 7 μm, and a height from the bottom of the trenches 102a and 102b of about 5 μm is formed. At this time, the silicon oxide film 101a and the silicon nitride film 101b, which are the protective film and the pad oxide film, remain on the upper surfaces of the individual island regions 10a. For the etching of the silicon nitride film 101b, for example, dry etching using a mixed gas of CHF ₃ , CF _4, and O ₂ as an etching gas can be applied. The gas flow ratio at this time can be set to, for example, CHF ₃ : CF ₄ : O ₂ = 100: 100: 3. For etching the silicon oxide film 101a, for example, dry etching using a mixed gas of CF ₄ and CHF ₃ as an etching gas can be applied. In this case, the gas flow rate ratio can be, for example, CF ₄ : CHF ₃ = 1: 10. Further, for example, reactive dry etching using a mixed gas of Cl ₂ , HBr _3, and O ₂ as an etching gas can be applied to the etching of the semiconductor substrate 11. The gas flow rate ratio at this time can be, for example, Cl ₂ : HBr ₃ : O ₂ = 100: 100: 2-4.

  Next, after removing the resist pattern R1, a silicon oxide film 103a having a thickness of, for example, about 3 μm is formed on the entire upper surface of the semiconductor substrate 11 by, for example, an existing CVD method. Subsequently, a glass oxide film 103b is formed on the entire top surface of the semiconductor substrate 11 by spin coating SOG (Spin On Grass). Thus, as shown in FIG. 5C, a glass oxide film 103b having a flat surface is formed on the silicon oxide film 103a and in the trenches 102a and 102b. The thickness of the glass oxide film 103b from the upper surface of the silicon oxide film 103a can be set to about 1 μm, for example.

Next, by etching back the glass oxide film 103b and the silicon oxide film 103a under the condition that the selection ratio with the silicon nitride film 101b can be taken, as shown in FIG. 6A, in the trenches 102a and 102b, A silicon oxide film 103 having a thickness from the bottom of, for example, about 2 μm is formed. In the etch back of the glass oxide film 103b and the silicon oxide film 103a, for example, dry etching using a mixed gas of CF ₄ and CHF ₃ as an etching gas can be applied. In this case, the gas flow rate ratio can be, for example, CF ₄ : CHF ₃ = 1: 10.

Next, the exposed semiconductor substrate 11 is thermally oxidized to form a silicon oxide film 104a having a thickness of about 20 nm, for example. Specifically, a silicon oxide film 104a is formed in a region inside the trenches 102a and 102b and not covered with the silicon oxide film 103. Subsequently, a silicon nitride film 104B having a thickness of, for example, about 300 nm is formed on the entire upper surface of the semiconductor substrate 11 and the entire interior of the trenches 102a and 102b by, for example, a CVD method. As a result, as shown in FIG. 6B, a stacked film of a silicon oxide film 101a and silicon nitride films 104a and 104B is formed on the upper surface of each island-like region 10a, and silicon oxide is formed inside and on the bottom surface of the trenches 102a and 102b. A stacked film of the film 104a and the silicon nitride film 104B is formed. In thermal oxidation when forming the silicon oxide film 104a, the heating temperature is set to 850 ° C., for example, and the heating time is set to 30 minutes, for example. In forming the silicon nitride film 104B, for example, a mixed gas of NH ₃ and SiH ₂ Cl ₂ is used. The gas flow ratio at this time can be NH ₃ : SiH ₂ Cl ₂ = 10: 1. The film forming conditions can be set such that the pressure in the chamber is 0.2 Torr and the stage temperature is 780 ° C.

Next, by anisotropically etching the silicon nitride film 104B by, for example, RIE (reactive ion etching), as shown in FIG. 6C, the silicon oxide film 104a at the bottom of each of the trenches 102a and 102b is formed. A side wall 104b having a thickness of, for example, about 200 nm is formed on the surface of the silicon oxide film 104a on the side surfaces of the trenches 102a and 102b. The film thickness of the sidewall 104b is a thickness in the vertical direction with respect to the side surface of the trench 102a or 102b. Further, it is preferable to apply a condition that allows a sufficient selection ratio with respect to the silicon oxide film in the etching of the silicon nitride film 104B. For this anisotropic etching, for example, dry etching using a mixed gas of CHF ₃ , CF ₄ and O ₂ as an etching gas can be applied. The gas flow rate ratio at this time can be set to CHF ₃ : CF ₄ : O ₂ = 100: 100: 3. However, the silicon nitride film 101b is left on the upper surface of each island-like region 10a by appropriately selecting the etching conditions.

  Next, by removing the silicon oxide films 104a and 103 at the bottoms of the trenches 102a and 102b, for example, by wet etching, the semiconductor substrate 11 is exposed at the bottoms of the trenches 102a and 102b as shown in FIG. A cavity 105 is formed. For this wet etching, for example, a hydrofluoric acid solution having a concentration of about 5% and a temperature of about 25 ° C. can be used. By using this hydrofluoric acid solution, a sufficient selectivity can be obtained for the silicon nitride film and the silicon substrate.

  Next, the semiconductor substrate 11 exposed on the inner surface of the cavity 105 at the bottom of the trenches 102a and 102b is thermally oxidized to expand the bottoms of the trenches 102a and 102b, respectively, thereby forming the bottom surface of the element formation region 10A as shown in FIG. Then, a silicon oxide film 12C is formed. Part or all of the silicon oxide film 12C is a buried insulating film 12c that electrically isolates the lower surface of the element formation region 10A from the semiconductor substrate 11. By this buried insulating film 12 c, the bottom surface of each island-like region 10 a is electrically separated from the semiconductor substrate 11, and this is in a state of being electrically floated from the semiconductor substrate 11. Note that, as described above, the horizontal width of the silicon oxide film 12C extending from the side surface of the cavity 105 under the individual trenches 102a and 102b during thermal oxidation is at least about 0.5 μm. In the present embodiment, this is, for example, about 1 μm. In this thermal oxidation, the heating temperature is 1000 ° C., and the heating time is about 5 hours.

  Next, the silicon nitride film 101b and the sidewalls 104b covering the surface of the semiconductor substrate 11 and the silicon oxide films 101a and 104a are sequentially removed by etching, as shown in FIG. And expose the sides. For etching the silicon nitride film 101b and the sidewall 104b, for example, wet etching using a hydrofluoric acid solution having a concentration of about 5% and a temperature of about 25 ° C. can be applied. For etching the silicon oxide films 101a and 104a, for example, wet etching using a hot phosphoric acid solution having a concentration of about 86% and a temperature of about 160 ° C. can be applied. In these etchings, it is preferable that a sufficient selectivity with respect to the semiconductor substrate 11 can be obtained.

Next, as shown in FIG. 8A, a silicon oxide film 12B having a thickness of, for example, about 5 μm is formed on the entire upper surface of the semiconductor substrate 11 by, for example, an existing CVD method. At this time, the silicon oxide film 12B is also formed in the trenches 102a and 102b. In forming the silicon oxide film 12B, for example, a mixed gas of TEOS and O ₂ is used. In this case, the gas flow rate ratio can be TEOS: O ₂ = 1: 1. The film forming conditions can be set such that the pressure in the chamber is 7 Torr and the stage temperature is 400 ° C.

  Next, the upper surface of the silicon oxide film 12B is planarized by, for example, CMP (Chemical and Mechanical Polishing), so that the silicon oxide film 12B remains in the trenches 102a and 102b. 12B is removed. As a result, as shown in FIG. 8B, the surface of the semiconductor substrate 11, that is, the upper surface of each island-like region 10 a is exposed, and the element for electrically separating the side surface of the element formation region 10 A from the semiconductor substrate 11. An isolation insulating film 12a is formed on the side surface of the element formation region 10A, and an isolation insulating film 12b for electrically dividing the element formation region 10A into a plurality of island regions 10a arranged in the gate width direction is an island region. 10a.

  Through the above steps, the partial SOI structure 10B is formed on the semiconductor substrate 11 which is a bulk substrate. In this embodiment, the impurity concentration of the semiconductor substrate 11 is used as it is as the impurity concentration of the n-well region 17w.

Next, a predetermined resist solution is spin-coated on the entire upper surface of the semiconductor substrate 11, and this is subjected to an existing exposure process and development process, thereby forming regions for forming the gate insulating films 14a and 14b and the gate electrodes 15a and 15b in a later process. A resist pattern R2 having an opening thereon is formed. Subsequently, by using the existing etching technique and patterning the isolation insulating film 12b inside the trenches 102a and 102b using the resist pattern R2 as a mask, as shown in FIG. 9A and FIG. The region of the substrate 11 where the gate electrode 15b is formed, that is, the side surface of the second region 10-2 in each island-shaped region 10a is exposed. As a result, a trench 102c having a depth of, for example, about 2 μm is formed inside the element isolation insulating film 12a and the isolation insulating film 12b and on the side surface of the island-shaped region 10a. Note that the upper surface of the island-like region 10a is exposed as a result of the planarization of the silicon oxide film 12B. Etching at the time of forming the trench 102c is performed so that a silicon oxide film (including the embedded insulating film 12c) having a thickness of, for example, about 4 to 6 μm remains at the bottoms of the trenches 102a and 102b. 8B and 8C both show a cross section of the layer structure formed by this step, and FIG. 8B shows a layer structure based on the CC ′ cross section in FIG. (C) shows the layer structure based on the BB 'cross section in FIG. For the etching of the element isolation insulating film 12a and the isolation insulating film 12b, for example, dry etching using a mixed gas of CF ₄ and CHF ₃ as an etching gas can be applied. In this case, the gas flow rate ratio can be, for example, CF ₄ : CHF ₃ = 1: 10.

  Next, after removing the resist pattern R2, the surface of the semiconductor substrate 11 exposed by etching, that is, the upper surface of the island-shaped region 10a and the side surface of the second region 10-2 in each island-shaped region is thermally oxidized, thereby FIG. As shown in a), gate insulating films 14A and 14b having a film thickness of, for example, about 20 nm are formed. Note that the gate insulating film 14A is a silicon oxide film formed on the entire upper surface of each island-shaped region 10a, and the gate insulating film 14A is removed by removing the portions other than the second region 10-2 in the island-shaped region 10a in a later step. The insulating film 14a is processed. The gate insulating film 14b is a silicon oxide film formed in an exposed region on the side surface of each island-like region 10a. In thermal oxidation when forming the gate insulating films 14A and 14b, the heating temperature is set to 850 ° C., for example, and the heating time is set to 30 minutes, for example.

Next, by depositing, for example, about 3 μm of polysilicon containing impurities having n-type conductivity such as phosphorus on the entire upper surface of the semiconductor substrate 11 by, for example, the existing CVD method, as shown in FIG. As described above, a polysilicon film 15A having a thickness from the upper surface of the gate insulating film 14A of, for example, about 3 μm is formed. At this time, the trench 102c is also filled with polysilicon, thereby forming a gate electrode 15b continuous with the polysilicon film 15A, as shown in FIG. 10B. In forming the polysilicon film 15A and the gate electrode 15b, for example, a mixed gas of SiH ₄ and PH ₃ is used. The gas flow ratio at this time can be set to SiH ₄ : PH ₃ = 10: 1, for example. The film forming conditions can be set such that the pressure in the chamber is 0.6 Torr and the stage temperature is 620 ° C.

Next, a predetermined resist solution is spin-coated on the polysilicon film 15A, and this is subjected to existing exposure processing and development processing, thereby forming a resist pattern R3 on a region crossing the plurality of island-shaped regions 10a. . The region that crosses the plurality of island-like regions 10a is a region where the gate electrode 15a is formed. Subsequently, by using the existing etching technique, the polysilicon film 15A is patterned using the resist pattern R3 as a mask, so that the plurality of island regions 10a are formed on the plurality of island regions 10a as shown in FIGS. A gate electrode 15a that crosses and is continuous with the gate electrode 15b is formed. 10 (c) and 11 (a) both show a cross section of the layer structure formed by this process, FIG. 10 (c) shows a layer structure based on the CC ′ cross section in FIG. FIG. 11A shows a layer structure based on the BB ′ cross section in FIG. For the etching of the polysilicon film 15A, it is preferable to apply conditions that allow a sufficient selection ratio with the silicon oxide film. Etching that satisfies this condition includes, for example, dry etching using a mixed gas of Cl ₂ , HBr _3, and O ₂ as an etching gas. Incidentally gas flow ratio at this time, for example, _{Cl 2: HBr 3: O 2} = 100: 100: it can be 2-4.

Next, after removing the resist pattern R3, the gate insulating film 14A is patterned by using, for example, an existing etching technique with the gate electrode 15a as a mask, as shown in FIG. Then, the gate insulating film 14a is formed, and the upper surface of the island-like region 10a other than under the gate electrode 15a, that is, the upper surface of the first region 10-1 and the upper surface of the third region 10-3 is exposed. In the etching of the silicon oxide film as the gate insulating film 14A, it is preferable to apply a condition that allows a sufficient selection ratio with respect to the polysilicon film as the gate electrode 15a. This etching includes, for example, dry etching using a mixed gas of CF ₄ and CHF ₃ as an etching gas. In this case, the gas flow rate ratio can be, for example, CF ₄ / CHF ₃ = 1: 10.

  Next, the exposed surface of the semiconductor substrate 11 is thermally oxidized again, and as shown in FIG. 11C, the surface of the island-like region 10a where the silicon oxide film 106 having a thickness of, for example, about 20 nm is exposed, That is, it is formed on the upper surface of the first region 10-1 and the upper surface of the third region 10-3. This silicon oxide film 106 is a film for reducing damage to the element formation region 10A when impurities are implanted in a later process. In the thermal oxidation when forming the silicon oxide film 106, the heating temperature is set to 850 ° C., for example, and the heating time is set to 30 minutes, for example.

Next, a predetermined resist solution is spin-coated on the entire upper surface of the semiconductor substrate 11, and this is subjected to an existing exposure process and development process, thereby forming a resist pattern having an opening on the first region 10-1. Subsequently, for example, an impurity having p-type conductivity such as arsenic ions or boron ions is implanted into the upper portion of the first region 10-1 in each island-like region 10a through the silicon oxide film 106 from the opening of the resist pattern. At this time, the dose is set to about 1 × 10 ¹⁴ / cm ² , for example, and the acceleration energy is set to about 10 KeV, for example. Subsequently, after removing the resist pattern, the semiconductor substrate 11 is heated to, for example, about 1100 ° C. for about 1 hour to thermally diffuse the impurities implanted as described above. As a result, as shown in FIG. 12A, a p-type body region 17 that partially extends to below the gate electrode 15a (that is, the second region 10-2) is formed above each island-shaped region 10a. .

Next, a predetermined resist solution is spin-coated on the entire upper surface of the semiconductor substrate 11, and this is subjected to an existing exposure process and development process, thereby opening an opening in a part on the first area 10-1 in each island-shaped area 10a. A resist pattern having the same is formed. This opening is located in a region not adjacent to the gate electrode 15a in the first region 10-1. Subsequently, an impurity having p-type conductivity, such as arsenic ions or boron ions, is implanted into a part of the upper part of each island-like region 10a through the silicon oxide film 106 from the opening of the resist pattern. At this time, the dose is set to about 1 × 10 ¹⁷ / cm ² , for example, and the acceleration energy is set to about 10 KeV. Subsequently, after removing the resist pattern, a predetermined resist solution is spin-coated again on the entire upper surface of the semiconductor substrate 11, and this is subjected to an existing exposure process and development process, whereby the first area in each island-shaped area 10a. Resist patterns having openings are formed in a part on 10-1 and a part on the third region 10-3. The opening on the first region 10-1 is a region adjacent to the gate electrode 15a in the first region 10-1, and is located in a region where the impurity having p-type conductivity is not implanted. The opening on the third region 10-3 is located in a region not adjacent to the gate electrode 15a in the third region 10-3. Subsequently, an impurity having n-type conductivity, such as phosphorus ions, is added from the opening of the resist pattern through the silicon oxide film 106 to a part of the upper part of the first region 10-1 and the third region 10 in each island-like region 10a. -3 It injects into a part of upper part, respectively. At this time, the dose is set to 1 × 10 ¹⁷ / cm ² , for example, and the acceleration energy is set to 10 KeV, for example. Subsequently, after removing the resist pattern, the semiconductor substrate 11 is heated to, for example, about 900 ° C. for about 30 minutes to thermally diffuse the p-type and n-type impurities implanted as described above. At this time, by applying an electric field in the direction parallel to the surface of the semiconductor substrate 11, that is, in the horizontal direction, the impurities are diffused in the horizontal direction. As a result, as shown in FIG. 12B, a pair of source region 18s and drain region 18d sandwiching the gate electrode 15a is formed on each island-shaped region 10a, and the body is formed in the region adjacent to the source region 18s. A pulling area 19 is formed. Note that the source region 18 s and the body pulling region 19 are formed above the p-type body region 17. Further, a part of the source region 18s extends under the gate electrode 15a.

  Through the above steps, a semiconductor element is formed in the element formation region 10A in the partial SOI structure 10B that is electrically separated from the semiconductor substrate 11. In the above, an LDMOSFET that forms an n-type channel has been described as an example of a semiconductor element. However, the present invention is not limited to this, and for example, the polarity of a semiconductor substrate 11 to be used and the polarity of an impurity to be implanted are switched. Thus, it is also possible to manufacture an LDMOSFET that forms a p-type channel.

  Next, a silicon oxide film is formed by depositing silicon oxide on the entire upper surface of the semiconductor substrate 11 by, for example, an existing CVD method, and planarizing the upper surface of the silicon substrate by, for example, a CMP method. As shown in FIG. 2, the semiconductor element formed as described above is buried, and an interlayer insulating film 21 having a film thickness from the upper surface of the element formation region 10A of, for example, about 1 μm is formed.

  Next, a predetermined resist solution is spin-coated on the interlayer insulating film 21, and an existing exposure process and development process are performed thereon, so that each island is similarly formed on the drain region 18 d formed in each island-shaped region 10 a. A resist pattern R4 having an opening is formed on the source region 18s and the body pulling region 19 formed on the planar region 10a and on the gate electrode 15a. For convenience of explanation, the opening on the gate electrode 15a is omitted. Subsequently, using the existing etching technique, the interlayer insulating film 21 is etched using the resist pattern R4 as a mask to expose the drain region 18d in each island-shaped region 10a as shown in FIG. A contact hole, a contact hole exposing the source region 18s and the body pulling region 19 in each island-like region 10a, and a contact hole exposing the gate electrode 15a are formed. The contact hole exposing the surface of the drain region 18d extends over the plurality of island regions 10a so as to expose the surface of the drain region 18d formed in each of the plurality of island regions 10a arranged in parallel in the gate width direction. Formed. Similarly, a contact hole exposing the surface of the source region 18s and the body pulling region 19 is formed on the boundary between the source region 18s and the body pulling region 19, and a plurality of island-like regions arranged in parallel in the gate width direction. 10a is formed across the plurality of island-like regions 10a so as to expose the surface of the source region 18s and the surface of the body pulling region 19 formed on each.

  Next, after removing the resist pattern R4, a refractory metal is deposited on the entire top surface of the semiconductor substrate 11 by sputtering, for example. Here, for example, titanium and titanium nitride are sequentially deposited. Subsequently, for example, by RTN (Rapid Thermal Nitridation) or RTO (Rapid Thermal Oxidation), the drain region 18d upper part, the source region 18s and the body pulling region 19 upper part, and the gate electrode 15a upper part, which are part of the silicon semiconductor substrate 11, respectively. Then, silicide films 18a and 15c made of titanium silicide are formed. Titanium and titanium nitride that have not caused a thermal reaction are selectively removed. However, since this method is known, description thereof is omitted here.

  Next, for example, by using an existing sputtering method, a contact hole formed in the interlayer insulating film 21 is filled with a conductor such as tungsten, so that all the drain regions 18d in each of the plurality of island regions 10a are filled. In-contact wiring 22 electrically connected to (specifically, silicide film 18a), and all source regions 18s and body pulling regions 19 (specifically, silicide film 18a) in the plurality of island-like regions 10a. An in-contact wiring 22 electrically connected and an in-contact wiring 22 electrically connected to the gate electrode 15a (specifically, the silicide film 15c) are formed.

  Next, a metal such as titanium is deposited on the interlayer insulating film 21 by, for example, a sputtering method, for example, about 50 nm. Subsequently, aluminum containing silicon and copper is deposited on the interlayer insulating film 21, for example, by a sputtering method, for example, 500 nm. Deposition to a degree. Subsequently, the titanium film formed as described above and the aluminum film containing silicon and copper are patterned by the existing photolithography technique and etching technique to be electrically connected to each of the in-contact wirings 22. Metal wirings 23 and 24 are formed. Thereby, the semiconductor device 100 shown in FIGS. 1 to 4 is manufactured.

As described above, the semiconductor device 100 according to the present embodiment has the first to third regions 10-arranged in the gate width direction (first direction) and arranged in order in the gate length direction (second direction). A semiconductor substrate 11 having a first conductivity type (for example, n-type) element formation region 10A (also referred to as a first well region) including a plurality of island-like regions 10a having 1 to 10-3; An element isolation insulating film 12a and a buried insulating film 12c (first electrode) are formed on the entire side surface and lower surface and electrically isolate the element forming region 10A from the semiconductor substrate 11 by insulating between the element forming region 10A and the semiconductor substrate 11. A plurality of island-like regions 1 that are formed between adjacent island-like regions 10a and in which the element-forming regions 10A are arranged in the gate width direction by insulating between the adjacent island-like regions 10a. An isolation insulating film 12b (also referred to as a second insulating film) that is electrically divided into 0a, and a gate electrode 15a (also referred to as a first conductor film) formed on the second region 10-2 of the island-shaped region 10a The gate electrode 15b (second conductor) formed in the trench 102c formed in the isolation insulating film 12b between the opposing second regions 10-2 in the adjacent island regions 10a and electrically continuous with the gate electrode 15a A series of gate electrodes 15a and 15b formed so as to straddle the plurality of island-like regions 10a along the gate width direction, and a part thereof extends to a part under the gate electrode 15a. As shown, a second conductivity type (for example, p-type) p-type body region 17 (also referred to as a second well region) formed from the upper portion of the first region 10-1 to the upper portion of the second region 10-2 in the island-like region 10a. Say) and gate power The first conductivity type (for example, n-type) formed on the p-type body region 17 so that a part of the upper surface of the p-type body region 17 extends below the gate electrode 15a while leaving a part of the upper surface of the p-type body region 17 below 15a. A source region 18s and a second conductivity type (for example, p-type) body pulling region 19 (also referred to as a first high-concentration region) formed in a part of the upper portion of the p-type body region 17 and adjacent to the source region 18s. And a drain region 18d of the first conductivity type (for example, n-type) formed in a part of the island-like region 10a above the third region 10-3 and not adjacent to the region below the gate electrode 15a, In-contact wiring 22 and metal wiring 23 (also referred to as first wiring) electrically connected to the plurality of drain regions 18d formed in each of the plurality of island-shaped regions 10a, and formed in each of the plurality of island-shaped regions 10a. A plurality of source regions 18s and body pulling region 19 and electrically connected to the contact plugs 22 and metal wiring 23 (also referred to as a second wiring) and configured to have a.

  In this embodiment, the gate electrode 15b is also formed in the trench 102c formed in the element isolation insulating film 12a located on the side surface of the second region 10-2 in the island-shaped region 10a. The gate electrode 15b is electrically continuous with the gate electrode 15a formed on the island-like region 10a.

  Further, in the method of manufacturing the semiconductor device 100 according to the present embodiment, the semiconductor substrate 11 having the first conductivity type (for example, n-type) element formation region 10A (first well region) is prepared, and the side surface of the element formation region 10A is prepared. A trench 102a (this is referred to as a first trench) is formed as a whole, and element formation regions 10A are arranged in the gate width direction (first direction) and are arranged in order in the gate length direction (second direction). Are formed into a plurality of island-like regions 10a having third regions 10-1 to 10-3 (this is referred to as a second trench), and the bottoms of the first and second trenches 102a and 102b are heated. By oxidizing, a buried insulating film 12c (also referred to as a first insulating film) that insulates between the entire lower surface of each of the plurality of island-like regions 10a and the semiconductor substrate 11 is formed under each of the plurality of island-like regions 10a. The first trench 102a is filled with an element isolation insulating film 12a (also referred to as a second insulating film), and the second trench 102b is filled with an isolation insulating film 12b (also referred to as a third insulating film). A trench 102c (this is referred to as a third trench) is formed in the isolation insulating film 12b located between the opposing second regions 10-2 in the island region 10a, and the second region 10-2 in the plurality of island regions 10a In addition, by forming a series of conductor films (for example, a polysilicon film containing a predetermined impurity) in the third trench 102c, a series of gate electrodes 15a and 15b straddling the plurality of island regions 10a along the gate width direction. (Also referred to as a first gate electrode) is formed, and an impurity of a second conductivity type (for example, p-type) is implanted and diffused from the upper surface of the first region 10-1 in the island region 10a. Then, a p-type body region 17 (second well region) extending from the upper portion of the first region 10-1 to a part under the gate electrode 15a is formed, and the first region 10-1 in the island region 10a is By injecting and diffusing impurities of a conductivity type (for example, n-type), a source region 18s extending partly below the gate electrode 15a while leaving part of the upper surface of the p-type body region 17 below the gate electrode 15a. Is formed on the p-type body region 17, and a first conductivity type (for example, n-type) impurity is implanted and diffused from the upper surface of the third region 10-3 in the island-shaped region 10a, so that the first region in the island-shaped region 10a is diffused. The drain region 18d is formed in a region that is a part of the upper portion of the third region 10-3 and that is not adjacent to the region under the gate electrode 15a, and the second conductivity type (for example, p) Type) impurities To form a body pulling region 19 (first high-concentration region) in a region adjacent to the source region 18s above the p-type body region 17 and other than under the gate electrode 15a. In-contact wiring 22 and metal wiring 23 (first wiring) electrically connected to the plurality of drain regions 18d formed in each of the island-shaped regions 10a are formed, and a plurality of formed in the plurality of island-shaped regions 10a. An in-contact wiring 22 and a metal wiring 23 (second wiring) electrically connected to the source region 18s and the body pulling region 19 are formed.

  In this way, insulation is provided between the semiconductor substrate 11 and the entire side surface and bottom surface of the element formation region 10A (first well region) in which a semiconductor element such as an LDMOS transistor is formed in a part of the semiconductor substrate 11. The element formation region 10A can be isolated from the semiconductor substrate 11 by forming the conductive element isolation insulating film 12a and the buried insulating film 12c. As described above, by using the element isolation insulating film 12a and the buried insulating film 12c to electrically isolate the element formation region 10A from the semiconductor substrate 11, similarly to the semiconductor device created using the SOI substrate, The semiconductor element formed in the element formation region 10A can have a structure that does not require electric interference. Thereby, it is possible to reduce leakage current and electrical interference between semiconductor elements. Further, not only on the upper surface of the element formation region 10A, but also in a trench formed between the individual element formation regions 10A divided into a plurality of island-like regions 10a, that is, parallel to the gate length direction in the individual island-like regions 10a. By forming the gate electrode 15b also on the side surface, when a predetermined bias voltage is applied to the gate electrodes 15a and 15b, the side portion in addition to the upper portion of the island-like region 10a is driven. It becomes possible. As a result, the drive region can be enlarged regardless of the chip mounting area, and as a result, the element formation region 10A can be reduced and the drive capability can be improved. Furthermore, in the present embodiment, for example, a bulk substrate or the like can be used as the semiconductor substrate 11, so that the gate length of each island-like region 10a is not limited to the thickness of the silicon thin film on the SOI substrate, for example. The width in the vertical direction (depth direction) of the gate electrode 15b formed on the side surface parallel to the direction can be set.

  Further, according to the present embodiment, the structure for electrically separating the element forming region 10A where the semiconductor element is formed from the semiconductor substrate 11 does not require a complicated process such as bonding of the semiconductor substrates 11 to each other. Therefore, the semiconductor device 100 can be manufactured at a low cost. Furthermore, since the method of manufacturing the semiconductor device 100 according to the present embodiment does not use oxygen ion implantation or the like, it does not cause deterioration of the crystallinity of the semiconductor substrate in the element formation region 10A. For this reason, there is also an advantage that the device performance and reliability are not lowered.

  Further, as in this embodiment, a partial SOI structure 10B is formed on the semiconductor substrate 11, and an LDMOS transistor is formed as a semiconductor element on the semiconductor substrate 11, so that the latch-up resistance is the same as when an LDMOS transistor is formed on the SOI substrate. In addition, the semiconductor device 100 with improved inter-element breakdown voltage can be realized.

  Next, a second embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration not specifically mentioned is the same as that of the first embodiment.

Configuration FIG. 14 is a top view showing the configuration of the semiconductor device 200 according to this embodiment. 14 is a cross-sectional view taken along the line DD ′ in FIG. 14 are the same as the AA ′ cross section (see FIG. 2) and the BB ′ cross section (see) in FIG. 1, and are quoted here. To do. However, in the semiconductor device 200 according to the present embodiment, the partial SOI structure 10B in the semiconductor device 100 is replaced with the partial SOI structure 20B. Further, in this embodiment, the combined shape of the element isolation insulating film 12a and the isolation insulating film 12b is replaced with the “day” shape from the “eye” shape in the first embodiment.

  As shown in FIG. 14, in the semiconductor device 200, similarly to the semiconductor device 100, the side surface of the element formation region 10A is electrically isolated from the semiconductor substrate 11 by the element isolation insulating film 12a, and the element formation region 10A is isolated. The insulating film 12b is electrically divided into a plurality of island regions 10a arranged in the gate width direction. The semiconductor device 200 has a configuration in which the lower surface of the element formation region 10A is electrically separated from the semiconductor substrate 11 by the buried insulating film 22c instead of the buried insulating film 12c. That is, in the semiconductor device 200, the embedded insulating film 12c for electrically isolating the lower surface of the element formation region 10A from the semiconductor substrate 11 is replaced with the embedded insulating film 22c in the same configuration as the semiconductor device 100 according to the first embodiment. .

  The buried insulating film 22c is a silicon oxide film formed by etching and expanding the cavity 105 formed when forming the buried insulating film 12c in Example 1, and then thermally oxidizing the surface thereof.

  As described above, when the buried insulating film 22c is formed under the element formation region 10A, the bottoms of the trenches 102a and 102b are expanded, that is, the cavities 105 under the trenches 102a and 102b are widened in the lateral direction, thereby lowering the trenches 102a and 102b. It is possible to further increase the lateral extent of the thermal oxide film formed on the substrate. As a result, in this embodiment, the interval between the plurality of island-like regions 10a can be made wider than that in the first embodiment, and the drive region per unit area can be expanded. As a result, the driving capability per unit area in the semiconductor chip can be improved.

  The buried oxide film 22c can be, for example, a silicon oxide film as in the first embodiment. Such a buried insulating film 22c is formed so as to divide, for example, the trench 102a formed so as to surround the side surface of the element formation region 10A and the plurality of island regions 10a arranged in the gate width direction. The lower portion of each trench 102b can be formed by, for example, expanding the bottom by anisotropic dry etching or wet etching, and further expanding the bottom by, for example, a thermal oxidation method. In the above-described etching, for example, when the size of the island-shaped region 10a in the gate width direction is about 2 μm, for example, the width is expanded by about 0.5 μm from the side surfaces of the lower portions of the trenches 102a and 102b. In the thermal oxidation, the lower portions of the trenches 102a and 102b widened by etching are widened by at least 0.5 μm in the horizontal direction. For example, in this embodiment, the bottoms of the widened trenches 102a and 102b (corresponding to a cavity 205 described later) are expanded by about 1 μm in the horizontal direction by thermal oxidation, so that the buried insulating film 22c is formed over the entire element forming region 10A. Form. As a result, the trenches located in parallel, that is, the entire bottom of the element formation region 10A can be closed by the silicon oxide film (embedded insulating film 22c) formed by thermal oxidation. The structure formed thereby is a partial SOI structure 20B according to this embodiment.

  The element isolation insulating film 12a and the isolation insulating film 12b are silicon oxide films formed using, for example, the STI method, as in the first embodiment. However, in this embodiment, the trenches 102a and 102b are combined in a “day” shape. Therefore, in this embodiment, the dimensions of the trench formed by combining strip-shaped trenches in a lattice shape are such that the length of the short side (hereinafter referred to as width) on the upper surface is, for example, about 1 μm (micrometer), and the long side on the upper surface. The length (hereinafter referred to as length) is, for example, about 9 to 11 μm, and the length from the top surface to the bottom surface (hereinafter referred to as thickness) is, for example, about 4 to 6 μm.

  Since the other configuration is the same as that of the semiconductor device 100 according to the first embodiment, detailed description thereof is omitted here.

  Further, the semiconductor device 200 having the above-described configuration can be switched in the same manner as a normal n-type MOSFET, similarly to the semiconductor device 100 according to the first embodiment. Specifically, by applying a positive potential or a ground potential to the gate electrode while applying a positive potential to the drain region 18d while grounding the source region 18s, the p-type bodies below the gate electrodes 15a and 15b are applied. The region 17 is inverted, depleted or accumulated. Thereby, the amount of current flowing from the drain region 18d to the source region 18s can be controlled.

Manufacturing Method Next, a manufacturing method of the semiconductor device 200 according to the present embodiment will be described in detail with reference to the drawings. 16 and 17 are process diagrams showing a method for manufacturing the semiconductor device 200. In the method for manufacturing the semiconductor device 200, the steps from the preparation of the semiconductor substrate 11 to the formation of the cavity 105 at the bottoms of the trenches 102a and 102b formed in the semiconductor substrate 11 are as follows. a) to FIG. 7A), and the process after the partial SOI structure 20B is formed on the semiconductor substrate 11 is the same as the manufacturing method of the semiconductor device 100 according to the first embodiment (from FIG. 8B). Since it is substantially the same as FIG. 13B, detailed description is omitted here.

  In this manufacturing method, the top surface of each island-like region 10a is covered with the silicon oxide film 101a and the silicon nitride film 101b in the same process as the manufacturing method of the semiconductor device 100 according to the first embodiment, except for the bottoms of the side surfaces of the trenches 102a and 102b. Then, the cavity 105 is formed at the bottoms of the trenches 102a and 102b. Next, the trenches 102a and 102b are masked using the silicon nitride film 101b and the side wall 104b made of silicon nitride film as a mask. By etching the exposed semiconductor substrate 11 at the bottom, as shown in FIG. 16A, the bottom of the trenches 102a and 102b is expanded in the horizontal direction by about 0.5 μm, for example. As a result, a cavity 205 having a wider width in the horizontal direction than the cavity 105 is formed at the bottom of the trenches 102a and 102b. For this etching, for example, wet etching using a hydrofluoric acid solution having a concentration of about 5% and a temperature of about 25 ° C. as an etchant can be applied.

  Next, by thermally oxidizing the semiconductor substrate 11 exposed on the inner surfaces of the cavities 205 at the bottoms of the trenches 102a and 102b, a silicon oxide film 22C is formed on the bottom surface of the element formation region 10A as shown in FIG. Part or all of the silicon oxide film 22C is a buried insulating film 22c for electrically isolating the lower surface of the element formation region 10A from the semiconductor substrate 11. By this buried insulating film 22 c, the bottom surface of each island-like region 10 a is electrically separated from the semiconductor substrate 11, and is electrically floated from the semiconductor substrate 11. The horizontal width of the silicon oxide film 22C extending from the side surface of the cavity 205 is at least about 0.5 μm as described above. In the present embodiment, this is, for example, about 1 μm. In this thermal oxidation, the heating temperature is 1000 ° C., and the heating time is about 5 hours.

  Next, as in Example 1, the silicon nitride film 101b and the sidewalls 104b covering the surface of the semiconductor substrate 11 and the silicon oxide films 101a and 104a are sequentially removed by etching, as shown in FIG. The upper and side surfaces of the individual island regions 10a are exposed. For etching the silicon nitride film 101b and the sidewall 104b, for example, wet etching using a hydrofluoric acid solution having a concentration of about 5% and a temperature of about 25 ° C. can be applied. For etching the silicon oxide films 101a and 104a, for example, wet etching using a hot phosphoric acid solution having a concentration of about 86% and a temperature of about 160 ° C. can be applied. In these etchings, it is preferable that a sufficient selectivity with respect to the semiconductor substrate 11 can be obtained.

Next, as shown in FIG. 17A, a silicon oxide film 12B having a thickness of, for example, about 5 μm is formed on the entire top surface of the semiconductor substrate 11 by, for example, an existing CVD method. At this time, the trenches 102a and 102b and the cavity 205 remaining in the trenches 102a and 102b are filled with silicon oxide. In forming the silicon oxide film 12B, for example, a mixed gas of TEOS and O ₂ is used. In this case, the gas flow rate ratio can be TEOS: O ₂ = 1: 1. The film forming conditions can be set such that the pressure in the chamber is 7 Torr and the stage temperature is 400 ° C.

  Next, the silicon oxide film 12B on the semiconductor substrate 11 is removed so that the silicon oxide film 12B remains in the trenches 102a and 102b by planarizing the upper surface of the silicon oxide film 12B by, for example, CMP. As a result, as shown in FIG. 17B, the surface of the semiconductor substrate 11, that is, the upper surface of each island-like region 10 a is exposed, and the element isolation for electrically separating the side surface of the element formation region 10 A from the semiconductor substrate 11. An insulating film 12a is formed on the side surface of the element formation region 10A, and an isolation insulating film 12b for electrically separating the element formation region 10A into a plurality of island regions 10a arranged in the gate width direction is an island region 10a. Formed between.

  Through the above steps, the partial SOI structure 20B is formed on the semiconductor substrate 11 which is a bulk substrate. In this embodiment, the impurity concentration of the semiconductor substrate 11 is used as it is as the impurity concentration of the n-well region 17w.

  After that, the semiconductor device according to the present embodiment as shown in FIGS. 14, 2, 3 and 14 is obtained through the same steps as in the first embodiment (see FIGS. 8B to 13B). 200 is manufactured.

As described above, the semiconductor device 200 according to the present embodiment is arranged in the gate width direction (first direction) and the first to third regions 10-are arranged in order in the gate length direction (second direction). A semiconductor substrate 11 having a first conductivity type (for example, n-type) element formation region 10A (also referred to as a first well region) including a plurality of island-like regions 10a having 1 to 10-3; An element isolation insulating film 12a and a buried insulating film 22c (first insulating film) are formed on the entire side surface and lower surface, and electrically isolate the element forming region 10A from the semiconductor substrate 11 by insulating between the element forming region 10A and the semiconductor substrate 11. A plurality of island-like regions 1 that are formed between adjacent island-like regions 10a and in which the element-forming regions 10A are arranged in the gate width direction by insulating between the adjacent island-like regions 10a. An isolation insulating film 12b (also referred to as a second insulating film) that is electrically divided into 0a, and a gate electrode 15a (also referred to as a first conductor film) formed on the second region 10-2 of the island-shaped region 10a The gate electrode 15b (second conductor) formed in the trench 102c formed in the isolation insulating film 12b between the opposing second regions 10-2 in the adjacent island regions 10a and electrically continuous with the gate electrode 15a A series of gate electrodes 15a and 15b formed so as to straddle the plurality of island-like regions 10a along the gate width direction, and a part thereof extends to a part under the gate electrode 15a. As shown, a second conductivity type (for example, p-type) p-type body region 17 (also referred to as a second well region) formed from the upper portion of the first region 10-1 to the upper portion of the second region 10-2 in the island-like region 10a. Say) and gate power The first conductivity type (for example, n-type) formed on the p-type body region 17 so that a part of the upper surface of the p-type body region 17 extends below the gate electrode 15a while leaving a part of the upper surface of the p-type body region 17 below 15a. A source region 18s and a second conductivity type (for example, p-type) body pulling region 19 (also referred to as a first high-concentration region) formed in a part of the upper portion of the p-type body region 17 and adjacent to the source region 18s. And a drain region 18d of the first conductivity type (for example, n-type) formed in a part of the island-like region 10a above the third region 10-3 and not adjacent to the region below the gate electrode 15a, In-contact wiring 22 and metal wiring 23 (also referred to as first wiring) electrically connected to the plurality of drain regions 18d formed in each of the plurality of island-shaped regions 10a, and formed in each of the plurality of island-shaped regions 10a. A plurality of source regions 18s and body pulling region 19 and electrically connected to the contact plugs 22 and metal wiring 23 (also referred to as a second wiring) and configured to have a.

  In this embodiment, the gate electrode 15b is also formed in the trench 102c formed in the element isolation insulating film 12a located on the side surface of the second region 10-2 in the island-shaped region 10a. The gate electrode 15b is electrically continuous with the gate electrode 15a formed on the island-like region 10a.

  Further, in the method of manufacturing the semiconductor device 200 according to the present embodiment, the semiconductor substrate 11 having the first conductivity type (for example, n-type) element formation region 10A (first well region) is prepared, and the side surface of the element formation region 10A is prepared. A trench 102a (this is referred to as a first trench) is formed as a whole, and element formation regions 10A are arranged in the gate width direction (first direction) and are arranged in order in the gate length direction (first direction). Trenches 102b (this is referred to as second trenches) to be divided into a plurality of island-like regions 10a having the third regions 10-1 to 10-3 are formed, and the lower portions of the first and second trenches 102a and 102b are etched. As a result, the lower portions of the first and second trenches 102a and 102b are expanded, and the lower portions of the expanded first and second trenches 102a and 102b (cavities 205) are thermally oxidized. Thus, a buried insulating film 22c (also referred to as a first insulating film) that insulates between the entire lower surface of each of the plurality of island regions 10a and the semiconductor substrate 11 is formed on the entire lower surface of each of the plurality of island regions 10a. The first trench 102a is filled with an element isolation insulating film 12a (also referred to as a second insulating film), and the second trench 102b is filled with an isolation insulating film 12b (also referred to as a third insulating film) to face each other in the adjacent island region 10a. A trench 102c (this is referred to as a third trench) is formed in the isolation insulating film 12b located between the second regions 10-2, and the second region 10-2 in the plurality of island regions 10a and in the third trench 102c. A series of gate electrodes 1 straddling the plurality of island-like regions 10a along the gate width direction by forming a series of conductor films (for example, polysilicon films containing predetermined impurities) a and 15b (also referred to as a first gate electrode) are formed, and impurities of a second conductivity type (for example, p-type) are implanted and diffused from the upper surface of the first region 10-1 in the island-shaped region 10a. A p-type body region 17 (second well region) extending from the upper portion of the region 10-1 to a part below the gate electrode 15a is formed, and the first conductivity type (from the upper surface of the first region 10-1 in the island-like region 10a) is formed. For example, n-type impurities are implanted and diffused to leave the p-type body region 17 under the gate electrode 15a, while leaving a part of the upper surface of the p-type body region 17 and the source region 18s extending partly below the gate electrode 15a. The third region 10 in the island region 10a is formed by injecting and diffusing a first conductivity type (for example, n-type) impurity from the upper surface of the third region 10-3 in the island region 10a. -3 part of the top A drain region 18d is formed in a region not adjacent to the region under the gate electrode 15a, and a second conductivity type (for example, p-type) impurity is implanted and diffused from the upper surface of the first region 10-1 in the island region 10a. Thus, a body pulling region 19 (first high-concentration region) is formed in a region adjacent to the source region 18s in the upper part of the p-type body region 17 and other than under the gate electrode 15a. In-contact wiring 22 and metal wiring 23 (first wiring) electrically connected to the plurality of drain regions 18d formed are formed, and a plurality of source regions 18s and body pulling regions formed in the plurality of island-shaped regions 10a, respectively. In-contact wiring 22 and metal wiring 23 (second wiring) electrically connected to 19 are formed.

  In this way, a part of the semiconductor substrate 11, which is an insulating material between the entire bottom surface of the element formation region 10 </ b> A (first well region) where a semiconductor element such as an LDMOS transistor is formed, and the semiconductor substrate 11. By forming the buried insulating film 22c, the entire bottom surface of the element forming region 10A can be insulated and separated from the semiconductor substrate 11. Further, by forming the element isolation insulating film 12a in the first trench 102a surrounding the entire side surface of the element formation region 10A, the entire side surface of the element formation region 10A can be isolated from the semiconductor substrate 11. Therefore, according to the present embodiment, the element formation region 10A can be electrically isolated from the semiconductor substrate 11 by the buried insulating film 22c and the element isolation insulating film 12a. As described above, by using the element isolation insulating film 12a and the buried insulating film 22c to electrically isolate the element formation region 10A from the semiconductor substrate 11, the semiconductor device manufactured using the SOI substrate is similar to the semiconductor device manufactured using the SOI substrate. The semiconductor element formed in the element formation region 10A can have a structure that does not require electric interference. Thereby, it is possible to reduce leakage current and electrical interference between semiconductor elements. Further, not only on the upper surface of the element formation region 10A, but also in a trench formed between the individual element formation regions 10A divided into a plurality of island-like regions 10a, that is, parallel to the gate length direction in the individual island-like regions 10a. By forming the gate electrode 15b also on the side surface, when a predetermined bias voltage is applied to the gate electrodes 15a and 15b, the side portion in addition to the upper portion of the island-like region 10a is driven. It becomes possible. As a result, the drive region can be enlarged regardless of the chip mounting area, and as a result, the element formation region 10A can be reduced and the drive capability can be improved. Furthermore, in the present embodiment, for example, a bulk substrate or the like can be used as the semiconductor substrate 11, so that the gate length of each island-like region 10a is not limited to the thickness of the silicon thin film on the SOI substrate, for example. The width in the vertical direction (depth direction) of the gate electrode 15b formed on the side surface parallel to the direction can be set.

  Further, according to the present embodiment, the configuration for electrically separating the element formation region 10A where the semiconductor element is formed from the semiconductor substrate 11 does not require a complicated process such as bonding of the semiconductor substrates 11 together. Therefore, the semiconductor device 200 can be manufactured at a low cost. Furthermore, since the manufacturing method of the semiconductor device 200 according to the present embodiment does not use oxygen ion implantation or the like, it does not cause deterioration of crystallinity of the semiconductor substrate in the element formation region 10A. For this reason, there is also an advantage that the device performance and reliability are not lowered.

  Further, as in this embodiment, the partial SOI structure 20B is formed on the semiconductor substrate 11, and the LDMOS transistor is formed as a semiconductor element on the semiconductor substrate 11, so that the latch-up resistance is the same as in the case where the LDMOS transistor is formed on the SOI substrate. In addition, the semiconductor device 200 with improved inter-element breakdown voltage can be realized.

  Furthermore, in this embodiment, since the buried insulating film 22c is formed by expanding the lower portions of the trenches 102a and 102b by etching and then thermally oxidizing, the width in the gate width direction of each island-like region 10a is set to the embodiment. Can be wider than 1. Thereby, since the driving force per unit area is improved, the design freedom of the semiconductor element is improved, and as a result, it can be applied to various semiconductor elements.

  Next, Example 3 of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first embodiment or the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration not specifically mentioned is the same as that of the first embodiment or the second embodiment. Further, in the present embodiment, the semiconductor device 200 exemplified in the second embodiment is cited, and description will be made based on the difference from this. However, the present invention is not limited to this. For example, the present embodiment can be similarly applied to a configuration based on the semiconductor device 100 illustrated in the first embodiment.

Configuration FIG. 18 is a top view showing the configuration of the semiconductor device 300 according to the present embodiment. The AA ′ section, BB ′ section, and CC ′ section in FIG. 18 are the AA ′ section (see FIG. 2) and BB ′ section (see FIG. 3) in FIG. Since these are the same as the CC ′ cross section (see FIG. 14), these are quoted here. However, in the semiconductor device 300 according to the present embodiment, the partial SOI structure 20B in the semiconductor device 200 is replaced with the partial SOI structure 30B.

  As shown in FIG. 18, in the semiconductor device 300, the side surface of the element formation region 10A is electrically isolated from the semiconductor substrate 11 by the element isolation insulating films 32a and 32b instead of the element isolation insulating film 12a. The region 10A is electrically divided into a plurality of island regions 10a arranged in the gate width direction by the isolation insulating film 12b. The semiconductor device 300 has a configuration in which the lower surface of the element formation region 10A is electrically isolated from the semiconductor substrate 11 by a buried insulating film 32c instead of the buried oxide film 22c. That is, in the semiconductor device 300, the element isolation insulating film 12a is replaced with the element isolation insulating films 32a and 32b and the embedded insulating film 22c is replaced with the embedded insulating film 32c in the same configuration as the semiconductor device 200 according to the second embodiment. .

  The element isolation insulating films 32a and 32b can be silicon oxide films formed using, for example, the STI method, similarly to the element isolation insulating film 12a in the first or second embodiment. However, in this embodiment, after the element isolation insulating film 32a is formed together with the isolation insulating film 12b parallel to the element isolation insulating film 32a, the element isolation insulating film 32b that connects both ends thereof is formed. In other words, in this embodiment, first, the element isolation insulating film 32a is formed on the side surface parallel to the gate length direction in the element formation region 10A, thereby electrically isolating the side surface from the semiconductor substrate 11 and isolating and insulating. By forming the film 12b, the element formation region 10A is electrically divided into a plurality of island regions 10a arranged in the gate width direction. Thereafter, an element isolation insulating film 32b is formed on a side surface parallel to the gate width direction of the element formation region 10A, so that the side surface is electrically isolated from the semiconductor substrate 11. As a result, the entire side surface of the element formation region 10A is electrically isolated from the semiconductor substrate 11 by the element isolation insulating films 32a and 32b, and the plurality of islands in which the element formation region 10A is arranged in the gate width direction by the isolation insulating film 12b. It divides | segments into the shape area | region 10a.

  In addition, the dimensions of the trench (corresponding to 102b and 302a described later) when forming the element isolation insulating film 12a and the isolation insulating film 12b are, for example, the length of the short side (hereinafter referred to as the width) on the upper surface as in the second embodiment. For example, about 1 μm (micrometer), the length of the long side (hereinafter referred to as length) on the top surface is about 9 to 11 μm, and the length from the top surface to the bottom surface (hereinafter referred to as thickness) is, for example, The thickness is about 4 to 6 μm.

  The buried insulating film 32c can be, for example, a silicon oxide film, similarly to the buried oxide film 12c or 22c in the first or second embodiment. However, the formation method of the buried insulating film 32c according to the present embodiment is different from that of the buried insulating film 12c or 22c according to the first or second embodiment. That is, in this embodiment, for example, the bottom of each island-like region 10a in the semiconductor substrate 11 is made hollow, and this is filled with an insulator such as silicon oxide by using, for example, a CVD method to form the buried insulating film 32c. Form. According to this forming method, the semiconductor device 300 according to the present embodiment does not require high-temperature heat treatment for forming the silicon oxide film (buried insulating film 32c) at the bottom of the partial SOI structure 30B. Therefore, it is possible to prevent deterioration of characteristics due to thermal stress and to form a partial SOI structure 30B with good crystallinity. As a result, the performance and reliability of the semiconductor element formed in the partial SOI structure 30B can be improved.

  Since other configurations are the same as those of the semiconductor device 100 according to the first embodiment or the semiconductor device 200 according to the second embodiment, detailed description thereof is omitted here.

  In addition, the semiconductor device 300 having the above configuration can be switched in the same manner as a normal n-type MOSFET, as in the first and second embodiments. Specifically, by applying a positive potential or a ground potential to the gate electrode while applying a positive potential to the drain region 18d while grounding the source region 18s, the p-type bodies below the gate electrodes 15a and 15b are applied. The region 17 is inverted, depleted or accumulated. Thereby, the amount of current flowing from the drain region 18d to the source region 18s can be controlled.

Manufacturing Method Next, a manufacturing method of the semiconductor device 300 according to the present embodiment will be described in detail with reference to the drawings. 19 to 23 are process diagrams illustrating a method for manufacturing the semiconductor device 300. FIG. In the method of manufacturing the semiconductor device 300, the process after the partial SOI structure 30B is formed on the semiconductor substrate 11 is the method of manufacturing the semiconductor device 100 according to the first embodiment (see FIGS. 8B to 13B). The detailed description is omitted here. In addition, each step will be described below based on the top view and the AA ′, BB ′, and DD ′ sections in FIG. 18 as appropriate.

In this manufacturing method, as in the first or second embodiment, a bulk n-type silicon substrate is first prepared as the semiconductor substrate 11. Next, the surface of the semiconductor substrate 11 is thermally oxidized to form a silicon oxide film 101a having a thickness of about 20 nm, for example. Subsequently, a silicon nitride film 101b having a thickness of, for example, about 500 nm is formed on the silicon oxide film 101b by, for example, a CVD method. Thereby, as shown in FIG. 19A, a laminated film of the silicon oxide film 101a and the silicon nitride film 101b is formed on the semiconductor substrate 11. The silicon nitride film 101b functions as a protective film for protecting the surface of the semiconductor substrate 11 from etching (see FIG. 22B) in a later process. The silicon oxide film 101 a is a pad oxide film for bringing the silicon nitride film 101 b into close contact with the semiconductor substrate 11. In the thermal oxidation when forming the silicon oxide film 101a, the heating temperature is set to 850 ° C., for example, and the heating time is set to 30 minutes, for example. In forming the silicon nitride film 101b, for example, a mixed gas of NH ₃ and SiH ₂ Cl ₂ is used. The gas flow ratio at this time can be NH ₃ : SiH ₂ Cl ₂ = 10: 1. The film forming conditions can be set such that the pressure in the chamber is 0.2 Torr and the stage temperature is 780 ° C.

  Next, a predetermined resist solution is spin-coated on the silicon nitride film 101b, and this is subjected to existing exposure processing and development processing, thereby forming a resist pattern R5 having a strip-shaped opening shape. In this example, the resist pattern R5 has a plurality of (three in this example) strip-shaped openings arranged in parallel. That is, the resist pattern R5 has only openings corresponding to the three horizontal lines in the “day” -shaped lattice shape. In this shape, the width of each opening is, for example, about 1 μm, and the length is, for example, about 7 μm. The adjacent interval is, for example, about 2 μm.

Next, using the resist pattern R5 as a mask, the silicon nitride film 101b, the silicon oxide film 101a, and the semiconductor substrate 11 are sequentially etched using, for example, an existing etching technique, so that FIGS. ), Trenches 302a and 102b having the same opening shape as that of the resist pattern R5 described above are formed in the semiconductor substrate 11. That is, the trench 302a in which the element isolation insulating film 32a for electrically isolating the side surface parallel to the gate length direction in the element formation region 10A from the semiconductor substrate 11 and the element formation region 10A are arranged in the gate length direction. The semiconductor substrate 11 is formed with the trench 102b in which the isolation insulating film 12b for electrically dividing the plurality of island-like regions 10a is formed. FIG. 19B shows a layer structure based on the DD ′ cross section in FIG. 18, and FIG. 20A shows a view of the semiconductor substrate 11 in which the trench 302a is formed as viewed from above. However, in FIG. 20A, the resist pattern R5 is omitted for clarity of explanation. The depth of the bottom of the trench 302a from the surface of the semiconductor substrate 11 is, for example, 5 μm. At this time, the silicon oxide film 101a and the silicon nitride film 101b, which are the protective film and the pad oxide film, remain on the upper surface of the semiconductor substrate 11 (including the plurality of island-like regions 10a) where the trenches 302a and 102b are not formed. To do. For the etching of the silicon nitride film 101b, for example, dry etching using a mixed gas of CHF ₃ , CF _4, and O ₂ as an etching gas can be applied. The gas flow ratio at this time can be set to, for example, CHF ₃ : CF ₄ : O ₂ = 100: 100: 3. For etching the silicon oxide film 101a, for example, dry etching using a mixed gas of CF ₄ and CHF ₃ as an etching gas can be applied. In this case, the gas flow rate ratio can be, for example, CF ₄ : CHF ₃ = 1: 10. Further, for example, reactive dry etching using a mixed gas of Cl ₂ , HBr _3, and O ₂ as an etching gas can be applied to the etching of the semiconductor substrate 11. The gas flow rate ratio at this time can be, for example, Cl ₂ : HBr ₃ : O ₂ = 100: 100: 2-4.

  Next, after removing the resist pattern R5, a silicon oxide film 103a having a film thickness of, for example, about 3 μm is formed on the entire upper surface of the semiconductor substrate 11, for example, by an existing CVD method. Subsequently, a glass oxide film 103b is formed on the entire top surface of the semiconductor substrate 11 by spin coating SOG (Spin On Grass). Thus, as shown in FIG. 20B, a glass oxide film 103b having a flat surface is formed on the silicon oxide film 103a and in the trenches 302a and 102b. The thickness of the glass oxide film 103b from the upper surface of the silicon oxide film 103a can be set to about 1 μm, for example.

Next, by etching back the glass oxide film 103b and the silicon oxide film 103a under the condition that the selection ratio with the silicon nitride film 101b can be obtained, as shown in FIG. 21A, in the trenches 302a and 102b, A silicon oxide film 103 having a thickness from the bottom of, for example, about 2 μm is formed. In the etch back of the glass oxide film 103b and the silicon oxide film 103a, for example, dry etching using a mixed gas of CF ₄ and CHF ₃ as an etching gas can be applied. In this case, the gas flow rate ratio can be, for example, CF ₄ : CHF ₃ = 1: 10.

Next, the exposed semiconductor substrate 11 is thermally oxidized to form a silicon oxide film 104a having a thickness of about 20 nm, for example. Specifically, the silicon oxide film 104a is formed on the inner side surfaces of the trenches 302a and 102b and in regions not covered with the silicon oxide film 103. Subsequently, as shown in FIG. 21B, a silicon nitride film 104B having a film thickness of, eg, about 300 nm is formed on the entire upper surface of the semiconductor substrate 11 and the entire inside of the trenches 302a and 102b by, eg, CVD. In the thermal oxidation when forming the silicon oxide film 104a, the heating temperature is set to 500 ° C., for example, and the heating time is set to 2 hours, for example. In forming the silicon nitride film 104B, for example, a mixed gas of NH ₃ and SiH ₂ Cl ₂ is used. The gas flow ratio at this time can be NH ₃ : SiH ₂ Cl ₂ = 10: 1. The film forming conditions can be set such that the pressure in the chamber is 0.2 Torr and the stage temperature is 780 ° C.

Next, by anisotropically etching the silicon nitride film 104B by, for example, RIE (reactive ion etching), the silicon oxide film 104a at the bottom of each of the trenches 302a and 102b is formed as shown in FIG. A side wall 104b having a thickness of, for example, about 200 nm is formed on the surface of the silicon oxide film 104a on the side surfaces of the trenches 302a and 102b. The film thickness of the sidewall 104b is a thickness in the vertical direction with respect to the side surface of the trench 302a or 102b. Further, it is preferable to apply a condition that allows a sufficient selection ratio with respect to the silicon oxide film in the etching of the silicon nitride film 104B. For this anisotropic etching, for example, dry etching using a mixed gas of CHF ₃ , CF ₄ and O ₂ as an etching gas can be applied. The gas flow rate ratio at this time can be set to CHF ₃ : CF ₄ : O ₂ = 100: 100: 3. However, by appropriately selecting the etching conditions, the silicon nitride film 101b is left on the upper surface of the mesa-like semiconductor substrate 11 processed into the individual island-like regions 10a.

  Next, by removing the silicon oxide films 104a and 103 at the bottoms of the trenches 302a and 102b, for example, by wet etching, the semiconductor substrate 11 is formed at the bottoms of the trenches 302a and 102b as shown in FIG. Cavity 105 is formed to expose. For this wet etching, for example, a hydrofluoric acid solution having a concentration of about 5% and a temperature of about 25 ° C. can be used. By using a hydrofluoric acid solution, it is possible to obtain a sufficient selectivity with respect to the silicon nitride film and the silicon substrate.

  Next, the exposed semiconductor substrate 11 at the bottom of each of the trenches 302a and 102b is etched by wet etching, for example, using the silicon nitride film 101b and the side wall 104b made of the silicon nitride film as a mask. As shown in FIG. 5, the bottoms of the trenches 302a and 102b are expanded in the horizontal direction by at least about 1 μm. At this time, the etching is performed so that the lower part of the region to be the element formation region 10A sandwiched between the adjacent trenches 302a is completely hollowed out. Thereby, the cavity 305 is formed under the entire element formation region 10A, and each island-shaped region 10a is in a hollow state. For this wet etching, for example, a hydrofluoric acid solution having a concentration of about 5% and a temperature of about 25 ° C. can be used. By using a hydrofluoric acid solution, it is possible to obtain a sufficient selectivity with respect to the silicon nitride film and the silicon substrate.

  Next, the silicon nitride film 101b and the sidewalls 104b covering the surface of the semiconductor substrate 11 and the silicon oxide films 101a and 104a are sequentially removed by etching, so that the upper surfaces of the individual island regions 10a are obtained as shown in FIG. And expose the sides. For etching the silicon nitride film 101b and the sidewall 104b, for example, wet etching using a hydrofluoric acid solution having a concentration of about 5% and a temperature of about 25 ° C. can be applied. For etching the silicon oxide films 101a and 104a, for example, wet etching using a hot phosphoric acid solution having a concentration of about 86% and a temperature of about 160 ° C. can be applied. In these etchings, it is preferable that a sufficient selectivity with respect to the semiconductor substrate 11 can be obtained.

Next, as shown in FIG. 23A, a silicon oxide film 32A having a thickness of, for example, about 7 μm is formed on the entire upper surface of the semiconductor substrate 11 by, for example, an existing CVD method. At this time, the insides of the trenches 302a and 102b and the cavity 305 below the element formation region 10A are filled with silicon oxide. Part or all of the silicon oxide film 32A formed in the cavity 305 is a buried insulating film 32c for electrically isolating the lower surface of the element formation region 10A from the semiconductor substrate 11. However, the silicon oxide film may not be completely filled in the cavity 305 under each island-like region 10a. In forming the silicon oxide film 32A, for example, a mixed gas of TEOS and O ₂ is used. In this case, the gas flow rate ratio can be TEOS: O ₂ = 1: 1. The film forming conditions can be set such that the pressure in the chamber is 7 Torr and the stage temperature is 400 ° C.

  Next, the upper surface of the formed silicon oxide film 32A is planarized by, eg, CMP, so that the silicon oxide film 32A remains in the trenches 302a and 102b as shown in FIG. 11 is removed. As a result, as shown in FIG. 23B, the surface of the semiconductor substrate 11, that is, the upper surface of each island-like region 10a is exposed, and the lower surface of the element formation region 10A is embedded for electrically separating from the semiconductor substrate 11. An insulating film 32c is formed, and an element isolation insulating film 32a for electrically isolating the side surface in the gate length direction in the element formation region 10A from the semiconductor substrate 11 is formed on the side surface parallel to the gate length direction in the element formation region 10A. Further, an isolation insulating film 12b is formed between the island regions 10a for electrically dividing the element formation region 10A into a plurality of island regions 10a arranged in the gate width direction.

  Next, a predetermined resist solution is spin-coated on the semiconductor substrate 11, and this is subjected to an existing exposure process and a development process, whereby the short side of each of the trenches 302a and 102b formed in the above-described process is contacted or overlapped. Then, a resist pattern R6 having a strip-shaped opening is formed. That is, the resist pattern R6 has openings corresponding to the two vertical lines in the “day” -shaped lattice shape. In this shape, each strip-shaped opening in the resist pattern R6 has a width of, for example, about 1 μm and a length of, for example, about 9 μm.

Next, the resist pattern R6 is used as a mask, and the semiconductor substrate 11 is sequentially etched using, for example, an existing etching technique, so that the resist pattern described above is obtained as shown in FIGS. 23 (c) and 24 (a). A trench 302b having the same opening shape as that of R6 is formed in the semiconductor substrate 11. As a result, a lattice-shaped trench including the trenches 302a, 102b, and 302b is formed in the semiconductor substrate 11. At this time, the trench is formed to a depth that reaches at least the silicon oxide film 32A (including the buried insulating film 32c) formed in the cavity 305 below the element formation region 10A. In order to satisfy this, the depth of the trench 302b is, for example, about 5 μm or more. As a result, the island-like region 10 a having a width of about 2 μm, a length of about 7 μm, and a height from the trench bottom of about 2 μm is electrically isolated from the semiconductor substrate 11. FIG. 23B shows a layer structure based on the AA ′ cross section in FIG. 18, and FIG. 24A shows a semiconductor substrate in which a lattice-like trench composed of the trench 302a, the trench 302b, and the trench 102b is formed. The figure which looked at 11 from the upper surface is shown. However, in FIG. 24A, the resist pattern R6 is omitted for simplification of description. For example, reactive dry etching using a mixed gas of Cl ₂ , HBr _3, and O ₂ as an etching gas can be applied to the etching of the semiconductor substrate 11. The gas flow rate ratio at this time can be, for example, Cl ₂ : HBr ₃ : O ₂ = 100: 100: 2-4.

Next, after removing the resist pattern R6, as shown in FIG. 24B, a silicon oxide film 32B having a film thickness of, for example, about 7 μm is formed on the entire upper surface of the semiconductor substrate 11, for example, by an existing CVD method. At this time, the trench 302b is filled with silicon oxide. In forming the silicon oxide film 32B, for example, a mixed gas of TEOS and O ₂ is used. In this case, the gas flow rate ratio can be TEOS: O ₂ = 1: 1. The film forming conditions can be set such that the pressure in the chamber is 7 Torr and the stage temperature is 400 ° C.

  Next, the silicon oxide film 32B on the semiconductor substrate 11 is removed so that the silicon oxide film 32B remains in the trench 302b by planarizing the upper surface of the formed silicon oxide film 32B by, for example, CMP. As a result, as shown in FIG. 24C, the surface of the semiconductor substrate 11, that is, the upper surface of each island region 10a is exposed, and the side surface parallel to the gate width direction in the element formation region 10A is electrically connected from the semiconductor substrate 11. An element isolation insulating film 32b is formed on the side surface of the element formation region 10A.

  Through the above steps, the partial SOI structure 30B is formed on the semiconductor substrate 11 which is a bulk substrate. In this embodiment, the impurity concentration of the semiconductor substrate 11 is used as it is as the impurity concentration of the n-well region 17w.

  Thereafter, the semiconductor device according to the present embodiment as shown in FIGS. 18, 2, 3, and 14 is obtained through the same steps as in the first embodiment (see FIGS. 8B to 13B). 300 is manufactured.

As described above, the semiconductor device 300 according to the present embodiment is arranged in the gate width direction (first direction) and the first to third regions 10-are arranged in order in the gate length direction (second direction). A semiconductor substrate 11 having a first conductivity type (for example, n-type) element formation region 10A (also referred to as a first well region) including a plurality of island-like regions 10a having 1 to 10-3; Element isolation insulating films 32a and 32b and a buried insulating film 32c that are formed on the entire side surface and bottom surface and electrically isolate the element formation region 10A from the semiconductor substrate 11 by insulating between the element formation region 10A and the semiconductor substrate 11. (Also referred to as a first insulating film) is formed between adjacent island regions 10a, and a plurality of element formation regions 10A are arranged in the gate width direction by insulating between the adjacent island regions 10a. An isolation insulating film 12b (also referred to as a second insulating film) that is electrically divided into the island-shaped region 10a, and a gate electrode 15a (first conductor film) formed on the second region 10-2 of the island-shaped region 10a In other words, the gate electrode 15b (which is formed in the trench 102c formed in the isolation insulating film 12b between the opposing second regions 10-2 in the adjacent island regions 10a and is electrically continuous with the gate electrode 15a). A series of gate electrodes 15a and 15b formed so as to straddle the plurality of island-like regions 10a along the gate width direction, and partly below the gate electrode 15a. A p-type body region 17 (second type) of the second conductivity type (for example, p-type) formed from the upper portion of the first region 10-1 to the upper portion of the second region 10-2 in the island-like region 10a so as to extend partially. Also called a 2-well region) First conductivity type (for example, n-type) formed on the p-type body region 17 so that a part of the upper surface of the p-type body region 17 is left below the gate electrode 15a and a part extends below the gate electrode 15a. Type source region 18s and second conductivity type (for example, p-type) body pulling region 19 (first high concentration) formed in a part of upper part of p type body region 17 and adjacent to source region 18s. A first conductivity type (for example, n-type) drain region formed in a part of the island-like region 10a above the third region 10-3 and not adjacent to the region below the gate electrode 15a. 18d, the in-contact wiring 22 and the metal wiring 23 (also referred to as first wiring) electrically connected to the plurality of drain regions 18d formed in each of the plurality of island regions 10a, and the plurality of island regions 10a Constituted by a plurality of source regions 18s and body pulling region 19 and electrically connected to the inside of the contact wires 22 and the metal wiring 23 formed on the LES (also referred to as a second wiring).

  In this embodiment, the gate electrode 15b is also formed in the trench 102c formed in the element isolation insulating film 12a located on the side surface of the second region 10-2 in the island-shaped region 10a. The gate electrode 15b is electrically continuous with the gate electrode 15a formed on the island-like region 10a.

  Further, in the method of manufacturing the semiconductor device 300 according to the present embodiment, the semiconductor substrate 11 having the first conductivity type (for example, n-type) element formation region 10A (first well region) is prepared, and the gate in the element formation region 10A is prepared. A trench 302a (this is referred to as a first trench) is formed on a side surface perpendicular to the width direction (first direction), that is, a side surface parallel to the gate length direction (second direction), and the element formation region 10A is formed in the gate width direction. And trenches 102b (this is referred to as second trenches) that are divided into a plurality of island-like regions 10a having first to third regions 10-1 to 10-3, which are arranged in order in the gate length direction. By etching the lower portions of the first trench 302a and the second trench 102b, a cavity 305 is formed under each of the plurality of island-like regions 10a, and the cavity 305 is reduced. Both of them are buried and filled with an insulating film 32c (also referred to as a first insulating film), the first trench 302a is filled with an element isolation insulating film 32a (also referred to as a second insulating film), and the second trench 102b is filled with an isolating insulating film 12b (also referred to as an insulating film 12b). A trench 302b (this is referred to as a third trench) is formed on a side surface parallel to the gate width direction in the element formation region 10A, and the third trench 302b is formed as an element isolation insulating film 32b (first isolation film). A trench 102c (this is referred to as a fourth trench) is formed in the isolation insulating film 12b positioned between the opposing second regions 10-2 in the adjacent island regions 10a. A series of conductor films (for example, a polysilicon film containing a predetermined impurity) is formed on the second region 10-2 in the island region 10a and in the fourth trench 102c. A series of gate electrodes 15a and 15b (also referred to as first gate electrodes) straddling the plurality of island-like regions 10a along the gate width direction is formed, and the second conductive is performed from the upper surface of the first region 10-1 in the island-like region 10a. A p-type body region 17 (second well region) extending from the upper portion of the first region 10-1 to a portion below the gate electrode 15a is formed by injecting and diffusing a type (for example, p-type) impurity. Then, by implanting and diffusing a first conductivity type (for example, n-type) impurity from the upper surface of the first region 10-1 in the island region 10a, a part of the upper surface of the p-type body region 17 below the gate electrode 15a is left. On the other hand, a source region 18 s partially extending below the gate electrode 15 a is formed on the p-type body region 17, and the first conductivity type (for example, n-type) is formed from the upper surface of the third region 10-3 in the island-shaped region 10 a. Impurities are implanted to expand By scattering, the drain region 18d is formed in a part of the island region 10a above the third region 10-3 and not adjacent to the region below the gate electrode 15a, and the first region 10 in the island region 10a. -1 by implanting and diffusing impurities of the second conductivity type (for example, p-type) from the upper surface, so that the body is formed in a region adjacent to the source region 18s above the p-type body region 17 and other than under the gate electrode 15a. The pull-in region 19 (first high concentration region) is formed, and the in-contact wiring 22 and the metal wiring 23 (first wiring) electrically connected to the plurality of drain regions 18d formed in each of the plurality of island-like regions 10a. In-contact wiring 22 and metal that are formed and electrically connected to the plurality of source regions 18s and the body pulling region 19 formed in each of the plurality of island-shaped regions 10a Line 23 to form a (second wiring).

  In this way, a part of the semiconductor substrate 11, which is an insulating material between the entire bottom surface of the element formation region 10 </ b> A (first well region) where a semiconductor element such as an LDMOS transistor is formed, and the semiconductor substrate 11. By forming the buried insulating film 32c (which may include a gap that remains without being partially filled with the cavity 305), the entire bottom surface of the element formation region 10A can be isolated from the semiconductor substrate 11. Further, by forming element isolation insulating films 32a and 32b in the first and fourth trenches 302a and 302b surrounding the entire side surface of the element formation region 10A, the entire side surface of the element formation region 10A is isolated from the semiconductor substrate 11. be able to. Therefore, according to the present embodiment, the element formation region 10A can be electrically isolated from the semiconductor substrate 11 by the element isolation insulating films 32a and 32b and the buried insulating film 32c. In this way, the element forming region 10A is electrically isolated from the semiconductor substrate 11 using the element isolation insulating films 32a and 32b and the buried insulating film 32c, and thus, similar to the semiconductor device manufactured using the SOI substrate. In addition, the semiconductor element formed in the element formation region 10A can have a structure that does not require consideration of electrical interference. Thereby, it is possible to reduce leakage current and electrical interference between semiconductor elements. Further, not only on the upper surface of the element formation region 10A, but also in a trench formed between the individual element formation regions 10A divided into a plurality of island-like regions 10a, that is, parallel to the gate length direction in the individual island-like regions 10a. By forming the gate electrode 15b also on the side surface, when a predetermined bias voltage is applied to the gate electrodes 15a and 15b, the side portion in addition to the upper portion of the island-like region 10a is driven. It becomes possible. As a result, the drive region can be enlarged regardless of the chip mounting area, and as a result, the element formation region 10A can be reduced and the drive capability can be improved. Furthermore, in the present embodiment, for example, a bulk substrate or the like can be used as the semiconductor substrate 11, so that the gate length of each island-like region 10a is not limited to the thickness of the silicon thin film on the SOI substrate, for example. The width in the vertical direction (depth direction) of the gate electrode 15b formed on the side surface parallel to the direction can be set.

  Further, according to the present embodiment, the structure for electrically separating the element forming region 10A where the semiconductor element is formed from the semiconductor substrate 11 does not require a complicated process such as bonding of the semiconductor substrates 11 to each other. Therefore, the semiconductor device 300 can be manufactured at low cost. Furthermore, since the method for manufacturing the semiconductor device 300 according to the present embodiment does not use oxygen ion implantation or the like, the crystallinity deterioration of the semiconductor substrate in the element formation region 10A is not caused. For this reason, there is also an advantage that the device performance and reliability are not lowered.

  Further, as in this embodiment, the partial SOI structure 20B is formed on the semiconductor substrate 11, and the LDMOS transistor is formed as a semiconductor element on the partial SOI structure 20B. In addition, the semiconductor device 300 with improved inter-device breakdown voltage can be realized.

  Further, in this embodiment, since the high temperature heat treatment is not performed for forming the buried insulating film 32c which is a structure for electrically isolating the element formation region 10A from the semiconductor substrate 11, the influence of thermal stress and the like is reduced. In addition, the partial SOI structure 30B with good crystallinity can be formed. As a result, the performance and reliability of the semiconductor element can be improved.

  Next, a fourth embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first to third embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration not specifically mentioned is the same as any one of the first to third embodiments. Furthermore, in the present embodiment, the semiconductor device 100 exemplified in the first embodiment is cited, and description will be made based on the difference from this. However, the present invention is not limited to this. For example, the present embodiment can be similarly applied to a configuration based on the semiconductor device 100 or 300 illustrated in the second or third embodiment.

Configuration FIG. 25 is a top view showing the configuration of the semiconductor device 400 according to this embodiment. 26 is a sectional view taken along line EE ′ in FIG. 25, FIG. 27 is a sectional view taken along line FF ′ in FIG. 25, and FIG. 28 is a sectional view taken along line GG ′ in FIG.

  As shown in FIGS. 25 to 28, in the semiconductor device 400 according to the present embodiment, the partial SOI structure 10B in the semiconductor device 100 is replaced with a junction isolation structure 40B in the same configuration as the semiconductor device 100 according to the first embodiment. In this embodiment, a p-type silicon bulk substrate (hereinafter referred to as a p-type silicon substrate) is used as the semiconductor substrate 11 and a MOSFET for forming an n-type channel is manufactured in this case. Take an example.

  As shown in FIG. 25, in the semiconductor device 400, as in the first to third embodiments, the side surface of the element formation region 10A is electrically isolated from the semiconductor substrate 11 by the element isolation insulating film 12a and the element formation region 10A. Is electrically divided into a plurality of island regions 10a arranged in the gate width direction by the isolation insulating film 12b. The semiconductor device 400 has a configuration in which the lower surface of the element formation region 10A is electrically isolated from the semiconductor substrate 11 by the impurity buried layer 42c instead of the buried insulating film 12c. That is, in the semiconductor device 400, in the same configuration as the semiconductor device 100 according to the first embodiment, the buried insulating film 12c for electrically separating the lower surface of the element formation region 10A from the semiconductor substrate 11 is replaced with the impurity buried layer 42c. .

  The impurity buried layer 42c is a region in which an impurity having conductivity opposite to that of the n-well region 17w, for example, an impurity having p-type conductivity such as arsenic ions is diffused to a concentration higher than the impurity concentration of the semiconductor substrate 11, for example. It is. In the impurity buried layer 42c, for example, when a higher electric field is applied to the drain region 18d than during normal operation, a depletion layer of the p-type body region 17 is formed between the semiconductor substrate 11 and the n-well region 17w. This is a film for preventing connection with the depletion layer. A phenomenon in which a depletion layer in p-type body region 17 is connected to a depletion layer formed between semiconductor substrate 11 and n-well region 17w is called a punch-through phenomenon. For example, when the potential of the semiconductor substrate 11 and the potential of the source region 18 s are different, a leak current flows between the source region 18 s and the semiconductor substrate 11 once the punch-through phenomenon occurs. Therefore, in this embodiment, the impurity buried layer 42c is provided below the element forming region 10A, thereby separating the junction between the semiconductor substrate 11 and the n well region 17w. As a result, a depletion layer can be prevented from being formed between the semiconductor substrate 11 and the n-well region 17w. As a result, the depletion layer in the p-type body region 17 is connected to another depletion layer, resulting in a punch-through phenomenon. Can be prevented. According to this, it is possible to obtain the same effect as that of electrically isolating the element formation region from the semiconductor substrate by the partial SOI structure shown in the first to third embodiments.

  Since the other configuration is the same as that of the semiconductor device 100, 200, or 300 according to any one of the first to third embodiments, detailed description thereof is omitted here.

  Further, the semiconductor device 300 having the above configuration can be switched in the same manner as a normal n-type MOSFET, as in the first to third embodiments. Specifically, by applying a positive potential or a ground potential to the gate electrode while applying a positive potential to the drain region 18d while grounding the source region 18s, the p-type bodies below the gate electrodes 15a and 15b are applied. The region 17 is inverted, depleted or accumulated. Thereby, the amount of current flowing from the drain region 18d to the source region 18s can be controlled.

Manufacturing Method Next, a manufacturing method of the semiconductor device 400 according to the present embodiment will be described in detail with reference to the drawings. FIG. 29 to FIG. 32 are process diagrams showing a method for manufacturing the semiconductor device 400. In the method for manufacturing the semiconductor device 400, the process after the formation of the junction isolation structure 40B on the semiconductor substrate 11 is the same as the method for manufacturing the semiconductor device 100 according to the first embodiment (see FIGS. 8B to 13B). Since it is substantially the same, detailed description is abbreviate | omitted here.

  In this manufacturing method, first, a bulk p-type silicon substrate is prepared as the semiconductor substrate 11. Next, by thermally oxidizing the surface of the semiconductor substrate 11, as shown in FIG. 29A, a silicon oxide film 401a having a thickness of, for example, about 50 nm is formed. The silicon oxide film 401a is a film for reducing damage that the element formation region 10A receives when ions are implanted to form the n-well region 17w. Further, in this thermal oxidation, the heating temperature can be set to, for example, about 850 ° C., and the heating time can be set to, for example, about 30 minutes.

Next, a predetermined resist solution is spin-coated on the silicon oxide film 401a, and this is subjected to an existing exposure process and development process, so that an impurity is implanted into a region where an n-well region 17w is formed in a later process. A resist pattern having an opening is formed. Subsequently, for example, impurities having n-type conductivity such as phosphorus ions are implanted into the upper portion of the semiconductor substrate 11 through the silicon oxide film 401a from the opening of the resist pattern. At this time, the dose is set to about 1 × 10 ¹⁴ / cm ² , for example, and the acceleration energy is set to about 10 KeV, for example. Subsequently, after removing the resist pattern, the semiconductor substrate 11 is heated to, for example, about 1200 ° C. for about 1 hour, so that the impurities implanted as described above are thermally diffused. As a result, an n-well region 17w is formed on the semiconductor substrate 11 as shown in FIG.

Next, as shown in FIG. 29C, a silicon oxide film 401b having a thickness of, for example, about 300 nm is formed on the entire top surface of the semiconductor substrate 11 by, for example, an existing CVD method. In forming the silicon oxide film 401b, for example, a mixed gas of TEOS and O ₂ is used. In this case, the gas flow rate ratio can be TEOS: O ₂ = 1: 1. The film forming conditions can be set such that the pressure in the chamber is 7 Torr and the stage temperature is 400 ° C.

  Next, a predetermined resist solution is spin-coated on the silicon oxide film 401b, and this is subjected to existing exposure processing and development processing, thereby forming a resist pattern R7 having a grid-like opening shape. In this example, the opening shape of the resist pattern R <b> 7 has an “eye” shape as in the first embodiment. However, in this embodiment, the dimensions of the four rectangles arranged in parallel in the vertical direction in the drawing have a width of, for example, about 0.5 μm and a length of, for example, about 5 μm. The adjacent interval is, for example, about 0.5 μm. Further, the two rectangles arranged in the horizontal direction in the drawing have a width of, for example, about 0.5 μm and a length of, for example, about 2.5 μm. According to this dimension, in the drawing, the vertical length of the outer periphery is about 2.5 μm, and the horizontal length is about 6 μm.

Next, using the resist pattern R7 as a mask, the silicon oxide film 401b, the silicon oxide film 401a, and the semiconductor substrate 11 are sequentially etched using, for example, an existing etching technique, as shown in FIG. Trenches 102 a and 102 b having the same opening shape as the resist pattern R 7 described above are formed in the semiconductor substrate 11. The trench 102a is a groove in which an element isolation insulating film 12a for electrically isolating the side surface of the element formation region 10A from the semiconductor substrate 11 is formed, and the trench 102b arranges the element formation region 10A in the gate length direction. This is a groove in which an isolation insulating film 12b for dividing into a plurality of island-like regions 10a is formed. The depth of the trenches 102a and 102b from the surface of the semiconductor substrate 11 is, for example, about 2 μm. As a result, a strip-like island region 10a having a width of about 1 μm, a length of about 7 μm, and a height from the bottom of the trenches 102a and 102b of about 2 μm is formed. At this time, silicon oxide films 401a and 401b remain on the upper surfaces of the individual island regions 10a. For etching the silicon oxide films 401b and 401a, for example, dry etching using a mixed gas of CF ₄ and CHF ₃ as an etching gas can be applied. In this case, the gas flow rate ratio can be, for example, CF ₄ : CHF ₃ = 1: 10. Further, for example, reactive dry etching using a mixed gas of Cl ₂ , HBr _3, and O ₂ as an etching gas can be applied to the etching of the semiconductor substrate 11. The gas flow rate ratio at this time can be, for example, Cl ₂ : HBr ₃ : O ₂ = 100: 100: 2-4.

Next, after removing the resist pattern R7, the semiconductor substrate 11 is again thermally oxidized to form a silicon oxide film 404a having a thickness of, for example, about 20 nm on the exposed surface of the semiconductor substrate 11. Specifically, the silicon oxide film 404 a is formed on the side surface and the bottom surface of each of the trenches 102 a and 102 b formed in the semiconductor substrate 11. Subsequently, a silicon oxide film 404B having a film thickness of, for example, about 200 nm is formed on the entire upper surface of the semiconductor substrate 11 and the entire inside of the trenches 102a and 102b by, for example, the CVD method. As a result, as shown in FIG. 30B, a stacked film of silicon oxide films 401a, 401b, and 404B is formed on the upper surface of each island-shaped region 10a, and silicon oxide films 404a and 404b are formed on the side and bottom surfaces of the trenches 102a and 102b. A laminated film 404B is formed. In thermal oxidation when forming the silicon oxide film 404a, the heating temperature is set to about 500 ° C., and the heating time is set to about 2 hours, for example. For forming the silicon oxide film 404B, for example, a mixed gas of TEOS and O ₂ is used. In this case, the gas flow rate ratio can be TEOS: O ₂ = 1: 1. The film forming conditions can be set such that the pressure in the chamber is 7 Torr and the stage temperature is 400 ° C.

Next, the silicon oxide films 404B and 404a are anisotropically etched by, for example, the RIE method, thereby exposing the semiconductor substrate 11 at the bottom of each of the trenches 102a and 102b as shown in FIG. Side walls 404b made of silicon oxide films 404a and 404B having a film thickness of, for example, about 150 nm are formed on the side surfaces of 102a and 102b. In the etching at this time, it is preferable to apply conditions that allow a sufficient selectivity with respect to the semiconductor substrate 11. For this anisotropic etching, for example, dry etching using a mixed gas of CF ₄ and CHF ₃ as an etching gas can be applied. The gas flow ratio at this time can be set to CF ₄ : CHF ₃ = 1: 10. However, the silicon oxide film is left on the upper surface of each island-like region 10a by appropriately selecting the etching conditions.

  Next, the exposed semiconductor substrate 11 is thermally oxidized to form a silicon oxide film 405 having a thickness of, for example, about 20 nm on the bottom surfaces of the trenches 102a and 102b, as shown in FIG. In the thermal oxidation at this time, the heating temperature is set to, for example, about 500 ° C., and the heating time is set to, for example, about 2 hours.

Next, an impurity having p-type conductivity such as arsenic ions is implanted into the bottom of each of the trenches 102a and 102b via the silicon oxide film 405, as shown in FIG. Diffusion regions 42A are formed below 102a and 102b, respectively. At this time, the dose is set to about 1 × 10 ¹⁵ / cm ² , for example, and the acceleration energy is set to about 10 KeV, for example. In addition, since a laminated film of the silicon oxide films 401a and 401b and the sidewalls 404b are formed in regions other than the bottom portions of the trenches 102a and 102b, that is, the upper portions of the island-like regions 10a and the side surfaces of the trenches 102a and 102b, respectively. It is possible to prevent impurities such as arsenic ions from being implanted.

  Next, the semiconductor substrate 11 is heated to, for example, about 1100 ° C. for about 1 hour to thermally diffuse the impurities implanted into the diffusion region 42A as described above. Thereby, as shown in FIG. 31C, impurities are diffused across the entire bottom of the element formation region 10A. In this embodiment, part or all of the diffusion region 42B after thermal diffusion is used as the impurity buried layer 42c. The bottom surface of each island-like region 10a is electrically separated from the semiconductor substrate 11 by the impurity buried layer 42c.

  Next, the silicon oxide films 401a and 401b and the sidewalls 404b covering the surface of the semiconductor substrate 11 are removed by etching, so that the upper and side surfaces of the individual island regions 10a are exposed as shown in FIG. For the etching at this time, for example, wet etching using a hot phosphoric acid solution having a concentration of about 86% and a temperature of about 160 ° C. can be applied. In this etching, it is preferable that a sufficient selectivity with respect to the semiconductor substrate 11 can be obtained.

Next, as shown in FIG. 32B, a silicon oxide film 12B having a thickness of, for example, about 3 μm is formed on the entire upper surface of the semiconductor substrate 11 by, for example, an existing CVD method. At this time, the silicon oxide film 12B is also formed in the trenches 102a and 102b. In forming the silicon oxide film 12B, for example, a mixed gas of TEOS and O ₂ is used. In this case, the gas flow rate ratio can be TEOS: O ₂ = 1: 1. The film forming conditions can be set such that the pressure in the chamber is 7 Torr and the stage temperature is 400 ° C.

  Next, the silicon oxide film 12B on the semiconductor substrate 11 is removed so that the silicon oxide film 12B remains in the trenches 102a and 102b by planarizing the upper surface of the silicon oxide film 12B by, for example, CMP. As a result, as shown in FIG. 32C, the surface of the semiconductor substrate 11, that is, the upper surface of each island-like region 10a is exposed, and the element for electrically isolating the side surface of the element formation region 10A from the semiconductor substrate 11. An isolation insulating film 12a is formed on the side surface of the element formation region 10A, and an isolation insulating film 12b for electrically dividing the element formation region 10A into a plurality of island regions 10a arranged in the gate width direction is an island region. 10a.

  Through the above steps, the junction separation structure 40B is formed on the semiconductor substrate 11 which is a bulk substrate.

  Thereafter, through the same steps as in the first embodiment (see FIGS. 8B to 13B), the semiconductor device 400 according to the present embodiment as shown in FIGS. 25 to 28 is manufactured.

As described above, the semiconductor device 400 according to the present embodiment is arranged in the gate width direction (first direction) and the first to third regions 10-are arranged in order in the gate length (second direction) direction. A semiconductor substrate 11 having a first conductivity type (for example, n-type) element formation region 10A (also referred to as a first well region) including a plurality of island-like regions 10a having 1 to 10-3; An element isolation insulating film 12a (also referred to as a first insulating film) is formed over the entire side surface and electrically isolates the side surface of the element formation region 10A from the semiconductor substrate 11 by insulating between the side surface of the element formation region 10A and the semiconductor substrate 11. ) And the lower surface of the element formation region 10A surrounded by the element isolation insulating film 12a, and the lower surface of the element formation region 10A is halved by bonding and separating the lower surface of the element formation region 10A and the semiconductor substrate 11. Formed between the impurity buried layer 42c (also referred to as a first high-concentration region) that is electrically isolated from the conductor substrate 11 and the adjacent island regions 10a, and insulates between the adjacent island regions 10a. An isolation insulating film 12b (also referred to as a second insulating film) that electrically divides the region 10A into a plurality of island-like regions 10a arranged in the gate width direction and a second region 10-2 of the island-like region 10a are formed. The gate electrode 15a (also referred to as a first conductor film) is formed in the trench 102b formed in the isolation insulating film 12b between the second regions 10-2 facing each other in the adjacent island region 10a. And a gate electrode 15b (also referred to as a second conductor film) electrically continuous with each other, a series of gate electrodes 15a and a plurality of gate electrodes 15a formed so as to straddle the plurality of island regions 10a along the gate width direction. 15b and a second conductivity type (for example, formed on the island region 10a from the upper part of the first region 10-1 to the upper part of the second region 10-2 so that a part thereof extends partly below the gate electrode 15a. (p-type) p-type body region 17 (also referred to as a second well region) and a part of the upper surface of the p-type body region 17 are left under the gate electrode 15a and a part thereof extends under the gate electrode 15a. , A first conductivity type (for example, n-type) source region 18s formed on the p-type body region 17 and a part of the upper portion of the p-type body region 17 adjacent to the source region 18s. A two-conductivity type (for example, p-type) body pulling region 19 (also referred to as a second high concentration region) and a part of the island region 10a above the third region 10-3 and adjacent to the region below the gate electrode 15a The first conductivity type formed in the region that does not For example, an n-type drain region 18d, a contact wiring 22 and a metal wiring 23 (also referred to as a first wiring) electrically connected to the plurality of drain regions 18d formed in each of the plurality of island regions 10a, A plurality of source regions 18 s formed in each of the plurality of island-like regions 10 a and an in-contact wiring 22 and a metal wiring 23 (also referred to as a second wiring) electrically connected to the body pulling region 19 are configured. The

  In this embodiment, the gate electrode 15b is also formed in the trench 102c formed in the element isolation insulating film 12a located on the side surface of the second region 10-2 in the island-shaped region 10a. The gate electrode 15b is electrically continuous with the gate electrode 15a formed on the island-like region 10a.

  Further, in the method of manufacturing the semiconductor device 400 according to the present embodiment, the semiconductor substrate 11 having the first conductivity type (for example, n-type) element formation region 10A (first well region) is prepared, and the side surface of the element formation region 10A is prepared. A trench 102a (this is referred to as a first trench) is formed as a whole, and element formation regions 10A are arranged in the gate width direction (first direction) and are arranged in order in the gate length direction (second direction). Trench 102b (this is referred to as a second trench) that is divided into a plurality of island-like regions 10a having third regions 10-1 to 10-3 is formed so as to have a higher impurity concentration than element formation region 10A. By implanting and diffusing impurities of the second conductivity type (for example, p-type) into the bottoms of the first and second trenches 102a and 102b, the entire lower surface of each of the plurality of island-like regions 10a, the semiconductor substrate 11, Impurity buried layers 42c (also referred to as first high-concentration regions) for junction separation are formed on the entire lower surfaces of the plurality of island-like regions 10a, and the first trenches 102a are also referred to as element isolation insulating films 12a (also referred to as first insulating films). ) And the second trench 102b is filled with an isolation insulating film 12b (also referred to as a second insulating film), and a trench is formed in the isolation insulating film 12b positioned between the opposing second regions 10-2 in the adjacent island regions 10a. 102c (this is referred to as a third trench), and a series of conductor films (for example, a polysilicon film containing a predetermined impurity) on the second region 10-2 and in the third trench 102c in the plurality of island-like regions 10a ) To form a series of gate electrodes 15a and 15b (also referred to as first gate electrodes) straddling the plurality of island-like regions 10a along the gate width direction. By injecting and diffusing impurities of the second conductivity type (for example, p-type) from the upper surface of the first region 10-1 in the region 10a, the region 10a extends from the upper part of the first region 10-1 to a part below the gate electrode 15a. A p-type body region 17 (second well region) is formed, and a first conductivity type (for example, n-type) impurity is implanted and diffused from the upper surface of the first region 10-1 in the island-shaped region 10a, whereby the gate electrode A source region 18s extending partly below the gate electrode 15a is formed on the p-type body region 17 while leaving a part of the upper surface of the p-type body region 17 below 15a, and the third region 10 in the island region 10a is formed. -3 by implanting and diffusing impurities of the first conductivity type (for example, n-type) from the upper surface, adjacent to the region below the gate electrode 15a that is a part of the island region 10a above the third region 10-3 Do not drain into the area A region 18d is formed, and a second conductivity type (for example, p-type) impurity is implanted and diffused from the upper surface of the first region 10-1 in the island-shaped region 10a, so that the source region 18s above the p-type body region 17 A body pulling region 19 (also referred to as a second high concentration region) is formed in an adjacent region other than under the gate electrode 15a, and electrically connected to the plurality of drain regions 18d formed in each of the plurality of island regions 10a. Connected in-contact wiring 22 and metal wiring 23 (first wiring) are formed, and in-contact wiring electrically connected to the plurality of source regions 18s and the body pulling region 19 formed in each of the plurality of island-like regions 10a. 22 and metal wiring 23 (second wiring) are formed.

  As described above, an insulating element is formed in a part of the semiconductor substrate 11 and in the first trench 102a surrounding the entire side surface of the element formation region 10A (first well region) where a semiconductor element such as an LDMOS transistor is formed. By forming the isolation insulating film 12a, the entire side surface of the element formation region 10A can be isolated from the semiconductor substrate 11. Further, by forming an impurity buried layer 42c having a conductivity type (eg, p-type) opposite to the conductivity type (eg, n-type) of the element formation region 10A on the entire bottom surface of the element formation region 10A, the entire bottom surface of the element formation region 10A is formed. It can be separated from the semiconductor substrate 11. Therefore, according to the present embodiment, the element formation region 10A can be electrically isolated from the semiconductor substrate 11 by the element isolation insulating film 12a and the impurity buried layer 42c. As described above, by using the element isolation insulating film 12a and the impurity buried layer 42c to electrically isolate the element formation region 10A from the semiconductor substrate 11, similarly to the semiconductor device formed using the SOI substrate, The semiconductor element formed in the element formation region 10A can have a structure that does not require electric interference. Thereby, it is possible to reduce leakage current and electrical interference between semiconductor elements. Further, not only on the upper surface of the element formation region 10A, but also in a trench formed between the individual element formation regions 10A divided into a plurality of island-like regions 10a, that is, parallel to the gate length direction in the individual island-like regions 10a. By forming the gate electrode 15b also on the side surface, when a predetermined bias voltage is applied to the gate electrodes 15a and 15b, the side portion in addition to the upper portion of the island-like region 10a is driven. It becomes possible. As a result, the drive region can be enlarged regardless of the chip mounting area, and as a result, the element formation region 10A can be reduced and the drive capability can be improved. Furthermore, in the present embodiment, for example, a bulk substrate or the like can be used as the semiconductor substrate 11, so that the gate length of each island-like region 10a is not limited to the thickness of the silicon thin film on the SOI substrate, for example. The width in the vertical direction (depth direction) of the gate electrode 15b formed on the side surface parallel to the direction can be set.

  Further, according to the present embodiment, the structure for electrically separating the element forming region 10A where the semiconductor element is formed from the semiconductor substrate 11 does not require a complicated process such as bonding of the semiconductor substrates 11 to each other. Therefore, the semiconductor device 400 can be manufactured at low cost. Furthermore, since the method of manufacturing the semiconductor device 400 according to the present embodiment does not use oxygen ion implantation or the like, the crystallinity deterioration of the semiconductor substrate in the element formation region 10A is not caused. For this reason, there is also an advantage that the device performance and reliability are not lowered.

  Further, as in this embodiment, a partial SOI structure 40B is formed on the semiconductor substrate 11, and an LDMOS transistor is formed as a semiconductor element on the semiconductor substrate 11, so that the latch-up resistance is the same as in the case where the LDMOS transistor is formed on the SOI substrate. In addition, the semiconductor device 400 with improved inter-device breakdown voltage can be realized.

  Furthermore, in this embodiment, when the impurity buried layer 42c for electrically isolating the element formation region 10A from the semiconductor substrate 11 is formed on the semiconductor substrate 11, the epitaxial growth is not used, so that the semiconductor can be manufactured at low cost. The device 400 can be manufactured. For the same reason, since there is no diffusion of impurities from the impurity buried layer 42c that occurs during epitaxial growth, there is no concern about deterioration of characteristics due to this.

  Next, a fifth embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first to fourth embodiments are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration not specifically mentioned is the same as that of any one of the first to fourth embodiments.

Configuration FIG. 33 is a top view showing the configuration of the semiconductor device 500 according to this embodiment. 34 is a cross-sectional view taken along line HH ′ in FIG. 33, FIG. 35 is a cross-sectional view taken along line JJ ′ in FIG. 33, and FIG. 36 is a cross-sectional view taken along line KK ′ in FIG. In the present embodiment, a case where a p-type conductive silicon substrate is used as the semiconductor substrate 11 and an n-type transistor is formed thereon will be described as an example.

  As shown in FIGS. 33 to 36, the semiconductor device 500 according to this embodiment includes an element forming region 50A electrically isolated from the semiconductor substrate 11, a p-type body region 57 formed in the element forming region 50A, a source The region 58s and the body pulling region 59, the gate insulating film 54a formed on a part of the element forming region 50A, the gate insulating film 54b formed on a part of the side surface of the element forming region 50A, and the element forming region 50A Impurity buried layer 52c formed in semiconductor substrate 11 so as to include the lower part, gate electrode 55a formed on part of element formation region 50A via gate insulating film 54a, and part of element formation region 50A And a gate electrode 55b formed through a gate insulating film 54b.

  In the above configuration, the element formation region 50A includes a quadrangular columnar first region 50a and a plurality of second regions 50b protruding from the first region 50a in a comb shape. As in the first to fourth embodiments, the element isolation insulating film 52a and the isolation insulating film 52b are formed on the side surface of the element forming region 50A. The element isolation insulating film 52a is a “B” -shaped insulating film surrounding the element formation region 50A. The isolation insulating film 52b is an insulating film formed between the second regions 50b protruding in a comb shape from the first region 50a. Thus, by surrounding the element formation region 50A with the element isolation insulating film 52a and the isolation insulating film 52b, in this embodiment, the side surface of the element formation region 50A is the same as in the first to fourth embodiments in the semiconductor substrate. 11 is electrically separated.

  The impurity buried layer 52c is formed so as to completely cover the element isolation insulating film 52a surrounding the element formation region 50A. The impurity buried layer 52c is a region in which, for example, an impurity having the same conductivity type as that of the source region 58s, for example, an impurity having n-type conductivity such as phosphorus ions is diffused at a higher concentration than the impurity concentration of the semiconductor substrate 11, for example. is there. Such an impurity buried layer 52c functions as a diffusion region for junction separation between the semiconductor substrate 11 and the element formation region 50A, similarly to the impurity buried layer 42c in the fourth embodiment. Therefore, also in this embodiment, the lower surface of the element formation region 50A can be electrically isolated from the semiconductor substrate 11 by the junction isolation structure 50B having the impurity buried layer 52c below the element formation region 50A.

  In this embodiment, a part of the impurity buried layer 52c is used as the drain region 58d. Such an impurity buried layer 52c forms, for example, a trench (corresponding to trenches 502a and 502b described later) surrounding the element formation region 50A, and implants an n-type conductivity impurity such as phosphorus ions from the bottom of the trench. Then, it can be formed by diffusing.

  The source region 58s is a diffusion region formed from a part of the upper part of the first region 50a to the upper part of the second region 50b in the element formation region 50A by injecting and diffusing impurities having n-type conductivity. In the present embodiment, the region sandwiched between the source region 58s and the drain region 58d (impurity buried layer 52c) in the element formation region 50A is the p-type body region 57.

  Therefore, the gate insulating films 54a and 54b according to the present embodiment are formed from a part on the first region 50a to a part on the second region 50b in the element formation region 50A. In other words, the gate insulating films 54a and 54b are formed on the first region 50a so as to wrap each of the plurality of comb-like second regions 50b in the element formation region 50A from the three side surfaces and the upper surface that are not continuous with the first region 50a. Are formed in series, on the second region 50b, between the adjacent second regions 50b, and at the tip. Similarly, the gate electrodes 55a and 55b are formed on the first region 50a so as to wrap each of the plurality of comb-shaped second regions 50b in the element formation region 50A from the three side surfaces and the upper surface that are not continuous with the first region 50a. Are formed in series, on the second region 50b, between the adjacent second regions 50b, and at the tip. In this description, the portion formed on the side surface of the second region 50b is referred to as the gate insulating film 54b and the gate electrode 55b, and other portions, that is, a part on the first region 50a and the second region 50b are formed. The portion including the formed portion is referred to as a gate insulating film 54a and a gate electrode 55b.

  As described above, in the semiconductor device 500, the source region 58s and the drain region 58d are arranged vertically, and the p-type body region 57 is arranged in a region between them. Further, the gate electrodes 55a and 55b are formed not only on the comb-shaped protruding second region 50b in the element formation region 50A but also on all three side surfaces thereof. Thereby, in this embodiment, the semiconductor device 500 is formed as a vertical transistor in which a channel is formed in the vertical direction. For this reason, in the semiconductor device 500 according to this embodiment, a region (driving region) driven by the bias voltage applied to the gate electrode during operation can be made larger than, for example, other embodiments according to the present invention. . As a result, the driving capability per unit area in the semiconductor chip can be improved.

  Further, in this embodiment, in order to electrically draw out the drain region 58d on the interlayer insulating film 21, the impurity buried layer 52c including the drain region 58d is formed wider than the lower surface of the element formation region 50A and the element formation region 50A. An in-contact wiring 62 electrically connected to the impurity buried layer 52c is formed in the element isolation insulating film 52a surrounding the element isolation insulating film 52a.

  Since the other configuration is the same as that of any of the semiconductor devices 100 to 400 according to any of the first to fourth embodiments, detailed description thereof is omitted here.

Manufacturing Method Next, a manufacturing method of the semiconductor device 500 according to the present embodiment will be described in detail with reference to the drawings. 37 and 40 are process diagrams showing a method for manufacturing the semiconductor device 500. In the method of manufacturing the semiconductor device 500, after forming the trenches 502a and 502b on the side surfaces of the element formation region 50A, an n-type conductivity impurity (for example, phosphorus ions in this example) is implanted into the bottom surfaces of the trenches 502a and 502b. Then, from the step of forming the impurity buried layer 52c by diffusing to the step of forming the element isolation insulating film 52a and the isolation insulating film 52b in the trenches 502a and 502b, respectively, the method for manufacturing the semiconductor device 400 according to the fourth embodiment ( The semiconductor device 100 according to the first embodiment is substantially the same as that shown in FIG. 30B to FIG. 32C, and the steps after the step of forming the interlayer insulating film 21 on the semiconductor substrate 11 on which the semiconductor elements are formed are the same. Since the manufacturing method is substantially the same as the manufacturing method (see FIGS. 12C to 13B), detailed description thereof is omitted here. However, in this embodiment, when the drain region 58d is electrically drawn out on the interlayer insulating film 21, a contact exposing the drain region 58d is also formed in the element isolation insulating film 52a. Therefore, the contact wiring 62 according to the present embodiment is formed so as to penetrate the interlayer insulating film 21 and the element isolation insulating film 52a.

In this manufacturing method, first, a bulk p-type silicon substrate is prepared as the semiconductor substrate 11. Next, the surface of the semiconductor substrate 11 is thermally oxidized to form a silicon oxide film 501a having a thickness of about 50 nm, for example. In the thermal oxidation at this time, the heating temperature can be about 850 ° C., and the heating time can be about 30 minutes, for example. Subsequently, a silicon oxide film 501b having a thickness of, for example, about 300 nm is formed on the silicon oxide film 501a by, for example, an existing CVD method. In forming the silicon oxide film 501b, for example, a mixed gas of TEOS and O ₂ is used. In this case, the gas flow rate ratio can be TEOS: O ₂ = 1: 1. The film forming conditions can be set such that the pressure in the chamber is 7 Torr and the stage temperature is 400 ° C.

  Next, a predetermined resist solution is spin-coated on the silicon oxide film 501a, and this is subjected to existing exposure processing and development processing, whereby a resist pattern R8 having an opening having comb-like convex portions on one side surface. Form. In this example, the opening shape of the resist pattern R8 forms an “E” shape. However, in this embodiment, in the dimension of the comb-like protrusion, the width is set to, for example, about 0.5 μm and the length is set to, for example, about 2 μm. The adjacent interval is, for example, about 0.5 μm.

Next, using the resist pattern R8 as a mask, the silicon nitride film 101b, the silicon oxide film 101a, and the semiconductor substrate 11 are sequentially etched using, for example, an existing etching technique, so that FIGS. ), Trenches 502a and 502b having the same opening shape as the resist pattern R8 described above are formed in the semiconductor substrate 11. The trench 502a is a groove in which an element isolation insulating film 52a for electrically isolating the side surface of the element formation region 50A from the semiconductor substrate 11 is formed, and the trench 502b is a comb from the first region 50a in the element formation region 50A. This is a groove in which the isolation insulating film 52b between the second regions 50b protruding in a tooth shape is formed. Further, the depth of the trenches 502a and 502b from the surface of the semiconductor substrate 11 is 2 μm, for example, and the length of the trench 502b in the gate length direction is 4 μm, for example. As a result, an element formation region 50A having a second region 50b protruding in a comb shape having a width of about 1 μm, a length of about 4 μm, and a height from the bottom of the trenches 102a and 102b of about 2 μm is formed. For etching the silicon oxide films 501a and 501b, for example, dry etching using a mixed gas of CF ₄ and CHF ₃ as an etching gas can be applied. In this case, the gas flow rate ratio can be, for example, CF ₄ : CHF ₃ = 1: 10. Further, for example, reactive dry etching using a mixed gas of Cl ₂ , HBr _3, and O ₂ as an etching gas can be applied to the etching of the semiconductor substrate 11. The gas flow rate ratio at this time can be, for example, Cl ₂ : HBr ₃ : O ₂ = 100: 100: 2-4.

  When the trenches 502a and 502b are formed on the side surfaces of the element formation region 50A in this way, as described above, the trench 502a is obtained through the steps described in the fourth embodiment (see FIGS. 30B to 32C). And the isolation insulating film 52a and the isolation insulating film 52b are respectively formed in the semiconductor elements 502b.

  Next, by subjecting the exposed surface of the semiconductor substrate 11 to thermal oxidation, as shown in FIG. 39A, the surface of the semiconductor substrate 11 from which the silicon oxide film 506 having a thickness of, for example, about 20 nm is exposed, that is, element formation is performed. It is formed on the upper surface of the region 50A. This silicon oxide film 506 is a film for reducing damage to the element formation region 50A when impurities are implanted in a later process. In the thermal oxidation when forming the silicon oxide film 506, the heating temperature is set to 850 ° C., for example, and the heating time is set to 30 minutes, for example.

Next, a predetermined resist solution is spin-coated on the entire upper surface of the semiconductor substrate 11, and this is subjected to existing exposure processing and development processing, whereby a part of the upper surface of the first region 50a and the upper surface of the second region 50b in the element formation region 50A. And forming a resist pattern having openings. That is, a resist pattern having an opening in a region where the source region 58 s is formed is formed on the semiconductor substrate 11. Subsequently, an impurity having n-type conductivity, such as phosphorus ions, is implanted into a part of the upper portion of the element formation region 50A through the silicon oxide film 506 from the opening of the resist pattern. At this time, the dose is set to about 1 × 10 ¹⁷ / cm ² , for example, and the acceleration energy is set to about 10 KeV. Subsequently, after removing the resist pattern, a predetermined resist solution is spin-coated again on the entire upper surface of the semiconductor substrate 11, and this is subjected to existing exposure processing and development processing, whereby the first region 50a in the element formation region 50A. A resist pattern having an opening in a region which is a part of the upper portion and which is not adjacent to a region under which the gate electrode 55a is formed in a later step is formed. Subsequently, an impurity having p-type conductivity, such as arsenic ions or boron ions, is implanted into part of the upper portion of the first region 50a through the silicon oxide film 506 from the opening of the resist pattern. At this time, the dose is set to 1 × 10 ¹⁷ / cm ² , for example, and the acceleration energy is set to 10 KeV, for example. Subsequently, after removing the resist pattern, the semiconductor substrate 11 is heated to, for example, about 900 ° C. for about 30 minutes to thermally diffuse the p-type and n-type impurities implanted as described above. As a result, as shown in FIG. 39B, the source region 58s is formed above the element formation region 50A, above the first region 50a (the base portion of the second region 50b) and above the second region 50b. In addition to being formed, a body pulling region 59 is formed in a part of the upper portion of the first region 50a.

Next, a predetermined resist solution is spin-coated on the entire upper surface of the semiconductor substrate 11, and this is subjected to existing exposure processing and development processing, whereby a part of the element formation region 50A on the first region 50a and the second region 50b. A resist pattern R9 having a series of openings is formed on the top, between adjacent second regions 50b, and at the tip. That is, a resist pattern R9 having an opening is formed in a region where the gate insulating films 54a and 54b and the gate electrodes 55a and 55b are to be formed in a later step. Subsequently, the silicon oxide film 506, the element isolation insulating film 52a, and the isolation insulating film 52b are sequentially etched by the existing etching technique using the resist pattern R9 as a mask, as shown in FIG. A part of the upper surface of the first region 50a and the upper surface of the second region in the element formation region 50A are exposed, and a trench 502c that exposes a side surface of the second region 50b is formed. That is, the upper surface of the region where the gate electrode 55a is to be formed in the element formation region 50A (the base portion of the second region 50b and the second region 50b in the first region 50a) is exposed, and the side surface and the tip of the second region 50b are continuously formed. The trench 502c is formed. For etching the silicon oxide film 506, the element isolation insulating film 52a, and the isolation insulating film 52b, for example, dry etching using a mixed gas of CF ₄ and CHF ₃ as an etching gas can be applied. In this case, the gas flow rate ratio can be, for example, CF ₄ : CHF ₃ = 1: 10.

  Next, after removing the resist pattern R9 and further removing the silicon oxide film 506 remaining on the surface of the semiconductor substrate 11, the surface of the semiconductor substrate 11 is thermally oxidized again, as shown in FIG. Gate insulating films 54A and 54B having a film thickness of, for example, about 20 nm are formed on the upper surface of the element formation region 50A and the exposed side surfaces of the surface of the trench 502c, that is, the element formation region 50A. The gate insulating films 54A and 54B are silicon oxide films.

  Next, a predetermined resist solution is spin-coated on the semiconductor substrate 11 including the gate insulating films 54A and 54B, and this is subjected to an existing exposure process and a development process, whereby a part of the first region 50a and A resist pattern R10 is formed on the second region 50b and a part on the trench 502c. That is, a resist pattern R10 is formed to cover the regions where the gate insulating films 54a and 54b are to be formed. Subsequently, the gate insulating films 54A and 54B are patterned by the existing etching technique by patterning the gate insulating films 54A and 54B using the resist pattern R10 as a mask. Thereby, as shown in FIG. 40B, the gate insulating film 54a is formed on a part of the first region 50a and the second region 50b in the element formation region 50A, and the element formation in the trench 502c is performed. A gate insulating film 54b is formed on the side surface on the region 50A side, that is, on the side surface of the second region 50b.

Next, by depositing, for example, about 3 μm of polysilicon containing an n-type conductivity impurity such as phosphorus on the entire upper surface of the semiconductor substrate 11 by, for example, the existing CVD method, the gate insulating film 54a is exposed from the upper surface. A polysilicon film having a thickness of, for example, about 3 μm is formed. At this time, the trench 502c is also filled with polysilicon, thereby forming the gate electrode 55b. Subsequently, a predetermined resist solution is spin-coated on the polysilicon film, and this is subjected to existing exposure processing and development processing, thereby forming a resist pattern R11 on the gate insulating films 54a and 54b. Subsequently, the polysilicon film on the semiconductor substrate 11 is patterned by the existing etching technique using the resist pattern R11 as a mask. As a result, as shown in FIG. 40C, the gate electrode 55a is formed on a part of the first region 50a and the second region 50b in the element formation region 50A, and the gate electrode 55b is formed in the trench 502c. To do. In forming the polysilicon film, for example, a mixed gas of SiH ₄ and PH ₃ is used. The gas flow ratio at this time can be set to SiH ₄ : PH ₃ = 10: 1, for example. The film forming conditions can be set such that the pressure in the chamber is 0.6 Torr and the stage temperature is 620 ° C. In addition, it is preferable to apply conditions for etching the polysilicon film that allow a sufficient selection ratio with the silicon oxide film. Etching that satisfies this condition includes, for example, dry etching using a mixed gas of Cl ₂ , HBr _3, and O ₂ as an etching gas. Incidentally gas flow ratio at this time, for example, _{Cl 2: HBr 3: O 2} = 100: 100: it can be 2-4.

  Thereafter, through the same steps as in the first embodiment (see FIGS. 12C to 13B), the semiconductor device 500 according to the present embodiment as shown in FIGS. 33 to 36 is manufactured.

As described above, the semiconductor device 500 according to the present embodiment includes the first region 50a and the second region 50b including the plurality of second regions 50b protruding from the first region 50a in a comb shape when viewed from above. The semiconductor substrate 11 having the element formation region 50A of one conductivity type (for example, p-type) and the entire side surface of the element formation region 50A are formed, and the side surface of the element formation region 50A and the semiconductor substrate 11 are insulated from each other. Formed on the entire lower surface of the element formation region 50A surrounded by the element isolation insulating film 52a and the isolation insulating film 52b that electrically isolate the side surface of the formation region 50A from the semiconductor substrate 11, and the element isolation insulating film 52a and the isolation insulating film 52b. The second conductivity type (for example, n-type) that electrically separates the lower surface of the element formation region 50A from the semiconductor substrate 11 by bonding and separating the lower surface of the element formation region 50A and the semiconductor substrate 11 ) Of the drain region 58d (impurity buried layer 52c), a part on the first region 50a so as to wrap each of the plurality of second regions 50b from the three side surfaces and the upper surface not continuous with the first region 50a, Gate electrodes 55a and 55b formed in series on the region 50b, between adjacent second regions 50b and at the tip, and a second conductivity formed from a part of the upper portion of the first region 50a to the upper portion of the second region 50b. Type (for example, n-type) source region 18s and the first conductivity type (for example, p-type) formed in a region adjacent to the source region 58s in the upper portion of the first region 50a and other than under the gate electrode 55a. A first conductivity type (for example, p-type) p formed between the body pulling region 59 (also referred to as a high concentration region) and the source region 58s and the drain region 58d in the element formation region 50A. Constructed and a body region 57 (also referred to as the well region).

  In addition, the method of manufacturing the semiconductor device 500 according to the present embodiment includes a first conductivity type (for example, a first region 50a and a plurality of second regions 50b protruding in a comb shape from the first region 50a as viewed from above). A semiconductor substrate 11 having a p-type device formation region 50A is prepared, and trenches 502a and 502b (which are referred to as first trenches) are formed on the entire side surface of the device formation region 50A, which is higher than the device formation region 50A. By implanting and diffusing impurities of the second conductivity type (for example, n-type) into the bottom surfaces of the first trenches 502a and 502b so as to achieve an impurity concentration, the lower surface of the element formation region 50A and the semiconductor substrate 11 are separated by junction. A drain region 58d (impurity buried layer 52c) to be formed is formed under the element formation region 50A, the first trench 502a is filled with the element isolation insulating film 52a, and the first trench is formed. The source region 58s is formed by filling 502b with the isolation insulating film 52b and injecting and diffusing a second conductivity type (for example, n-type) impurity into a part of the upper portion of the first region 50a and the upper portion of the second region 50b. Then, a body pulling region 59 (also referred to as a high concentration region) is formed by injecting and diffusing a first conductivity type (for example, p-type) impurity in a region adjacent to the source region 58s above the first region 50a. Then, a series of trenches 502c (this is referred to as a second trench) is formed between the adjacent second regions 50b and at the tip, and each of the plurality of second regions 50b is not connected to the first region 50a on the three side surfaces and A series of gate electrodes 55a and 55b are formed in a part on the first region 50a, on the second region 50b, and in the second trench 502c so as to wrap from the upper surface.

  Thus, by forming the insulating element isolation insulating film 52a and the isolation insulating film 52b between the side surface of the element forming area 50A, which is a partial area in the semiconductor substrate 11, and the semiconductor substrate 11, the element forming area The 50A side surface can be insulated and separated from the semiconductor substrate 11. Further, by forming a drain region 58d (impurity buried layer 52c) having a conductivity type (eg, n-type) opposite to the conductivity type (eg, p-type) of the element formation region 50A on the entire bottom surface of the element formation region 50A, element formation is performed. The entire bottom surface of the region 50 </ b> A can be bonded and separated from the semiconductor substrate 11. Therefore, according to the present embodiment, the element formation region 50A can be electrically isolated from the semiconductor substrate 11 by the element isolation insulating film 52a, the isolation insulating film 52b, and the drain region 58d (impurity buried layer 52c). As described above, the element formation region 50A is electrically separated from the semiconductor substrate 11 by using the impurity buried layer 52c including the drain region 58d, so that the element formation region 50A is similar to the semiconductor device manufactured using the SOI substrate. The semiconductor element formed in the formation region 50A can have a structure that does not require electrical interference. Thereby, it is possible to reduce leakage current and electrical interference between semiconductor elements. Further, not only in the upper surface of the second region 50b protruding like a comb tooth in the element formation region 50A, but also between the second regions 50b protruding like a comb tooth and in the trench 502c formed earlier, that is, in a comb tooth shape. By forming the gate electrode 55b also on the side surface of the protruding second region 50b, when a predetermined bias voltage is applied to the gate electrodes 55a and 55b, the side portion is driven in addition to the upper portion of the element formation region 50A. It becomes possible to comprise. As a result, the drive region can be enlarged regardless of the chip mounting area, and as a result, the element formation region 50A can be reduced and the drive capability can be improved. Furthermore, in the present embodiment, for example, a bulk substrate or the like can be used as the semiconductor substrate 11, so that the gate length direction of the element formation region 50A is not limited to the thickness of the silicon thin film in the SOI substrate, for example. It is possible to set the width in the vertical direction (depth direction) of the gate electrode 55b formed on the parallel side surfaces. Furthermore, in this embodiment, the impurity buried layer 52c for electrically isolating the lower surface of the element formation region 50A from the semiconductor substrate is used as the drain region 58d, and the source region 58s is formed above the element formation region 50A. Therefore, the semiconductor device 500 in which the channel is formed in the vertical direction can be realized.

  In this embodiment, since the impurity buried layer 52c (including the drain region 58d) is formed in the trenches 502a and 502b, the gate length of the semiconductor element can be determined by the depth of the trenches 502a and 502b. Further, in this embodiment, by reducing the height of the element formation region 50A from the bottom surfaces of the trenches 502a and 502b, the amount of current of the semiconductor element formed thereon can be increased. As a result, the driving force per unit area can be improved.

  In addition, the said Example 1- Example 5 is only an example for implementing this invention, this invention is not limited to these, Various deformation | transformation of these Examples is in the range of this invention. It is obvious from the above description that various other embodiments are possible within the scope of the present invention.

It is a top view which shows schematic structure of the semiconductor device 100 by Example 1 of this invention. It is A-A 'sectional drawing in FIG. It is B-B 'sectional drawing in FIG. It is C-C 'sectional drawing in FIG. It is a process diagram which shows the manufacturing method of the semiconductor device 100 by Example 1 of this invention (1). It is a process diagram which shows the manufacturing method of the semiconductor device 100 by Example 1 of this invention (2). It is a process diagram which shows the manufacturing method of the semiconductor device 100 by Example 1 of this invention (3). It is a process diagram which shows the manufacturing method of the semiconductor device 100 by Example 1 of this invention (4). It is a process diagram which shows the manufacturing method of the semiconductor device 100 by Example 1 of this invention (5). It is a process diagram which shows the manufacturing method of the semiconductor device 100 by Example 1 of this invention (6). It is a process diagram which shows the manufacturing method of the semiconductor device 100 by Example 1 of this invention (7). It is a process diagram which shows the manufacturing method of the semiconductor device 100 by Example 1 of this invention (8). It is a process diagram which shows the manufacturing method of the semiconductor device 100 by Example 1 of this invention (9). It is a top view which shows schematic structure of the semiconductor device 200 by Example 2 of this invention. It is D-D 'sectional drawing in FIG. It is a process diagram which shows the manufacturing method of the semiconductor device 200 by Example 2 of this invention (1). It is a process diagram which shows the manufacturing method of the semiconductor device 200 by Example 2 of this invention (2). It is a top view which shows schematic structure of the semiconductor device 300 by Example 3 of this invention. It is a process diagram which shows the manufacturing method of the semiconductor device 300 by Example 3 of this invention (1). It is a process diagram which shows the manufacturing method of the semiconductor device 300 by Example 3 of this invention (2). It is a process diagram which shows the manufacturing method of the semiconductor device 300 by Example 3 of this invention (3). It is a process diagram which shows the manufacturing method of the semiconductor device 300 by Example 3 of this invention (4). It is a process diagram which shows the manufacturing method of the semiconductor device 300 by Example 3 of this invention (5). It is a process diagram which shows the manufacturing method of the semiconductor device 300 by Example 3 of this invention (6). It is a top view which shows schematic structure of the semiconductor device 400 by Example 4 of this invention. It is E-E 'sectional drawing in FIG. It is F-F 'sectional drawing in FIG. It is G-G 'sectional drawing in FIG. It is a process figure which shows the manufacturing method of the semiconductor device 400 by Example 4 of this invention (1). It is a process diagram which shows the manufacturing method of the semiconductor device 400 by Example 4 of this invention (2). It is a process diagram which shows the manufacturing method of the semiconductor device 400 by Example 4 of this invention (3). It is a process diagram which shows the manufacturing method of the semiconductor device 400 by Example 4 of this invention (4). It is a top view which shows schematic structure of the semiconductor device 500 by Example 5 of this invention. It is H-H 'sectional drawing in FIG. It is J-J 'sectional drawing in FIG. It is K-K 'sectional drawing in FIG. It is a process diagram which shows the manufacturing method of the semiconductor device 500 by Example 5 of this invention (1). It is a process diagram which shows the manufacturing method of the semiconductor device 500 by Example 5 of this invention (2). It is process drawing which shows the manufacturing method of the semiconductor device 500 by Example 5 of this invention (3). It is a process diagram which shows the manufacturing method of the semiconductor device 500 by Example 5 of this invention (4).

Explanation of symbols

100, 200, 300, 400, 500 Semiconductor device 10A Element formation region 10a Island-like region 10B, 20B, 30B Partial SOI structure 10-1, 50a First region 10-2, 50b Second region 10-3 Third region 11 Semiconductor substrate 12a, 32a, 32b, 52a Element isolation insulating film 12b, 52b Isolation insulating film 12c, 22c, 32c Embedded insulating film 12B, 12C, 22C, 32A, 32B Silicon oxide film 14A, 14a, 14b, 54A, 54B, 54a , 54b Gate insulating film 15A Polysilicon film 15a, 15b, 55a, 55b Gate electrode 15c, 18a Silicide film 17 P-type body region 17w, 57 n well region 18d, 58d Drain region 18s, 58s Source region 19, 59 Body pulling region 21 Interlayer insulation film 22 62 In-contact wiring 23, 24 Metal wiring 40B, 50B Junction isolation structure 42A, 42B Diffusion region 42c Impedance buried layer 101a, 103, 103a, 104a, 106, 401a, 401b, 404a, 404B, 405, 501a, 501b, 506 Silicon Oxide film 101b, 104B Silicon nitride film 102a, 102b, 102c, 302a, 302b, 502a, 502b, 502c Trench 103b Glass oxide film 104b, 404b Side wall 105, 205, 305 Cavity R1, R2, R3, R4, R5, R6 , R7, R8, R9, R10, R11 resist pattern

Claims (12)

A semiconductor comprising a first well region of a first conductivity type including a plurality of island-like regions having first to third regions arranged in a first direction and arranged in order in a second direction perpendicular to the first direction. A substrate,
A first insulating film formed on the entire side surface and lower surface of the first well region, and electrically isolates the first well region from the semiconductor substrate by insulating between the first well region and the semiconductor substrate. When,
A second layer is formed between the adjacent island regions, and electrically separates the first well region into the plurality of island regions arranged in the first direction by insulating between the adjacent island regions. An insulating film;
In a trench formed in the second insulating film located between the first conductor film formed on the second region of the island-shaped region and the second region facing each other in the adjacent island-shaped region. A series of gate electrodes formed so as to straddle the plurality of island-like regions along the first direction by including a second conductor film that is electrically continuous with the first conductor film. When,
A second well region of a second conductivity type formed from the upper part of the first region in the island-like region to the upper part of the second region so that a part thereof extends to a part under the gate electrode;
A source region of a first conductivity type formed above the second well region so that a part of the upper surface of the second well region remains below the gate electrode and a part extends below the gate electrode; ,
A first high concentration region of a second conductivity type formed in a part of the upper portion of the second well region and adjacent to the source region;
A drain region of a first conductivity type formed in a region that is a part of the upper portion of the third region in the island region and is not adjacent to the region under the gate electrode;
A first wiring electrically connected to the plurality of drain regions formed in each of the plurality of island-shaped regions;
A semiconductor device comprising: a plurality of the source regions formed in each of the plurality of island-like regions; and a second wiring electrically connected to the first high concentration region. A semiconductor comprising a first well region of a first conductivity type including a plurality of island-like regions having first to third regions arranged in a first direction and arranged in order in a second direction perpendicular to the first direction. A substrate,
A first insulating film formed on the entire side surface of the first well region and electrically isolating the side surface of the first well region from the semiconductor substrate by insulating between the side surface of the first well region and the semiconductor substrate. When,
The lower surface of the first well region is formed over the entire lower surface of the first well region surrounded by the first insulating film, and the lower surface of the first well region is bonded to and separated from the semiconductor substrate. A first high concentration region of a second conductivity type that is electrically separated from the first conductivity region;
A second layer is formed between the adjacent island regions, and electrically separates the first well region into the plurality of island regions arranged in the first direction by insulating between the adjacent island regions. An insulating film;
In a trench formed in the second insulating film located between the first conductor film formed on the second region of the island-shaped region and the second region facing each other in the adjacent island-shaped region. A series of gate electrodes formed so as to straddle the plurality of island-like regions along the first direction by including a second conductor film that is electrically continuous with the first conductor film. When,
A second well region of a second conductivity type formed from the upper part of the first region in the island-like region to the upper part of the second region so that a part thereof extends to a part under the gate electrode;
A source region of a first conductivity type formed above the second well region so that a part of the upper surface of the second well region remains below the gate electrode and a part extends below the gate electrode; ,
A second conductivity type second high-concentration region formed in a part of the upper portion of the second well region and adjacent to the source region;
A drain region of a first conductivity type formed in a region that is a part of the upper portion of the third region in the island region and is not adjacent to the region under the gate electrode;
A first wiring electrically connected to the plurality of drain regions formed in each of the plurality of island-shaped regions;
A semiconductor device comprising: a plurality of source regions formed in each of the plurality of island-like regions; and a second wiring electrically connected to the second high concentration region.   The gate electrode is formed in a trench formed in the first insulating film located on a side surface of the second region in the island region, and is a third conductor that is electrically continuous with the first conductor film. The semiconductor device according to claim 1, further comprising a film. A semiconductor substrate including a first conductivity type element formation region including a first region and a plurality of second regions protruding in a comb-like shape from the first region when viewed from above;
An insulating film that is formed on the entire side surface of the element formation region and electrically isolates the element formation region side surface from the semiconductor substrate by insulating between the element formation region side surface and the semiconductor substrate;
It is formed on the entire lower surface of the element formation region surrounded by the insulating film, and the lower surface of the element formation region is electrically separated from the semiconductor substrate by bonding and separating the lower surface of the element formation region and the semiconductor substrate. A drain region of a second conductivity type that
A portion on the first region, on the second region, and between the adjacent second regions so as to wrap each of the plurality of second regions from three side surfaces and an upper surface that are not continuous with the first region. And a gate electrode formed in series at the tip, and
A source region of a second conductivity type formed from a part of the upper portion of the first region to the upper portion of the second region;
A high-concentration region of a first conductivity type formed in a region adjacent to the source region in the upper portion of the first region and other than under the gate electrode;
A semiconductor device comprising: a well region of a first conductivity type formed between the source region and the drain region in the element formation region. Preparing a semiconductor substrate including a first well region of a first conductivity type;
Forming a first trench on the entire side surface of the first well region;
Forming a second trench that divides the first well region into a plurality of island regions having first to third regions arranged in a first direction and arranged in order in a second direction perpendicular to the first direction. And a process of
By thermally oxidizing the bottoms of the first and second trenches, a first insulating film that insulates between the entire bottom surface of each of the plurality of island-shaped regions and the semiconductor substrate is formed on the bottom surface of each of the plurality of island-shaped regions. Forming the entire process,
Filling the first trench with a second insulating film and filling the second trench with a third insulating film;
Forming a third trench in the third insulating film located between the second regions facing each other in the adjacent island-shaped regions;
A series of first gates straddling the plurality of island regions along the first direction by forming a series of conductor films on the second region and in the third trench in the plurality of island regions. Forming an electrode;
By injecting and diffusing impurities of the second conductivity type from the upper surface of the first region in the island region, a second well region extending from the upper portion of the first region to a portion under the first gate electrode is formed. Forming, and
By implanting and diffusing impurities of the first conductivity type from the upper surface of the first region in the island-shaped region, a part of the upper surface of the second well region under the first gate electrode is left, and a part thereof Forming a source region extending under the first gate electrode on the second well region;
By implanting and diffusing impurities of the first conductivity type from the upper surface of the third region in the island-shaped region, a part of the island-shaped region above the third region and under the first gate electrode Forming a drain region in a region not adjacent to
By implanting and diffusing impurities of the second conductivity type from the upper surface of the first region in the island region, the region adjacent to the source region above the second well region and other than under the first gate electrode Forming a first high concentration region in the region;
Forming a first wiring electrically connected to the plurality of drain regions formed in each of the plurality of island-shaped regions;
Forming a plurality of the source regions formed in each of the plurality of island-like regions and a second wiring electrically connected to the first high concentration region. Preparing a semiconductor substrate having a first well region of a first conductivity type;
Forming a first trench on the entire side surface of the first well region;
Forming a second trench that divides the first well region into a plurality of island regions having first to third regions arranged in a first direction and arranged in order in a second direction perpendicular to the first direction. And a process of
Etching the bottom of the first and second trenches to widen the bottom of the first and second trenches;
A first insulating film that insulates between the entire bottom surface of each of the plurality of island-shaped regions and the semiconductor substrate by thermally oxidizing the bottom of the expanded first and second trenches is provided for each of the plurality of island-shaped regions. Forming on the entire lower surface of
Filling the first trench with a second insulating film and filling the second trench with a third insulating film;
Forming a third trench in the third insulating film located between the second regions facing each other in the adjacent island-shaped regions;
A series of first gates straddling the plurality of island regions along the first direction by forming a series of conductor films on the second region and in the third trench in the plurality of island regions. Forming an electrode;
By injecting and diffusing impurities of the second conductivity type from the upper surface of the first region in the island region, a second well region extending from the upper portion of the first region to a portion under the first gate electrode is formed. Forming, and
By implanting and diffusing impurities of the first conductivity type from the upper surface of the first region in the island-shaped region, a part of the upper surface of the second well region under the first gate electrode is left, and a part thereof Forming a source region extending under the first gate electrode on the second well region;
By implanting and diffusing impurities of the first conductivity type from the upper surface of the third region in the island-shaped region, a part of the island-shaped region above the third region and under the first gate electrode Forming a drain region in a region not adjacent to
By implanting and diffusing impurities of the second conductivity type from the upper surface of the first region in the island region, the region adjacent to the source region above the second well region and other than under the first gate electrode Forming a first high concentration region in the region;
Forming a first wiring electrically connected to the plurality of drain regions formed in each of the plurality of island-shaped regions;
Forming a plurality of the source regions formed in each of the plurality of island-like regions and a second wiring electrically connected to the first high concentration region. Forming a fourth trench in the second insulating film located on a side surface of the second region in the island region;
The method of manufacturing a semiconductor device according to claim 5, further comprising: forming a second gate electrode continuous with the first gate electrode in the fourth trench. Preparing a semiconductor substrate having a first well region of a first conductivity type;
Forming a first trench on a side surface perpendicular to the first direction in the first well region;
A second trench that divides the first well region into a plurality of island-shaped regions having first to third regions arranged in the first direction and sequentially arranged in a second direction perpendicular to the first direction; Forming, and
Etching the lower portions of the first and second trenches to form voids under each of the plurality of island regions;
Filling at least part of the gap with a first insulating film, filling the first trench with a second insulating film and filling the second trench with a third insulating film;
Forming a third trench on a side surface parallel to the first direction in the first well region;
Filling the third trench with a fourth insulating film;
Forming a fourth trench in the third insulating film located between the second regions facing each other in the adjacent island-shaped regions;
A series of first gates straddling the plurality of island-like regions along the first direction by forming a series of conductor films on the second region and in the fourth trench in the plurality of island-like regions. Forming an electrode;
By injecting and diffusing impurities of the second conductivity type from the upper surface of the first region in the island region, a second well region extending from the upper portion of the first region to a portion under the first gate electrode is formed. Forming, and
By implanting and diffusing impurities of the first conductivity type from the upper surface of the first region in the island-shaped region, a part of the upper surface of the second well region under the first gate electrode is left, and a part thereof Forming a source region extending under the first gate electrode on the second well region;
By implanting and diffusing impurities of the first conductivity type from the upper surface of the third region in the island-shaped region, a part of the island-shaped region above the third region and under the first gate electrode Forming a drain region in a region not adjacent to
By implanting and diffusing impurities of the second conductivity type from the upper surface of the first region in the island region, the region adjacent to the source region above the second well region and other than under the first gate electrode Forming a first high concentration region in the region;
Forming a first wiring electrically connected to the plurality of drain regions formed in each of the plurality of island-shaped regions;
Forming a plurality of the source regions formed in each of the plurality of island-like regions and a second wiring electrically connected to the first high concentration region. Forming a fifth trench in the second insulating film located on a side surface of the second region in the island region;
The method for manufacturing a semiconductor device according to claim 8, further comprising: forming a second gate electrode continuous with the first gate electrode in the fifth trench. Preparing a semiconductor substrate having a first well region of a first conductivity type;
Forming a first trench on the entire side surface of the first well region;
Forming a second trench that divides the first well region into a plurality of island regions having first to third regions arranged in a first direction and arranged in order in a second direction;
By implanting and diffusing impurities of the second conductivity type into the bottom surfaces of the first and second trenches so that the impurity concentration is higher than that of the first well region, the entire lower surface of each of the plurality of island-like regions and the Forming a first high-concentration region that separates the semiconductor substrate from the lower surface of each of the plurality of island-shaped regions;
Filling the first trench with a first insulating film and filling the second trench with a second insulating film;
Forming a third trench in the second insulating film located between the second regions facing each other in the adjacent island-shaped regions;
A series of first gates straddling the plurality of island regions along the first direction by forming a series of conductor films on the second region and in the third trench in the plurality of island regions. Forming an electrode;
By injecting and diffusing impurities of the second conductivity type from the upper surface of the first region in the island region, a second well region extending from the upper portion of the first region to a portion under the first gate electrode is formed. Forming, and
By implanting and diffusing impurities of the first conductivity type from the upper surface of the first region in the island-shaped region, a part of the upper surface of the second well region under the first gate electrode is left, and a part thereof Forming a source region extending under the first gate electrode on the second well region;
By implanting and diffusing impurities of the first conductivity type from the upper surface of the third region in the island-shaped region, a part of the island-shaped region above the third region and under the first gate electrode Forming a drain region in a region not adjacent to
By implanting and diffusing impurities of the second conductivity type from the upper surface of the first region in the island region, the region adjacent to the source region above the second well region and other than under the first gate electrode Forming a second high concentration region in the region;
Forming a first wiring electrically connected to the plurality of drain regions formed in each of the plurality of island-shaped regions;
Forming a plurality of the source regions formed in each of the plurality of island-like regions and the second wiring electrically connected to the second high-concentration region. Forming a fourth trench in the first insulating film located on a side surface of the second region in the island region;
The method of manufacturing a semiconductor device according to claim 10, further comprising: forming a second gate electrode continuous with the first gate electrode in the fourth trench. Preparing a semiconductor substrate having a first conductivity type element formation region including a first region and a plurality of second regions protruding in a comb-like shape from the first region when viewed from above;
Forming a first trench on the entire side surface of the element formation region;
By implanting and diffusing impurities of the second conductivity type into the bottom surface of the first trench so that the impurity concentration is higher than that of the element formation region, the lower surface of the element formation region and the semiconductor substrate are joined and separated. Forming a drain region to be entirely under the element formation region;
Filling the first trench with an insulating film;
Forming a source region by implanting and diffusing a first conductivity type impurity in a part of the upper portion of the first region and the upper portion of the second region;
Forming a high concentration region by injecting and diffusing impurities of a second conductivity type in a region adjacent to the source region above the first region;
Forming a series of second trenches between adjacent second regions and at the tip;
A series of gates on a part of the first region, on the second region, and in the second trench so as to wrap each of the plurality of second regions from three side surfaces and an upper surface that are not continuous with the first region. A method of manufacturing a semiconductor device, comprising: forming an electrode.

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