JP6637139B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a concave portion and a method for manufacturing the same.

  A deep groove for taking out a potential on the other (lower) main surface side of the pair of main surfaces on one (upper) main surface side of the pair of main surfaces facing each other of the semiconductor substrate. (Recess) may be formed. Such a deep recess for extracting the potential of the semiconductor substrate is sometimes called a substrate electrode or a substrate contact. The above substrate electrode is disclosed in, for example, Patent Document 1, Patent Document 2, Patent Document 3, Patent Document 4, and Patent Document 5 below.

  Further, in order to electrically separate elements formed on the semiconductor substrate from other regions on the semiconductor substrate, a deep recess is formed in one (upper) main surface of the pair of main surfaces of the semiconductor substrate. A technique for forming a device isolation recess is disclosed in, for example, Patent Document 6 below.

JP 2008-130829 A JP 2008-511981 A JP-A-5-29603 JP-A-62-213121 JP 2003-218356 A JP-A-11-45890

  In many cases, a long heat treatment is required to form a deep concave portion as described in each of the above-mentioned patent documents, and the production cost may increase.

  In forming a semiconductor device, in addition to the step of forming the deep recess, for example, on the one main surface side of the semiconductor substrate, a shallower than the deep recess for extracting an electrode from a semiconductor element is usually provided. In some cases, a step of forming a concave portion is required. In each of the above patent documents, the step of forming a deep recess and the step of forming a shallow recess are processed as separate steps. In this case, the process becomes complicated, and the number of masks required for forming the concave portion increases, which may increase the manufacturing cost.

  Other problems and novel features will be apparent from the description of this specification and the accompanying drawings.

A method for manufacturing a semiconductor device according to one embodiment includes the following steps.
First, an element having a conductive portion located on a main surface of a semiconductor substrate is formed. A first recess extending from the main surface to the inside of the semiconductor substrate is formed. An insulating film is formed on the main surface and on the side wall and the bottom wall of the first concave portion so as to cover the element and form a closed hollow in the first concave portion. The insulating film is formed so as to reach the hollow inside the first recess from the upper surface of the insulating film and reach the semiconductor substrate at the bottom wall of the first recess while leaving the insulating film on the side wall of the first recess. One hole is formed. A second hole reaching the conductive portion from the upper surface of the insulating film is formed. The first and second holes are formed by the same etching process.

A semiconductor device according to another embodiment has the following configuration.
The semiconductor device includes a semiconductor substrate, a first insulating film, and a first conductive layer. The semiconductor substrate has a first concave portion formed on the main surface, and has a semiconductor element formed on the main surface. The first insulating film includes a region on the sidewall in the first recess and a region extending along the main surface outside the first recess, and is formed in the region on the sidewall in the first recess. A first hole is formed in one recess, and a second hole is formed in a region extending along the main surface. The first conductive layer is formed inside the first hole and the second hole. The second hole communicates with the first hole. The first conductive layer is in direct contact with the semiconductor substrate at the bottom of the first hole. In a region extending along the main surface of the first insulating film, a contact hole reaching the semiconductor element is formed. A second conductive layer is formed inside the contact hole. The first conductive layer and the second conductive layer are formed of the same material.
The semiconductor device includes: a semiconductor substrate having a first concave portion; an element having a conductive region; and a semiconductor substrate formed on a main surface so as to cover the element, and a first bottom wall of the first concave portion. And an insulating film formed to be exposed. A first hole reaching the bottom wall of the first recess from the upper surface of the insulating film through the first recess is formed, and a second hole reaching the conductive region from the upper surface of the insulating film is formed. I have. A first conductive layer formed in the first hole; and a second conductive layer formed in the second hole. The first conductive layer and the second conductive layer are made of the same material.

  According to the semiconductor device and the method for manufacturing the same according to one or another embodiment, a semiconductor device having a first concave portion can be provided with a reduced number of steps, processing time, and manufacturing cost.

FIG. 2 is a schematic plan view showing a configuration of a semiconductor device in a chip state according to the first embodiment; FIG. 2 is a partially cutaway perspective view showing a state where the element formation region shown in FIG. 1 is surrounded by a concave portion in plan view. FIG. 3 is a schematic cross-sectional view showing a configuration of the semiconductor device in a chip state according to the first embodiment, taken along a line III-III in FIG. 1. FIG. 4 is a schematic sectional view showing in detail an aspect of an element and the like formed in each region of FIG. 3. FIG. 5 is a schematic cross-sectional view showing a first step of the method for manufacturing a semiconductor device in First Embodiment. FIG. 5 is a schematic cross-sectional view showing a second step of the method for manufacturing a semiconductor device in First Embodiment. FIG. 5 is a schematic cross-sectional view showing a third step of the method for manufacturing a semiconductor device in First Embodiment. FIG. 5 is a schematic cross-sectional view showing a fourth step of the method for manufacturing a semiconductor device in First Embodiment. FIG. 5 is a schematic cross-sectional view showing a fifth step of the method for manufacturing a semiconductor device in First Embodiment. FIG. 7 is a schematic sectional view showing a sixth step of the method for manufacturing a semiconductor device in First Embodiment; FIG. 13 is a schematic cross-sectional view showing a seventh step of the method for manufacturing a semiconductor device in First Embodiment. FIG. 9 is a schematic sectional view showing an eighth step of the method for manufacturing a semiconductor device in First Embodiment; FIG. 15 is a schematic sectional view showing a ninth step of the method for manufacturing a semiconductor device in First Embodiment; FIG. 11 is a schematic sectional view showing a tenth step of the method for manufacturing a semiconductor device in First Embodiment; FIG. 13 is a schematic cross-sectional view showing an eleventh step of the method for manufacturing a semiconductor device in First Embodiment. FIG. 12 is a schematic sectional view showing a twelfth step of the method for manufacturing a semiconductor device in First Embodiment; FIG. 3 is a schematic cross-sectional view showing a configuration of a semiconductor device in a chip state in a comparative example of the first embodiment, taken along a line III-III in FIG. 1. FIG. 3A is a schematic perspective view illustrating the configuration and size of a substrate contact according to the first embodiment, and FIG. 3B is a schematic perspective view illustrating the configuration and size of a substrate contact according to a comparative example. FIG. 3 is a schematic cross-sectional view illustrating a configuration of a semiconductor device in a chip state according to a second embodiment, which is similar to a portion along line III-III in FIG. 1. FIG. 3 is a schematic cross-sectional view showing a configuration of a semiconductor device in a chip state according to a comparative example of the second embodiment, taken along a line III-III in FIG. 1. FIG. 13 is a schematic cross-sectional view showing a configuration of a semiconductor device in a chip state according to a third embodiment, which is similar to a portion along the line III-III in FIG. 1. FIG. 13 is a schematic cross-sectional view illustrating a configuration of a semiconductor device in a chip state according to a comparative example of the third embodiment, taken along a line similar to the line III-III in FIG. 1. FIG. 18 is a schematic plan view showing a configuration of a semiconductor device in a chip state according to a fourth embodiment. FIG. 24 is a schematic sectional view showing a configuration of a semiconductor device in a chip state according to a fourth embodiment, taken along a line XXIV-XXIV of FIG. 23; FIG. 25 is a schematic cross-sectional view showing in detail an aspect of an element and the like formed in each region of FIG. 24.

Hereinafter, an embodiment will be described with reference to the drawings.
(Embodiment 1)
First, the arrangement of each element formation region on the main surface of the semiconductor substrate of the semiconductor device of the present embodiment will be described with reference to FIGS.

  Referring to FIG. 1, the semiconductor device of the present embodiment has a CMOS transistor region in which, for example, a low-breakdown-voltage CMOS (Complementary MOS) transistor is integrated on the main surface of semiconductor substrate SUB included in semiconductor chip CHP. It has a logic section LG and an output driver section HV as a high breakdown voltage MOS transistor region using a high breakdown voltage element. In the above-described semiconductor device, for example, one logic unit LG and three output driver units HV are arranged so as to form a matrix in a plan view.

  A substrate electrode region is arranged outside a region where the logic unit LG and the output driver unit HV are arranged (for example, a region relatively close to the outer edge of the semiconductor chip CHP), and a substrate contact SCN is formed in the substrate electrode region. . However, the position where the substrate contact SCN is formed is not limited to the outer edge side of the semiconductor chip CHP, but may be any position. For example, the substrate contact SCN may be formed at the center of the semiconductor chip CHP.

  Referring to FIGS. 1 and 2, an element formation region DFR as a logic portion LG or an output driver portion HV has a so-called DTI (Deep Trench Isolation) structure having an insulating film in a recess having a high aspect ratio. It is surrounded by the DTR in plan view. The element isolation region DTR is formed on the main surface of the semiconductor substrate SUB.

Next, a cross-sectional configuration of the semiconductor device will be described with reference to FIG.
Referring to FIG. 3, semiconductor substrate SUB has a configuration in which, for example, p-type impurity region PSB, p-type epitaxial layer PE1, n-type buried layer NBL, and p-type epitaxial layer PE2 are stacked in this order. ing.

The p-type impurity region PSR is a substrate region having a relatively high p-type (first conductivity type) impurity concentration (as a p ⁺ region), and is farthest from a main surface of the semiconductor substrate SUB where a CMOS transistor or the like is formed. (The lowermost region of the semiconductor substrate SUB in FIG. 3).

The n-type buried layer NBL (buried region) is formed in the semiconductor substrate SUB so as to be located closer to the main surface on which the CMOS transistor and the like are formed (upper side in FIG. 3) than the p-type impurity region PSB. Further, the n-type impurity region has a medium n-type (second conductivity type) impurity concentration. The p-type epitaxial layers PE1 and PE2 are p ⁻ regions having a relatively low p-type impurity concentration.

  Each of these layers constituting the semiconductor substrate SUB is formed as a semiconductor region containing n-type or p-type conductive impurities. The above-described regions (p-type impurity region PSB, p-type epitaxial layer PE1, n-type buried layer NBL, and p-type epitaxial layer PE2) are formed over the entire surface of semiconductor substrate SUB in plan view. However, the entire surface here means the entire region of the semiconductor substrate SUB in plan view excluding the region where the element isolation region DTR and the substrate contact SCN are formed.

  Both an n-type transistor and a p-type transistor may be formed in the CMOS transistor region as the logic portion LG and the high breakdown voltage MOS transistor region as the output driver portion HV. Therefore, as shown in FIG. 3, a high-breakdown-voltage n-type well region HNW may be formed in a region where the p-type epitaxial layer PE2 is formed, or, for example, a p-not-shown p-type well may be used instead of the high-breakdown-voltage n-type well region HNW. A mold well region may be formed. Alternatively, both the n-type well region and the p-type well region may be formed.

  The element isolation region DTR surrounding the CMOS transistor region as the logic portion LG and the high breakdown voltage MOS transistor region as the output driver portion HV has a configuration in which the insulating film II1 and the hollow AG are formed inside the concave portion TI. . Specifically, the semiconductor substrate SUB extends from the main surface (the main surface of the p-type epitaxial layer PE2 opposite to the main surface in contact with the n-type buried layer NBL) into the inside of the semiconductor substrate SUB, and the main surface of the semiconductor substrate SUB. Is formed so as to extend in a direction perpendicular to the vertical direction (the direction in which the epitaxial layers PE1 and the like are stacked). An insulating film II1 is formed on the side wall and the bottom wall of the concave portion TI, and a hollow AG as a void (bubble) in which the insulating film II1 is not disposed is formed in a region surrounded by the insulating film II1 in the concave portion TI. .

  The substrate contact SCN in the substrate electrode region has a configuration in which the insulating film II1 and the substrate contact conductive layer CDL are formed inside the concave portion TI. Specifically, the insulating film II1 is formed on the side wall of the concave portion TI, and a region surrounded by the insulating film II1 in the concave portion TI is filled with the substrate contact conductive layer CDL. Substrate contact conductive layer CDL extends along the direction in which concave portion TI extends, and is formed to reach the bottom wall of concave portion TI.

  The insulating film II1 is an interlayer covering a region other than the region where the element isolation region DTR, the substrate contact SCN and the plug conductive layer PL1 (in the CMOS transistor region or the like) are formed on the main surface of the semiconductor substrate SUB (p-type epitaxial layer PE2). It is formed so as to cover the upper surface of the insulating film II. The insulating film II1 is formed so as to extend from the region on the upper surface of the interlayer insulating film II to the inside of the concave portion TI. Here, the inside of the concave portion TI means on the side wall and the bottom wall of the concave portion TI forming the element isolation region DTR, and on the side wall of the concave portion TI forming the substrate contact SCN.

  The element isolation region DTR and the concave portion TI of the substrate contact SCN are formed by forming the p-type epitaxial layer PE2, the n-type buried layer NBL and the p-type epitaxial layer PE1 from one main surface of the p-type epitaxial layer PE2 inside the semiconductor substrate SUB. It is formed so as to penetrate into p-type impurity region PSB. However, the concave portion TI is not limited to such an embodiment. For example, the concave portion TI may penetrate through the p-type epitaxial layer PE2, the n-type buried layer NBL and the p-type epitaxial layer PE1 to the lowermost portion of the p-type epitaxial layer PE1 (of the p-type impurity region PSB). It may be a mode that extends (so as not to enter the inside). However, it is preferable that the concave portion TI is formed so as to penetrate the n-type buried layer NBL and reach the p-type impurity region PSB.

  As described later, a wiring layer ICL1 is formed so as to cover the substrate contact conductive layer CDL of the substrate contact SCN and the plug conductive layer PL1, and to be electrically connected to these.

  Next, the configurations of the CMOS transistor region and the high-voltage MOS transistor region of FIG. 3 will be described in more detail with reference to FIG.

  Referring to FIG. 4, a semiconductor substrate SUB included in a semiconductor chip CHP includes a p-type impurity region PSB (as described above), a p-type epitaxial layer PE1, an n-type buried layer NBL, and a p-type epitaxial layer PE2. These are all semiconductor regions containing conductive impurities. That is, the semiconductor substrate SUB includes only a semiconductor region.

  Here, the expression that the semiconductor substrate SUB is composed of only a semiconductor region means that it is a bulk semiconductor substrate, and does not include a substrate such as an SOI (Silicon on Insulator) substrate with an insulating film interposed therebetween. However, an insulating film for element isolation such as LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation) may be formed on the “semiconductor substrate”.

  Therefore, the concave portion TI such as the element isolation region DTR is formed without penetrating the insulating region. However, as described later, the semiconductor substrate SUB may further include a p-type buried layer.

  For example, a CMOS transistor is formed in the CMOS transistor region, and this CMOS transistor has a configuration in which an NMOS transistor on the left side of FIG. 4 and a PMOS transistor on the right side are combined. That is, the CMOS transistor region has an NMOS region in which an NMOS transistor is formed and a PMOS region in which a PMOS transistor is formed. An NMOS transistor is formed in the NMOS region, and a PMOS transistor is formed in the PMOS region. I have. Note that among the CMOS transistors used as logic circuits, NMOS transistors and PMOS transistors used as input / output circuits (I / O circuits) electrically connected to other semiconductor devices are shown as examples. I have.

The NMOS transistor includes a p-type well region PWR formed in the p-type epitaxial layer PE2, an n ⁺ region NR (conductive region) as a source or drain region, a gate insulating film GI, a gate electrode layer GE, and a sidewall insulating layer. And a film SW. The PMOS transistor includes an n-type well region NWR formed in a p-type epitaxial layer PE2, ap ⁺ region PR (conductive region) as a source region or a drain region, a gate insulating film GI, a gate electrode layer GE, and sidewall insulation. And a film SW.

In the high withstand voltage MOS transistor region, a high withstand voltage MOS transistor that can withstand use under a high voltage is formed. This high voltage MOS transistor includes an n-type well region NWR, an n-type offset region NOR, a p-type well region PWR, an n ⁺ region NR and a p ⁺ region PR (conductive region) as a source or drain region, It mainly has a gate insulating film GI, a gate electrode layer GE, and a sidewall insulating film SW. As described above, an element such as an NMOS transistor is formed so as to have a conductive region on the main surface of the semiconductor substrate SUB.

Although the p-type well region PWR and the n-type well region NWR constituting the CMOS transistor and the high-voltage MOS transistor are formed in the p-type epitaxial layer PE2 in FIG. 4, the high-voltage n-type well region shown in FIG. It may be formed in the HNW. In the present embodiment, it is preferable that cobalt silicide layer SC is formed on each surface of n ⁺ region NR, p ⁺ region PR, and gate electrode layer GE, but cobalt silicide layer SC is omitted. Is also good. It is preferable that a nitride film NF is further formed on cobalt silicide layer SC such as gate electrode layer GE, but this nitride film NF may be omitted.

  A buried insulating film BIL is formed on the main surface of the semiconductor substrate SUB between the pair of NMOS transistors and PMOS transistors as a CMOS transistor formed in the CMOS transistor region of FIG. Is formed. The buried insulating film BIL has a configuration in which the inside of a concave portion selectively formed on the main surface of the semiconductor substrate SUB is filled with an insulating film (for example, a silicon oxide film).

  The similar buried insulating film BIL is also formed in a part of the high voltage MOS transistor. The element isolation region DTR which surrounds the CMOS transistor (region) and the high-voltage MOS transistor (region) from the outside in a plan view electrically connects the CMOS transistor (region) and the high-voltage MOS transistor (region) to the respective outer regions. In order to separate the buried insulating film BIL formed on the main surface of the semiconductor substrate SUB, the buried insulating film BIL is divided into a left side and a right side. Further, the substrate contact SCN also penetrates through the buried insulating film BIL formed on the main surface of the semiconductor substrate SUB, and bisects the buried insulating film BIL into a left side and a right side.

  On the main surface of semiconductor substrate SUB (p-type epitaxial layer PE2) on which element isolation region DTR is formed, an interlayer insulating film II made of, for example, a silicon oxide film is formed so as to cover the CMOS transistor and the high voltage MOS transistor. ing. An interlayer insulating film II1 (insulating film) made of, for example, a silicon oxide film is formed so as to cover the upper surface of interlayer insulating film II. This interlayer insulating film II1 is formed so as to cover the CMOS transistor and the high voltage MOS transistor (element) similarly to the interlayer insulating film II, and the semiconductor substrate SUB is provided outside the CMOS transistor region and the high voltage MOS transistor region in plan view. Is formed so as to cover also the side walls and the bottom wall of the element isolation region DTR formed on the main surface of the semiconductor device.

  The concave portion TI formed so as to extend from the main surface of the semiconductor substrate SUB to the inside, the first concave portion TI forming the substrate contact SCN in the substrate electrode region, and the CMOS transistor region and the high-voltage MOS transistor region outside in a plan view. And a second concave portion TI different from the first concave portion, which constitutes an element isolation region DTR formed so as to surround from the first concave portion. Both the first and second recesses TI are formed to extend from the main surface of the semiconductor substrate SUB to the inside.

  The interlayer insulating film II1 formed on the main surface of the semiconductor substrate SUB is formed so as to bury a part of the inside of the concave portion TI constituting the element isolation region DTR formed on the main surface of the semiconductor substrate SUB. However, the interlayer insulating film II1 is not completely filled in the recesses TI constituting the element isolation regions DTR but is partially filled. Therefore, a closed hollow AG is formed inside the concave portion TI constituting the element isolation region DTR. As a result, the element isolation region DTR is formed such that the inner side of the concave portion TI, particularly on the side wall and the bottom wall, is covered with the interlayer insulating film II1. It is preferable that the interlayer insulating film II1 entirely covers the side walls and the bottom wall of the concave portion TI forming the element isolation region DTR.

  The hollow AG in the element isolation region DTR extends along the direction in which the concave portion TI extends (vertical direction in FIG. 4), is shorter than the length of the concave portion TI (vertical direction in FIG. 4), and has the concave portion TI. (Width in the left-right direction of FIG. 4). However, the hollow AG preferably has a length relatively close to the length of the concave portion TI in the vertical direction in FIG. In other words, the hollow AG preferably extends from a region near the main surface of the semiconductor substrate SUB (p-type epitaxial layer PE2) to a region near the bottom wall of the concave portion TI.

  Further, it is preferable that the hollow AG is formed so that the width is narrower on the upper side in FIG. 4 than on the lower side. That is, in FIG. 3, the hollow AG is illustrated so that the width thereof is substantially constant over the whole, but it is preferable that the hollow AG actually has a tapered shape as shown in FIG. The upper end of the hollow AG having a tapered shape is closed, and the hollow AG is formed as a bubble surrounded by the interlayer insulating film II1.

  Also in the substrate contact SCN in the substrate electrode region, similarly to the element isolation region DTR, the concave portion TI extends from one main surface of the semiconductor substrate SUB (the main surface in contact with the interlayer insulating film II1) to the concave portion TI of the element isolation region DTR. It is formed so as to extend in the vertical direction in FIG. 4 to almost the same depth as the bottom surface (for example, in the p-type impurity region PSB).

  The interlayer insulating film II1 formed on the main surface of the semiconductor substrate SUB is formed so as to bury a part of the inside of the first concave portion TI constituting the substrate contact SCN formed on the main surface of the semiconductor substrate SUB. I have. This interlayer insulating film II1 is formed so as to cover the side wall of the first recess TI, but does not cover at least a part (for example, the center) on the bottom wall of the recess TI and exposes the semiconductor substrate SUB on the bottom wall. It is formed so that. It is preferable that the interlayer insulating film II1 entirely covers the side wall of the first concave portion TI forming the substrate contact SCN.

  A first conductive material extending in the first concave portion TI of the substrate contact SCN (for example, a central portion surrounded by the insulating film II1 in the concave portion TI) in the direction in which the concave portion TI extends (the vertical direction in FIG. 4). The substrate contact conductive layer CDL as a layer is formed so as to reach the bottom wall of the concave portion TI from one main surface of the interlayer insulating film II1 (the main surface opposite to the main surface in contact with the semiconductor substrate SUB). In other words, the substrate contact conductive layer CDL of the substrate contact SCN fills the inside of the interlayer insulating film II1 and the contact hole CH1A formed in a part of the region within the concave portion TI, and the hollow AG similar to the above-described element isolation region DTR. It is formed as follows.

  A wiring layer ICL1 is formed on one main surface of the interlayer insulating film II1 where the first concave portion TI of the substrate contact SCN is formed, and the wiring layer ICL1 is a substrate contact conductive layer of the substrate contact SCN. It is formed so as to cover the CDL. Therefore, substrate contact conductive layer CDL of substrate contact SCN is electrically connected to both wiring layer ICL1 and semiconductor substrate SUB (p-type impurity region PSB).

  The wiring layer ICL1 is formed on one main surface of the interlayer insulating film II1 not only in a region directly above the substrate contact conductive layer CDL of the substrate contact SCN but also in a source / drain region (conductive region) of a CMOS transistor and a high voltage MOS transistor. It is also formed in the region just above the regions NR and PR as (parts). Between the regions NR and PR and the wiring layer ICL1 formed immediately above the regions NR and PR, a plug conductive film extending so as to penetrate the interlayer insulating film II and the interlayer insulating film II1 in the vertical direction of FIG. The layer PL1 is formed.

  On the other hand, plug conductive layer PL1 as a second conductive layer is formed of a CMOS transistor and a high-voltage MOS transistor formed from one main surface of interlayer insulating film II1 to the other main surface (one main surface of semiconductor substrate SUB). Of the contact holes CH1B formed so as to reach the regions NR and PR of FIG. The plug conductive layer PL1 electrically connects the wiring layer ICL1 directly above and the regions NR and PR (elements such as CMOS transistors) immediately below the wiring layer ICL1.

  The contact hole CH1A as the first hole portion reaches the bottom wall of the concave portion TI from the upper surface (upper surface) of the interlayer insulating film II1 through the first concave portion TI of the substrate electrode region. It extends in the up-down direction of FIG. 4 so as to communicate with the arranged p-type impurity region PSB. The contact hole CH1B as the second hole is formed so as to reach a source / drain region (conductive region) of a CMOS transistor or the like from the upper surface (upper surface) of the interlayer insulating film II1.

  The substrate contact conductive layer CDL of the substrate contact SCN as the first conductive layer and the plug conductive layer PL1 as the second conductive layer are formed of the same material.

  On the upper side of the wiring layer ICL1 (the opposite side of the semiconductor substrate SUB), an interlayer insulating film II2 is formed on the interlayer insulating film II1 so as to cover the wiring layer ICL1. Contact hole CH2 is formed to extend from one main surface of interlayer insulating film II2 (the side opposite to the side in contact with interlayer insulating film II1) to the upper surface of wiring layer ICL1, and plug conductive layer PL2 is buried in contact hole CH2. Are formed. That is, plug conductive layer PL2 extends to penetrate interlayer insulating film II2 in the up-down direction in FIG. Above them, the interlayer insulating films II3 and II4, the contact holes CH3 and CH4, the plug conductive layers PL3 and PL4, and the wiring layers ICL2, ICL3, and ICL4 are formed as described above. All of these materials are basically the same as the above-described interlayer insulating film II1, contact hole CH1, plug conductive layer PL1, and wiring layer ICL1. Further, a pattern of the glass coat film BM may be formed thereon.

  Next, a method of manufacturing a semiconductor chip CHP having a CMOS transistor region, a high-voltage MOS transistor region, and a substrate electrode region shown in FIG. 4 as a semiconductor device according to an embodiment will be described with reference to FIGS. 5 to 15 illustrate the manufacturing method of the configuration shown in FIG. 4 for each step, and each region shown in FIGS. 5 to 15 is basically the same as each region shown in FIG.

Referring to FIG. 5, a p-type impurity region PSB including a p-type impurity region having a relatively high concentration (p ⁺ region as a substrate region of the first conductivity type) is first prepared as a semiconductor substrate.

  Referring to FIG. 6, p-type epitaxial region having a relatively lower p-type impurity concentration than p-type impurity region PSB is formed on one (for example, upper) main surface of p-type impurity region PSB by using a normal epitaxial technique. The layer PE1 is formed.

  Referring to FIG. 7, an n-type impurity is implanted into p-type epitaxial layer PE1 as shown by an arrow in the figure using a normal ion implantation technique. Thus, referring to FIG. 8, n-type (second conductivity type) diffusion layers as n-type (second conductivity type) diffusion layers are formed over the entire surface of p-type epitaxial layer PE1 on the main surface side (upper side in FIG. 7) with respect to p-type impurity region PSB. A mold buried layer NBL is formed.

  Further, referring to FIG. 8, a p-type impurity is implanted into n-type buried layer NBL using a normal ion implantation technique, so that a p-type impurity is entirely formed on the main surface of n-type buried layer NBL. A p-type buried layer PBL as a diffusion layer may be formed. A p-type epitaxial layer PE2 having a relatively lower p-type impurity concentration than p-type impurity region PSB is further formed on p-type buried layer PBL by using a normal epitaxial technique.

  As described above, the p-type impurity region PSB, the p-type epitaxial layer PE1, the n-type buried layer NBL, the p-type buried layer PBL, and the p-type impurity region PSB are formed inside (along the main surface of the semiconductor substrate to be formed) on the entire surface in plan view. A semiconductor substrate SUB having the p-type epitaxial layer PE2 is formed.

  Referring to FIG. 9, elements such as CMOS transistors and MOS transistors are formed at predetermined positions on the main surface (upper main surface in FIG. 9) of semiconductor substrate SUB formed in each step of FIGS. Is done.

Specifically, an NMOS transistor is formed in the NMOS region of the CMOS transistor region, and a PMOS transistor is formed in the PMOS region in the p-type epitaxial layer PE2 (or the high breakdown voltage n-type well region HNW shown in FIG. 3). You. The NMOS transistor includes a p-type well region PWR formed in a p-type epitaxial layer PE2, an n ⁺ region NR as a source or drain region (conductive portion), a gate insulating film GI, a gate electrode layer GE, and a sidewall insulating layer. And a film SW. The PMOS transistor includes an n-type well region NWR formed in a p-type epitaxial layer PE2, ap ⁺ region PR as a source or drain region, a gate insulating film GI, a gate electrode layer GE, and a sidewall insulating film SW. Mainly have.

In the high-voltage MOS transistor region, a high-voltage MOS transistor is formed in the p-type epitaxial layer PE2 (or the high-voltage n-type well region HNW shown in FIG. 3). The high breakdown voltage MOS transistor includes an n-type well region NWR, an n-type offset region NOR, a p-type well region PWR, an n ⁺ region NR, a p ⁺ region PR, a gate insulating film GI, a gate electrode layer GE, And a sidewall insulating film SW.

  The above CMOS transistor and MOS transistor may include a cobalt silicide layer SC. In addition, a buried insulating film BIL is formed in a region surrounding each of the above elements from the outside in a plane, a substrate electrode region, and a region between the NMOS transistor and the PMOS transistor.

  Referring to FIG. 10, a nitride film NF (see FIG. 4) may be included so as to cover the formed CMOS transistor and the high breakdown voltage MOS transistor. On the semiconductor substrate SUB, an interlayer insulating film II made of a silicon oxide film is formed by using, for example, a CVD (Chemical Vapor Deposition) method.

  Referring to FIG. 11, a photoresist PHR is applied so as to cover interlayer insulating film II. This photoresist PHR is patterned by a usual photolithography technique. Using the patterned photoresist PHR as a mask, the interlayer insulating film II and the buried insulating film BIL are sequentially anisotropically etched. As a result, a penetrating concave portion TIA penetrating through the interlayer insulating film II and the buried insulating film BIL is formed. Thereafter, the photoresist PHR is removed by ashing or the like.

  Referring to FIG. 12, anisotropic etching is performed on p-type epitaxial layer PE2 using interlayer insulating film II as a mask. Thus, the semiconductor substrate SUB (p-type epitaxial layer PE2) immediately below the through recess TIA is selectively removed. Thus, the surface of the semiconductor substrate SUB (p-type epitaxial layer PE2) penetrates, for example, the p-type epitaxial layer PE2, the p-type buried layer PBL, the n-type buried layer NBL, and the p-type epitaxial layer PE1 into the p-type impurity region PSB. A concave portion TI is formed so as to reach. This recess TI is preferably formed to penetrate the n-type buried layer NBL and reach the p-type impurity region PSB.

  In this manner, a concave portion TI that finally extends from the main surface of the semiconductor substrate SUB to the inside of the semiconductor substrate SUB and that becomes the first concave portion and the second concave portion is formed. That is, the first concave portion TI and the second concave portion TI are formed by the same etching process, in other words, simultaneously.

  Referring to FIG. 13, each of the elements is formed so as to cover the interlayer insulating film II on the surface of the p-type epitaxial layer PE2 in the substrate electrode region and to form a closed hollow AG in the concave portion TI. An insulating film II1 (insulating film) is formed on the element and in the concave portion TI. Specifically, an interlayer insulating film II1 is formed on the main surface of semiconductor substrate SUB and on the side wall and bottom wall of concave portion TI. Here, since the concave portion TI has a high aspect ratio (interlayer) and it is difficult to fill the entirety of the concave portion TI, the insulating film II1 is formed at the central portion of the concave portion TI, especially on the side walls and on the bottom wall. As a result, the hollow AG is formed as a bubble.

  The insulating film II1 is formed of, for example, a BP-TEOS having a thickness of 1320 nm and a normal silicon oxide film. The upper surface of the insulating film II1 is polished and removed by, for example, a (Chemical Mechanical Polishing) method. However, the insulating film II1 is not limited to the insulating film containing conductive impurities (BP-TEOS) as described above, and may be, for example, a normal silicon oxide film containing no conductive impurities.

  Here, the hollow AG formed in the concave portion TI is (relatively) close to the length of the concave portion TI in the vertical direction of FIG. 13, that is, has substantially the same length (vertical direction of FIG. 13) as the concave portion TI. Is preferred. That is, hollow AG preferably extends from a region near the main surface of semiconductor substrate SUB (p-type epitaxial layer PE2) to a region near the bottom wall of concave portion TI. The hollow AG is formed so as to have a smaller width on the upper side (closer to the main surface of the semiconductor substrate SUB) of the concave portion TI in FIG. 13 than on the lower side (closer to the bottom wall of the concave portion TI). In other words, the thickness of the insulating film II1 (interlayer insulating film II1) formed on the side wall of the concave portion TI is greater above the concave portion TI than below.

  As described above, in the process of FIG. 13, the insulating film is formed on both the side wall and the bottom wall of the concave portion TI that finally becomes the first concave portion TI and the concave portion TI that becomes the second concave portion TI. II1 is formed.

  Referring to FIG. 14, photoresist PHR is applied so as to cover interlayer insulating film II1. By performing a normal photoengraving technique on the photoresist PHR, an opening is formed immediately above the conductive portion (source / drain region) of the CMOS transistor and the high breakdown voltage MOS transistor and directly above the concave portion TI in the substrate electrode region. It is patterned so that a part is formed. The interlayer insulating film II1 is anisotropically etched using the patterned photoresist PHR as a mask.

  Thereby, in the CMOS transistor region and the high-breakdown-voltage MOS transistor region, the second hole is formed so as to reach the conductive portion (source / drain region) of the CMOS transistor and the high-breakdown-voltage MOS transistor from the uppermost surface of interlayer insulating film II1. A contact hole CH1B is formed. At this time, in the substrate electrode region, a contact hole CH1A as a first hole is formed so as to reach the hollow AG in the concave portion TI, particularly in the concave portion TI.

  The contact hole CH1A formed here has a mode in which a portion formed by an etching process and the originally existing hollow AG are connected and integrated like the contact hole CH1B. After the contact hole CH1A is integrated with the hollow AG, the insulating film II1 formed on the bottom wall of the concave portion TI located immediately below the hollow AG is etched, and the bottom wall of the concave portion TI (p Is formed so that the semiconductor substrate SUB (p-type impurity region PSB) is exposed at the bottom wall of the concave portion TI. More specifically, the contact hole CH1A is first etched from the upper surface of the interlayer insulating film II1 so that the interlayer insulating film II1 reaches the lower side in the drawing and reaches the hollow AG in the concave portion TI. At this time, the etching is performed so as to reach the semiconductor substrate SUB (for example, the p-type impurity region PSB) at the bottom wall of the concave portion TI while leaving the insulating film II1 on the side wall of the concave portion TI. The insulating film II1 (between the bottom wall of the hollow AG and the bottom wall of the hollow AG) is removed.

  On the other hand, the contact hole CH1B is formed by the same etching process as that for etching the interlayer insulating film II1 in the downward direction in the drawing to form the contact hole CH1A (before reaching the hollow AG). That is, the contact hole CH1B is formed so as to reach the conductive portion (source / drain region or the like) of the element from the upper surface of the interlayer insulating film II1.

  The contact holes CH1A and CH1B are formed by the same etching process. As described above, the hollow AG as a bubble in which the insulating film II1 and the like formed in the concave portion TI are not disposed so as to extend to the uppermost portion of the concave portion TI, that is, near the main surface of the semiconductor substrate SUB (p-type epitaxial layer PE2). Is formed. Therefore, there is no significant difference in the distance from the upper surface of the interlayer insulating film II1 between the regions NR, PR, etc., which are the conductive portions to be reached by the contact hole CH1B, and the hollow AG, to be reached by the contact hole CH1A.

  Therefore, there is no significant difference between the depth at which the interlayer insulating film II1 should be etched to form the contact hole CH1A and the depth at which the interlayer insulating film II1 should be etched to form the contact hole CH1B. Therefore, it is possible to form the contact holes CH1A and CH1B having seemingly completely different depths by the same etching process.

  By the above-described etching process, after the contact hole CH1A in the concave portion TI in the substrate electrode region is integrated with the hollow AG, the insulating film II1 on the bottom wall of the concave portion TI, which is located immediately below the hollow AG, is further removed. You. Therefore, contact hole CH1A is formed so as to reach the bottom wall of concave portion TI from the upper surface of interlayer insulating film II1.

  The widths of the contact holes CH1A and CH1B (in the horizontal direction in FIG. 14) are preferably smaller than the widths (in the horizontal direction in FIG. 14) of the recesses TI for forming the element isolation regions DTR. In this way, the contact hole CH1A can be formed so as to reach the bottom wall of the recess TI through the inside of the recess TI. In addition, from the viewpoint that the contact hole CH1A and the contact hole CH1B are formed by the same etching process, it is preferable that both have the same width (in the horizontal direction in FIG. 14).

  As an example, the width of contact hole CH1A and contact hole CH1B is preferably 0.4 μm, and the width of concave portion TI for forming element isolation region DTR (and substrate contact SCN) is preferably 0.8 μm. When the element isolation region DTR is formed very deep, it is necessary to increase the width of the concave portion TI for forming the element isolation region DTR (and the substrate contact SCN), but when the depth is approximately 20 μm or less. The width of the concave portion TI can be 0.8 μm.

  Referring to FIG. 15, after the photoresist PHR is removed by ashing or the like, titanium (Ti) is applied to cover the interlayer insulating film II1 and the inner wall surfaces of the contact holes CH1A and CH1B by, for example, a normal sputtering method. After forming a thin film of titanium nitride (TiN) as a barrier metal, a metal thin film of tungsten (W) is formed by a plasma CVD method. Next, the barrier metal and the metal thin film on the interlayer insulating film II1 are removed by etch back.

  Thus, plug conductive layer PL1 made of a tungsten metal thin film is formed inside contact hole CH1B, and at the same time, substrate contact conductive layer CDL made of a tungsten metal thin film is formed inside contact hole CH1A. You. That is, the substrate contact conductive layer CDL and the plug conductive layer PL1 are formed by the same film forming process, and both are formed by the same material. Plug conductive layer PL1 is formed so as to be electrically connected to the source / drain regions (conductive portions) of the CMOS transistor and the high breakdown voltage MOS transistor. Substrate contact conductive layer CDL is formed so as to be electrically connected to semiconductor substrate SUB (for example, p-type impurity region PSB).

  The substrate contact conductive layer CDL may be formed so as to form therein a hollow AGA as a bubble similar to the above-mentioned hollow AG. However, the hollow AGA is omitted in the following drawings.

  As described above, the plug conductive layer PL1 and the substrate contact conductive layer CDL may be made of a metal thin film of tungsten, but may be a metal thin film made of, for example, aluminum.

  Referring to FIG. 16, contact is made with the upper surfaces of plug conductive layer PL1 and substrate contact conductive layer CDL to electrically connect them to the conductive portion of each element or semiconductor substrate SUB (p-type impurity region PSB). The wiring layer ICL1 is formed on the interlayer insulating film II1. This wiring layer ICL1 is preferably formed as a laminated structure of titanium nitride and an alloy of copper and aluminum (AlCu) by, for example, a normal sputtering method, but the above-described plug conductive layer PL1 and substrate contact conductive layer are formed. The same material as the CDL may be used. As an example, a laminated structure of, for example, 26.5 nm of titanium nitride and 450 nm of AlCu is formed.

  As described above, in the substrate electrode region, the substrate contact conductive layer CDL is formed in the contact hole CH1A in the concave portion TI. The substrate contact conductive layer CDL is formed so as to electrically connect the semiconductor substrate SUB (p-type impurity region PSB) and the wiring layer ICL1. In the CMOS transistor region and the high breakdown voltage MOS transistor region, plug conductive layer PL1 is formed in contact hole CH1B, and plug conductive layer PL1 electrically connects (a conductive portion of) a CMOS transistor or the like to wiring layer ICL1. It is formed so that it may be connected to.

  Thereafter, basically, by repeating the same forming steps as those for forming the interlayer insulating film II1, the plug conductive layer PL1, and the wiring layer ICL1, each layer above the wiring layer ICL1 as shown in FIG. 4 is formed. However, a detailed description of the process is omitted.

Next, the operation and effect of the present embodiment will be described.
In the present embodiment, a contact hole CH1A as a first hole formed in the concave portion TI for forming a substrate contact SCN (substrate contact conductive layer CDL) in a substrate electrode region, a CMOS transistor region, and the like. The contact hole CH1B as the second hole to be formed is formed by the same etching process. Therefore, for example, the number of masks required for the etching process and the time required for the process can be reduced as compared to the case where the contact holes CH1A and CH1B are formed by different etching processes. As a result, costs required for processing can be significantly reduced.

  In the present embodiment, the top surface of interlayer insulating film II1 reaches the bottom wall of concave portion TI through first concave portion TI of the substrate electrode region, and leads to p-type impurity region PSB in which the bottom wall of concave portion TI is arranged. In addition, a contact hole CH1A extends vertically in FIG. Further, a contact hole CH1B is formed so as to reach a source / drain region (conductive region) of a CMOS transistor or the like from the upper surface of the interlayer insulating film II1. From this, it can be verified that the contact hole CH1A and the contact hole CH1B are formed by the same etching process.

  The first reason that the step of forming the contact hole CH1A and the contact hole CH1B by the same etching process can be realized is that the hollow AG in which the insulating film II1 is not buried in the concave portion TI in the substrate electrode region where the contact hole CH1B is formed. It is because it is formed. That is, if the hollow AG does not exist, the depth to be etched to form the contact hole CH1A (substantially equal to the sum of the thickness of the interlayer insulating film II1 and the depth of the concave portion TI) forms the contact hole CH1B. For this reason, it becomes very large compared to the depth to be etched (the thickness of the interlayer insulating film II1), so that it is difficult to etch both of them in the same step. Since the concave portion TI has a very high aspect ratio and the interlayer insulating film II1 is partially embedded in the concave portion TI to form the hollow AG, the etching proceeds to the top of the hollow AG in order to form the contact hole CH1A. Would be almost enough.

  The second reason that the step of forming the contact hole CH1A and the contact hole CH1B by the same etching process can be realized is that the contact hole CH1A is formed so as to penetrate only the semiconductor region of the semiconductor substrate SUB. That is, if it is necessary to penetrate the insulating film buried in the so-called SOI substrate when forming the contact hole CH1A, the buried insulating film is thick and requires much time for etching. It is difficult to complete the etching by the same etching process as CH1B. The semiconductor substrate SUB used in the present embodiment is composed only of a semiconductor region having conductivity, and does not have the buried insulating film as described above, so that the contact hole CH1A is substantially equal to the contact hole CH1B. It can be easily formed by the etching amount.

  Next, in the present embodiment, a first recess TI for forming the substrate contact SCN and a second recess TI for forming the element isolation region DTR are formed as shown in FIGS. It is formed by the same etching process. Further, the insulating film II1 in the concave portion TI for forming the substrate contact SCN and the insulating film II1 in the concave portion TI for forming the element isolation region DTR are formed by the same film forming process as shown in FIG. You. Therefore, the number of steps, processing time, and manufacturing cost can be reduced as compared with the case where these are formed as separate processes.

  In the present embodiment, a recess TI formed for a substrate contact SCN in a substrate electrode region is formed by the same process as a recess TI formed for an element isolation region DTR such as a CMOS transistor region. In other words, in the present embodiment, the substrate contact SCN is formed using a part of the concave portion TI originally formed for forming the element isolation region DTR. As described above, the formation of the contact hole CH1A for forming the substrate contact SCN is facilitated by the existence of the hollow AG, as compared with the case where the hollow AG is not present. Therefore, the substrate contact SCN can be formed more easily by using the concave portion TI formed in another step (the step of forming the element isolation region DTR) without performing an additional step for forming the substrate contact SCN. can do. That is, the present embodiment has an advantage when there is a request to draw the potential on the back side of the substrate from the front surface of the semiconductor substrate SUB using the substrate contact SCN.

  Since the hollow AG is formed in the element isolation region DTR, the stress in the vicinity of the concave portion TI of the element isolation region DTR in the semiconductor substrate SUB can be reduced as compared with the case where the hollow AG is not formed.

  The substrate contact conductive layer CDL filling the contact hole CH1A and the plug conductive layer PL1 filling the contact hole CH1B are formed of the same material by the same film forming process. Also from this, the number of steps, processing time, and manufacturing cost can be reduced as compared with the case where these are formed by another film forming process.

  Next, referring to FIG. 17, a semiconductor chip CHP as a comparative example of the present embodiment has basically the same configuration as semiconductor chip CHP of the present embodiment in FIG. The configuration of the substrate contact in the electrode region is different from that of the present embodiment. Specifically, the substrate contact is formed by a p-type buried layer PBL and a deep p-type diffusion layer DPW formed as the same layer as the p-type epitaxial layer PE2. More specifically, in the vertical direction of FIG. 17, from the upper main surface side of the semiconductor substrate SUB (p-type epitaxial layer PE2), the deep p-type diffusion layer DPW, p-type buried layer PBL, p-type epitaxial layer PE1, The p-type impurity regions PSB are arranged in this order, and are continuous with each other in the vertical direction in the drawing. In FIG. 17, interlayer insulating film II is not formed, and interlayer insulating film II1 is formed so as to cover the main surface of semiconductor substrate SUB.

  Since both the deep p-type diffusion layer DPW and the p-type buried layer PBL are regions containing p-type impurities, all regions in the substrate electrode region are regions containing p-type impurities. Therefore, in the substrate electrode region, for example, a wiring layer formed on p-type epitaxial layer PE2 (deep p-type diffusion layer DPW) can be electrically connected to p-type impurity region PSB.

  On the other hand, in the CMOS transistor region and the high breakdown voltage MOS transistor region, for example, the electrical connection between the high breakdown voltage n-type well region HNW (p-type epitaxial layer PE2) in which the element is formed and the p-type impurity region PSB below the semiconductor substrate SUB. In order to cut off the connection, an n-type buried layer NBL is formed. If the n-type buried layer NBL is formed in the substrate electrode region, a pn junction is formed in the region, so that the substrate potential cannot be extracted. Therefore, in the comparative example of FIG. 17, it is necessary to pattern the n-type buried layer NBL so as not to be formed in the substrate electrode region (in other words, to form the n-type buried layer NBL only in the CMOS transistor region or the like). is there.

  However, if the substrate contact SCN formed using the same recess as the recess TI for forming the element isolation region DTR as in the present embodiment is used for the substrate electrode region, the substrate electrode region can be replaced with a CMOS transistor region or the like. A similar n-type buried layer NBL may be formed. This is because the substrate contact SCN is electrically connected to the p-type impurity region PSB by the substrate contact conductive layer CDL in the concave portion TI. This is because the mold does not affect the conductivity of the substrate contact SCN. Therefore, in the present embodiment, it is not necessary to perform patterning so that n-type buried layer NBL is locally (selectively) formed, and n-type buried layer NBL is entirely formed in plan view of semiconductor substrate SUB. It may be formed.

  Therefore, the step of patterning the n-type buried layer NBL can be omitted, and the preparation of a mask for patterning the n-type buried layer NBL becomes unnecessary. For this reason, the process can be further simplified, and the manufacturing cost can be reduced.

  Also, with reference to the perspective views of FIGS. 18A and 18B, a substrate including a deep p-type diffusion layer DPW and a p-type buried layer PBL as in the comparative example is applied by applying the substrate contact SCN of the present embodiment. The electric resistance of the substrate contact can be reduced as compared with the case where the contact is used. Here, the electric resistance of the substrate contact is an electric resistance value from the upper surface of the p-type epitaxial layer PE2 which is the uppermost layer of the semiconductor substrate SUB to the upper surface of the p-type impurity region PSB which is the lowermost layer of the semiconductor substrate SUB. Means

  Therefore, when this embodiment is applied, the width W1 (in the left-right direction of the drawing) of the substrate contact SCN shown in FIG. 18A is made smaller than the width W2 of the substrate contact shown in FIG. 18B. be able to. This is because, for example, when forming a deep diffusion layer DPW as a constituent member of a substrate contact as shown in FIG. 18B, it is necessary to form a deep diffusion layer by performing heat treatment for a long time. This is because the region of the diffusion layer becomes excessively large, and the area of the substrate contact may increase.

  As a result, even when the depth D1 of the substrate contact SCN shown in FIG. 18A is equal to the depth D1 of the substrate contact shown in FIG. 18B, FIG. 18A is compared with FIG. 18B. The area occupied by the substrate contact in plan view can be reduced. Therefore, the size of the semiconductor chip CHP (see FIG. 1) on which the semiconductor device is formed can be reduced.

(Embodiment 2)
In one embodiment, the substrate contact SCN may be formed as a drain electrode electrically connected to a drain region of a so-called vertical MOS transistor as an element.

  Referring to FIG. 19, in a semiconductor substrate SUB of the present embodiment, a p-type impurity region PSB, a p-type epitaxial layer PE1, an n-type buried layer NBL, and a high breakdown voltage n-type well region HNW are arranged in this order. It has a stacked configuration. Further, the semiconductor substrate SUB has a p-type epitaxial layer PE2 as the same layer as the high-breakdown-voltage n-type well region HNW around the high-breakdown-voltage n-type well region HNW with the element isolation region DTR interposed therebetween. I have.

  A vertical element region is formed in the high breakdown voltage n-type well region HNW, and a plurality of vertical MOS transistors are arranged in the vertical element region so as to be arranged in a direction along the main surface of the semiconductor substrate SUB. Each vertical MOS transistor mainly has a deep p-type diffusion layer DPW, a plug conductive layer PL1, a substrate contact SCN, a source wiring layer SO, and a drain wiring layer DR. In addition, FIG. 19 shows a gate insulating film GI, a gate electrode layer GE, and a buried insulating film BIL that constitute a vertical MOS transistor.

The deep p-type diffusion layer DPW is a p-type impurity region as a source region formed in the high breakdown voltage n-type well region HNW. Plug conductive layer PL1 is formed so as to penetrate interlayer insulating film II and interlayer insulating film II1 similarly to plug conductive layer PL1 of the first embodiment, and n ⁺ region NR described later formed in deep p-type diffusion layer DPW. And p ⁺ region PR. Source wiring layer SO corresponds to wiring layer ICL1 of the first embodiment, and is formed to cover plug conductive layer PL1.

  The substrate contact SCN in the present embodiment has a configuration in which the insulating film II1 and the substrate contact conductive layer CDL are formed inside the concave portion TI, similarly to the substrate contact SCN in the first embodiment. In FIG. 19, as an example, substrate contact SCN as a drain electrode extends from the main surface of semiconductor substrate SUB to reach the inside of n-type buried layer NBL as a drain region. The buried layer NBL is electrically connected. The drain wiring layer DR corresponds to the wiring layer ICL1 of the first embodiment, and is formed so as to cover the substrate contact SCN. Further, the element isolation region DTR in the present embodiment also has a configuration in which the insulating film II1 and the hollow AG are formed inside the concave portion TI, similarly to the element isolation region DTR in the first embodiment.

An n ⁺ region NR, a p ⁺ region PR, and an n ⁺ region NR are formed on the main surface of the semiconductor substrate SUB (high breakdown voltage n-type well region HNW) on which the deep p-type diffusion layer DPW as a source region is formed. They are arranged in order.

The n ⁺ region NR is formed between the source wiring layer SO and the high breakdown voltage n-type well by utilizing the electric field effect generated in the region of the high breakdown voltage n-type well region HNW immediately below the gate electrode layer GE and the gate insulating film GI. The region HNW is a region where the n-type buried layer NBL and the drain region are electrically connected to each other. Further, p ⁺ region PR is arranged to form a so-called back gate structure that electrically connects deep p-type diffusion layer DPW directly below it.

  The configuration of the present embodiment is different from the configuration of the first embodiment in the above points, and is otherwise the same as the configuration of the first embodiment. And the description thereof will not be repeated.

  Next, the operation and effect of the present embodiment will be described with reference to a comparative example of FIG. Although the present embodiment also has basically the same operation and effect as in the first embodiment, an additional operation and effect in addition to the operation and effect of the first embodiment will be described here.

  Referring to FIG. 20, a semiconductor chip CHP as a comparative example of the present embodiment has basically the same configuration as semiconductor chip CHP of the present embodiment in FIG. It is formed not of the contact SCN but of a deep n-type diffusion layer DNW extending from the main surface of the semiconductor substrate SUB to reach the n-type buried layer NBL. Although FIG. 20 differs from FIG. 19 in this point, the other points are basically the same as FIG. 19, and thus, the same elements will be denoted by the same reference characters and description thereof will not be repeated.

  By forming the drain region using the substrate contact SCN as in the present embodiment, the electric resistance of the drain region can be significantly reduced as compared with the case where the drain region is formed by the deep n-type diffusion layer DNW. Can be. As a result, the performance of the semiconductor device (semiconductor element) mounted on the semiconductor chip CHP can be significantly improved.

  When a deep n-type diffusion layer DNW is formed as a drain region, it is necessary to perform a heat treatment for a long time, so that the diffusion layer is widened and its area in a plan view is large. However, if the drain region is formed as a substrate contact SCN, In addition, the area of the drain region in plan view can be reduced. Therefore, in the present embodiment, the size of the semiconductor chip CHP (see FIG. 1) on which the semiconductor device is formed can be reduced.

(Embodiment 3)
The substrate contact SCN (substrate contact conductive layer CDL) in one embodiment may have an active barrier region forming a so-called active barrier structure.

  Referring to FIG. 21, semiconductor substrate SUB of the present embodiment has a configuration in which, for example, p-type impurity region PSB, p-type epitaxial layer PE1, and p-type well region PWR are stacked in this order. . In the semiconductor chip CHP of the present embodiment, similarly to the semiconductor chip CHP of the first embodiment, the semiconductor substrate SUB includes a CMOS transistor region (first element formation region) and a high breakdown voltage MOS transistor region (second element formation). Region).

The CMOS transistor region of FIG. 21 has a p-type epitaxial layer PE1, an n-type buried layer NBL, and a high-breakdown-voltage n-type well region HNW, similarly to the CMOS transistor region of the first embodiment of FIG. However, the high breakdown voltage MOS transistor region of FIG. 21 is simplified and shown to have a p-type epitaxial layer PE1, an n-type buried layer NBL, a deep n-type diffusion layer DNW, an n-type well region NWR and an n ⁺ region NR. I have. The high breakdown voltage MOS transistor region in FIG. 21 may have such a configuration, or may have the same configuration as the high breakdown voltage MOS transistor region in FIG.

  In FIG. 21, similarly to FIG. 3, an element isolation region DTR is formed so as to surround a CMOS transistor region and a high-breakdown-voltage MOS transistor region, and element isolation region DTR has an insulating film II1 and a hollow inside recessed portion TI. AG is formed. The substrate electrode region in FIG. 21 is formed in a region where the p-type epitaxial layer PE1 and the p-type well region PWR are stacked on the p-type impurity region PSB. Similarly to the substrate electrode region of the first embodiment, a substrate contact SCN having a configuration in which an insulating film II1 and a substrate contact conductive layer CDL are formed inside a concave portion TI is formed. The substrate contact SCN is connected to, for example, a ground terminal GND.

  In FIG. 21, the CMOS transistor region and the high-breakdown-voltage MOS transistor region are located apart from each other in a direction along the main surface of the semiconductor substrate SUB (the left-right direction in FIG. 21). An active barrier region is formed between the CMOS transistor region and the high breakdown voltage MOS transistor region.

The active barrier structure has a configuration in which an n-type buried layer NBL, a deep n-type diffusion layer DNW, an n-type well region NWR, and an n ⁺ region NR are stacked in this order, and the second of the second conductivity type (n-type). A region, a substrate contact SCN having a configuration similar to that of the other embodiments, and a wiring layer ICL1 as a connection conductive layer for electrically connecting the second region and the substrate contact SCN are provided. That is, the substrate contact conductive layer CDL of the substrate contact SCN extends from the uppermost surface of the interlayer insulating film II1 to the p-type impurity region PSB through the interlayer insulating films II1, II, the p-type well region PWR, and the p-type epitaxial layer PE1. Is formed.

  Since the above-mentioned substrate contact SCN is formed so as to reach the p-type impurity region PSB through the p-type well region PWR and the p-type epitaxial layer PE1, it functions as a p-type region of an active barrier structure. The substrate contact SCN as the p-type region of the active barrier structure also has a configuration in which the insulating film II1 and the substrate contact conductive layer CDL are formed inside the concave portion TI, similarly to the substrate contact SCN in the substrate electrode region. .

  The n-type region forming the active barrier structure is ohmically connected to the substrate contact SCN (particularly, the substrate contact conductive layer CDL). Although not shown, the ohmic-connected n-type region and substrate contact SCN may be connected to, for example, a ground terminal.

  In FIG. 21 (similar to the other embodiments), the p-type impurity region PSB of the semiconductor substrate SUB is formed over the entire surface of the semiconductor substrate SUB in plan view. That is, the p-type impurity region PSB extends in the direction along the main surface of the semiconductor substrate SUB from the CMOS transistor region through the active barrier region to at least the high breakdown voltage MOS transistor region, so that the first region of the first conductivity type (p-type). It is formed as.

The second region of the second conductivity type (n-type) constituting the active barrier structure forms a pn junction with the first conductivity type region including the first region (p ⁺ region included in the p-type impurity region PSB). As described above, it is formed on the main surface of the semiconductor substrate SUB in the active barrier region. That is, the n ⁺ region NR, which is the uppermost layer of the second region, is formed on the main surface of the semiconductor substrate SUB (p-type well region PWR). The n-type buried layer NBL, which is the lowermost layer of the second region, is formed in the p-type epitaxial layer PE1.

  Here, the operation principle of the active barrier structure in the semiconductor chip CHP of FIG. 21 will be briefly described. For example, when a negative potential is applied to the CMOS transistor region and electrons are absorbed from a device such as a CMOS transistor into the p-type impurity region PSB of the semiconductor substrate SUB, the electrons are high-voltage MOS transistors having a higher potential than the CMOS transistor region. It moves toward the area, that is, toward the right side in FIG. Some of the electrons are absorbed by the n-type region of the active barrier structure. Then, holes similar to the absorbed electrons move from the substrate contact SCN (functioning as a p-type region) having the active barrier structure to the p-type impurity region PSB. As a result, the potential drops near the substrate contact SCN (functioning as a p-type region) of the active barrier structure, and this becomes a potential barrier for electrons moving toward the high breakdown voltage MOS transistor region. This makes it difficult for the electrons to move in the direction of the high-breakdown-voltage MOS transistor region, and tends to move toward the deep region side (the lower side in the figure) of the p-type impurity region PSB. As described above, it is possible to suppress a malfunction of the high withstand voltage MOS transistor due to unintentional entry of electrons into the high withstand voltage MOS transistor region.

  The configuration of the present embodiment is different from the configuration of the first embodiment in the above points, and is otherwise the same as the configuration of the first embodiment. And the description thereof will not be repeated.

  Next, the operation and effect of the present embodiment will be described with reference to a comparative example of FIG. Although the present embodiment also has basically the same operation and effect as in the first embodiment, an additional operation and effect in addition to the operation and effect of the first embodiment will be described here.

Referring to FIG. 22, a semiconductor chip CHP as a comparative example of the present embodiment has basically the same configuration as semiconductor chip CHP of the present embodiment in FIG. 21, but has an active barrier structure. The p-type region is formed by ap ⁺ region PR having a relatively high impurity concentration instead of the substrate contact SCN. Although FIG. 22 differs from FIG. 21 in this point, the other points are basically the same as those in FIG. 21, and thus the same elements are denoted by the same reference characters and description thereof will not be repeated.

  By forming the p-type region having the active barrier structure using the substrate contact SCN as in the present embodiment, the electric resistance of the p-type region can be reduced as compared with the case where the p-type region is formed by the p-type impurity region PR. Can be reduced. As a result, holes move more smoothly from the substrate contact SCN as a p-type region to the p-type impurity region PSB of the substrate, and the efficiency of the active barrier structure forming a potential barrier for electrons can be increased. Therefore, the configuration of the present embodiment can enhance the function of the active barrier structure more than the configuration of the comparative example.

(Embodiment 4)
Referring to FIGS. 23 to 25, in the present embodiment, all of concave portions TI originally formed for forming element isolation region DTR are used for forming substrate contact SCN. In this regard, in the present embodiment, only a part of the concave portion TI originally formed for forming the element isolation region DTR (that is, only the first concave portion TI formed in the substrate electrode region) forms the substrate contact SCN. The other recesses TI are different from the first embodiment used as the second recesses TI for forming the element isolation regions DTR.

  Specifically, referring to FIG. 23, semiconductor chip CHP of the present embodiment is provided in a region (around logic portion LG and output driver portion HV) where element isolation region DTR is formed in semiconductor chip CHP of FIG. A substrate contact SCN is formed. In other words, in the semiconductor chip CHP of the present embodiment, the logic section LG and the output driver section HV are surrounded by the substrate contact SCN in plan view.

  In FIG. 23, no element isolation region DTR is formed. In FIG. 23, the substrate contact SCN is not formed in the region where the substrate contact SCN is formed in FIG.

  Similarly, referring to FIGS. 24 and 25, in the present embodiment, a substrate electrode region (substrate contact SCN) is formed so as to surround a CMOS transistor region and a high breakdown voltage MOS transistor region. In this point, the present embodiment is different from the first embodiment (FIGS. 3 and 4) in which the element isolation region DTR is formed so as to surround the CMOS transistor region and the high breakdown voltage MOS transistor region.

  The substrate contact SCN shown in FIGS. 24 and 25 is arranged at a position slightly away from the CMOS transistor region or the like than the element isolation region DTR shown in FIGS. 3 and 4, but the present embodiment is limited to such an embodiment. I can't.

  The substrate contact SCN of the present embodiment and each of the first to third embodiments is used as a substrate electrode for extracting a substrate potential from above, and the periphery of the substrate contact conductive layer CDL is covered with an insulating film II1 (interlayer insulating film). II1). Therefore, the substrate contact SCN has both a function as a substrate electrode and a function of electrically separating an element from another region as in the element isolation region DTR.

  Therefore, by adopting a structure in which the element formation region is surrounded by the substrate contact SCN as in this embodiment, the element formation region can be electrically separated from other regions, and the substrate potential can be extracted.

  Further, since the substrate contact SCN has the same function as the element isolation region DTR, it is not necessary to form the element isolation region DTR as in the first embodiment. Further, in the present embodiment, there is no need to form anything in the region where substrate contact SCN is formed in FIG. Therefore, the components of the semiconductor chip CHP can be reduced, and the size of the semiconductor chip CHP can be reduced.

  As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.

AG hollow, BIL buried insulating film, BM glass coat film, CDL substrate contact conductive layer, CH1A, CH1B, CH2, CH3, CH4 contact hole, CHP semiconductor chip, DFR element formation region, DNW deep n-type diffusion layer, DPW deep p Diffusion layer, DR drain wiring layer, DTR element isolation region, GE gate electrode layer, GI gate insulating film, HNW high breakdown voltage n-type well region, HV output driver, ICL1, ICL2, ICL3, ICL4 wiring layer, II, II1, II2, II3, II4 Insulating film, LG logic part, NBL n-type buried layer, NF nitride film, NOR n-type offset region, NR n ⁺ region, NWR n-type well region, SO source wiring layer, PBL p-type buried Layer, PE1, PE2 p-type epitaxial layer, PHR photoresist PL1, PL2, PL3, PL4 plug conductive layers, PR p ⁺ region, PSB p-type impurity region, PWR p-type well region, SC cobalt silicide layer, SCN substrate contact, SO source wiring layer, SUB semiconductor substrate, SW sidewall insulating film , TI recess, TIA through recess.

Claims (14)

A semiconductor substrate having a first recess formed on a main surface thereof and having a semiconductor element formed on the main surface;
The first recess includes a region on a side wall in the first recess and a region outside the first recess extending along the main surface, and is formed in a region on the sidewall in the first recess to form the first recess. A first insulating film in which a first hole is formed in one recess, and a second hole is formed in a region extending along the main surface;
A first conductive layer formed inside the first hole and the second hole,
The second hole communicates with the first hole,
The first conductive layer is in direct contact with the semiconductor substrate at a bottom of the first hole ,
A contact hole reaching the semiconductor element is formed in a region of the first insulating film extending along the main surface; and
A second conductive layer is formed inside the contact hole,
The semiconductor device, wherein the first conductive layer and the second conductive layer are formed of the same material . The semiconductor substrate includes a first impurity region having an impurity of a first conductivity type, and a second impurity region formed on the first impurity region and having an impurity of a second conductivity type different from the first conductivity type. An impurity region, and a third impurity region formed on the second impurity region and having the first conductivity type impurity,
Said first hole extends through said second impurity region and the third impurity region is formed to reach the first impurity region, the semiconductor device according to claim 1. The semiconductor substrate is formed between the first impurity region and the second impurity region, and has a first epitaxial layer having the first conductivity type impurity, and is formed on the third impurity region. 3. The semiconductor device according to claim 2 , further comprising: a second epitaxial layer having the first conductivity type impurity. The semiconductor device according to claim 2 , wherein the first conductivity type is a p-type, and the second conductivity type is an n-type. A second recess is formed in the main surface of the semiconductor substrate,
The first insulating film, the gap in the second recess is formed on the sidewalls of the second recess to be formed, the semiconductor device according to any one of claims 1-4. The semiconductor device according to claim 5 , wherein the second recess is formed so as to surround a region where the semiconductor element is formed in a plan view. The semiconductor device according to claim 6 , wherein the first recess is disposed outside the second recess. A second insulating film formed on the semiconductor substrate to cover the semiconductor element between the semiconductor substrate and the first insulating film;
A third recess communicating with each of the first recess and the second recess is formed in the second insulating film;
In the third recess communicating with the first recess, a third hole communicating with each of the first hole and the second hole is formed,
The first insulating film includes a region on a sidewall in the third recess, and the third insulating film is formed in a region on a sidewall in the third recess, so that the third insulating film is formed in the third recess. A hole is formed,
The semiconductor device according to claim 5 , wherein the first conductive layer is formed in the third hole. The semiconductor element is a MOS transistor, the semiconductor device according to any one of claims 1-8. The material of the first conductive layer is tungsten, semiconductor device according to any one of claims 1-9. It said first conductive layer includes a barrier metal, and a metal thin film formed on the barrier metal, a semiconductor device according to any one of claims 1-10. The barrier metal is a laminated film of a titanium film and a titanium nitride film,
The semiconductor device according to claim 11 , wherein the metal thin film is a tungsten film. The first insulating film is a silicon oxide film, a semiconductor device according to any one of claims 1 to 12. The first insulating film is formed on the semiconductor substrate, a semiconductor device according to any one of claims 1 to 13.

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