JP2006286696A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can effectively suppress the propagation of noise between circuit regions, and also to provide its manufacturing method. <P>SOLUTION: Between analog and digital circuit regions on a silicon substrate 10, a circuit separation region is formed wherein a dummy diffusion layer 14 is arranged. Into the dummy diffusion layer 14, impurities are introduced having an n-type conductivity type which is the opposite conductivity type to that of a p-well 12 wherein the dummy diffusion layer 14 is formed. The top face Sb of the dummy diffusion layer 14 is dug deeper into the silicon substrate 10 than the principal plane Sa of the silicon substrate 10. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to an improvement in structure and manufacturing technology related to suppression of noise propagation between two circuit regions on a semiconductor substrate.

  When a plurality of circuits are mixed in a semiconductor device, noise propagation between the circuits becomes a problem. In particular, in a semiconductor device including an integrated circuit including an analog circuit and a digital circuit, high-frequency noise generated in a digital circuit that operates at high speed is propagated to the analog circuit that is easily affected by the noise, thereby hindering the operation of the analog circuit. is there. Such noise propagation between the circuits can be reduced by providing a large circuit isolation region having an insulating layer formed on the main surface of the silicon substrate between the circuits.

  As the integration density of semiconductor devices increases, the formation of such circuit isolation regions is generally performed using shallow trench isolation (STI) processes. In the STI process, first, a trench having a predetermined depth is formed on the surface of the silicon substrate in the insulating layer forming portion by performing etching while masking the diffusion layer region of the silicon substrate. Next, an oxide film is deposited on the silicon substrate, and the oxide film is buried in the trench. Then, an unnecessary portion of the oxide film protruding from the trench is removed by chemical mechanical polishing (CMP), and the main surface of the silicon substrate is planarized to form an insulating isolation structure.

In the case of an insulating isolation structure having a large surface area such as a circuit isolation region, there is a risk that so-called dishing, in which the vicinity of the center portion is excessively polished and recessed into a dish shape during the CMP process, may occur. Thus, conventionally, as seen in Patent Document 1, for example, a dummy diffusion layer is disposed in the circuit isolation region, and the insulating isolation structure in the circuit isolation region is subdivided to prevent the occurrence of dishing. .
JP 2002-190516 A

  Although the arrangement of the dummy diffusion layer in the circuit isolation region as described above is effective in suppressing the occurrence of the dishing, the dummy diffusion layer serves as a noise propagation path, so that the effect of suppressing noise propagation is limited. . In addition, due to the salicide treatment of other diffusion layers and gate electrodes, a salicide layer is also formed on the dummy diffusion layer, and a noise propagation path is formed through the surface of the dummy diffusion layer where the salicide layer is formed. Sometimes.

Incidentally, Patent Document 1 proposes a technique for suppressing noise propagation through the surface of such a dummy diffusion layer. In the semiconductor device described in Patent Document 1, as shown in FIG. 5, a plurality of dummy diffusion layers 52 partitioned by an insulating isolation layer 51 are arranged on the main surface side of the silicon substrate 50 in the circuit isolation region. . Further, in this semiconductor device, a dummy gate electrode 53 is formed so as to cover the upper surface of the dummy diffusion layer 52. In such a semiconductor device, formation of the salicide layer on the dummy diffusion layer 52 is prevented by the dummy gate electrode 53. Therefore, in such a semiconductor device, it is possible to suppress noise propagation through the surface layer of the dummy diffusion layer 52. However, since the noise propagation in the well, which is the main noise propagation path, cannot be achieved by merely forming the dummy gate electrode 53, the noise in the well, such as a triple well structure, is not possible. A separate structure for suppressing propagation is required, and the structure of the semiconductor device may be further complicated.

  The present invention has been made in view of such a situation, and a problem to be solved is to provide a semiconductor device and a method for manufacturing the same that can suitably suppress noise propagation between circuit regions. .

  According to the first aspect of the present invention, a circuit isolation region in which a dummy diffusion layer is disposed is provided between two circuit regions on a semiconductor substrate, and the upper surface of the dummy diffusion layer extends from the main surface of the semiconductor substrate. The gist is that it is dug down.

  In the above configuration, the path length of noise propagation through the surface layer of the circuit isolation region is increased by dug down the upper surface of the dummy diffusion layer. As a result, the electric resistance of the noise propagation path through the surface layer of the circuit isolation region is increased, and the noise propagation through the surface layer is suppressed.

  The dummy diffusion layer is formed by introducing impurities into such a forming substrate using ion implantation or the like using a semiconductor substrate or a well provided in the semiconductor substrate as its forming substrate. In the configuration described in (1), an impurity having a conductivity type opposite to that of the forming substrate is introduced into the dummy diffusion layer. In such a case, capacitive coupling occurs between the dummy diffusion layer having the opposite conductivity type and the base material of the dummy diffusion layer, thereby suppressing the propagation of low-frequency components of noise between the dummy diffusion layer and the formation substrate. Can do. Also, since the dummy diffusion layer and its base material are electrostatically separated and the noise propagation path through the formation base material is narrowed, the electrical resistance of such noise propagation path is increased, and the noise Propagation of high frequency components can also be suppressed. Therefore, in addition to the propagation of noise through the surface layer of the circuit isolation region, the propagation of noise through the inside of the substrate on which the dummy diffusion layer is formed is also suppressed.

  On the other hand, the invention described in claim 4 is a method of manufacturing a semiconductor device in which a circuit isolation region in which a dummy diffusion layer is arranged is provided between two circuit regions on a semiconductor substrate, the dummy diffusion layer A first step of digging down the main surface of the semiconductor substrate in the formation site of the semiconductor, and a second step of forming the dummy diffusion layer by introducing impurities into the formation site of the dummy diffusion layer dug down in the main surface The gist is to provide the above.

  According to the manufacturing method, a semiconductor device having a circuit isolation region in which a dummy diffusion layer whose upper surface is dug down from the main surface of the semiconductor substrate is arranged is manufactured. In the semiconductor device manufactured in this way, the path length of noise propagation on the surface layer of the circuit isolation region is increased by dug down the upper surface of the dummy diffusion layer, and the circuit isolation region can be formed without newly forming a special layer structure. Propagation of noise through the surface layer is suppressed.

  If the impurity introduced into the dummy diffusion layer in the second step is an impurity having a conductivity type opposite to that of the substrate for forming the dummy diffusion layer as described in claim 5, Capacitive coupling occurs between the forming base material and the dummy diffusion layer and the forming base material are electrostatically separated from each other, so that the forming base material is thinned. Therefore, in addition to the propagation of noise through the surface layer of the circuit isolation region, it is possible to manufacture a semiconductor device capable of suppressing the propagation of noise through the inside of the base material for forming the dummy diffusion layer.

By the way, when forming a bipolar transistor, a base silicon layer may be formed on the collector well by epitaxial growth. When processing such a silicon layer or polysilicon film for emitters, if the upper surface of the dummy diffusion layer is exposed without being masked, the upper surface of the dummy diffusion layer can be dug down by overetching each layer. become. Thus, if the upper surface of the dummy diffusion layer is dug in parallel with the electrode processing of the bipolar transistor as described in claim 6, the semiconductor device is manufactured without adding a new manufacturing process. Will be able to.

  Note that each of the above-described configurations and manufacturing methods includes a circuit between a digital circuit region that generates high-frequency noise when operated at high speed and an analog circuit region that is susceptible to such high-frequency noise. By applying it to a semiconductor device provided with an isolation region and its manufacture, a more remarkable effect can be obtained.

  According to the semiconductor device and the manufacturing method thereof of the present invention, it is possible to suitably suppress noise propagation between circuit regions.

  DESCRIPTION OF EMBODIMENTS Hereinafter, an embodiment embodying a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to FIGS.

  FIG. 1 shows a partial cross-sectional structure of the semiconductor device of this embodiment. As shown in the figure, an analog circuit region in which an analog circuit is formed and a digital circuit region in which a digital circuit is formed are formed on the silicon substrate 10, and a circuit isolation region is formed between these two circuit regions. Is formed. The width of the circuit isolation region is about 100 to 200 micrometers.

  An insulating film layer 11 made of silicon oxide is stacked on the main surface Sa of the silicon substrate 10. On the insulating film layer 11, an aluminum signal wiring for electrically connecting the elements and the like is formed. As such signal wiring, a signal wiring 15 electrically connected to the analog circuit region and the digital circuit region is formed so as to straddle the circuit isolation region.

In the cross section of the silicon substrate 10 shown in FIG. 1, a bipolar transistor 20 is formed in the analog circuit region, and a CMOS (Complementary) is formed in the digital circuit region.
Metal Oxide Semiconductor) transistor 30 is formed. In the cross section shown in the figure, only a part of the analog circuit area and the digital circuit area is displayed, and a large number of other elements are formed in the analog circuit area and the digital circuit area, respectively.

  The bipolar transistor 20 in the analog circuit region is formed on an n-conductivity type collector well 21 formed in the silicon substrate 10, a base region 22 formed on the collector well 21, and further on the base region 22. An emitter region 23 is provided.

  The base region 22 is formed of a p conductivity type epitaxial silicon layer epitaxially grown on the collector well 21. The emitter region 23 is formed of an n-conductivity type polysilicon layer formed on the base region 22 by using a chemical vapor deposition (CVD) method. The surface of the collector well 21 is partitioned into two active regions by an insulating isolation layer 13 formed by an STI process. The base region 22 and the emitter region 23 are formed in one of the two active regions thus partitioned, and the collector lead portion 24 into which high-concentration n-conductivity type impurities are implanted is formed in the other. An insulating isolation layer 13 formed by an STI process is formed below the main surface Sa of the silicon substrate 10 so as to surround the periphery of the bipolar transistor 20.

On the other hand, the CMOS transistor 30 in the digital circuit area includes a pMOS formed on an n-well 31 formed in the silicon substrate 10 and an nMOS formed on a p-well formed in the silicon substrate 10. ing. The pMOS is arranged on the main surface of the silicon substrate 10 between the source 32 and the drain 33 each formed by a p conductivity type diffusion layer formed under the surface of the n-well 31 and an insulating film therebetween. A p-conductivity type polysilicon gate 34 is provided. The nMOS has a source 35 and a drain 36 each formed by an n conductivity type diffusion layer formed below the surface of the p-well 38, and an insulating film on the main surface of the silicon substrate 10 between these two regions. An n-conductivity type polysilicon gate 37 is provided. Under the main surface Sa of the silicon substrate 10, an insulating isolation layer 13 formed by an STI process is formed so as to partition the pMOS and the nMOS and surround the periphery of the CMOS transistor 30.

  A p-well 12 is formed in the silicon substrate 10 in the circuit isolation region interposed between the analog circuit region and the digital circuit region, and a dummy doped with n-conductivity type impurities is formed on the main surface side thereof. A plurality of diffusion layers 14 are arranged. In the circuit isolation region, an insulating isolation layer 13 formed by an STI process is formed so as to surround each dummy diffusion layer 14. In FIG. 1, only two of the plurality of dummy diffusion layers 14 are displayed.

  In the semiconductor device of this embodiment, the upper surface Sb of the dummy diffusion layer 14 in the circuit isolation region is dug down from the main surface Sa of the silicon substrate 10, and the interface between the silicon substrate 10 and the insulating film layer 11 is a dummy. The diffusion layer 14 is recessed in the silicon substrate 10. The depth of digging of the upper surface Sb of the dummy diffusion layer 14 from the main surface Sa of the silicon substrate 10 is the interface between the well and the lower layer of the diffusion layer formed in the well in each element of each circuit region. This is almost the same as the formation depth of the pn junction.

  FIG. 2 shows a noise propagation mode between circuit regions via the circuit isolation region in the semiconductor device of the present embodiment formed as described above. As shown in the figure, noise generated in the digital circuit area is propagated to the analog circuit area through three propagation paths A to C. That is, the propagation path A that passes through the surface layer of the silicon substrate 10 in the circuit isolation region and the interface between the silicon substrate 10 and the insulating film layer 11, the propagation path B that passes through the p-well 12 in the circuit isolation region, and the base material of the silicon substrate 10 A propagation path C passing through the inside is a noise propagation path. Among these, the propagation path B is the largest noise propagation path.

  In the semiconductor device of this embodiment, as described above, the upper surface Sb of the dummy diffusion layer 14 in the circuit isolation region is dug down from the main surface Sa of the silicon substrate 10, and the path length of the propagation path A is accordingly It is getting longer. Therefore, the electrical resistance of the noise propagation path A through the surface layer of the circuit isolation region is increased, and the noise propagation through the propagation path A is suppressed.

  Further, in the semiconductor device of this embodiment, n-type conductivity type impurities having a conductivity type opposite to that of the p-well 12 serving as the formation substrate are introduced into the dummy diffusion layer 14, and the dummy diffusion layers 14 having different conductivity types are introduced. And capacitive coupling occurs between the p-well 12 and the p-well 12. Therefore, propagation of low frequency components of noise between the dummy diffusion layer 14 and the p well 12 is suppressed. Further, since the dummy diffusion layer 14 and the p-well 12 which is a base material for the dummy diffusion layer 14 are electrostatically insulated and the noise propagation path B is narrowed to increase its electric resistance, noise through the propagation path B is increased. The propagation of high frequency components is also suppressed.

Further, in the semiconductor device of this embodiment, the signal wiring 15 passing over the circuit isolation region is separated from the dummy diffusion layer 14 by digging the upper surface Sb of the dummy diffusion layer 14. And the parasitic capacitance generated between the dummy diffusion layers 14 is reduced. As a result, the deterioration of the signal passing through the signal wiring 15 is suppressed, and the influence of noise on the element driven by the signal is also reduced.

  Next, the manufacturing mode of the semiconductor device of the present embodiment described above will be described with reference to FIG. 3 focusing on the manufacturing process related to the formation of the circuit isolation region.

  First, as shown in FIG. 3A, an insulating isolation layer 13 is formed in a silicon substrate 10 by an STI process, a collector well 21 of the bipolar transistor 20, a p-well 12 in a circuit isolation region, a CMOS Wells such as an n well 31 and a p well 38 of the transistor 30 are formed by ion implantation or the like.

  Subsequently, as shown in FIG. 3B, after the insulating film 11a and the laminated film 11b of the poly silicon are formed on the silicon substrate 10, the formation portion of the base region 22 of the bipolar transistor 20 and the dummy diffusion layer 14 are formed. Masking is performed so as to expose only the formed portion, and the silicon film 22a constituting the base region 22 is epitaxially grown. Then, as shown in FIG. 3C, unnecessary portions of the silicon film 22a are etched. At this time, the upper surface Sb of the p well 12 in which the dummy diffusion layer 14 is formed is dug down from the main surface Sa of the silicon substrate 10 by overetching.

  Next, as shown in FIG. 4D, a polysilicon film 23a constituting the emitter region 23 of the bipolar transistor 20 is formed on the silicon substrate 10 by CVD, and doping is performed by ion implantation. Further, as shown in FIG. 4E, a silicon nitride film 11c serving as an implantation mask is deposited on the formed polysilicon film 23a. Then, as shown in FIG. An unnecessary portion of the film 23a is etched. At this time, the upper surface Sb of the p well 12 where the dummy diffusion layer 14 is formed is further dug down from the main surface Sa of the silicon substrate 10 by overetching again.

  When processing the base region 22 and the emitter region 23 which are the electrodes of the bipolar transistor 20, the main surface Sa of the silicon substrate 10 other than the electrode forming portion is usually masked. However, in the present embodiment, as described above, since the upper surface Sb of the portion where the dummy diffusion layer 14 is formed is processed without being masked, it is processed simultaneously with the electrode processing of the bipolar transistor 20. The upper surface Sb of the dummy diffusion layer 14 is dug down from the main surface Sa of the silicon substrate 10.

  After the electrode processing of the bipolar transistor 20 is performed in this way, as shown in FIG. 4G, the collector extraction portion 24 and the external base layer are formed by ion implantation, and the dug-down dummy diffusion layer 14 is formed. Ion implantation of n-type impurities is performed on the formation portion. In parallel with the formation of each structure of the bipolar transistor 20 and the circuit isolation region, the formation of the polysilicon gates 34 and 37 of the CMOS transistor 30 and the formation of the sources 32 and 35 and the drains 33 and 36 are also performed. Done. Further, the insulating film layer 11 is formed on the silicon substrate 10 and signal wirings and electrodes are formed, whereby the semiconductor device as shown in FIG. 1 is manufactured.

  According to the semiconductor device of this embodiment described above, the following effects can be obtained.

  By digging down the upper surface Sb of the dummy diffusion layer 14, the path length of noise propagation through the surface layer of the circuit isolation region is increased, and noise propagation through the surface layer can be suppressed.

  Since the dummy diffusion layer 14 has a conductivity type opposite to that of the p-well 12 as a forming substrate, capacitive coupling occurs between them, and the dummy diffusion layer 14 and the p-well 12 are electrostatically Since the noise propagation path is narrowed by being insulated, noise propagation through the p-well 12 can be suppressed.

  By dug down the dummy diffusion layer 14, the signal wiring 15 formed on the circuit isolation region is separated from the dummy diffusion layer 14, and the parasitic capacitance generated between them is reduced. Deterioration can be suppressed and the influence of noise can be reduced.

  Since the upper surface Sb of the dummy diffusion layer 14 is dug down in parallel with the electrode processing of the bipolar transistor 20, it can be manufactured without adding a new manufacturing process.

  In addition, the said embodiment can also be changed and implemented as follows.

  For the convenience of the manufacturing process of other structures, the depth of the upper surface Sb of the dummy diffusion layer 14 is preferably about the formation depth of the pn coupling of each element, but even if it is shallower than that, Even if it is deep, the path length of noise propagation through the surface layer of the circuit isolation region is still increased, and noise propagation on the surface layer can be suppressed.

  Even if the conductivity types of the well and the dummy diffusion layer in the circuit isolation region are reversed, that is, the p conductivity type dummy diffusion layer is formed in the n conductivity type well, the in-well propagation noise in the circuit isolation region Can be suppressed. In the case where the dummy diffusion layer is directly formed on the semiconductor substrate itself, the propagation noise in the well can be similarly suppressed if the dummy diffusion layer has a conductivity type opposite to that of the semiconductor substrate.

  If the suppression of noise propagation in the well is not particularly required, the conductivity type of the dummy diffusion layer may be the same as the conductivity type of the well serving as the base material. Even in this case, if the upper surface Sb of the dummy diffusion layer is dug down from the main surface Sa of the silicon substrate 10, the noise propagation on the surface layer of the circuit isolation region is suppressed, and the parasitic capacitance of the signal wiring passing through the circuit isolation region is reduced. It is possible to reduce this.

  If the addition of a new manufacturing process is permitted, the upper surface of the dummy diffusion layer may be dug separately from the upper surface of the well related to the formation of the epitaxial layer. In addition, if there are other manufacturing processes in which the main surface of the silicon substrate is dug down, the upper surface of the dummy diffusion layer may be dug down at the same time.

  The structure of the circuit isolation region in the above embodiment can be applied in the same or a similar manner as a structure related to insulation isolation between circuit regions other than between the analog and digital circuit regions.

1 is a cross-sectional view of a circuit isolation region and its periphery in a semiconductor device according to an embodiment of the present invention. The schematic diagram which shows the noise propagation aspect in the circuit isolation | separation area | region in the semiconductor device. (A)-(c) Sectional drawing which each shows the cross-sectional structure of the circuit isolation region vicinity in the manufacture process of the semiconductor device. (D)-(g) Sectional drawing which each shows the cross-sectional structure of the circuit isolation region vicinity in the manufacture process of the semiconductor device. Sectional drawing of the circuit isolation region vicinity of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate (semiconductor substrate), 11 ... Insulating film layer, 11a ... Insulating film, 11b ... Polysilicon laminated film, 11c ... Silicon nitride film, 12 ... P well (dummy diffusion layer forming base material), 13 ... Insulating isolation layer, 14 ... dummy diffusion layer, 15 ... signal wiring, 20 ... bipolar transistor, 21 ... collector well, 22 ... base region (electrode of bipolar transistor), 22a ...
Silicon film, 23... Emitter region (electrode of bipolar transistor), 23 a... Polysilicon film, 24... Collector extraction part, 30... CMOS transistor, 31. 37, polysilicon gate, 38, p well, Sa, main surface of silicon substrate, Sb, upper surface of dummy diffusion layer.

Claims (7)

A circuit isolation region in which a dummy diffusion layer is arranged is provided between two circuit regions on a semiconductor substrate,
A semiconductor device, wherein an upper surface of the dummy diffusion layer is dug down from a main surface of the semiconductor substrate.   The semiconductor device according to claim 1, wherein an impurity having a conductivity type opposite to that of the base material for forming the dummy diffusion layer is introduced into the dug down dummy diffusion layer.   The semiconductor device according to claim 1, wherein the circuit isolation region is provided between an analog circuit region and a digital circuit region. A method of manufacturing a semiconductor device in which a circuit isolation region in which a dummy diffusion layer is disposed is provided between two circuit regions on a semiconductor substrate,
A first step of digging down the main surface of the semiconductor substrate at the formation site of the dummy diffusion layer;
A second step of forming the dummy diffusion layer by introducing impurities into the formation site of the dummy diffusion layer dug down on the main surface;
A method for manufacturing a semiconductor device, comprising:   5. The method of manufacturing a semiconductor device according to claim 4, wherein the impurity introduced into the dummy diffusion layer in the second step is an impurity having a conductivity type opposite to a substrate on which the dummy diffusion layer is formed.   6. The manufacturing of a semiconductor device according to claim 4, wherein the digging is performed in the first step in parallel with the electrode processing of the bipolar transistor formed on the main surface of the semiconductor substrate. Method.   The semiconductor device manufacturing method according to claim 4, wherein the circuit isolation region is provided between an analog circuit region and a digital circuit region.

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