JP2004096104A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which uses a SOI substrate, has a fined trench-type element separated area and can exhibit high dielectric strength and to provide a method of manufacturing the same. <P>SOLUTION: The trench-type element separating area Treis which separates activated areas 1a, 1b where MISFETs are formed is provided with a side wall insulator film 7 which covers both sides of the trench, a first conductive-type polycrystal semiconductor layer 9 which covers the side wall insulator film 7, and a second conductive-type polycrystal semiconductor layer 11 which fills up a space between the first conductive-type polycrystal semiconductor layers 9. Two pn bonded sections Jpn1, Jpn2 which extend toward the depth direction of the trench are formed between the first conductive-type polycrystal semiconductor layer 9 and the second conductive-type polycrystal semiconductor layer 11. If a voltage is applied between the activated areas 1a, 1b, since a depletion layer expands in either of pn-bonded areas, the voltage is also distributed to the depletion layer and an electric field in the side wall insulator film 7 is relaxed. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a semiconductor device provided using an SOI substrate and a method for manufacturing the same.

(4) In recent years, as semiconductor elements such as transistors have become smaller, a trench-type element isolation structure has been adopted as a method for element isolation in a semiconductor integrated circuit. This trench-type element isolation structure is a method of forming a trench (groove) so as to divide an active region in a surface region of a semiconductor substrate and providing an insulator film in the trench, thereby isolating adjacent active regions. It is.

In particular, in a semiconductor device using an SOI (Silicon On Insulator) substrate having a semiconductor layer for providing an active region on an insulating layer, forming a trench so as to reach this insulating layer ensures an element. Separation can be performed. For example, in Patent Literature 1, after using an SOI substrate formed by a bonding method, a trench reaching an insulating layer is formed in a semiconductor layer, and a thermal oxide film (sidewall insulating film) is formed on a side surface of the trench. By filling the space between the sidewall insulating films on both sides of the trench with polycrystalline silicon, a trench-type element isolation region is formed.
JP-A-61-059852 (abstract)

However, in the element isolation region of the conventional semiconductor device described in the above publication, when a high voltage is applied between the active regions at both ends of the element isolation region, a high voltage is applied to the sidewall insulating film (thermal oxide film) of the element isolation region. Intensively applied, it was found that the breakdown voltage characteristics were not good. On the other hand, if the thermal oxide film is made sufficiently thick, the withstand voltage is improved, but when a thick thermal oxide film is formed by a long-time thermal oxidation process, a large stress is applied to the active region because the thermal oxide film expands in volume. Crystal defects occur in the semiconductor crystal in the active region. When a crystal defect occurs, the current driving capability of the transistor may be deteriorated.

Note that even in a semiconductor device having an element isolation region formed by burying an insulator such as a CVD oxide film in the entire trench, a large stress due to a difference in thermal expansion coefficient between the insulator and the semiconductor is applied to the active region. May be present.

SUMMARY OF THE INVENTION It is an object of the present invention to improve the withstand voltage of a semiconductor device having a trench isolation structure using an SOI substrate, while suppressing the occurrence of stress in an active region, while reducing the concentration of an applied voltage on an insulating film on the trench side wall. It is to plan.

A semiconductor device according to the present invention is a semiconductor device using an SOI substrate, comprising: a side wall insulating film covering both side surfaces of the trench; and a pn junction interposed between the side wall insulating films on both sides and extending in the depth direction of the trench. A crystalline semiconductor region.

Thus, when a voltage is applied between the active regions on both sides of the element isolation region, the voltage is distributed not only to the sidewall insulating film but also to the depletion layer generated at the pn junction, so that the width of the element isolation region is narrow and the side wall is narrow. Even when the insulating film is thin, high withstand voltage can be exhibited. Therefore, withstand voltage can be improved while suppressing occurrence of embezzlement in the active region.

The polycrystalline semiconductor region includes two first conductive type polycrystalline semiconductor layers covering each side surface of the sidewall insulating film on both sides, and a second conductive type polycrystalline semiconductor layer interposed between the first conductive type polycrystalline semiconductor layers on both sides. By including the crystalline semiconductor layer, a high withstand voltage can be reliably exerted even if a high voltage is applied to any of the active regions.

Since the first conductive type polycrystalline semiconductor layer has a sidewall type structure formed by etching back the polycrystalline semiconductor layer, a mask is formed in a lateral dimension of the first conductive type polycrystalline semiconductor layer. It is not necessary to provide a margin in consideration of the positional deviation, and a structure suitable for a miniaturized semiconductor device can be obtained.

場合 When the semiconductor layer is made of single-crystal silicon, the polycrystalline semiconductor region is preferably made of polycrystalline silicon.

According to the method of manufacturing a semiconductor device of the present invention, a trench is formed in a region where an element isolation region of a semiconductor layer of an SOI substrate is to be formed, a sidewall insulating film is formed, and a sidewall insulating film on both sides of the trench is formed. Forming a first conductive type polycrystalline semiconductor layer covering each side surface of the sidewall insulating film and a second conductive type polycrystalline semiconductor layer interposed between the first conductive type polycrystalline semiconductor layers on both sides; It is.

According to this method, a pn junction extending in the depth direction of the trench is formed at the boundary between the two first conduction type polycrystalline semiconductor layers and the second conduction type polycrystalline semiconductor layer sandwiched between the two layers. A semiconductor device with a high withstand voltage can be obtained.

As a method of forming the first conduction type polycrystalline semiconductor film and the second conduction type polycrystalline semiconductor film, after burying a non-doped polycrystalline semiconductor film in a trench, implantation of a first conduction type impurity ion, There is a method of performing implantation of type impurity ions or utilizing CVD with in-situ doping.

According to the semiconductor device or the method of manufacturing the same of the present invention, the voltage applied to the active region on both sides of the element isolation region is distributed not only to the sidewall insulating film but also to the depletion layer at the pn junction in the polycrystalline semiconductor region. Therefore, high withstand voltage can be exhibited while suppressing application of stress to the active region.

(1st Embodiment)
-Structure of semiconductor device-
FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to the first embodiment using an SOI substrate. As shown in FIG. 1, the semiconductor device according to the present embodiment includes an insulating layer 2 having a thickness of 900 nm provided on a main surface of a semiconductor substrate 3 made of single crystal silicon, and a thickness provided on the insulating layer 2. It is formed using an SOI substrate having a semiconductor layer 1 of 3.5 μm single crystal silicon.

The semiconductor layer 1 is divided into a large number of active regions 1a, 1b,... By the trench-type element isolation region Treis, but FIG. 1 shows only two active regions 1a, 1b. The active region 1a is provided with a p-channel MISFET (hereinafter, referred to as pMISFET), and the active region 1b is provided with an n-channel MISFET (hereinafter, referred to as nMISFET). The substrate region in the active region 1a contains a low-concentration n-type impurity (phosphorous or arsenic), and the substrate region in the active region 1b contains a low-concentration p-type impurity (boron).

A gate insulating film 21a made of a silicon oxide film, a silicon oxynitride film, or the like, and a gate electrode 22a made of polycrystalline silicon containing a p-type impurity (boron) are provided on the active region 1a as elements of the pMISFET. ing. In the active region 1a, regions located on both sides of the gate electrode 22a are an extension region containing a low concentration p-type impurity (boron) and a high concentration source / drain containing a high concentration p-type impurity (boron). A source / drain region 23a composed of a region is formed.

On the active region 1b, as an nMISFET element, a gate insulating film 21b made of a silicon oxide film, a silicon oxynitride film, and the like, and a gate electrode 22b made of polycrystalline silicon containing an n-type impurity (phosphorous or arsenic) are provided. Is provided. In the active region 1b, regions located on both sides of the gate electrode 22b include an extension region containing a low-concentration n-type impurity (phosphorus or arsenic) and a high-concentration region containing a high-concentration n-type impurity (phosphorus or arsenic). A source / drain region 23b composed of a concentration impurity diffusion region is formed.

Here, the structure of the trench-type element isolation region Treis, which is a feature of the present embodiment, will be described. The trench-type element isolation region Treis of the present embodiment has two sidewall insulating layers each made of a 100-nm-thick silicon oxide film (thermal oxide film) covering the side surface of the trench penetrating the semiconductor layer 1 and reaching the insulating layer 2. The semiconductor device includes a film, two first conductive type polycrystalline semiconductor layers covering the sidewall insulating films, and a second conductive type polycrystalline semiconductor layer filling a space between the first conductive type polycrystalline semiconductor layers. ing. In the present embodiment, the first conductivity type polycrystalline semiconductor layer 9 is an n-type polycrystalline silicon film having a lateral thickness of 300 nm and containing an n-type impurity (for example, phosphorus or arsenic) having a concentration of about 5 × 10 ¹⁶ cm ^−3. The second conductivity type polycrystalline semiconductor layer 11 is a p-type polycrystalline silicon film containing a p-type impurity (for example, boron) having a concentration of about 5 × 10 ¹⁶ cm ⁻³ . Two pn junctions Jpn1 and Jpn2 extending in the vertical direction (depth direction) are formed between the first conduction type polycrystalline semiconductor layer 9 and the second conduction type polycrystalline semiconductor layer 11. That is, the first conductivity type polycrystalline semiconductor layer 9 and the second conductivity type polycrystalline semiconductor layer 11 form a semiconductor region having a pn junction Jpn extending in the depth direction of the trench.

However, even if the first conductive type polycrystalline semiconductor layer 9 is a p-type polycrystalline silicon film and the second conductive type polycrystalline semiconductor layer 11 is an n-type polycrystalline silicon film, the first conductive type polycrystalline semiconductor layer 9 may be formed. Since two pn junctions extending in the depth direction of the trench are formed between the second conduction type polycrystalline semiconductor layer 11 and the second conductivity type polycrystalline semiconductor layer 11, the function and effect of the present embodiment described later can be exerted. Since the lateral dimension of the trench is not always constant, the lateral dimension of the second conductivity type polycrystalline semiconductor layer 11 also differs depending on the location.

According to the semiconductor device of the present embodiment, the first conductive type polycrystalline semiconductor layer 9 and the second conductive type polycrystalline semiconductor layer 11 are provided in the trench type element isolation region Treis for separating the active regions 1a and 1b. Therefore, two pn junctions Jpn extending in the vertical direction are formed. With this structure, even when a voltage is applied between the source / drain regions 23a and 23b of the active region 1a and the active region 1b, a depletion layer expands in one of the two pn junctions Jpn1 and Jpn2. For example, when a high voltage at which the first active region 1a is at a high potential is applied, a depletion layer spreads at the pn junction Jpn2, so that the voltage is also distributed to this depletion layer and an electric field to the side wall insulating film 7 is generated. Concentration is reduced, and a sufficient breakdown voltage can be obtained even when the width of the trench isolation region Treis is narrow and the side wall insulating film 7 is thin. Therefore, according to the semiconductor device of the present embodiment, a high withstand voltage can be exhibited while reducing the generation of stress in the active regions 1a and 1b.

Note that the SOI substrate of the present embodiment is prepared by any method such as a known bonding method, a method of providing a BOX layer by implanting oxygen ions, and a method of epitaxially growing a semiconductor layer on an insulating substrate. Even so, the above-described effects can be exerted.

Further, the semiconductor material forming the SOI substrate is not limited to silicon, but the material forming the first and second conductivity type polycrystalline semiconductor layers 9 and 11 is the same as the semiconductor material forming the semiconductor layer 1. Preferably they are the same. If the semiconductor material forming the first and second conductivity type polycrystalline semiconductor layers 9 and 11 and the semiconductor material forming the semiconductor layer 1 are the same, there is almost no difference in the coefficient of thermal expansion between the two. , 1b can be further suppressed.

-Manufacturing method of semiconductor device-
FIGS. 2A to 4B are cross-sectional views illustrating the manufacturing steps of the semiconductor device of the first embodiment.

First, in a step shown in FIG. 2A, an SOI substrate having a semiconductor layer 1, a semiconductor substrate 3, and an insulating layer 2 interposed between the semiconductor layer 1 and the semiconductor substrate 3 is used. A pad oxide film 4 is formed on the main surface by a thermal oxidation method or a CVD method. Further, a nitride film 5 serving as an etching stopper is formed on the pad oxide film 4 by a CVD method.

Next, in the step shown in FIG. 2B, anisotropic dry etching is performed using a resist film (not shown) formed by photolithography as a mask, and the nitride film 5 and the pad oxide film 3 are patterned. An opening for a trench is formed. Then, anisotropic dry etching is performed using the nitride film 5 as a mask to form a trench 6 that penetrates the semiconductor layer 1 and reaches the insulating layer 2.

Next, in the step shown in FIG. 2C, a sidewall insulating film 7 (thermal oxide film) covering the side surface of the trench 6 (the side surface of the semiconductor layer 1) is formed by a thermal oxidation method.

Next, in the step shown in FIG. 3A, a non-doped polycrystalline silicon film 8 is deposited on the substrate by the CVD method. Thereby, the inside of the trench 6 is filled with the non-doped polycrystalline silicon film 8.

Next, in the step shown in FIG. 3B, anisotropic dry etching is performed using the nitride film 5 as an etching stopper to etch back the non-doped polycrystalline silicon film 8. As a result, portions of the non-doped polycrystalline silicon film 8 protruding from the trench 6 are removed. Further, ion implantation of an n-type impurity (for example, phosphorus) is performed using the nitride film 5 and the pad oxide film 4 as a mask, thereby changing the non-doped polycrystalline silicon film 8 to the first conductivity type polycrystalline semiconductor layer 9. At this time, when the dose is 2.9 × 10 ¹² cm ⁻² , the implantation energy is 800 keV, when the dose is 3.2 × 10 ¹² cm ⁻² , the implantation energy is 200 keV, and the dose is 3.8 × 10 ¹² cm ^{−. In step 2} , ion implantation is performed in three stages with an implantation energy of 4000 keV. Then, the trench 6 is filled with the first conductivity type polycrystalline semiconductor layer 9.

Next, in the step shown in FIG. 3C, after removing the nitride film 5 and the pad oxide film 3, an oxide film 10 for an implantation mask is deposited on the substrate. Then, the oxide film 10 is patterned by photolithography and dry etching to form an opening 10 a having a width smaller than the width of the trench 6.

Next, in the step shown in FIG. 4A, ions of a p-type impurity (for example, boron) are implanted using the oxide film 10 as a mask, and the first conductive type polycrystalline semiconductor layer 9 in the trench 6 is formed. A part (central part) is changed to the second conductivity type polycrystalline semiconductor layer 11. At this time, the dose amount is 400keV are implanted energy 1.4 × 10 ¹² cm ^-2, dose injection energy 1.5 × 10 ¹² cm ^-2 1200keV, dose 1.9 × 10 ¹² cm ^{- In step 2} , ion implantation is performed in three stages at an implantation energy of 2000 keV.

(4) Finally, in the step shown in FIG. 4B, the oxide film 10 is removed by etching. As a result, a trench isolation region Treis having the sidewall insulating film 7, the first conductive type polycrystalline semiconductor layer 9, and the second conductive type polycrystalline semiconductor layer 11 is formed.

Although illustration of subsequent steps is omitted, the gate insulating film, gate electrode, extension region, sidewall, and high concentration impurity diffusion region are formed using a general CMOS process, and the structure shown in FIG. A semiconductor device having the same.

に よ り The structure of the semiconductor device shown in FIG. 1 can be easily obtained by the method for manufacturing a semiconductor device of the present embodiment.

-Manufacturing method according to a modification of the first embodiment-
In the first embodiment, when the trench 6 is filled with the first conductivity type polycrystalline semiconductor layer 9, the non-doped polycrystalline silicon film 8 is deposited on the substrate in the step shown in FIG. In the step shown in FIG. 3B, the non-doped polycrystalline silicon film 8 is changed to a first conductivity type polycrystalline semiconductor film 9 by ion implantation of an n-type impurity.

On the other hand, in this modification, in the step shown in FIG. 3A, a polycrystalline silicon film containing an n-type impurity is deposited on a substrate by CVD with in-situ doping of an n-type impurity, and then dry etching is performed. As a result, the portion of the polycrystalline silicon film protruding from trench 6 is removed to form first conductivity type polycrystalline semiconductor layer 9.

The other steps are the same as the manufacturing steps of the first embodiment shown in FIGS. 2A to 4B. Also in this modified example, the same operation and effect as in the first embodiment can be exhibited. In particular, according to this method, it is possible to obtain the first conductivity type polycrystalline semiconductor layer 9 having a more uniform impurity concentration distribution than in the first embodiment, so that it is possible to suppress the variation in breakdown voltage. Become.

(Second embodiment)
In the method of manufacturing a semiconductor device according to the first embodiment or a modification of the first embodiment, when forming the second conductivity type polycrystalline semiconductor layer 11, the first conductivity type polycrystalline semiconductor layer 11 is formed by ion implantation. Although a part of the crystalline semiconductor layer 9 is changed to the second conductivity type polycrystalline semiconductor layer 11, in the method of manufacturing a semiconductor device according to the second embodiment, the second conductivity type polycrystalline semiconductor layer 11 is formed by CVD with in-situ doping. A method for forming a polycrystalline semiconductor layer is employed.

FIGS. 5A to 5C are cross-sectional views illustrating the steps of manufacturing the semiconductor device according to the second embodiment. Also in the present embodiment, before the process shown in FIG. 5A, the manufacturing process of the first embodiment or the modification of the first embodiment shown in FIGS. 2A to 3B is performed. Then, a pad oxide film 4, a nitride film 5, a trench 6, a side wall insulating film 7, and a first conductivity type polycrystalline semiconductor layer 9 are formed. However, in order to avoid duplication, illustration of steps prior to the step shown in FIG.

(5) In the step shown in FIG. 5A, after removing the pad oxide film 4 and the nitride film 5, a pad oxide film 13 and a nitride film 14 are newly deposited on the substrate. Then, the nitride film 14 and the pad oxide film 13 are patterned by photolithography and dry etching to form an opening 14 a having a width smaller than the width of the trench 6.

Next, in the step shown in FIG. 5B, the central portion of the first conductivity type polycrystalline semiconductor layer 9 is removed using the nitride film 14 as a mask, and a small trench 15 reaching the insulating layer 2 is formed.

Next, in a step shown in FIG. 5C, a p-type polycrystalline silicon film is deposited on the substrate by CVD accompanied with in-situ doping of a p-type impurity, and the inside of the small trench 15 is p-type polycrystalline. Fill with a silicon film. Further, the portion of the p-type polycrystalline silicon film protruding from the small trench 15 is removed by dry etching to form the second conductivity type polycrystalline semiconductor layer 11. At this time, the nitride film 14 is used as an etching stopper. As a result, a trench isolation region Treis having the sidewall insulating film 7, the first conductive type polycrystalline semiconductor layer 9, and the second conductive type polycrystalline semiconductor layer 11 is formed.

Although illustration of subsequent steps is omitted, after the pad oxide film 13 and the nitride film 14 are removed, a gate insulating film, a gate electrode, an extension region, a sidewall, a high-concentration impurity diffusion region are formed by using a general CMOS process. Is performed to obtain a semiconductor device having the structure shown in FIG.

(Third embodiment)
-Structure of semiconductor device-
FIG. 6 is a cross-sectional view illustrating a structure of a semiconductor device according to the third embodiment using an SOI substrate. As shown in FIG. 6, the semiconductor device according to the present embodiment includes an insulating layer 2 having a thickness of 900 nm provided on a main surface of a semiconductor substrate 3 made of single crystal silicon and a thickness provided on the insulating layer 2. It is formed using an SOI substrate having a semiconductor layer 1 of 3.5 μm single crystal silicon.

The semiconductor layer 1 is divided into a large number of active regions 1a, 1b,... By the trench-type element isolation region Treis, but FIG. 6 shows only two active regions 1a and 1b. The active region 1a is provided with a pMISFET having a structure similar to that of the first embodiment, and the active region 1b is provided with an nMISFET having a structure similar to that of the first embodiment. The substrate region in the active region 1a contains a low-concentration n-type impurity (phosphorous or arsenic), and the substrate region in the active region 1b contains a low-concentration p-type impurity (boron).

Here, the structure of the trench-type element isolation region Treis, which is a feature of the present embodiment, will be described. The trench-type element isolation region Treis of the present embodiment has a side wall made of a silicon oxide film (thermal oxide film) having a lateral thickness of 100 nm at the bottom covering the side surface of the trench that reaches the insulating layer 2 through the semiconductor layer 1. The insulating film 7, a sidewall-type first conductivity-type polycrystalline semiconductor layer 9 ′ that covers the sidewall insulating films 7 on both sides of the trench 6, and a space between the first conductivity-type polycrystalline semiconductor layers 9 ′ on both sides is filled. And a second conductivity type polycrystalline semiconductor layer 11. In the present embodiment, the first conductivity type polycrystalline semiconductor layer 9 ′ is an n-type polycrystalline silicon film having a lateral thickness of 300 nm at the bottom containing an n-type impurity (for example, phosphorus or arsenic), and The type polycrystalline semiconductor layer 11 is a p-type polycrystalline silicon film containing a p-type impurity (for example, boron). In the present embodiment, the first conductivity type polycrystalline semiconductor layer 9 ′ is formed by etching back a polycrystalline silicon film, so that the first conductivity type polycrystalline semiconductor layer 9 ′ and the second conductivity type Two pn junctions Jpn1 and Jpn2 extending slightly in the vertical direction (depth direction) are formed between the pn junctions and the polycrystalline semiconductor layer 11.

Also in the present embodiment, even if the first conductivity type polycrystalline semiconductor layer 9 ′ is a p-type polycrystalline silicon film and the second conductivity type polycrystalline semiconductor layer 11 is an n-type polycrystalline silicon film, Since two pn junctions extending in the depth direction of the trench are formed between the polycrystalline semiconductor layer 9 ′ and the second conductivity type polycrystalline semiconductor layer 11, the operation and effect of the present embodiment as described later can be achieved. Can demonstrate. Since the lateral dimension of the trench is not always constant, the lateral dimension of the second conductivity type polycrystalline semiconductor layer 11 also differs depending on the location.

According to the semiconductor device of the present embodiment, the first conductive type polycrystalline semiconductor layer 9 'and the second conductive type polycrystalline semiconductor layer 11 are provided in the trench type element isolation region Treis for separating the active regions 1a and 1b. Therefore, two pn junctions Jpn that are slightly inclined and extend in the vertical direction are formed. With this structure, as in the first embodiment, even when a voltage is applied between each of the source / drain regions 23a and 23b of the active region 1a and the active region 1b, of the two pn junctions Jpn1 and Jpn2, The depletion layer expands in either one. Therefore, according to the semiconductor device of the present embodiment, similarly to the first embodiment, a high withstand voltage can be exhibited while reducing the generation of stress in the active regions 1a and 1b.

In particular, in the present embodiment, the first conductive type polycrystalline semiconductor layer 9 ′ is formed in a self-aligned manner by etching back the polycrystalline silicon film. Can be set without providing a margin in consideration of the mask displacement, which is a structure particularly advantageous for miniaturization of a semiconductor device.

-Semiconductor device manufacturing process-
FIGS. 7A to 7C are cross-sectional views illustrating manufacturing steps of a semiconductor device according to the third embodiment. Also in the present embodiment, before the process shown in FIG. 7A, the manufacturing process of the first embodiment shown in FIGS. , Trench 6 and side wall insulating film 7 are formed. However, in order to avoid duplication, illustration of steps prior to the step shown in FIG. 7A is omitted.

7) In the step shown in FIG. 7A, the first conductivity type polycrystalline semiconductor film 9x is deposited on the substrate by CVD involving in-situ doping of an n-type impurity. Thereby, the inside of trench 6 is filled with first conductivity type polycrystalline semiconductor film 9x. However, the first conductivity type polycrystalline semiconductor film 9x may be formed by depositing a non-doped polycrystalline silicon film and then ion-implanting an n-type impurity.

Next, in the step shown in FIG. 7B, anisotropic dry etching is performed using the nitride film 5 as an etching stopper, and the n-type polycrystalline semiconductor film 9x is etched back until the insulating layer 2 is exposed. As a result, a first conductivity type polycrystalline semiconductor layer 9 'covering the side surfaces of the trench 6 (each side surface of the side wall insulating film 7, the pad oxide film 4, and the nitride film 5) is formed.

Next, in the step shown in FIG. 7C, a 4 μm-thick p-type polycrystalline silicon film is deposited on the substrate by CVD with in-situ doping of a p-type impurity, and the inside of the trench 6 is p-type. Is filled with a polycrystalline silicon film. Further, the portion of the p-type polycrystalline silicon film protruding from the trench 6, the nitride film 5, and the pad oxide film 4 are removed by CMP (Chemical Mechanical Polish) until the semiconductor layer 1 is exposed, and the second conductivity type is removed. A polycrystalline semiconductor layer 11 is formed. As a result, a trench isolation region Treis having the sidewall insulating film 7, the first conductive type polycrystalline semiconductor layer 9 'and the second conductive type polycrystalline semiconductor layer 11 is formed.

Although illustration of subsequent steps is omitted, a general CMOS process is used to form the gate insulating film, the gate electrode, the extension regions, the sidewalls, and the high-concentration impurity diffusion regions to form the structure shown in FIG. A semiconductor device having the same.

According to the manufacturing method of the present embodiment, the first conduction type polycrystalline semiconductor layer 9 ′ and the second conduction type polycrystalline semiconductor layer 11 can be formed without a mask forming step, so that the production cost is reduced. . Further, as described above, since the first conductivity type polycrystalline semiconductor layer 9 ′ is formed in a self-aligned manner, the thickness of the first conductivity type polycrystalline semiconductor layer 9 ′ is set to a value corresponding to the mask for forming the trench 6. Can be determined without providing a margin in consideration of the positional deviation. Therefore, the thickness of the first conductivity type polycrystalline semiconductor layer 9 'can be reduced to about 100 nm, and a structure suitable for miniaturization of a semiconductor device can be obtained.

In each of the above embodiments, an intrinsic (non-doped) layer is provided between the first conductivity type polycrystalline semiconductor layer 9 (or 9 ′) and the second conductivity type polycrystalline semiconductor layer 11 of the pn junctions Jpn1 and Jpn2. 3) Even if a polycrystalline semiconductor layer is interposed, the operation and effect of the present invention such as a high breakdown voltage structure using a depletion layer can be obtained.

In addition, when it is determined which of the two active regions 1a and 1b on both sides of the trench type element isolation region Treis has a higher potential, it is sufficient that at least one pn junction exists. Generally, the level of the voltage applied to the active regions 1a and 1b on both sides of the trench-type element isolation region Treis changes depending on the operation state of the semiconductor device. In order to produce the effect, it is preferable that two or more pn junctions exist in the trench type element isolation region.

Furthermore, four or more pn junctions may be provided in the semiconductor region. For example, when the third embodiment is used, in the step shown in FIG. 7B, after forming the sidewall type first conductivity type polycrystalline semiconductor layer 9 ′, the first conductivity type polycrystalline semiconductor film is formed. Is deposited and etched back to form a sidewall-type second conductivity-type polycrystalline semiconductor layer, and the remaining space is filled with the first conductivity-type polycrystalline semiconductor layer. A polycrystalline semiconductor region including the conductive type polycrystalline semiconductor layer and the two second conductive type polycrystalline semiconductor layers is formed. Then, four pn junctions exist in this polycrystalline semiconductor region. Therefore, a polycrystalline semiconductor region having a large number of pn junctions can be formed by alternately forming the sidewall type first conductive type polycrystalline semiconductor layers and the second conductive type polycrystalline semiconductor layers. . Similarly, even when the first and second embodiments are used, four or more ion implantations are performed by repeating the ion implantation many times, or by repeating the formation of the small trench and the CVD with the in-situ doping many times. The polycrystalline semiconductor region having the pn junction can be formed.

The sidewall insulating film 7 does not necessarily need to be an oxide film, but may be an oxynitride film, a nitride film, or the like. Further, as the sidewall insulating film 7, a CVD oxide film may be used instead of the thermal oxide film. However, it is necessary not to generate a large stress in the active regions 1a and 1b.

The semiconductor device of the present invention can be used for an LSI in which a large number of MISFETs are integrated, and is useful.

FIG. 2 is a cross-sectional view illustrating a structure of the semiconductor device according to the first embodiment using the SOI substrate. FIGS. 4A to 4C are cross-sectional views illustrating processes up to the formation of a sidewall insulating film in the process of manufacturing the semiconductor device according to the first embodiment. FIGS. 4A to 4C are cross-sectional views illustrating steps up to forming an implantation mask in the manufacturing steps of the semiconductor device of the first embodiment. FIGS. 3A and 3B are cross-sectional views illustrating the latter half of the manufacturing process of the semiconductor device according to the first embodiment. (A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device in 2nd Embodiment. FIG. 9 is a cross-sectional view illustrating a structure of a semiconductor device according to a third embodiment using an SOI substrate. (A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device in 3rd Embodiment.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 Semiconductor layer 2 Insulating layer 3 Semiconductor substrate 4 Pad oxide film 5 Nitride film 6 Trench 7 Side wall insulating film 8 Non-doped polycrystalline silicon film 9, 9 '2nd conductive type polycrystalline semiconductor layer 9x 2nd conductive type polycrystalline semiconductor film 10 Oxide film 11 Second conductivity type polycrystalline semiconductor layer 13 Pad oxide film 14 Nitride film 15 Small trench

Claims (10)

In a semiconductor device having a semiconductor layer provided on an insulating layer and an element isolation region for partitioning the semiconductor layer into a plurality of active regions provided with semiconductor elements,
The element isolation region,
A trench penetrating the semiconductor layer and reaching the insulating layer;
A sidewall insulating film covering both side surfaces of the trench,
A polycrystalline semiconductor region interposed between the side wall insulating films on both sides and having a pn junction extending in a depth direction of the trench. The semiconductor device according to claim 1,
The polycrystalline semiconductor region,
A first conductivity type polycrystalline semiconductor layer covering each side surface of the side wall insulating films on both sides;
A second conductivity type polycrystalline semiconductor layer interposed between the first conductivity type polycrystalline semiconductor layers on both sides,
A semiconductor device, wherein a pn junction extending in a depth direction of the trench is formed between each of the first conduction type polycrystalline semiconductor layer and the second conduction type polycrystalline semiconductor layer. The semiconductor device according to claim 2,
The semiconductor device, wherein the first conductivity type polycrystalline semiconductor layer has a sidewall type structure formed by etching back the polycrystalline semiconductor film. The semiconductor device according to claim 1,
The semiconductor layer is made of single crystal silicon,
The semiconductor device, wherein the polycrystalline semiconductor region is made of polycrystalline silicon. Forming a trench that penetrates a portion of the semiconductor layer provided on the insulating layer of the SOI substrate where an element isolation region is to be formed and reaches the insulating layer;
Forming a sidewall insulating film covering both side surfaces of the trench (b);
A first conductive type polycrystalline semiconductor layer covering each side surface of the side wall insulating films on both sides of the trench, and a second conductive layer interposed between the first conductive type polycrystalline semiconductor layers on both sides of the trench. And (c) forming a polycrystalline semiconductor layer. The method for manufacturing a semiconductor device according to claim 5,
The step (c) includes:
Burying a non-doped polycrystalline semiconductor film in the trench;
Implanting a first conductivity type impurity ion into the non-doped polycrystalline semiconductor film to change the non-doped polycrystalline semiconductor film into a first conductivity type polycrystalline semiconductor layer;
By performing ion implantation of the second conductivity type impurity using an implantation mask covering both ends of the first conductivity type polycrystalline semiconductor layer, a region excluding both ends of the first conductivity type polycrystalline semiconductor layer is removed. Converting to a two-conductivity type polycrystalline semiconductor layer. The method for manufacturing a semiconductor device according to claim 5,
The step (c) includes:
Filling the trench with a first conductivity type polycrystalline semiconductor film by CVD with in-situ doping of a first conductivity type impurity;
By ion implantation of impurities of the second conductivity type using an implantation mask covering both ends of the first conductivity type polycrystalline semiconductor film, a region excluding both ends of the first conductivity type polycrystalline semiconductor film is removed by the second conductivity type polycrystalline semiconductor film. Changing to a crystalline semiconductor layer and leaving both ends of the first conductive type polycrystalline semiconductor film as the first conductive type polycrystalline semiconductor layer. The method for manufacturing a semiconductor device according to claim 5,
The step (c) includes:
Filling the trench with a first conductivity type polycrystalline semiconductor layer;
Forming a small trench reaching the insulating layer in a region excluding both ends of the first conductivity type polycrystalline semiconductor layer;
Filling the small trench with a second conductivity type polycrystalline semiconductor layer using CVD with in-situ doping of a first conductivity type impurity. The method for manufacturing a semiconductor device according to claim 5,
The step (c) includes:
After depositing the first conductive type polycrystalline semiconductor film filling the trench, a sidewall type first conductive type polycrystalline semiconductor layer covering each side surface of the side wall insulating film on both sides of the trench is formed by etch back. Process and
Forming a second conductivity type polycrystalline semiconductor layer that fills the space between the first conductivity type polycrystalline semiconductor layers by performing CVD with in-situ doping of second conductivity type impurities. Method. The method of manufacturing a semiconductor device according to claim 5,
In the step (a), an SOI substrate having a semiconductor layer made of single crystal silicon is used,
In the step (c), a method of manufacturing a semiconductor device, wherein a first conductivity type polycrystalline semiconductor layer and a second conductivity type polycrystalline semiconductor layer each made of polycrystalline silicon are formed.

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