JP4495073B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4495073B2
JP4495073B2 JP2005343355A JP2005343355A JP4495073B2 JP 4495073 B2 JP4495073 B2 JP 4495073B2 JP 2005343355 A JP2005343355 A JP 2005343355A JP 2005343355 A JP2005343355 A JP 2005343355A JP 4495073 B2 JP4495073 B2 JP 4495073B2
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insulating film
germanium layer
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silicon layer
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ジュン，ミュン・ジン
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東部エレクトロニクス株式会社
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Description

本発明は半導体素子に関し、特に歪みシリコン層(strained silicon layer)を活性層として用いた半導体素子において、ソース・ドレイン領域の下部の歪みシリコン層に絶縁膜を形成することにより、半導体素子の動作特性を向上させた半導体素子とその製造方法に関する。   The present invention relates to a semiconductor device, and more particularly, in a semiconductor device using a strained silicon layer as an active layer, by forming an insulating film in a strained silicon layer below a source / drain region, the operating characteristics of the semiconductor device The present invention relates to a semiconductor device and a manufacturing method thereof.

一般的に、半導体素子は、シリコン(Ｓｉ)基板上にゲルマニウム(Ｇｅ)片を載置し、一定温度の条件下でシリコン基板上のゲルマニウム層を成長させ、ゲルマニウム層上にシリコン層を再成長させると、ゲルマニウム層と同一の格子間の距離を有する歪みシリコン層を成長させることができる。したがって、歪みシリコン層は、既存のシリコン格子の間隔よりさらに広がった格子構造となる。   In general, a semiconductor device is formed by placing a germanium (Ge) piece on a silicon (Si) substrate, growing a germanium layer on the silicon substrate under a constant temperature condition, and re-growing the silicon layer on the germanium layer. Then, a strained silicon layer having the same interstitial distance as the germanium layer can be grown. Therefore, the strained silicon layer has a lattice structure that is wider than the interval between the existing silicon lattices.

また、半導体素子のサイズが微小化するのに伴って、発生する電子とホールの移動度が減少するという問題点がある。したがって、前記のような電子とホールの移動度が減少するという問題点を解決するために、前記のような歪みシリコン層が半導体素子の基板として多く用いられている。   Further, as the size of the semiconductor element is reduced, there is a problem that the mobility of generated electrons and holes decreases. Therefore, in order to solve the problem that the mobility of electrons and holes is reduced as described above, a strained silicon layer as described above is often used as a substrate of a semiconductor element.

しかしながら、かかる従来技術による半導体素子には、次のような問題点があった。   However, the conventional semiconductor device has the following problems.

歪みシリコン層を基板として用いることにより、電子とホールの移動度を高めて半導体素子の動作特性を向上させたが、半導体素子がナノ系列の大きさに微小化する際に発生するリーク電流、これによるＤＩＢＬ(Drain Induced Barrier Lowing)、リーク電流の増加による接合降伏電圧の発生は解決することができなかった。   By using a strained silicon layer as a substrate, the mobility of electrons and holes has been increased to improve the operating characteristics of the semiconductor device. However, the leakage current generated when the semiconductor device is reduced to the nano-scale size, The generation of junction breakdown voltage due to DIBL (Drain Induced Barrier Lowing) due to the increase in leakage current cannot be solved.

本発明は、従来技術における制約や不都合に起因する問題点の一つ以上を解決できるような、半導体素子とその製造方法を提供する。   The present invention provides a semiconductor device and a method for manufacturing the same that can solve one or more problems caused by limitations and disadvantages in the prior art.

本発明の目的は、歪みシリコン層のソース・ドレイン領域の下部に絶縁膜を形成し、リーク電流を減少させ、リーク電流による接合降伏電圧を減少させ、動作電源を高電圧でも投入することができる半導体素子とその製造方法を提供することである。   An object of the present invention is to form an insulating film below the source / drain region of the strained silicon layer, reduce the leakage current, reduce the junction breakdown voltage due to the leakage current, and turn on the operating power even at a high voltage. It is to provide a semiconductor device and a manufacturing method thereof.

上記目的を達成するために、本発明に係る半導体素子は、アクティブ領域とフィールド領域とが区画されており、第１シリコン層、ゲルマニウム層、第２シリコン層を順次成長させた歪みシリコン基板と、前記歪みシリコン基板のアクティブ領域の上に形成されたゲート電極と、前記歪みシリコン基板の前記ゲート電極の両側に形成されるソース・ドレイン領域と、前記歪みシリコン基板の前記ソース・ドレイン領域の下部に形成される絶縁膜とを有することを特徴とする。   In order to achieve the above object, a semiconductor device according to the present invention includes a strained silicon substrate in which an active region and a field region are partitioned, and a first silicon layer, a germanium layer, and a second silicon layer are sequentially grown; A gate electrode formed on an active region of the strained silicon substrate; a source / drain region formed on both sides of the gate electrode of the strained silicon substrate; and a lower portion of the source / drain region of the strained silicon substrate. And an insulating film to be formed.

前記絶縁膜は、前記ソース・ドレイン領域の空乏箇所まで延長して形成されていることが望ましい。   The insulating film is preferably formed to extend to a depletion portion of the source / drain region.

前記絶縁膜は、前記歪みシリコン基板のゲルマニウム層に形成されていることが望ましい。   The insulating film is preferably formed on a germanium layer of the strained silicon substrate.

前記第２シリコン層の厚さは、５０Å〜２５０Åの範囲あることが望ましい。   The thickness of the second silicon layer is preferably in the range of 50 to 250 mm.

また、上記目的を達成するための本発明による半導体素子は、第１シリコン層、ゲルマニウム層、第２シリコン層が順次成長した歪みシリコン基板と、前記歪みシリコン基板上に形成される第１、第２ゲート電極と、前記歪みシリコン基板の前記第１ゲート電極の両側に形成される第１導電型ソース・ドレイン領域と、前記歪みシリコン基板の前記第２ゲート電極の両側に形成される第２導電型ソース・ドレイン領域と、前記歪みシリコン基板の前記第１、第２ソース・ドレイン領域の下部に形成される絶縁膜とを有することを特徴とする。   In order to achieve the above object, a semiconductor device according to the present invention includes a strained silicon substrate on which a first silicon layer, a germanium layer, and a second silicon layer are sequentially grown, and a first and a first formed on the strained silicon substrate. Two gate electrodes; first conductivity type source / drain regions formed on both sides of the first gate electrode of the strained silicon substrate; and second conductivity formed on both sides of the second gate electrode of the strained silicon substrate. And having an insulating film formed under the first and second source / drain regions of the strained silicon substrate.

一方、上記目的を達成するために、本発明に係る半導体素子の製造方法は、第１シリコン層上にゲルマニウム層を成長させる段階と、前記ゲルマニウム層に少なくとも２つのトレンチを形成する段階と、前記トレンチを備えているゲルマニウム層に絶縁膜を形成する段階と、前記トレンチの底面のみに前記絶縁膜が残るように、前記ゲルマニウム層と絶縁膜を研磨し、少なくとも２つの絶縁膜パターンを形成する段階と、前記平坦化させたゲルマニウム層にゲルマニウム層を再成長させて平坦化する段階と、前記ゲルマニウム層に第２シリコン層を形成する段階と、前記少なくとも２つの絶縁膜の間の第２シリコン層上に、ゲート絶縁膜とゲート電極を形成する段階と、前記第２シリコン層の前記ゲート電極の両側に不純物イオンを注入し、ソース・ドレイン領域を形成する段階とを有することを特徴とする。   Meanwhile, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of growing a germanium layer on a first silicon layer, a step of forming at least two trenches in the germanium layer, Forming an insulating film on a germanium layer having a trench; and polishing at least two insulating film patterns by polishing the germanium layer and the insulating film so that the insulating film remains only on a bottom surface of the trench. A step of re-growing a germanium layer on the planarized germanium layer to planarize, a step of forming a second silicon layer on the germanium layer, and a second silicon layer between the at least two insulating films A step of forming a gate insulating film and a gate electrode; and implanting impurity ions on both sides of the gate electrode of the second silicon layer; And having and forming over scan and drain regions.

前記第１シリコン層(ＳｉX−1)とゲルマニウム層(ＧｅX)の組成比(Ｘ)は、０．１〜０．５の比率とすることが望ましい。 The composition ratio (X) of the first silicon layer (Si x-1 ) and the germanium layer (Ge x ) is preferably set to a ratio of 0.1 to 0.5.

本発明の半導体素子とその製造方法には次のような効果がある。   The semiconductor device and the manufacturing method thereof according to the present invention have the following effects.

第一に、本発明は歪みシリコン基板内部のソース・ドレイン領域の下部に絶縁膜を形成することにより、徐々に微細化される半導体素子で、シリコン格子による電子とホールの移動度の減少を改善すると共に半導体素子のサイズを微小化し、チャンネル減少によるリーク電流を防止することができる。従って、飽和された駆動電流を２０〜４０％向上させることができる。   First, the present invention improves the reduction of mobility of electrons and holes due to the silicon lattice in a semiconductor element that is gradually miniaturized by forming an insulating film under the source / drain region inside the strained silicon substrate. At the same time, the size of the semiconductor element can be reduced, and leakage current due to channel reduction can be prevented. Therefore, the saturated drive current can be improved by 20 to 40%.

第二に、リーク電流を解決することにより、ＤＩＢＬと接合降伏電圧が減少するため、歪みシリコン基板においてナノ級以下の半導体素子と高電圧素子を得ることができる。   Second, by solving the leakage current, the DIBL and the junction breakdown voltage are reduced, so that a nano-class semiconductor element and a high-voltage element can be obtained in a strained silicon substrate.

第三に、電子移動度が５０％以上向上するため、半導体素子の性能が顕著に向上する。   Third, since the electron mobility is improved by 50% or more, the performance of the semiconductor element is remarkably improved.

第四に、ＣＭＯＳ半導体素子を製作しても、ｎ型ウェルとｐ型ウェルを形成する工程を減らすことができるため、生産性を向上させて単価を減らすことができる。   Fourth, even if a CMOS semiconductor device is manufactured, the number of steps for forming the n-type well and the p-type well can be reduced, so that the productivity can be improved and the unit price can be reduced.

第五に、絶縁膜によりソースとドレインとの間で発生する熱を容易に逃すことができるため、熱による半導体素子の性能が低下することを防止することができる。   Fifth, since heat generated between the source and the drain can be easily released by the insulating film, it is possible to prevent the performance of the semiconductor element from being deteriorated due to heat.

第六に、ＣＭＯＳ半導体素子を形成する時は、ｎＭＯＳとｐＭＯＳとの間で素子隔離膜の形成が不要なため、半導体素子のサイズを微小化することができる。   Sixth, when forming a CMOS semiconductor element, it is not necessary to form an element isolation film between the nMOS and the pMOS, so that the size of the semiconductor element can be reduced.

添付図面に例示された、本発明の好ましい実施形態について詳細に説明する。図面において対応する要素に同一の参照符号を付している。   Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Corresponding elements in the drawings have the same reference numerals.

以下、本発明に係る半導体素子とその製造方法の好適な実施の形態について、添付の図面に基づいて詳細に説明する。   Preferred embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described below in detail with reference to the accompanying drawings.

図１は本発明に係る半導体素子の構造断面図である。
本発明に係る半導体素子は、図１に示すように、第１シリコン層３上にゲルマニウム層５を成長させ、ゲルマニウム層５上に第２シリコン層６を再成長させた歪みシリコン基板１０と、アクティブ領域とフィールド領域を区画するために、歪みシリコン基板１０のフィールド領域に形成された素子隔離膜３１と、アクティブ領域の歪みシリコン基板１０上の所定領域に順次積層されたゲート絶縁膜４１とゲート電極４２と、歪みシリコン基板１０のゲート電極４２の両側に形成されるソース・ドレイン領域４４ａ、４４ｂと、歪みシリコン基板１０内のソース・ドレイン領域４４ａ、４４ｂの下部に形成される絶縁膜１７ａ、１７ｂとを備えている。 FIG. 1 is a structural sectional view of a semiconductor device according to the present invention.
As shown in FIG. 1, a semiconductor device according to the present invention includes a strained silicon substrate 10 in which a germanium layer 5 is grown on a first silicon layer 3 and a second silicon layer 6 is regrown on the germanium layer 5. In order to partition the active region and the field region, an element isolation film 31 formed in the field region of the strained silicon substrate 10, a gate insulating film 41 and a gate sequentially stacked in a predetermined region on the strained silicon substrate 10 in the active region An electrode 42, source / drain regions 44a, 44b formed on both sides of the gate electrode 42 of the strained silicon substrate 10, and an insulating film 17a formed under the source / drain regions 44a, 44b in the strained silicon substrate 10. 17b.

この絶縁膜１７ａ、１７ｂは素子隔離膜３１と接触するように形成されており、歪みシリコン基板１０内のゲルマニウム層３に形成される。
また、ゲート電極４２とゲート絶縁膜４１の側面には側壁絶縁膜４３が形成される。 The insulating films 17 a and 17 b are formed so as to be in contact with the element isolation film 31 and are formed on the germanium layer 3 in the strained silicon substrate 10.
A sidewall insulating film 43 is formed on the side surfaces of the gate electrode 42 and the gate insulating film 41.

このような原理を用いて形成された本発明に係る半導体素子の製造方法について説明すると次のとおりである。
図２ａないし図２ｆは本発明に係る半導体素子の製造工程断面図である。
図２ａに示したように、第１シリコン層３上にゲルマニウム層５をエピタキシャルタキシャル成長させ、ゲルマニウム層５上に第１絶縁膜１１を堆積させる。ゲルマニウム層５の格子間の距離は、第１シリコン層の格子間の距離よりも広くなる。 A method for manufacturing a semiconductor device according to the present invention formed using such a principle will be described as follows.
2a to 2f are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the present invention.
As shown in FIG. 2 a, the germanium layer 5 is epitaxially grown on the first silicon layer 3, and the first insulating film 11 is deposited on the germanium layer 5. The distance between the lattices of the germanium layer 5 is larger than the distance between the lattices of the first silicon layer.

第１シリコン層３上にゲルマニウム層５をエピタキシャルタキシャル成長させる方法以外の方法で、シリコン(ＳｉX−1)とゲルマニウム(ＧｅX)を備えた基板を形成することができる。この時、シリコンとゲルマニウムの組成比(Ｘ)は０．１〜０．５の比率とする。
次に、第１絶縁膜１１上に感光膜を塗布し、マスクを用いた露光工程と現像工程でその後に形成されるソース・ドレイン領域の感光膜を除去した第１感光膜パターン１２を形成する。 A substrate comprising silicon (Si x-1 ) and germanium (Ge x ) can be formed by a method other than the method of epitaxially growing the germanium layer 5 on the first silicon layer 3. At this time, the composition ratio (X) of silicon and germanium is set to a ratio of 0.1 to 0.5.
Next, a photosensitive film is applied on the first insulating film 11, and a first photosensitive film pattern 12 is formed by removing the photosensitive film in the source / drain regions formed thereafter in the exposure process and development process using a mask. .

図２ｂに示すように、第１感光膜パターン１２をマスクとして用いて、第１絶縁膜１１とゲルマニウム層５を所定の深さ除去してトレンチ１５を形成する。
次に、第１感光膜パターン１２と第１絶縁膜１１を全て除去する。
その後、トレンチ１５の内壁を含めてゲルマニウム層５の全面に、所定の厚さで第２絶縁膜１７を形成する。 As shown in FIG. 2B, the first insulating film 11 and the germanium layer 5 are removed to a predetermined depth using the first photosensitive film pattern 12 as a mask to form a trench 15.
Next, the first photosensitive film pattern 12 and the first insulating film 11 are all removed.
Thereafter, the second insulating film 17 is formed with a predetermined thickness on the entire surface of the germanium layer 5 including the inner wall of the trench 15.

図２ｃに示すように、第２絶縁膜１７とゲルマニウム層５の一部を化学機械研磨（ＣＭＰ）工程でトレンチ１５の下部面のみに第２絶縁膜１７が残るように平坦化した絶縁膜１７ａ、１７ｂパターンを形成する。
この絶縁膜１７ａ、１７ｂパターンはその後形成されるソース・ドレイン領域の空乏箇所まで延長させるようにし、ソース・ドレイン領域のリーク経路が長くなるようにすると共に、接合容量を減らす役割をする。それだけでなく、絶縁膜１７ａ、１７ｂパターンには、ソースとドレインとの間で発生する熱を容易に逃す機能がある。 As shown in FIG. 2c, the second insulating film 17 and a part of the germanium layer 5 are planarized so that the second insulating film 17 remains only on the lower surface of the trench 15 by a chemical mechanical polishing (CMP) process. , 17b pattern is formed.
The patterns of the insulating films 17a and 17b are extended to the depleted portions of the source / drain regions to be formed thereafter, so that the leakage path of the source / drain regions becomes longer and the junction capacitance is reduced. In addition, the insulating films 17a and 17b patterns have a function of easily releasing heat generated between the source and the drain.

図２ｄに示すように、絶縁膜１７ａ、１７ｂが形成された基板上にゲルマニウム層５を再びエピタキシャルタキシャル成長させた後、ＣＭＰ工程を用いてゲルマニウム層５を平坦化させる。平坦化させる理由は、前記ゲルマニウム層５を再成長させる時、絶縁膜１７ａ、１７ｂパターンの上側では、相対的にゲルマニウム層が薄く形成されるためである。   As shown in FIG. 2d, after the germanium layer 5 is epitaxially grown again on the substrate on which the insulating films 17a and 17b are formed, the germanium layer 5 is planarized using a CMP process. The reason for flattening is that when the germanium layer 5 is regrown, the germanium layer is relatively thinly formed on the upper side of the patterns of the insulating films 17a and 17b.

図２ｅに示すように、平坦化させたゲルマニウム層５上に、エピタキシャル工程で第２シリコン層６を５０Å〜２５０Åの厚さに成長させ、第１シリコン層３、ゲルマニウム層５、第２シリコン層６が順次積層した歪みシリコン基板１０を形成する。ゲルマニウム層５の上に形成される第２シリコン層６の格子間の距離はゲルマニウム層５の格子間の距離と同一に形成される。   As shown in FIG. 2e, a second silicon layer 6 is grown on the planarized germanium layer 5 to a thickness of 50 to 250 by an epitaxial process, and the first silicon layer 3, the germanium layer 5, and the second silicon layer are grown. A strained silicon substrate 10 in which 6 is sequentially stacked is formed. The distance between the lattices of the second silicon layer 6 formed on the germanium layer 5 is the same as the distance between the lattices of the germanium layer 5.

図２ｆに示すように、歪みシリコン基板１０をアクティブ領域とフィールド領域とを決め、フィールド領域において歪みシリコン基板１０を所定の深さでエッチングしてトレンチを形成し、トレンチ内に絶縁膜を形成して素子分離膜３１を形成する。
また、素子分離膜３１が形成された歪みシリコン基板１０の全面にゲート絶縁用絶縁膜４１ａと導電層４２ａを順次堆積させる。 As shown in FIG. 2f, an active region and a field region are determined for the strained silicon substrate 10, and a trench is formed by etching the strained silicon substrate 10 at a predetermined depth in the field region, and an insulating film is formed in the trench. Thus, the element isolation film 31 is formed.
Further, an insulating film 41a for gate insulation and a conductive layer 42a are sequentially deposited on the entire surface of the strained silicon substrate 10 on which the element isolation film 31 is formed.

図２ｇに示すように、ゲート絶縁用絶縁膜４１ａと導電層４２ａを選択的に除去してゲート絶縁膜４１とゲート電極４２を形成する。
この時、ゲート絶縁膜４１とゲート電極４２の幅はトランジスタのチャンネルの幅に相当するもので、絶縁膜１７ａ、１７ｂのパターンの間の距離より長く形成され、その後形成されるソース・ドレイン領域の空乏箇所が絶縁膜１７ａ、１７ｂパターンにより覆われるようにする。即ち、ゲート電極４２は絶縁膜１７ａ、１７ｂパターンとオーバーラップするように形成される。これはリーク電流のリーク経路を長くする役割をする。 As shown in FIG. 2g, the gate insulating film 41a and the gate electrode 42 are formed by selectively removing the gate insulating film 41a and the conductive layer 42a.
At this time, the width of the gate insulating film 41 and the gate electrode 42 corresponds to the width of the channel of the transistor, and is formed longer than the distance between the patterns of the insulating films 17a and 17b. The depletion part is covered with the insulating film 17a, 17b pattern. That is, the gate electrode 42 is formed so as to overlap the patterns of the insulating films 17a and 17b. This serves to lengthen the leakage path of the leakage current.

次に、ゲート絶縁膜４１とゲート電極４２をマスクとして用いて、低濃度の不純物イオンを注入し、歪みシリコン基板１０のゲート電極４２の両側にＬＤＤ領域２３ａ、２３ｂを形成する。
さらに、全面に絶縁膜を堆積し、異方性エッチングを施してゲート電極４２とゲート絶縁膜４１の側面にスペーサ４３を形成する。次に、ゲート電極４２とスペーサ４３をマスクとして用いて歪みシリコン基板１０のアクティブ領域に不純物イオンを高濃度で注入してソース・ドレイン領域４４ａ、４４ｂを形成する。 Next, using the gate insulating film 41 and the gate electrode 42 as a mask, low concentration impurity ions are implanted to form LDD regions 23 a and 23 b on both sides of the gate electrode 42 of the strained silicon substrate 10.
Further, an insulating film is deposited on the entire surface, and anisotropic etching is performed to form spacers 43 on the side surfaces of the gate electrode 42 and the gate insulating film 41. Next, using the gate electrode 42 and the spacer 43 as a mask, impurity ions are implanted at a high concentration into the active region of the strained silicon substrate 10 to form source / drain regions 44a and 44b.

図３は、このような本発明の半導体素子をＣＭＯＳに適用した断面図である。
即ち、第１シリコン層１３上にゲルマニウム層１５が成長し、ゲルマニウム層１５上に第２シリコン層１６が再成長した歪みシリコン基板１００の所定領域にｎ−ＭＯＳゲート絶縁膜１４１ａとゲート電極１４２ａが形成され、他の領域にｐ−ＭＯＳ用ゲート絶縁膜１４１ｂとゲート電極１４２ａが形成されている。 FIG. 3 is a sectional view in which such a semiconductor device of the present invention is applied to a CMOS.
That is, the n-MOS gate insulating film 141a and the gate electrode 142a are formed in a predetermined region of the strained silicon substrate 100 in which the germanium layer 15 is grown on the first silicon layer 13 and the second silicon layer 16 is regrown on the germanium layer 15. The p-MOS gate insulating film 141b and the gate electrode 142a are formed in other regions.

ｎ−ＭＯＳ用ゲート電極１４２ａの両側の歪みシリコン基板１００に高濃度のｎ型ソース・ドレイン領域１４４ａ、１４４ｂが形成され、ｐ−ＭＯＳ用ゲート電極１４２ｂの両側の歪みシリコン基板１００に高濃度のｐ型ソース・ドレイン領域１４５ａ、１４５ｂが形成されている。そして、歪みシリコン基板１００内のｎ型とｐ型のソース・ドレイン領域１４４ａ、１４４ｂ、１４５ａ、１４５ｂの下部に絶縁膜１１７ａ、１１７ｂが形成される。
絶縁膜１１７ａ、１１７ｂは歪みシリコン基板１００のゲルマニウム層１３に形成され、各ソース・ドレイン領域１４４ａ、１４４ｂと１４５ａ、１４５ｂの空乏箇所を覆うようにチャンネル領域側に延長して形成される。 High-concentration n-type source / drain regions 144a and 144b are formed on the strained silicon substrate 100 on both sides of the n-MOS gate electrode 142a, and high-concentration p is formed on the strained silicon substrate 100 on both sides of the p-MOS gate electrode 142b. Type source / drain regions 145a and 145b are formed. Then, insulating films 117 a and 117 b are formed below the n-type and p-type source / drain regions 144 a, 144 b, 145 a and 145 b in the strained silicon substrate 100.
The insulating films 117a and 117b are formed on the germanium layer 13 of the strained silicon substrate 100, and are extended to the channel region side so as to cover the depletion portions of the source / drain regions 144a, 144b and 145a and 145b.

このように、ＣＭＯＳトランジスタを製作しても、電子移動度が優れているため、別途のｎ型ウェルとｐ型ウェルの形成が不要なため、ｎ−ＭＯＳとｐ−ＭＯＳとの間に素子隔離膜を必要としない。   Thus, even if a CMOS transistor is manufactured, since the electron mobility is excellent, it is not necessary to form a separate n-type well and p-type well, so that element isolation is provided between the n-MOS and the p-MOS. Does not require a membrane.

本発明に係る半導体素子の構造断面図である。1 is a structural cross-sectional view of a semiconductor element according to the present invention. 本発明に係る半導体素子の工程断面図である。It is process sectional drawing of the semiconductor element which concerns on this invention. 本発明に係る半導体素子の工程断面図である。It is process sectional drawing of the semiconductor element which concerns on this invention. 本発明に係る半導体素子の工程断面図である。It is process sectional drawing of the semiconductor element which concerns on this invention. 本発明に係る半導体素子の工程断面図である。It is process sectional drawing of the semiconductor element which concerns on this invention. 本発明に係る半導体素子の工程断面図である。It is process sectional drawing of the semiconductor element which concerns on this invention. 本発明に係る半導体素子の工程断面図である。It is process sectional drawing of the semiconductor element which concerns on this invention. 本発明に係る半導体素子の工程断面図である。It is process sectional drawing of the semiconductor element which concerns on this invention. 本発明に係るＣＭＯＳ半導体素子の構造断面図である。1 is a structural cross-sectional view of a CMOS semiconductor device according to the present invention.

符号の説明Explanation of symbols

１０、１００ 基板、３、１３ 第１シリコン層、５、１５ ゲルマニウム層、６、１６ 第２シリコン層、１１ 第１絶縁膜、１２ 第１感光膜、１５ トレンチ、１７ 第２絶縁膜、１７ａ、１７ｂ、１１７ａ、１１７ｂ 絶縁膜、２３ａ、２３ｂ ＬＤＤ領域、３１ 素子隔離膜、４１、１４１ａ、１４１ｂ ゲート絶縁膜、４２、１４２ａ、１４２ｂ ゲート電極、４４ａ、４４ｂ、１４４ａ、１４４ｂ、１４５ａ、１４５ｂ ソース・ドレイン領域   10, 100 substrate, 3, 13 first silicon layer, 5, 15 germanium layer, 6, 16 second silicon layer, 11 first insulating film, 12 first photosensitive film, 15 trench, 17 second insulating film, 17a, 17b, 117a, 117b Insulating film, 23a, 23b LDD region, 31 Device isolation film, 41, 141a, 141b Gate insulating film, 42, 142a, 142b Gate electrode, 44a, 44b, 144a, 144b, 145a, 145b Source / drain region

Claims (3)

第１シリコン層上に格子間の距離がこの第１シリコン層の格子間の距離より広いゲルマニウム層を成長させる段階と、
前記ゲルマニウム層に少なくとも２つのトレンチを形成する段階と、
前記トレンチを備えているゲルマニウム層に絶縁膜を形成する段階と、
前記トレンチの底面のみに前記絶縁膜が残るように、前記ゲルマニウム層と絶縁膜を研磨し、少なくとも２つの絶縁膜パターンを形成する段階と、
前記平坦化させたゲルマニウム層にゲルマニウム層を再成長させて平坦化する段階と、
前記ゲルマニウム層上に格子間の距離が前記ゲルマニウム層の格子間の距離と同一となるように第２シリコン層を形成する段階と、
前記少なくとも２つの絶縁膜パターンの間の前記第２シリコン層上に、ゲート絶縁膜とゲート電極を形成する段階と、
前記ゲート電極の両側の前記第２シリコン層に、不純物イオンを注入し、ソース・ドレイン領域を形成する段階と
を有し、
前記少なくとも二つの絶縁膜パターンは、前記ソース・ドレイン領域の下部に前記ソース・ドレイン領域の空乏箇所まで延長して形成される
ことを特徴とする半導体素子の製造方法。 Growing a germanium layer on the first silicon layer having a greater interstitial distance than the interstitial distance of the first silicon layer ;
Forming at least two trenches in the germanium layer;
Forming an insulating film on the germanium layer having the trench;
Polishing the germanium layer and the insulating film so as to leave the insulating film only on the bottom surface of the trench, and forming at least two insulating film patterns;
Re-growth and planarize the germanium layer on the planarized germanium layer;
Forming a second silicon layer on the germanium layer such that a distance between lattices is the same as a distance between lattices of the germanium layer ;
The second silicon layer between the at least two insulating pattern, forming a gate insulating film and the gate electrode,
The second silicon layer on both sides of the gate electrode, the impurity ions are implanted, possess and forming source and drain regions,
The method of manufacturing a semiconductor device, wherein the at least two insulating film patterns are formed under the source / drain regions so as to extend to a depletion portion of the source / drain regions . 前記第２シリコン層の厚さは、５０Å〜２５０Åの範囲で形成されていることを特徴とする請求項１に記載の半導体素子の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1 , wherein a thickness of the second silicon layer is in a range of 50 to 250 mm. 3. 前記ゲート電極は、前記少なくとも２つの絶縁膜パターンとオーバーラップするように形成されていることを特徴とする請求項１または２に記載の半導体素子の製造方法。 The gate electrode, The method according to claim 1 or 2, characterized in that it is formed to the overlapping at least two of the insulating film pattern.
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